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mx6sxsabresd: Fix Ethernet PHY reset sequence

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Since commit 59370f3fcd ("net: phy: delay only if reset handler is
registered") Ethernet is no longer functional.

This commit does not have an issue in itself, but it revelead a problem
with the Ethernet initialization.

Fix this by calling enable_fec_anatop_clock() earlier and also
by adding a 10ms reset delay as recommended in the AR8031 datasheet.

Suggested-by: Jörg Krause <joerg.krause@embedded.rocks>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Fabio Estevam 2015-11-23 16:18:02 -02:00 committed by Stefano Babic
parent 6768146aef
commit 29bc24ec4f
1 changed files with 7 additions and 3 deletions
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10
board/freescale/mx6sxsabresd/mx6sxsabresd.c
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@ -150,11 +150,15 @@ static int setup_fec(void)
{ {
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
int reg; int reg, ret;
/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
ret = enable_fec_anatop_clock(0, ENET_125MHZ);
if (ret)
return ret;
imx_iomux_v3_setup_multiple_pads(phy_control_pads, imx_iomux_v3_setup_multiple_pads(phy_control_pads,
ARRAY_SIZE(phy_control_pads)); ARRAY_SIZE(phy_control_pads));
@ -163,14 +167,14 @@ static int setup_fec(void)
/* Reset AR8031 PHY */ /* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
udelay(500); mdelay(10);
gpio_set_value(IMX_GPIO_NR(2, 7), 1); gpio_set_value(IMX_GPIO_NR(2, 7), 1);
reg = readl(&anatop->pll_enet); reg = readl(&anatop->pll_enet);
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
writel(reg, &anatop->pll_enet); writel(reg, &anatop->pll_enet);
return enable_fec_anatop_clock(0, ENET_125MHZ); return 0;
} }
int board_eth_init(bd_t *bis) int board_eth_init(bd_t *bis)