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Subtree merge tag 'v6.18-dts' of dts repo [1] into dts/upstream

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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
This commit is contained in:
Tom Rini 2025-12-19 14:28:07 -06:00
commit 29ab19c2be
1510 changed files with 83066 additions and 21665 deletions
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3
arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi
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@ -17,9 +17,8 @@
}; };
}; };
&usb_1_dwc3 { &usb_1 {
dr_mode = "host"; dr_mode = "host";
/delete-property/ usb-role-switch;
}; };
// RAM Entry 0 : Base 0x0080000000 Size 0x003A800000 // RAM Entry 0 : Base 0x0080000000 Size 0x003A800000

2
dts/upstream/Bindings/.yamllint
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@ -4,7 +4,7 @@ rules:
quoted-strings: quoted-strings:
required: only-when-needed required: only-when-needed
extra-allowed: extra-allowed:
- '[$^,[]' - '[$^[]'
- '^/$' - '^/$'
line-length: line-length:
# 80 chars should be enough, but don't fail if a line is longer # 80 chars should be enough, but don't fail if a line is longer

15
dts/upstream/Bindings/arm/altera/socfpga-sdram-edac.txt
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@ -1,15 +0,0 @@
Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
The EDAC accesses a range of registers in the SDRAM controller.
Required properties:
- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10"
- altr,sdr-syscon : phandle of the sdr module
- interrupts : Should contain the SDRAM ECC IRQ in the
appropriate format for the IRQ controller.
Example:
sdramedac {
compatible = "altr,sdram-edac";
altr,sdr-syscon = <&sdr>;
interrupts = <0 39 4>;
};

41
dts/upstream/Bindings/arm/apple.yaml
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@ -92,10 +92,11 @@ description: |
Devices based on the "M2" SoC: Devices based on the "M2" SoC:
- MacBook Air (M2, 2022) - MacBook Air (M2, 2022)
- MacBook Air (15-inch, M2, 2023)
- MacBook Pro (13-inch, M2, 2022) - MacBook Pro (13-inch, M2, 2022)
- Mac mini (M2, 2023) - Mac mini (M2, 2023)
And devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: Devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs:
- MacBook Pro (14-inch, M1 Pro, 2021) - MacBook Pro (14-inch, M1 Pro, 2021)
- MacBook Pro (14-inch, M1 Max, 2021) - MacBook Pro (14-inch, M1 Max, 2021)
@ -104,6 +105,17 @@ description: |
- Mac Studio (M1 Max, 2022) - Mac Studio (M1 Max, 2022)
- Mac Studio (M1 Ultra, 2022) - Mac Studio (M1 Ultra, 2022)
Devices based on the "M2 Pro", "M2 Max" and "M2 Ultra" SoCs:
- MacBook Pro (14-inch, M2 Pro, 2023)
- MacBook Pro (14-inch, M2 Max, 2023)
- MacBook Pro (16-inch, M2 Pro, 2023)
- MacBook Pro (16-inch, M2 Max, 2023)
- Mac mini (M2 Pro, 2023)
- Mac Studio (M2 Max, 2023)
- Mac Studio (M2 Ultra, 2023)
- Mac Pro (M2 Ultra, 2023)
The compatible property should follow this format: The compatible property should follow this format:
compatible = "apple,<targettype>", "apple,<socid>", "apple,arm-platform"; compatible = "apple,<targettype>", "apple,<socid>", "apple,arm-platform";
@ -279,6 +291,7 @@ properties:
items: items:
- enum: - enum:
- apple,j413 # MacBook Air (M2, 2022) - apple,j413 # MacBook Air (M2, 2022)
- apple,j415 # MacBook Air (15-inch, M2, 2023)
- apple,j473 # Mac mini (M2, 2023) - apple,j473 # Mac mini (M2, 2023)
- apple,j493 # MacBook Pro (13-inch, M2, 2022) - apple,j493 # MacBook Pro (13-inch, M2, 2022)
- const: apple,t8112 - const: apple,t8112
@ -308,6 +321,32 @@ properties:
- const: apple,t6002 - const: apple,t6002
- const: apple,arm-platform - const: apple,arm-platform
- description: Apple M2 Pro SoC based platforms
items:
- enum:
- apple,j414s # MacBook Pro (14-inch, M2 Pro, 2023)
- apple,j416s # MacBook Pro (16-inch, M2 Pro, 2023)
- apple,j474s # Mac mini (M2 Pro, 2023)
- const: apple,t6020
- const: apple,arm-platform
- description: Apple M2 Max SoC based platforms
items:
- enum:
- apple,j414c # MacBook Pro (14-inch, M2 Max, 2023)
- apple,j416c # MacBook Pro (16-inch, M2 Max, 2023)
- apple,j475c # Mac Studio (M2 Max, 2023)
- const: apple,t6021
- const: apple,arm-platform
- description: Apple M2 Ultra SoC based platforms
items:
- enum:
- apple,j180d # Mac Pro (M2 Ultra, 2023)
- apple,j475d # Mac Studio (M2 Ultra, 2023)
- const: apple,t6022
- const: apple,arm-platform
additionalProperties: true additionalProperties: true
... ...

33
dts/upstream/Bindings/arm/apple/apple,pmgr.yaml
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@ -20,19 +20,26 @@ properties:
pattern: "^power-management@[0-9a-f]+$" pattern: "^power-management@[0-9a-f]+$"
compatible: compatible:
items: oneOf:
- enum: - items:
- apple,s5l8960x-pmgr - enum:
- apple,t7000-pmgr # Do not add additional SoC to this list.
- apple,s8000-pmgr - apple,s5l8960x-pmgr
- apple,t8010-pmgr - apple,t7000-pmgr
- apple,t8015-pmgr - apple,s8000-pmgr
- apple,t8103-pmgr - apple,t8010-pmgr
- apple,t8112-pmgr - apple,t8015-pmgr
- apple,t6000-pmgr - apple,t8103-pmgr
- const: apple,pmgr - apple,t8112-pmgr
- const: syscon - apple,t6000-pmgr
- const: simple-mfd - const: apple,pmgr
- const: syscon
- const: simple-mfd
- items:
- const: apple,t6020-pmgr
- const: apple,t8103-pmgr
- const: syscon
- const: simple-mfd
reg: reg:
maxItems: 1 maxItems: 1

4
dts/upstream/Bindings/arm/arm,coresight-cti.yaml
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@ -98,6 +98,10 @@ properties:
power-domains: power-domains:
maxItems: 1 maxItems: 1
label:
description:
Description of a coresight device.
arm,cti-ctm-id: arm,cti-ctm-id:
$ref: /schemas/types.yaml#/definitions/uint32 $ref: /schemas/types.yaml#/definitions/uint32
description: description:

4
dts/upstream/Bindings/arm/arm,coresight-dummy-sink.yaml
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@ -39,6 +39,10 @@ properties:
enum: enum:
- arm,coresight-dummy-sink - arm,coresight-dummy-sink
label:
description:
Description of a coresight device.
in-ports: in-ports:
$ref: /schemas/graph.yaml#/properties/ports $ref: /schemas/graph.yaml#/properties/ports

4
dts/upstream/Bindings/arm/arm,coresight-dummy-source.yaml
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@ -38,6 +38,10 @@ properties:
enum: enum:
- arm,coresight-dummy-source - arm,coresight-dummy-source
label:
description:
Description of a coresight device.
arm,static-trace-id: arm,static-trace-id:
description: If dummy source needs static id support, use this to set trace id. description: If dummy source needs static id support, use this to set trace id.
$ref: /schemas/types.yaml#/definitions/uint32 $ref: /schemas/types.yaml#/definitions/uint32

4
dts/upstream/Bindings/arm/arm,coresight-dynamic-funnel.yaml
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@ -57,6 +57,10 @@ properties:
power-domains: power-domains:
maxItems: 1 maxItems: 1
label:
description:
Description of a coresight device.
in-ports: in-ports:
$ref: /schemas/graph.yaml#/properties/ports $ref: /schemas/graph.yaml#/properties/ports

4
dts/upstream/Bindings/arm/arm,coresight-dynamic-replicator.yaml
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@ -54,6 +54,10 @@ properties:
- const: apb_pclk - const: apb_pclk
- const: atclk - const: atclk
label:
description:
Description of a coresight device.
power-domains: power-domains:
maxItems: 1 maxItems: 1

4
dts/upstream/Bindings/arm/arm,coresight-etb10.yaml
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@ -54,6 +54,10 @@ properties:
- const: apb_pclk - const: apb_pclk
- const: atclk - const: atclk
label:
description:
Description of a coresight device.
power-domains: power-domains:
maxItems: 1 maxItems: 1

4
dts/upstream/Bindings/arm/arm,coresight-etm.yaml
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@ -85,6 +85,10 @@ properties:
CPU powers down the coresight component also powers down and loses its CPU powers down the coresight component also powers down and loses its
context. context.
label:
description:
Description of a coresight device.
arm,cp14: arm,cp14:
type: boolean type: boolean
description: description:

4
dts/upstream/Bindings/arm/arm,coresight-static-funnel.yaml
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@ -30,6 +30,10 @@ properties:
power-domains: power-domains:
maxItems: 1 maxItems: 1
label:
description:
Description of a coresight device.
in-ports: in-ports:
$ref: /schemas/graph.yaml#/properties/ports $ref: /schemas/graph.yaml#/properties/ports

4
dts/upstream/Bindings/arm/arm,coresight-static-replicator.yaml
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@ -43,6 +43,10 @@ properties:
- const: dbg_trc - const: dbg_trc
- const: dbg_apb - const: dbg_apb
label:
description:
Description of a coresight device.
in-ports: in-ports:
$ref: /schemas/graph.yaml#/properties/ports $ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false additionalProperties: false

4
dts/upstream/Bindings/arm/arm,coresight-tmc.yaml
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@ -55,6 +55,10 @@ properties:
- const: apb_pclk - const: apb_pclk
- const: atclk - const: atclk
label:
description:
Description of a coresight device.
iommus: iommus:
maxItems: 1 maxItems: 1

4
dts/upstream/Bindings/arm/arm,coresight-tpiu.yaml
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@ -54,6 +54,10 @@ properties:
- const: apb_pclk - const: apb_pclk
- const: atclk - const: atclk
label:
description:
Description of a coresight device.
power-domains: power-domains:
maxItems: 1 maxItems: 1

7
dts/upstream/Bindings/arm/arm,vexpress-juno.yaml
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@ -103,8 +103,9 @@ properties:
- const: arm,juno-r2 - const: arm,juno-r2
- const: arm,juno - const: arm,juno
- const: arm,vexpress - const: arm,vexpress
- description: Arm AEMv8a Versatile Express Real-Time System Model - description: Arm AEMv8a (Architecture Envelope Model)
(VE RTSM) is a programmers view of the Versatile Express with Arm Versatile Express Real-Time System Model (VE RTSM)
is a programmers view of the Versatile Express with Arm
v8A hardware. See ARM DUI 0575D. v8A hardware. See ARM DUI 0575D.
items: items:
- const: arm,rtsm_ve,aemv8a - const: arm,rtsm_ve,aemv8a
@ -139,7 +140,7 @@ patternProperties:
the connection between the motherboard and any tiles. Sometimes the the connection between the motherboard and any tiles. Sometimes the
compatible is placed directly under this node, sometimes it is placed compatible is placed directly under this node, sometimes it is placed
in a subnode named "motherboard-bus". Sometimes the compatible includes in a subnode named "motherboard-bus". Sometimes the compatible includes
"arm,vexpress,v2?-p1" sometimes (on software models) is is just "arm,vexpress,v2?-p1" sometimes (on software models) it is just
"simple-bus". If the compatible is placed in the "motherboard-bus" node, "simple-bus". If the compatible is placed in the "motherboard-bus" node,
it is stricter and always has two compatibles. it is stricter and always has two compatibles.
type: object type: object

4
dts/upstream/Bindings/arm/aspeed/aspeed.yaml
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@ -46,6 +46,7 @@ properties:
- facebook,yamp-bmc - facebook,yamp-bmc
- facebook,yosemitev2-bmc - facebook,yosemitev2-bmc
- facebook,wedge400-bmc - facebook,wedge400-bmc
- facebook,wedge400-data64-bmc
- hxt,stardragon4800-rep2-bmc - hxt,stardragon4800-rep2-bmc
- ibm,mihawk-bmc - ibm,mihawk-bmc
- ibm,mowgli-bmc - ibm,mowgli-bmc
@ -81,9 +82,12 @@ properties:
- asus,x4tf-bmc - asus,x4tf-bmc
- facebook,bletchley-bmc - facebook,bletchley-bmc
- facebook,catalina-bmc - facebook,catalina-bmc
- facebook,clemente-bmc
- facebook,cloudripper-bmc - facebook,cloudripper-bmc
- facebook,darwin-bmc
- facebook,elbert-bmc - facebook,elbert-bmc
- facebook,fuji-bmc - facebook,fuji-bmc
- facebook,fuji-data64-bmc
- facebook,greatlakes-bmc - facebook,greatlakes-bmc
- facebook,harma-bmc - facebook,harma-bmc
- facebook,minerva-cmc - facebook,minerva-cmc

13
dts/upstream/Bindings/arm/axis.txt
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@ -1,13 +0,0 @@
Axis Communications AB
ARTPEC series SoC Device Tree Bindings
ARTPEC-6 ARM SoC
================
Required root node properties:
- compatible = "axis,artpec6";
ARTPEC-6 Development board:
---------------------------
Required root node properties:
- compatible = "axis,artpec6-dev-board", "axis,artpec6";

36
dts/upstream/Bindings/arm/axis.yaml Normal file
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@ -0,0 +1,36 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/axis.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Axis ARTPEC platforms
maintainers:
- Jesper Nilsson <jesper.nilsson@axis.com>
- Lars Persson <lars.persson@axis.com>
- linux-arm-kernel@axis.com
description: |
ARM platforms using SoCs designed by Axis branded as "ARTPEC".
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Axis ARTPEC-6 SoC board
items:
- enum:
- axis,artpec6-dev-board
- const: axis,artpec6
- description: Axis ARTPEC-8 SoC board
items:
- enum:
- axis,artpec8-grizzly
- const: axis,artpec8
additionalProperties: true
...

1
dts/upstream/Bindings/arm/bcm/brcm,bcm4708.yaml
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@ -25,6 +25,7 @@ properties:
- enum: - enum:
- asus,rt-ac56u - asus,rt-ac56u
- asus,rt-ac68u - asus,rt-ac68u
- buffalo,wxr-1750dhp
- buffalo,wzr-1166dhp - buffalo,wzr-1166dhp
- buffalo,wzr-1166dhp2 - buffalo,wzr-1166dhp2
- buffalo,wzr-1750dhp - buffalo,wzr-1750dhp

28
dts/upstream/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
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@ -103,6 +103,28 @@ properties:
- compatible - compatible
- "#pwm-cells" - "#pwm-cells"
touchscreen:
type: object
$ref: /schemas/input/touchscreen/touchscreen.yaml#
additionalProperties: false
properties:
compatible:
const: raspberrypi,firmware-ts
firmware:
deprecated: true
description: Phandle to RPi's firmware device node.
touchscreen-size-x: true
touchscreen-size-y: true
touchscreen-inverted-x: true
touchscreen-inverted-y: true
touchscreen-swapped-x-y: true
required:
- compatible
required: required:
- compatible - compatible
- mboxes - mboxes
@ -135,5 +157,11 @@ examples:
compatible = "raspberrypi,firmware-poe-pwm"; compatible = "raspberrypi,firmware-poe-pwm";
#pwm-cells = <2>; #pwm-cells = <2>;
}; };
ts: touchscreen {
compatible = "raspberrypi,firmware-ts";
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
};
}; };
... ...

19
dts/upstream/Bindings/arm/cavium,thunder-88xx.yaml Normal file
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@ -0,0 +1,19 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/cavium,thunder-88xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cavium Thunder 88xx SoC
maintainers:
- Robert Richter <rric@kernel.org>
properties:
$nodename:
const: '/'
compatible:
items:
- const: cavium,thunder-88xx
additionalProperties: true

10
dts/upstream/Bindings/arm/cavium-thunder.txt
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@ -1,10 +0,0 @@
Cavium Thunder platform device tree bindings
--------------------------------------------
Boards with Cavium's Thunder SoC shall have following properties.
Root Node
---------
Required root node properties:
- compatible = "cavium,thunder-88xx";

8
dts/upstream/Bindings/arm/cavium-thunder2.txt
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@ -1,8 +0,0 @@
Cavium ThunderX2 CN99XX platform tree bindings
----------------------------------------------
Boards with Cavium ThunderX2 CN99XX SoC shall have the root property:
compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
These SoC uses the "cavium,thunder2" core which will be compatible
with "brcm,vulcan".

43
dts/upstream/Bindings/arm/cpus.yaml
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@ -80,6 +80,8 @@ properties:
compatible: compatible:
enum: enum:
- apm,potenza
- apm,strega
- apple,avalanche - apple,avalanche
- apple,blizzard - apple,blizzard
- apple,cyclone - apple,cyclone
@ -121,6 +123,10 @@ properties:
- arm,arm1176jzf-s - arm,arm1176jzf-s
- arm,arm11mpcore - arm,arm11mpcore
- arm,armv8 # Only for s/w models - arm,armv8 # Only for s/w models
- arm,c1-nano
- arm,c1-premium
- arm,c1-pro
- arm,c1-ultra
- arm,cortex-a5 - arm,cortex-a5
- arm,cortex-a7 - arm,cortex-a7
- arm,cortex-a8 - arm,cortex-a8
@ -143,11 +149,14 @@ properties:
- arm,cortex-a78 - arm,cortex-a78
- arm,cortex-a78ae - arm,cortex-a78ae
- arm,cortex-a78c - arm,cortex-a78c
- arm,cortex-a320
- arm,cortex-a510 - arm,cortex-a510
- arm,cortex-a520 - arm,cortex-a520
- arm,cortex-a520ae
- arm,cortex-a710 - arm,cortex-a710
- arm,cortex-a715 - arm,cortex-a715
- arm,cortex-a720 - arm,cortex-a720
- arm,cortex-a720ae
- arm,cortex-a725 - arm,cortex-a725
- arm,cortex-m0 - arm,cortex-m0
- arm,cortex-m0+ - arm,cortex-m0+
@ -345,14 +354,37 @@ properties:
deprecated: true deprecated: true
description: Use 'cpu-supply' instead description: Use 'cpu-supply' instead
pu-supply:
deprecated: true
description: Only for i.MX6Q/DL/SL SoCs.
soc-supply:
deprecated: true
description: Only for i.MX6/7 Soc.
sram-supply: sram-supply:
deprecated: true deprecated: true
description: Use 'mem-supply' instead description: Use 'mem-supply' instead
fsl,soc-operating-points:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: FSL i.MX6 Soc operation-points when change cpu frequency
deprecated: true
items:
items:
- description: Frequency in kHz
- description: Voltage for OPP in uV
mediatek,cci: mediatek,cci:
$ref: /schemas/types.yaml#/definitions/phandle $ref: /schemas/types.yaml#/definitions/phandle
description: Link to Mediatek Cache Coherent Interconnect description: Link to Mediatek Cache Coherent Interconnect
edac-enabled:
$ref: /schemas/types.yaml#/definitions/flag
description:
A72 CPUs support Error Detection And Correction (EDAC) on their L1 and
L2 caches. This flag marks this function as usable.
qcom,saw: qcom,saw:
$ref: /schemas/types.yaml#/definitions/phandle $ref: /schemas/types.yaml#/definitions/phandle
description: description:
@ -399,6 +431,17 @@ properties:
allOf: allOf:
- $ref: /schemas/cpu.yaml# - $ref: /schemas/cpu.yaml#
- $ref: /schemas/opp/opp-v1.yaml# - $ref: /schemas/opp/opp-v1.yaml#
- if:
not:
properties:
compatible:
contains:
const: arm,cortex-a72
then:
# Allow edac-enabled only for Cortex A72
properties:
edac-enabled: false
- if: - if:
# If the enable-method property contains one of those values # If the enable-method property contains one of those values
properties: properties:

8
dts/upstream/Bindings/arm/freescale/fsl,imx7ulp-pm.yaml
View File

@ -28,6 +28,14 @@ properties:
reg: reg:
maxItems: 1 maxItems: 1
clocks:
maxItems: 2
clock-names:
items:
- const: divcore
- const: hsrun_divcore
required: required:
- compatible - compatible
- reg - reg

50
dts/upstream/Bindings/arm/fsl.yaml
View File

@ -1112,6 +1112,7 @@ properties:
- skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel - skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
- skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control with LED frontplate - skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control with LED frontplate
- skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate control with 7" panel - skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate control with 7" panel
- ultratronik,imx8mp-ultra-mach-sbc # Ultratronik SBC i.MX8MP based board
- ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board - ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board
- const: fsl,imx8mp - const: fsl,imx8mp
@ -1200,6 +1201,24 @@ properties:
- const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A - const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A
- const: fsl,imx8mp - const: fsl,imx8mp
- description: SolidRun i.MX8MP SoM based boards
items:
- enum:
- solidrun,imx8mp-cubox-m # SolidRun i.MX8MP SoM on CuBox-M
- solidrun,imx8mp-hummingboard-mate # SolidRun i.MX8MP SoM on HummingBoard Mate
- solidrun,imx8mp-hummingboard-pro # SolidRun i.MX8MP SoM on HummingBoard Pro
- solidrun,imx8mp-hummingboard-pulse # SolidRun i.MX8MP SoM on HummingBoard Pulse
- solidrun,imx8mp-hummingboard-ripple # SolidRun i.MX8MP SoM on HummingBoard Ripple
- const: solidrun,imx8mp-sr-som
- const: fsl,imx8mp
- description: TechNexion EDM-G-IMX8M-PLUS SoM based boards
items:
- enum:
- technexion,edm-g-imx8mp-wb # TechNexion EDM-G-IMX8MP SOM on WB-EDM-G
- const: technexion,edm-g-imx8mp # TechNexion EDM-G-IMX8MP SOM
- const: fsl,imx8mp
- description: Toradex Boards with SMARC iMX8M Plus Modules - description: Toradex Boards with SMARC iMX8M Plus Modules
items: items:
- const: toradex,smarc-imx8mp-dev # Toradex SMARC iMX8M Plus on Toradex SMARC Development Board - const: toradex,smarc-imx8mp-dev # Toradex SMARC iMX8M Plus on Toradex SMARC Development Board
@ -1382,9 +1401,16 @@ properties:
- description: i.MX8ULP based Boards - description: i.MX8ULP based Boards
items: items:
- enum: - enum:
- fsl,imx8ulp-9x9-evk # i.MX8ULP EVK9 Board
- fsl,imx8ulp-evk # i.MX8ULP EVK Board - fsl,imx8ulp-evk # i.MX8ULP EVK Board
- const: fsl,imx8ulp - const: fsl,imx8ulp
- description: i.MX91 based Boards
items:
- enum:
- fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board
- const: fsl,imx91
- description: i.MX93 based Boards - description: i.MX93 based Boards
items: items:
- enum: - enum:
@ -1425,6 +1451,24 @@ properties:
- fsl,imxrt1170-evk # i.MXRT1170 EVK Board - fsl,imxrt1170-evk # i.MXRT1170 EVK Board
- const: fsl,imxrt1170 - const: fsl,imxrt1170
- description:
TQMa91xxLA and TQMa91xxCA are two series of feature compatible SOM
using NXP i.MX91 SOC in 11x11 mm package.
TQMa91xxLA is designed to be soldered on different carrier boards.
TQMa91xxCA is a compatible variant using board to board connectors.
All SOM and CPU variants use the same device tree hence only one
compatible is needed. Bootloader disables all features not present
in the assembled SOC.
MBa91xxCA mainboard can be used as starterkit for the SOM
soldered on an adapter board or for the connector variant
MBa91xxLA mainboard is a single board computer using the solderable
SOM variant
items:
- enum:
- tq,imx91-tqma9131-mba91xxca # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM on MBa91xxCA
- const: tq,imx91-tqma9131 # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM
- const: fsl,imx91
- description: - description:
TQMa93xxLA and TQMa93xxCA are two series of feature compatible SOM TQMa93xxLA and TQMa93xxCA are two series of feature compatible SOM
using NXP i.MX93 SOC in 11x11 mm package. using NXP i.MX93 SOC in 11x11 mm package.
@ -1537,6 +1581,12 @@ properties:
- fsl,ls1012a-qds - fsl,ls1012a-qds
- const: fsl,ls1012a - const: fsl,ls1012a
- description: TQ Systems TQMLS12AL SoM on MBLS1012AL board
items:
- const: tq,ls1012a-tqmls1012al-mbls1012al
- const: tq,ls1012a-tqmls1012al
- const: fsl,ls1012a
- description: LS1021A based Boards - description: LS1021A based Boards
items: items:
- enum: - enum:

2
dts/upstream/Bindings/arm/intel-ixp4xx.yaml
View File

@ -16,6 +16,8 @@ properties:
oneOf: oneOf:
- items: - items:
- enum: - enum:
- actiontec,mi424wr-ac
- actiontec,mi424wr-d
- adieng,coyote - adieng,coyote
- arcom,vulcan - arcom,vulcan
- dlink,dsm-g600-a - dlink,dsm-g600-a

42
dts/upstream/Bindings/arm/keystone/keystone.txt
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@ -1,42 +0,0 @@
TI Keystone Platforms Device Tree Bindings
-----------------------------------------------
Boards with Keystone2 based devices (TCI66xxK2H) SOC shall have the
following properties.
Required properties:
- compatible: All TI specific devices present in Keystone SOC should be in
the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
type UART should use the specified compatible for those devices.
SoC families:
- Keystone 2 generic SoC:
compatible = "ti,keystone"
SoCs:
- Keystone 2 Hawking/Kepler
compatible = "ti,k2hk", "ti,keystone"
- Keystone 2 Lamarr
compatible = "ti,k2l", "ti,keystone"
- Keystone 2 Edison
compatible = "ti,k2e", "ti,keystone"
- K2G
compatible = "ti,k2g", "ti,keystone"
Boards:
- Keystone 2 Hawking/Kepler EVM
compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"
- Keystone 2 Lamarr EVM
compatible = "ti,k2l-evm", "ti, k2l", "ti,keystone"
- Keystone 2 Edison EVM
compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"
- K2G EVM
compatible = "ti,k2g-evm", "ti,k2g", "ti-keystone"
- K2G Industrial Communication Engine EVM
compatible = "ti,k2g-ice", "ti,k2g", "ti-keystone"

45
dts/upstream/Bindings/arm/marvell,berlin.yaml Normal file
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@ -0,0 +1,45 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/marvell,berlin.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synaptics/Marvell Berlin SoC
maintainers:
- Jisheng Zhang <jszhang@kernel.org>
description:
According to https://www.synaptics.com/company/news/conexant-marvell
Synaptics has acquired the Multimedia Solutions Business of Marvell, so
Berlin SoCs are now Synaptics' SoCs.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- sony,nsz-gs7
- const: marvell,berlin2
- const: marvell,berlin
- items:
- enum:
- google,chromecast
- valve,steamlink
- const: marvell,berlin2cd
- const: marvell,berlin
- items:
- enum:
- marvell,berlin2q-dmp
- const: marvell,berlin2q
- const: marvell,berlin
- items:
- enum:
- marvell,berlin4ct-dmp
- marvell,berlin4ct-stb
- const: marvell,berlin4ct
- const: marvell,berlin
additionalProperties: true

23
dts/upstream/Bindings/arm/marvell/98dx3236.txt
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@ -1,23 +0,0 @@
Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings
----------------------------------------------------------------------
Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families
shall have the following property:
Required root node property:
compatible: must contain "marvell,armadaxp-98dx3236"
In addition, boards using the Marvell 98DX3336 SoC shall have the
following property:
Required root node property:
compatible: must contain "marvell,armadaxp-98dx3336"
In addition, boards using the Marvell 98DX4251 SoC shall have the
following property:
Required root node property:
compatible: must contain "marvell,armadaxp-98dx4251"

39
dts/upstream/Bindings/arm/marvell/ap80x-system-controller.txt
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@ -115,45 +115,6 @@ ap_syscon: system-controller@6f4000 {
SYSTEM CONTROLLER 1 SYSTEM CONTROLLER 1
=================== ===================
Thermal:
--------
For common binding part and usage, refer to
Documentation/devicetree/bindings/thermal/thermal*.yaml
The thermal IP can probe the temperature all around the processor. It
may feature several channels, each of them wired to one sensor.
It is possible to setup an overheat interrupt by giving at least one
critical point to any subnode of the thermal-zone node.
Required properties:
- compatible: must be one of:
* marvell,armada-ap806-thermal
- reg: register range associated with the thermal functions.
Optional properties:
- interrupts: overheat interrupt handle. Should point to line 18 of the
SEI irqchip. See interrupt-controller/interrupts.txt
- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
to this IP and represents the channel ID. There is one sensor per
channel. O refers to the thermal IP internal channel, while positive
IDs refer to each CPU.
Example:
ap_syscon1: system-controller@6f8000 {
compatible = "syscon", "simple-mfd";
reg = <0x6f8000 0x1000>;
ap_thermal: thermal-sensor@80 {
compatible = "marvell,armada-ap806-thermal";
reg = <0x80 0x10>;
interrupt-parent = <&sei>;
interrupts = <18>;
#thermal-sensor-cells = <1>;
};
};
Cluster clocks: Cluster clocks:
--------------- ---------------

24
dts/upstream/Bindings/arm/marvell/armada-370-xp.txt
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@ -1,24 +0,0 @@
Marvell Armada 370 and Armada XP Platforms Device Tree Bindings
---------------------------------------------------------------
Boards with a SoC of the Marvell Armada 370 and Armada XP families
shall have the following property:
Required root node property:
compatible: must contain "marvell,armada-370-xp"
In addition, boards using the Marvell Armada 370 SoC shall have the
following property:
Required root node property:
compatible: must contain "marvell,armada370"
In addition, boards using the Marvell Armada XP SoC shall have the
following property:
Required root node property:
compatible: must contain "marvell,armadaxp"

9
dts/upstream/Bindings/arm/marvell/armada-375.txt
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@ -1,9 +0,0 @@
Marvell Armada 375 Platforms Device Tree Bindings
-------------------------------------------------
Boards with a SoC of the Marvell Armada 375 family shall have the
following property:
Required root node property:
compatible: must contain "marvell,armada375"

1
dts/upstream/Bindings/arm/marvell/armada-37xx.yaml
View File

@ -23,6 +23,7 @@ properties:
- marvell,armada-3720-db - marvell,armada-3720-db
- methode,edpu - methode,edpu
- methode,udpu - methode,udpu
- ripe,atlas-v5
- const: marvell,armada3720 - const: marvell,armada3720
- const: marvell,armada3710 - const: marvell,armada3710

31
dts/upstream/Bindings/arm/marvell/armada-39x.txt
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@ -1,31 +0,0 @@
Marvell Armada 39x Platforms Device Tree Bindings
-------------------------------------------------
Boards with a SoC of the Marvell Armada 39x family shall have the
following property:
Required root node property:
- compatible: must contain "marvell,armada390"
In addition, boards using the Marvell Armada 395 SoC shall have the
following property before the common "marvell,armada390" one:
Required root node property:
compatible: must contain "marvell,armada395"
Example:
compatible = "marvell,a395-gp", "marvell,armada395", "marvell,armada390";
Boards using the Marvell Armada 398 SoC shall have the following
property before the common "marvell,armada390" one:
Required root node property:
compatible: must contain "marvell,armada398"
Example:
compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";

43
dts/upstream/Bindings/arm/marvell/cp110-system-controller.txt
View File

@ -189,46 +189,3 @@ CP110_LABEL(syscon0): system-controller@440000 {
}; };
}; };
SYSTEM CONTROLLER 1
===================
Thermal:
--------
The thermal IP can probe the temperature all around the processor. It
may feature several channels, each of them wired to one sensor.
It is possible to setup an overheat interrupt by giving at least one
critical point to any subnode of the thermal-zone node.
For common binding part and usage, refer to
Documentation/devicetree/bindings/thermal/thermal*.yaml
Required properties:
- compatible: must be one of:
* marvell,armada-cp110-thermal
- reg: register range associated with the thermal functions.
Optional properties:
- interrupts-extended: overheat interrupt handle. Should point to
a line of the ICU-SEI irqchip (116 is what is usually used by the
firmware). The ICU-SEI will redirect towards interrupt line #37 of the
AP SEI which is shared across all CPs.
See interrupt-controller/interrupts.txt
- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
to this IP and represents the channel ID. There is one sensor per
channel. O refers to the thermal IP internal channel.
Example:
CP110_LABEL(syscon1): system-controller@6f8000 {
compatible = "syscon", "simple-mfd";
reg = <0x6f8000 0x1000>;
CP110_LABEL(thermal): thermal-sensor@70 {
compatible = "marvell,armada-cp110-thermal";
reg = <0x70 0x10>;
interrupts-extended = <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <1>;
};
};

27
dts/upstream/Bindings/arm/marvell/kirkwood.txt
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@ -1,27 +0,0 @@
Marvell Kirkwood Platforms Device Tree Bindings
-----------------------------------------------
Boards with a SoC of the Marvell Kirkwood
shall have the following property:
Required root node property:
compatible: must contain "marvell,kirkwood";
In order to support the kirkwood cpufreq driver, there must be a node
cpus/cpu@0 with three clocks, "cpu_clk", "ddrclk" and "powersave",
where the "powersave" clock is a gating clock used to switch the CPU
between the "cpu_clk" and the "ddrclk".
Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "marvell,sheeva-88SV131";
clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
clock-names = "cpu_clk", "ddrclk", "powersave";
};

78
dts/upstream/Bindings/arm/marvell/marvell,armada-370-xp.yaml Normal file
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@ -0,0 +1,78 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
---
$id: http://devicetree.org/schemas/arm/marvell/marvell,armada-370-xp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 370 and Armada XP platforms
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- ctera,c200-v2
- dlink,dns327l
- globalscale,mirabox
- netgear,readynas-102
- netgear,readynas-104
- marvell,a370-db
- marvell,a370-rd
- seagate,dart-2
- seagate,dart-4
- seagate,cumulus-max
- seagate,cumulus
- synology,ds213j
- const: marvell,armada370
- const: marvell,armada-370-xp
- items:
- enum:
- mikrotik,crs305-1g-4s
- mikrotik,crs326-24g-2s
- mikrotik,crs328-4c-20s-4s
- const: marvell,armadaxp-98dx3236
- const: marvell,armada-370-xp
- items:
- const: marvell,db-xc3-24g4xg
- const: marvell,armadaxp-98dx3336
- const: marvell,armada-370-xp
- items:
- const: marvell,db-dxbc2
- const: marvell,armadaxp-98dx4251
- const: marvell,armada-370-xp
- items:
- enum:
- lenovo,ix4-300d
- linksys,mamba
- marvell,rd-axpwifiap
- netgear,readynas-2120
- synology,ds414
- const: marvell,armadaxp-mv78230
- const: marvell,armadaxp
- const: marvell,armada-370-xp
- items:
- const: plathome,openblocks-ax3-4
- const: marvell,armadaxp-mv78260
- const: marvell,armadaxp
- const: marvell,armada-370-xp
- items:
- enum:
- marvell,axp-db
- marvell,axp-gp
- marvell,axp-matrix
- const: marvell,armadaxp-mv78460
- const: marvell,armadaxp
- const: marvell,armada-370-xp
additionalProperties: true

21
dts/upstream/Bindings/arm/marvell/marvell,armada375.yaml Normal file
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@ -0,0 +1,21 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/marvell/marvell,armada375.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 375 Platform
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
$nodename:
const: '/'
compatible:
items:
- const: marvell,a375-db
- const: marvell,armada375
additionalProperties: true

32
dts/upstream/Bindings/arm/marvell/marvell,armada390.yaml Normal file
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@ -0,0 +1,32 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/marvell/marvell,armada390.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 39x Platforms
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- const: marvell,a390-db
- const: marvell,armada390
- items:
- enum:
- marvell,a398-db
- const: marvell,armada398
- const: marvell,armada390
- items:
- enum:
- marvell,a395-gp
- const: marvell,armada395
- const: marvell,armada390
additionalProperties: true

7
dts/upstream/Bindings/arm/marvell/marvell,dove.txt
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@ -1,7 +0,0 @@
Marvell Dove Platforms Device Tree Bindings
-----------------------------------------------
Boards with a Marvell Dove SoC shall have the following properties:
Required root node property:
- compatible: must contain "marvell,dove";

35
dts/upstream/Bindings/arm/marvell/marvell,dove.yaml Normal file
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@ -0,0 +1,35 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/marvell/marvell,dove.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Dove SoC
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- compulab,cm-a510
- solidrun,cubox
- globalscale,d2plug
- globalscale,d3plug
- marvell,dove-db
- const: marvell,dove
- items:
- const: solidrun,cubox-es
- const: solidrun,cubox
- const: marvell,dove
- items:
- const: compulab,sbc-a510
- const: compulab,cm-a510
- const: marvell,dove
additionalProperties: true

105
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@ -1,105 +0,0 @@
Marvell Kirkwood SoC Family Device Tree Bindings
------------------------------------------------
Boards with a SoC of the Marvell Kirkwook family, eg 88f6281
* Required root node properties:
compatible: must contain "marvell,kirkwood"
In addition, the above compatible shall be extended with the specific
SoC. Currently known SoC compatibles are:
"marvell,kirkwood-88f6192"
"marvell,kirkwood-88f6281"
"marvell,kirkwood-88f6282"
"marvell,kirkwood-88f6283"
"marvell,kirkwood-88f6702"
"marvell,kirkwood-98DX4122"
And in addition, the compatible shall be extended with the specific
board. Currently known boards are:
"buffalo,linkstation-lsqvl"
"buffalo,linkstation-lsvl"
"buffalo,linkstation-lswsxl"
"buffalo,linkstation-lswxl"
"buffalo,linkstation-lswvl"
"buffalo,lschlv2"
"buffalo,lsxhl"
"buffalo,lsxl"
"cloudengines,pogo02"
"cloudengines,pogoplugv4"
"dlink,dns-320"
"dlink,dns-320-a1"
"dlink,dns-325"
"dlink,dns-325-a1"
"dlink,dns-kirkwood"
"excito,b3"
"globalscale,dreamplug-003-ds2001"
"globalscale,guruplug"
"globalscale,guruplug-server-plus"
"globalscale,sheevaplug"
"globalscale,sheevaplug"
"globalscale,sheevaplug-esata"
"globalscale,sheevaplug-esata-rev13"
"iom,iconnect"
"iom,iconnect-1.1"
"iom,ix2-200"
"keymile,km_kirkwood"
"lacie,cloudbox"
"lacie,inetspace_v2"
"lacie,laplug"
"lacie,nas2big"
"lacie,netspace_lite_v2"
"lacie,netspace_max_v2"
"lacie,netspace_mini_v2"
"lacie,netspace_v2"
"marvell,db-88f6281-bp"
"marvell,db-88f6282-bp"
"marvell,mv88f6281gtw-ge"
"marvell,rd88f6281"
"marvell,rd88f6281"
"marvell,rd88f6281-a0"
"marvell,rd88f6281-a1"
"mpl,cec4"
"mpl,cec4-10"
"netgear,readynas"
"netgear,readynas"
"netgear,readynas-duo-v2"
"netgear,readynas-nv+-v2"
"plathome,openblocks-a6"
"plathome,openblocks-a7"
"raidsonic,ib-nas6210"
"raidsonic,ib-nas6210-b"
"raidsonic,ib-nas6220"
"raidsonic,ib-nas6220-b"
"raidsonic,ib-nas62x0"
"seagate,dockstar"
"seagate,goflexnet"
"synology,ds109"
"synology,ds110jv10"
"synology,ds110jv20"
"synology,ds110jv30"
"synology,ds111"
"synology,ds209"
"synology,ds210jv10"
"synology,ds210jv20"
"synology,ds212"
"synology,ds212jv10"
"synology,ds212jv20"
"synology,ds212pv10"
"synology,ds409"
"synology,ds409slim"
"synology,ds410j"
"synology,ds411"
"synology,ds411j"
"synology,ds411slim"
"synology,ds413jv10"
"synology,rs212"
"synology,rs409"
"synology,rs411"
"synology,rs812"
"usi,topkick"
"usi,topkick-1281P2"
"zyxel,nsa310"
"zyxel,nsa310a"

266
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@ -0,0 +1,266 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/marvell/marvell,kirkwood.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Kirkwood SoC Family
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- qnap,ts219
- qnap,ts419
- synology,ds110
- synology,ds111
- synology,ds209
- synology,ds409slim
- synology,ds411j
- synology,ds411slim
- synology,rs212
- synology,rs409
- const: marvell,kirkwood
- items:
- const: synology,ds109
- const: synology,ds110jv20
- const: synology,ds110
- const: marvell,kirkwood
- items:
- const: synology,ds110jv10
- const: synology,ds110jv30
- const: marvell,kirkwood
- items:
- const: synology,ds210jv10
- const: synology,ds210jv20
- const: synology,ds210jv30
- const: synology,ds211j
- const: marvell,kirkwood
- items:
- const: synology,ds212jv10
- const: synology,ds212jv20
- const: marvell,kirkwood
- items:
- const: synology,ds212
- const: synology,ds212pv10
- const: synology,ds212pv10
- const: synology,ds212pv20
- const: synology,ds213airv10
- const: synology,ds213v10
- const: marvell,kirkwood
- items:
- const: synology,ds409
- const: synology,ds410j
- const: marvell,kirkwood
- items:
- const: synology,ds411
- const: synology,ds413jv10
- const: marvell,kirkwood
- items:
- const: synology,rs411
- const: synology,rs812
- const: marvell,kirkwood
- items:
- enum:
- cloudengines,pogoplugv4
- lacie,laplug
- lacie,netspace_lite_v2
- lacie,netspace_mini_v2
- marvell,rd88f6192
- seagate,blackarmor-nas220
- enum:
- marvell,kirkwood-88f6192
- const: marvell,kirkwood
- items:
- enum:
- buffalo,lswsxl
- buffalo,lswxl
- checkpoint,l-50
- cloudengines,pogoe02
- ctera,c200-v1
- dlink,dir-665
- endian,4i-edge-200
- excito,b3
- globalscale,sheevaplug
- hp,t5325
- iom,ix2-200
- lacie,inetspace_v2
- lacie,netspace_v2
- lacie,netspace_max_v2
- marvell,db-88f6281-bp
- marvell,mv88f6281gtw-ge
- seagate,dockstar
- seagate,goflexnet
- zyxel,nsa310
- zyxel,nsa320
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- enum:
- buffalo,lschlv2
- buffalo,lsxhl
- const: buffalo,lsxl
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- const: dlink,dns-320-a1
- const: dlink,dns-320
- const: dlink,dns-kirkwood
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- const: dlink,dns-325-a1
- const: dlink,dns-325
- const: dlink,dns-kirkwood
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- const: globalscale,dreamplug-003-ds2001
- const: globalscale,dreamplug
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- const: globalscale,guruplug-server-plus
- const: globalscale,guruplug
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- const: globalscale,sheevaplug-esata-rev13
- const: globalscale,sheevaplug-esata
- const: globalscale,sheevaplug
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- const: iom,iconnect-1.1
- const: iom,iconnect
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- const: lacie,d2net_v2
- const: lacie,netxbig
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- enum:
- lacie,net2big_v2
- lacie,net5big_v2
- const: lacie,netxbig
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- enum:
- marvell,openrd-base
- marvell,openrd-client
- marvell,openrd-ultimate
- const: marvell,openrd
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- enum:
- marvell,rd88f6281-a
- marvell,rd88f6281-z0
- const: marvell,rd88f6281
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- const: mpl,cec4-10
- const: mpl,cec4
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- const: raidsonic,ib-nas6210-b
- const: raidsonic,ib-nas6220-b
- const: raidsonic,ib-nas6210
- const: raidsonic,ib-nas6220
- const: raidsonic,ib-nas62x0
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- const: zyxel,nsa310a
- const: zyxel,nsa310
- const: marvell,kirkwood-88f6281
- const: marvell,kirkwood
- items:
- enum:
- buffalo,lsqvl
- buffalo,lsvl
- buffalo,lswvl
- linksys,viper
- marvell,db-88f6282-bp
- zyxel,nsa325
- const: marvell,kirkwood-88f6282
- const: marvell,kirkwood
- items:
- const: lacie,nas2big
- const: lacie,netxbig
- const: marvell,kirkwood-88f6282
- const: marvell,kirkwood
- items:
- enum:
- netgear,readynas-duo-v2
- netgear,readynas-nv+-v2
- const: netgear,readynas
- const: marvell,kirkwood-88f6282
- const: marvell,kirkwood
- items:
- const: usi,topkick-1281P2
- const: usi,topkick
- const: marvell,kirkwood-88f6282
- const: marvell,kirkwood
- items:
- enum:
- plathome,openblocks-a6
- plathome,openblocks-a7
- const: marvell,kirkwood-88f6283
- const: marvell,kirkwood
- items:
- enum:
- lacie,cloudbox
- zyxel,nsa310s
- const: marvell,kirkwood-88f6702
- const: marvell,kirkwood
- items:
- enum:
- keymile,km_fixedeth
- keymile,km_kirkwood
- const: marvell,kirkwood-98DX4122
- const: marvell,kirkwood
additionalProperties: true

25
dts/upstream/Bindings/arm/marvell/marvell,orion5x.txt
View File

@ -1,25 +0,0 @@
Marvell Orion SoC Family Device Tree Bindings
---------------------------------------------
Boards with a SoC of the Marvell Orion family, eg 88f5181
* Required root node properties:
compatible: must contain "marvell,orion5x"
In addition, the above compatible shall be extended with the specific
SoC. Currently known SoC compatibles are:
"marvell,orion5x-88f5181"
"marvell,orion5x-88f5182"
And in addition, the compatible shall be extended with the specific
board. Currently known boards are:
"buffalo,lsgl"
"buffalo,lswsgl"
"buffalo,lswtgl"
"lacie,ethernet-disk-mini-v2"
"lacie,d2-network"
"marvell,rd-88f5182-nas"
"maxtor,shared-storage-2"
"netgear,wnr854t"

37
dts/upstream/Bindings/arm/marvell/marvell,orion5x.yaml Normal file
View File

@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/marvell/marvell,orion5x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Orion5x SoC Family
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- netgear,wnr854t
- const: marvell,orion5x-88f5181
- const: marvell,orion5x
- items:
- enum:
- buffalo,kurobox-pro
- buffalo,lschl
- buffalo,lsgl
- buffalo,lswsgl
- buffalo,lswtgl
- lacie,ethernet-disk-mini-v2
- lacie,d2-network
- marvell,rd-88f5182-nas
- maxtor,shared-storage-2
- const: marvell,orion5x-88f5182
- const: marvell,orion5x
additionalProperties: true

2
dts/upstream/Bindings/arm/mediatek.yaml
View File

@ -431,11 +431,13 @@ properties:
- const: mediatek,mt8365 - const: mediatek,mt8365
- items: - items:
- enum: - enum:
- grinn,genio-510-sbc
- mediatek,mt8370-evk - mediatek,mt8370-evk
- const: mediatek,mt8370 - const: mediatek,mt8370
- const: mediatek,mt8188 - const: mediatek,mt8188
- items: - items:
- enum: - enum:
- grinn,genio-700-sbc
- mediatek,mt8390-evk - mediatek,mt8390-evk
- const: mediatek,mt8390 - const: mediatek,mt8390
- const: mediatek,mt8188 - const: mediatek,mt8188

16
dts/upstream/Bindings/arm/mediatek/mediatek,audsys.yaml
View File

@ -23,6 +23,7 @@ properties:
- mediatek,mt7622-audsys - mediatek,mt7622-audsys
- mediatek,mt8167-audsys - mediatek,mt8167-audsys
- mediatek,mt8173-audsys - mediatek,mt8173-audsys
- mediatek,mt8183-audiosys
- mediatek,mt8183-audsys - mediatek,mt8183-audsys
- mediatek,mt8186-audsys - mediatek,mt8186-audsys
- mediatek,mt8192-audsys - mediatek,mt8192-audsys
@ -41,13 +42,26 @@ properties:
const: 1 const: 1
audio-controller: audio-controller:
$ref: /schemas/sound/mediatek,mt2701-audio.yaml#
type: object type: object
required: required:
- compatible - compatible
- '#clock-cells' - '#clock-cells'
if:
properties:
compatible:
contains:
const: mediatek,mt8183-audiosys
then:
properties:
audio-controller:
$ref: /schemas/sound/mediatek,mt8183-audio.yaml#
else:
properties:
audio-controller:
$ref: /schemas/sound/mediatek,mt2701-audio.yaml#
additionalProperties: false additionalProperties: false
examples: examples:

2
dts/upstream/Bindings/arm/nxp/lpc32xx.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC32xx Platforms title: NXP LPC32xx Platforms
maintainers: maintainers:
- Roland Stigge <stigge@antcom.de> - Vladimir Zapolskiy <vz@mleia.com>
properties: properties:
compatible: compatible:

7
dts/upstream/Bindings/arm/pmu.yaml
View File

@ -28,6 +28,10 @@ properties:
- arm,arm1136-pmu - arm,arm1136-pmu
- arm,arm1176-pmu - arm,arm1176-pmu
- arm,arm11mpcore-pmu - arm,arm11mpcore-pmu
- arm,c1-nano-pmu
- arm,c1-premium-pmu
- arm,c1-pro-pmu
- arm,c1-ultra-pmu
- arm,cortex-a5-pmu - arm,cortex-a5-pmu
- arm,cortex-a7-pmu - arm,cortex-a7-pmu
- arm,cortex-a8-pmu - arm,cortex-a8-pmu
@ -48,11 +52,14 @@ properties:
- arm,cortex-a76-pmu - arm,cortex-a76-pmu
- arm,cortex-a77-pmu - arm,cortex-a77-pmu
- arm,cortex-a78-pmu - arm,cortex-a78-pmu
- arm,cortex-a320-pmu
- arm,cortex-a510-pmu - arm,cortex-a510-pmu
- arm,cortex-a520-pmu - arm,cortex-a520-pmu
- arm,cortex-a520ae-pmu
- arm,cortex-a710-pmu - arm,cortex-a710-pmu
- arm,cortex-a715-pmu - arm,cortex-a715-pmu
- arm,cortex-a720-pmu - arm,cortex-a720-pmu
- arm,cortex-a720ae-pmu
- arm,cortex-a725-pmu - arm,cortex-a725-pmu
- arm,cortex-x1-pmu - arm,cortex-x1-pmu
- arm,cortex-x2-pmu - arm,cortex-x2-pmu

4
dts/upstream/Bindings/arm/qcom,coresight-ctcu.yaml
View File

@ -39,6 +39,10 @@ properties:
items: items:
- const: apb - const: apb
label:
description:
Description of a coresight device.
in-ports: in-ports:
$ref: /schemas/graph.yaml#/properties/ports $ref: /schemas/graph.yaml#/properties/ports

4
dts/upstream/Bindings/arm/qcom,coresight-remote-etm.yaml
View File

@ -20,6 +20,10 @@ properties:
compatible: compatible:
const: qcom,coresight-remote-etm const: qcom,coresight-remote-etm
label:
description:
Description of a coresight device.
out-ports: out-ports:
$ref: /schemas/graph.yaml#/properties/ports $ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false additionalProperties: false

113
dts/upstream/Bindings/arm/qcom,coresight-tnoc.yaml Normal file
View File

@ -0,0 +1,113 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/qcom,coresight-tnoc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Trace Network On Chip - TNOC
maintainers:
- Yuanfang Zhang <quic_yuanfang@quicinc.com>
description: >
The Trace Network On Chip (TNOC) is an integration hierarchy hardware
component that integrates the functionalities of TPDA and funnels.
It sits in the different subsystem of SOC and aggregates the trace and
transports it to Aggregation TNOC or to coresight trace sink eventually.
TNOC embeds bridges for all the interfaces APB, ATB, TPDA and NTS (Narrow
Time Stamp).
TNOC can take inputs from different trace sources i.e. ATB, TPDM.
Note this binding is specifically intended for Aggregator TNOC instances.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
enum:
- qcom,coresight-tnoc
required:
- compatible
properties:
$nodename:
pattern: "^tn(@[0-9a-f]+)$"
compatible:
items:
- const: qcom,coresight-tnoc
- const: arm,primecell
reg:
maxItems: 1
clock-names:
items:
- const: apb_pclk
clocks:
items:
- description: APB register access clock
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port(@[0-9a-f]{1,2})?$':
description: Input connections from CoreSight Trace Bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description:
Output connection to CoreSight Trace Bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
- out-ports
additionalProperties: false
examples:
- |
tn@109ab000 {
compatible = "qcom,coresight-tnoc", "arm,primecell";
reg = <0x109ab000 0x4200>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tn_ag_in_tpdm_gcc: endpoint {
remote-endpoint = <&tpdm_gcc_out_tn_ag>;
};
};
};
out-ports {
port {
tn_ag_out_funnel_in1: endpoint {
remote-endpoint = <&funnel_in1_in_tn_ag>;
};
};
};
};
...

4
dts/upstream/Bindings/arm/qcom,coresight-tpda.yaml
View File

@ -64,6 +64,10 @@ properties:
items: items:
- const: apb_pclk - const: apb_pclk
label:
description:
Description of a coresight device.
in-ports: in-ports:
description: | description: |
Input connections from TPDM to TPDA Input connections from TPDM to TPDA

4
dts/upstream/Bindings/arm/qcom,coresight-tpdm.yaml
View File

@ -76,6 +76,10 @@ properties:
minimum: 0 minimum: 0
maximum: 32 maximum: 32
label:
description:
Description of a coresight device.
clocks: clocks:
maxItems: 1 maxItems: 1

5
dts/upstream/Bindings/arm/qcom-soc.yaml
View File

@ -23,7 +23,9 @@ description: |
select: select:
properties: properties:
compatible: compatible:
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" oneOf:
- pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
- pattern: "^qcom,.*(glymur|milos).*$"
required: required:
- compatible - compatible
@ -34,6 +36,7 @@ properties:
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$" - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$"
- pattern: "^qcom,sar[0-9]+[a-z]?-.*$" - pattern: "^qcom,sar[0-9]+[a-z]?-.*$"
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
- pattern: "^qcom,(glymur|milos)-.*$"
# Legacy namings - variations of existing patterns/compatibles are OK, # Legacy namings - variations of existing patterns/compatibles are OK,
# but do not add completely new entries to these: # but do not add completely new entries to these:

121
dts/upstream/Bindings/arm/qcom.yaml
View File

@ -10,100 +10,6 @@ maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org> - Bjorn Andersson <bjorn.andersson@linaro.org>
description: | description: |
For devices using the Qualcomm SoC the "compatible" properties consists of
one or several "manufacturer,model" strings, describing the device itself,
followed by one or several "qcom,<SoC>" strings, describing the SoC used in
the device.
The 'SoC' element must be one of the following strings:
apq8016
apq8026
apq8064
apq8074
apq8084
apq8094
apq8096
ipq4018
ipq4019
ipq5018
ipq5332
ipq5424
ipq6018
ipq8064
ipq8074
ipq9574
mdm9615
msm8226
msm8660
msm8916
msm8917
msm8926
msm8929
msm8939
msm8953
msm8956
msm8960
msm8974
msm8974pro
msm8976
msm8992
msm8994
msm8996
msm8996pro
msm8998
qcs404
qcs615
qcs8300
qcs8550
qcm2290
qcm6490
qcs9100
qdu1000
qrb2210
qrb4210
qru1000
sa8155p
sa8540p
sa8775p
sar2130p
sc7180
sc7280
sc8180x
sc8280xp
sda660
sdm450
sdm630
sdm632
sdm636
sdm660
sdm670
sdm845
sdx55
sdx65
sdx75
sm4250
sm4450
sm6115
sm6115p
sm6125
sm6350
sm6375
sm7125
sm7150
sm7225
sm7325
sm8150
sm8250
sm8350
sm8450
sm8550
sm8650
sm8750
x1e78100
x1e80100
x1p42100
There are many devices in the list below that run the standard ChromeOS There are many devices in the list below that run the standard ChromeOS
bootloader setup and use the open source depthcharge bootloader to boot the bootloader setup and use the open source depthcharge bootloader to boot the
OS. These devices use the bootflow explained at OS. These devices use the bootflow explained at
@ -203,6 +109,12 @@ properties:
- samsung,expressatt - samsung,expressatt
- const: qcom,msm8960 - const: qcom,msm8960
- items:
- enum:
- sony,huashan
- const: qcom,msm8960t
- const: qcom,msm8960
- items: - items:
- enum: - enum:
- lge,hammerhead - lge,hammerhead
@ -281,6 +193,7 @@ properties:
- items: - items:
- enum: - enum:
- flipkart,rimob
- motorola,potter - motorola,potter
- xiaomi,daisy - xiaomi,daisy
- xiaomi,mido - xiaomi,mido
@ -424,6 +337,7 @@ properties:
- items: - items:
- enum: - enum:
- fairphone,fp5 - fairphone,fp5
- particle,tachyon
- qcom,qcm6490-idp - qcom,qcm6490-idp
- qcom,qcs6490-rb3gen2 - qcom,qcs6490-rb3gen2
- shift,otter - shift,otter
@ -942,6 +856,7 @@ properties:
- items: - items:
- enum: - enum:
- qcom,monaco-evk
- qcom,qcs8300-ride - qcom,qcs8300-ride
- const: qcom,qcs8300 - const: qcom,qcs8300
@ -949,6 +864,7 @@ properties:
- enum: - enum:
- qcom,qcs615-ride - qcom,qcs615-ride
- const: qcom,qcs615 - const: qcom,qcs615
- const: qcom,sm6150
- items: - items:
- enum: - enum:
@ -969,6 +885,7 @@ properties:
- items: - items:
- enum: - enum:
- qcom,lemans-evk
- qcom,qcs9100-ride - qcom,qcs9100-ride
- qcom,qcs9100-ride-r3 - qcom,qcs9100-ride-r3
- const: qcom,qcs9100 - const: qcom,qcs9100
@ -976,9 +893,6 @@ properties:
- items: - items:
- enum: - enum:
- google,cheza
- google,cheza-rev1
- google,cheza-rev2
- lenovo,yoga-c630 - lenovo,yoga-c630
- lg,judyln - lg,judyln
- lg,judyp - lg,judyp
@ -1076,6 +990,8 @@ properties:
- qcom,qrb5165-rb5 - qcom,qrb5165-rb5
- qcom,sm8250-hdk - qcom,sm8250-hdk
- qcom,sm8250-mtp - qcom,sm8250-mtp
- samsung,r8q
- samsung,x1q
- sony,pdx203-generic - sony,pdx203-generic
- sony,pdx206-generic - sony,pdx206-generic
- xiaomi,elish - xiaomi,elish
@ -1095,6 +1011,7 @@ properties:
- enum: - enum:
- qcom,sm8450-hdk - qcom,sm8450-hdk
- qcom,sm8450-qrd - qcom,sm8450-qrd
- samsung,r0q
- sony,pdx223 - sony,pdx223
- sony,pdx224 - sony,pdx224
- const: qcom,sm8450 - const: qcom,sm8450
@ -1146,6 +1063,8 @@ properties:
- enum: - enum:
- asus,vivobook-s15 - asus,vivobook-s15
- asus,zenbook-a14-ux3407ra - asus,zenbook-a14-ux3407ra
- dell,inspiron-14-plus-7441
- dell,latitude-7455
- dell,xps13-9345 - dell,xps13-9345
- hp,elitebook-ultra-g1q - hp,elitebook-ultra-g1q
- hp,omnibook-x14 - hp,omnibook-x14
@ -1156,9 +1075,17 @@ properties:
- qcom,x1e80100-qcp - qcom,x1e80100-qcp
- const: qcom,x1e80100 - const: qcom,x1e80100
- items:
- enum:
- qcom,hamoa-iot-evk
- const: qcom,hamoa-iot-som
- const: qcom,x1e80100
- items: - items:
- enum: - enum:
- asus,zenbook-a14-ux3407qa - asus,zenbook-a14-ux3407qa
- hp,omnibook-x14-fe1
- lenovo,thinkbook-16
- qcom,x1p42100-crd - qcom,x1p42100-crd
- const: qcom,x1p42100 - const: qcom,x1p42100

29
dts/upstream/Bindings/arm/rockchip.yaml
View File

@ -54,6 +54,11 @@ properties:
- const: ariaboard,photonicat - const: ariaboard,photonicat
- const: rockchip,rk3568 - const: rockchip,rk3568
- description: ArmSoM Sige1 board
items:
- const: armsom,sige1
- const: rockchip,rk3528
- description: ArmSoM Sige5 board - description: ArmSoM Sige5 board
items: items:
- const: armsom,sige5 - const: armsom,sige5
@ -253,6 +258,11 @@ properties:
- const: firefly,roc-rk3576-pc - const: firefly,roc-rk3576-pc
- const: rockchip,rk3576 - const: rockchip,rk3576
- description: Firefly ROC-RK3588-RT
items:
- const: firefly,roc-rk3588-rt
- const: rockchip,rk3588
- description: Firefly Station M2 - description: Firefly Station M2
items: items:
- const: firefly,rk3566-roc-pc - const: firefly,rk3566-roc-pc
@ -320,6 +330,11 @@ properties:
- friendlyarm,nanopi-r6s - friendlyarm,nanopi-r6s
- const: rockchip,rk3588s - const: rockchip,rk3588s
- description: FriendlyElec NanoPi Zero2
items:
- const: friendlyarm,nanopi-zero2
- const: rockchip,rk3528
- description: FriendlyElec NanoPC T6 series boards - description: FriendlyElec NanoPC T6 series boards
items: items:
- enum: - enum:
@ -683,6 +698,13 @@ properties:
- const: hardkernel,odroid-m2 - const: hardkernel,odroid-m2
- const: rockchip,rk3588s - const: rockchip,rk3588s
- description: HINLINK H66K / H68K
items:
- enum:
- hinlink,h66k
- hinlink,h68k
- const: rockchip,rk3568
- description: Hugsun X99 TV Box - description: Hugsun X99 TV Box
items: items:
- const: hugsun,x99 - const: hugsun,x99
@ -881,6 +903,13 @@ properties:
- const: radxa,rock - const: radxa,rock
- const: rockchip,rk3188 - const: rockchip,rk3188
- description: Radxa ROCK 2A/2F
items:
- enum:
- radxa,rock-2a
- radxa,rock-2f
- const: rockchip,rk3528
- description: Radxa ROCK Pi 4A/A+/B/B+/C - description: Radxa ROCK Pi 4A/A+/B/B+/C
items: items:
- enum: - enum:

6
dts/upstream/Bindings/arm/samsung/samsung-boards.yaml
View File

@ -14,12 +14,6 @@ properties:
const: '/' const: '/'
compatible: compatible:
oneOf: oneOf:
- description: S3C2416 based boards
items:
- enum:
- samsung,smdk2416 # Samsung SMDK2416
- const: samsung,s3c2416
- description: S3C6410 based boards - description: S3C6410 based boards
items: items:
- enum: - enum:

4
dts/upstream/Bindings/arm/sti.yaml
View File

@ -14,12 +14,8 @@ properties:
const: '/' const: '/'
compatible: compatible:
oneOf: oneOf:
- items:
- const: st,stih407-b2120
- const: st,stih407
- items: - items:
- enum: - enum:
- st,stih410-b2120
- st,stih410-b2260 - st,stih410-b2260
- const: st,stih410 - const: st,stih410
- items: - items:

31
dts/upstream/Bindings/arm/stm32/st,stm32-syscon.yaml
View File

@ -36,20 +36,31 @@ properties:
clocks: clocks:
maxItems: 1 maxItems: 1
"#clock-cells":
const: 0
required: required:
- compatible - compatible
- reg - reg
if: allOf:
properties: - if:
compatible: properties:
contains: compatible:
enum: contains:
- st,stm32mp157-syscfg enum:
- st,stm32f4-gcan - st,stm32mp157-syscfg
then: - st,stm32f4-gcan
required: then:
- clocks required:
- clocks
- if:
properties:
compatible:
const: st,stm32mp25-syscfg
then:
required:
- "#clock-cells"
additionalProperties: false additionalProperties: false

13
dts/upstream/Bindings/arm/sunxi.yaml
View File

@ -595,6 +595,14 @@ properties:
- const: netcube,kumquat - const: netcube,kumquat
- const: allwinner,sun8i-v3s - const: allwinner,sun8i-v3s
- description: NetCube Systems Nagami SoM based boards
items:
- enum:
- netcube,nagami-basic-carrier
- netcube,nagami-keypad-carrier
- const: netcube,nagami
- const: allwinner,sun8i-t113s
- description: NextThing Co. CHIP - description: NextThing Co. CHIP
items: items:
- const: nextthing,chip - const: nextthing,chip
@ -963,6 +971,11 @@ properties:
- const: hechuang,x96-mate - const: hechuang,x96-mate
- const: allwinner,sun50i-h616 - const: allwinner,sun50i-h616
- description: X96Q
items:
- const: amediatech,x96q
- const: allwinner,sun50i-h616
- description: X96Q Pro+ - description: X96Q Pro+
items: items:
- const: amediatech,x96q-pro-plus - const: amediatech,x96q-pro-plus

89
dts/upstream/Bindings/arm/syna.txt
View File

@ -1,89 +0,0 @@
Synaptics SoC Device Tree Bindings
According to https://www.synaptics.com/company/news/conexant-marvell
Synaptics has acquired the Multimedia Solutions Business of Marvell, so
berlin SoCs are now Synaptics' SoCs now.
---------------------------------------------------------------
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
shall have the following properties:
* Required root node properties:
compatible: must contain "marvell,berlin"
In addition, the above compatible shall be extended with the specific
SoC and board used. Currently known SoC compatibles are:
"marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
"marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
"marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
"marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
"marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
* Example:
/ {
model = "Sony NSZ-GS7";
compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
...
}
* Marvell Berlin CPU control bindings
CPU control register allows various operations on CPUs, like resetting them
independently.
Required properties:
- compatible: should be "marvell,berlin-cpu-ctrl"
- reg: address and length of the register set
Example:
cpu-ctrl@f7dd0000 {
compatible = "marvell,berlin-cpu-ctrl";
reg = <0xf7dd0000 0x10000>;
};
* Marvell Berlin2 chip control binding
Marvell Berlin SoCs have a chip control register set providing several
individual registers dealing with pinmux, padmux, clock, reset, and secondary
CPU boot address. Unfortunately, the individual registers are spread among the
chip control registers, so there should be a single DT node only providing the
different functions which are described below.
Required properties:
- compatible:
* the first and second values must be:
"simple-mfd", "syscon"
- reg: address and length of following register sets for
BG2/BG2CD: chip control register set
BG2Q: chip control register set and cpu pll registers
* Marvell Berlin2 system control binding
Marvell Berlin SoCs have a system control register set providing several
individual registers dealing with pinmux, padmux, and reset.
Required properties:
- compatible:
* the first and second values must be:
"simple-mfd", "syscon"
- reg: address and length of the system control register set
Example:
chip: chip-control@ea0000 {
compatible = "simple-mfd", "syscon";
reg = <0xea0000 0x400>;
/* sub-device nodes */
};
sysctrl: system-controller@d000 {
compatible = "simple-mfd", "syscon";
reg = <0xd000 0x100>;
/* sub-device nodes */
};

12
dts/upstream/Bindings/arm/tegra.yaml
View File

@ -36,8 +36,12 @@ properties:
- toradex,colibri_t20-iris - toradex,colibri_t20-iris
- const: toradex,colibri_t20 - const: toradex,colibri_t20
- const: nvidia,tegra20 - const: nvidia,tegra20
- items: - description: ASUS Transformers T20 Device family
- const: asus,tf101 items:
- enum:
- asus,sl101
- asus,tf101
- asus,tf101g
- const: nvidia,tegra20 - const: nvidia,tegra20
- items: - items:
- const: acer,picasso - const: acer,picasso
@ -174,6 +178,10 @@ properties:
- const: google,nyan-big - const: google,nyan-big
- const: google,nyan - const: google,nyan
- const: nvidia,tegra124 - const: nvidia,tegra124
- description: Xiaomi Mi Pad (A0101)
items:
- const: xiaomi,mocha
- const: nvidia,tegra124
- items: - items:
- enum: - enum:
- nvidia,darcy - nvidia,darcy

13
dts/upstream/Bindings/arm/ti/k3.yaml
View File

@ -58,6 +58,13 @@ properties:
- ti,am62-lp-sk - ti,am62-lp-sk
- const: ti,am625 - const: ti,am625
- description: K3 AM6254atl SiP
items:
- enum:
- ti,am6254atl-sk
- const: ti,am6254atl
- const: ti,am625
- description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards - description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards
items: items:
- enum: - enum:
@ -106,6 +113,12 @@ properties:
- const: toradex,verdin-am62p # Verdin AM62P Module - const: toradex,verdin-am62p # Verdin AM62P Module
- const: ti,am62p5 - const: ti,am62p5
- description: K3 AM62P5 SoC Variscite SOM and Carrier Boards
items:
- const: variscite,var-som-am62p-symphony
- const: variscite,var-som-am62p
- const: ti,am62p5
- description: K3 AM642 SoC - description: K3 AM642 SoC
items: items:
- enum: - enum:

42
dts/upstream/Bindings/arm/ti/ti,keystone.yaml Normal file
View File

@ -0,0 +1,42 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/ti/ti,keystone.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI Keystone Platforms
maintainers:
- Nishanth Menon <nm@ti.com>
- Santosh Shilimkar <ssantosh@kernel.org>
properties:
compatible:
oneOf:
- description: K2G
items:
- enum:
- ti,k2g-evm
- ti,k2g-ice
- const: ti,k2g
- const: ti,keystone
- description: Keystone 2 Edison
items:
- enum:
- ti,k2e-evm
- const: ti,k2e
- const: ti,keystone
- description: Keystone 2 Lamarr
items:
- enum:
- ti,k2l-evm
- const: ti,k2l
- const: ti,keystone
- description: Keystone 2 Hawking/Kepler
items:
- enum:
- ti,k2hk-evm
- const: ti,k2hk
- const: ti,keystone
additionalProperties: true

21
dts/upstream/Bindings/ata/apm,xgene-ahci.yaml
View File

@ -9,14 +9,11 @@ title: APM X-Gene 6.0 Gb/s SATA host controller
maintainers: maintainers:
- Rob Herring <robh@kernel.org> - Rob Herring <robh@kernel.org>
allOf:
- $ref: ahci-common.yaml#
properties: properties:
compatible: compatible:
enum: enum:
- apm,xgene-ahci - apm,xgene-ahci
- apm,xgene-ahci-pcie - apm,xgene-ahci-v2
reg: reg:
minItems: 4 minItems: 4
@ -35,12 +32,22 @@ properties:
required: required:
- compatible - compatible
- clocks
- phys
- phy-names
unevaluatedProperties: false unevaluatedProperties: false
allOf:
- $ref: ahci-common.yaml#
- if:
properties:
compatible:
contains:
const: apm,xgene-ahci
then:
required:
- clocks
- phys
- phy-names
examples: examples:
- | - |
sata@1a400000 { sata@1a400000 {

3
dts/upstream/Bindings/ata/imx-sata.yaml
View File

@ -80,6 +80,9 @@ properties:
power-domains: power-domains:
maxItems: 1 maxItems: 1
target-supply:
description: Power regulator for the SATA target device.
required: required:
- compatible - compatible
- reg - reg

2
dts/upstream/Bindings/ata/sata_highbank.yaml
View File

@ -85,7 +85,7 @@ examples:
dma-coherent; dma-coherent;
calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>, calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>,
<&combophy0 2>, <&combophy0 3>; <&combophy0 2>, <&combophy0 3>;
calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>; calxeda,sgpio-gpio = <&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>;
calxeda,led-order = <4 0 1 2 3>; calxeda,led-order = <4 0 1 2 3>;
calxeda,tx-atten = <0xff 22 0xff 0xff 23>; calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
calxeda,pre-clocks = <10>; calxeda,pre-clocks = <10>;

2
dts/upstream/Bindings/bus/allwinner,sun50i-a64-de2.yaml
View File

@ -44,7 +44,7 @@ properties:
patternProperties: patternProperties:
# All other properties should be child nodes with unit-address and 'reg' # All other properties should be child nodes with unit-address and 'reg'
"^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+$": "@[0-9a-f]+$":
type: object type: object
additionalProperties: true additionalProperties: true
properties: properties:

12
dts/upstream/Bindings/bus/renesas,bsc.yaml
View File

@ -41,6 +41,18 @@ properties:
interrupts: interrupts:
maxItems: 1 maxItems: 1
patternProperties:
# All other properties should be child nodes with unit-address and 'reg'
"@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
reg:
maxItems: 1
required:
- reg
required: required:
- reg - reg

6
dts/upstream/Bindings/cache/andestech,ax45mp-cache.yaml vendored
View File

@ -47,7 +47,7 @@ properties:
const: 2 const: 2
cache-sets: cache-sets:
const: 1024 enum: [1024, 2048]
cache-size: cache-size:
enum: [131072, 262144, 524288, 1048576, 2097152] enum: [131072, 262144, 524288, 1048576, 2097152]
@ -81,6 +81,10 @@ allOf:
const: 2048 const: 2048
cache-size: cache-size:
const: 2097152 const: 2097152
else:
properties:
cache-sets:
const: 1024
examples: examples:
- | - |

4
dts/upstream/Bindings/clock/adi,axi-clkgen.yaml
View File

@ -42,6 +42,9 @@ properties:
- const: clkin2 - const: clkin2
- const: s_axi_aclk - const: s_axi_aclk
clock-output-names:
maxItems: 1
'#clock-cells': '#clock-cells':
const: 0 const: 0
@ -65,4 +68,5 @@ examples:
reg = <0xff000000 0x1000>; reg = <0xff000000 0x1000>;
clocks = <&osc 1>, <&clkc 15>; clocks = <&osc 1>, <&clkc 15>;
clock-names = "clkin1", "s_axi_aclk"; clock-names = "clkin1", "s_axi_aclk";
clock-output-names = "spi_sclk";
}; };

37
dts/upstream/Bindings/clock/allwinner,sun55i-a523-ccu.yaml
View File

@ -19,6 +19,7 @@ properties:
compatible: compatible:
enum: enum:
- allwinner,sun55i-a523-ccu - allwinner,sun55i-a523-ccu
- allwinner,sun55i-a523-mcu-ccu
- allwinner,sun55i-a523-r-ccu - allwinner,sun55i-a523-r-ccu
reg: reg:
@ -26,11 +27,11 @@ properties:
clocks: clocks:
minItems: 4 minItems: 4
maxItems: 5 maxItems: 9
clock-names: clock-names:
minItems: 4 minItems: 4
maxItems: 5 maxItems: 9
required: required:
- "#clock-cells" - "#clock-cells"
@ -63,6 +64,38 @@ allOf:
- const: iosc - const: iosc
- const: losc-fanout - const: losc-fanout
- if:
properties:
compatible:
enum:
- allwinner,sun55i-a523-mcu-ccu
then:
properties:
clocks:
items:
- description: High Frequency Oscillator (usually at 24MHz)
- description: Low Frequency Oscillator (usually at 32kHz)
- description: Internal Oscillator
- description: Audio PLL (4x)
- description: Peripherals PLL 0 (300 MHz output)
- description: DSP module clock
- description: MBUS clock
- description: PRCM AHB clock
- description: PRCM APB0 clock
clock-names:
items:
- const: hosc
- const: losc
- const: iosc
- const: pll-audio0-4x
- const: pll-periph0-300m
- const: dsp
- const: mbus
- const: r-ahb
- const: r-apb0
- if: - if:
properties: properties:
compatible: compatible:

17
dts/upstream/Bindings/clock/apple,nco.yaml
View File

@ -19,12 +19,17 @@ description: |
properties: properties:
compatible: compatible:
items: oneOf:
- enum: - items:
- apple,t6000-nco - const: apple,t6020-nco
- apple,t8103-nco - const: apple,t8103-nco
- apple,t8112-nco - items:
- const: apple,nco - enum:
# Do not add additional SoC to this list.
- apple,t6000-nco
- apple,t8103-nco
- apple,t8112-nco
- const: apple,nco
clocks: clocks:
description: description:

213
dts/upstream/Bindings/clock/axis,artpec8-clock.yaml Normal file
View File

@ -0,0 +1,213 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Axis ARTPEC-8 SoC clock controller
maintainers:
- Jesper Nilsson <jesper.nilsson@axis.com>
description: |
ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit)
units, generating clocks for different domains. Those CMU units are modeled
as separate device tree nodes, and might depend on each other.
The root clock in that root tree is an external clock: OSCCLK (25 MHz).
This external clock must be defined as a fixed-rate clock in dts.
CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
dividers; all other clocks of function blocks (other CMUs) are usually
derived from CMU_CMU.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
'include/dt-bindings/clock/axis,artpec8-clk.h' header.
properties:
compatible:
enum:
- axis,artpec8-cmu-cmu
- axis,artpec8-cmu-bus
- axis,artpec8-cmu-core
- axis,artpec8-cmu-cpucl
- axis,artpec8-cmu-fsys
- axis,artpec8-cmu-imem
- axis,artpec8-cmu-peri
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 5
clock-names:
minItems: 1
maxItems: 5
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- "#clock-cells"
allOf:
- if:
properties:
compatible:
const: axis,artpec8-cmu-cmu
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
clock-names:
items:
- const: fin_pll
- if:
properties:
compatible:
const: axis,artpec8-cmu-bus
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_BUS BUS clock (from CMU_CMU)
- description: CMU_BUS DLP clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: bus
- const: dlp
- if:
properties:
compatible:
const: axis,artpec8-cmu-core
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_CORE main clock (from CMU_CMU)
- description: CMU_CORE DLP clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: main
- const: dlp
- if:
properties:
compatible:
const: axis,artpec8-cmu-cpucl
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_CPUCL switch clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: switch
- if:
properties:
compatible:
const: axis,artpec8-cmu-fsys
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_FSYS SCAN0 clock (from CMU_CMU)
- description: CMU_FSYS SCAN1 clock (from CMU_CMU)
- description: CMU_FSYS BUS clock (from CMU_CMU)
- description: CMU_FSYS IP clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: scan0
- const: scan1
- const: bus
- const: ip
- if:
properties:
compatible:
const: axis,artpec8-cmu-imem
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_IMEM ACLK clock (from CMU_CMU)
- description: CMU_IMEM JPEG clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: aclk
- const: jpeg
- if:
properties:
compatible:
const: axis,artpec8-cmu-peri
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_PERI IP clock (from CMU_CMU)
- description: CMU_PERI AUDIO clock (from CMU_CMU)
- description: CMU_PERI DISP clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: ip
- const: audio
- const: disp
additionalProperties: false
examples:
# Clock controller node for CMU_FSYS
- |
#include <dt-bindings/clock/axis,artpec8-clk.h>
cmu_fsys: clock-controller@16c10000 {
compatible = "axis,artpec8-cmu-fsys";
reg = <0x16c10000 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>,
<&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>,
<&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>,
<&cmu_cmu CLK_DOUT_CMU_FSYS_IP>;
clock-names = "fin_pll", "scan0", "scan1", "bus", "ip";
};
...

26
dts/upstream/Bindings/clock/fujitsu,mb86s70-crg11.txt
View File

@ -1,26 +0,0 @@
Fujitsu CRG11 clock driver bindings
-----------------------------------
Required properties :
- compatible : Shall contain "fujitsu,mb86s70-crg11"
- #clock-cells : Shall be 3 {cntrlr domain port}
The consumer specifies the desired clock pointing to its phandle.
Example:
clock: crg11 {
compatible = "fujitsu,mb86s70-crg11";
#clock-cells = <3>;
};
mhu: mhu0@2b1f0000 {
#mbox-cells = <1>;
compatible = "arm,mhu";
reg = <0 0x2B1F0000 0x1000>;
interrupts = <0 36 4>, /* LP Non-Sec */
<0 35 4>, /* HP Non-Sec */
<0 37 4>; /* Secure */
clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
clock-names = "clk";
};

18
dts/upstream/Bindings/clock/loongson,ls2k-clk.yaml
View File

@ -16,6 +16,7 @@ description: |
properties: properties:
compatible: compatible:
enum: enum:
- loongson,ls2k0300-clk
- loongson,ls2k0500-clk - loongson,ls2k0500-clk
- loongson,ls2k-clk # This is for Loongson-2K1000 - loongson,ls2k-clk # This is for Loongson-2K1000
- loongson,ls2k2000-clk - loongson,ls2k2000-clk
@ -24,8 +25,7 @@ properties:
maxItems: 1 maxItems: 1
clocks: clocks:
items: maxItems: 1
- description: 100m ref
clock-names: clock-names:
items: items:
@ -38,11 +38,23 @@ properties:
ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h
for the full list of Loongson-2 SoC clock IDs. for the full list of Loongson-2 SoC clock IDs.
allOf:
- if:
properties:
compatible:
contains:
const: loongson,ls2k0300-clk
then:
properties:
clock-names: false
else:
required:
- clock-names
required: required:
- compatible - compatible
- reg - reg
- clocks - clocks
- clock-names
- '#clock-cells' - '#clock-cells'
additionalProperties: false additionalProperties: false

30
dts/upstream/Bindings/clock/marvell,pxa1908.yaml
View File

@ -19,11 +19,14 @@ description: |
properties: properties:
compatible: compatible:
enum: oneOf:
- marvell,pxa1908-apbc - enum:
- marvell,pxa1908-apbcp - marvell,pxa1908-apbc
- marvell,pxa1908-mpmu - marvell,pxa1908-apbcp
- marvell,pxa1908-apmu - marvell,pxa1908-mpmu
- items:
- const: marvell,pxa1908-apmu
- const: syscon
reg: reg:
maxItems: 1 maxItems: 1
@ -31,6 +34,9 @@ properties:
'#clock-cells': '#clock-cells':
const: 1 const: 1
'#power-domain-cells':
const: 1
required: required:
- compatible - compatible
- reg - reg
@ -38,11 +44,23 @@ required:
additionalProperties: false additionalProperties: false
if:
not:
properties:
compatible:
contains:
const: marvell,pxa1908-apmu
then:
properties:
'#power-domain-cells': false
examples: examples:
# APMU block: # APMU block:
- | - |
clock-controller@d4282800 { clock-controller@d4282800 {
compatible = "marvell,pxa1908-apmu"; compatible = "marvell,pxa1908-apmu", "syscon";
reg = <0xd4282800 0x400>; reg = <0xd4282800 0x400>;
#clock-cells = <1>; #clock-cells = <1>;
#power-domain-cells = <1>;
}; };

112
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@ -0,0 +1,112 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8196
maintainers:
- Guangjie Song <guangjie.song@mediatek.com>
- Laura Nao <laura.nao@collabora.com>
description: |
The clock architecture in MediaTek SoCs is structured like below:
PLLs -->
dividers -->
muxes
-->
clock gate
The device nodes provide clock gate control in different IP blocks.
properties:
compatible:
items:
- enum:
- mediatek,mt8196-imp-iic-wrap-c
- mediatek,mt8196-imp-iic-wrap-e
- mediatek,mt8196-imp-iic-wrap-n
- mediatek,mt8196-imp-iic-wrap-w
- mediatek,mt8196-mdpsys0
- mediatek,mt8196-mdpsys1
- mediatek,mt8196-pericfg-ao
- mediatek,mt8196-pextp0cfg-ao
- mediatek,mt8196-pextp1cfg-ao
- mediatek,mt8196-ufscfg-ao
- mediatek,mt8196-vencsys
- mediatek,mt8196-vencsys-c1
- mediatek,mt8196-vencsys-c2
- mediatek,mt8196-vdecsys
- mediatek,mt8196-vdecsys-soc
- mediatek,mt8196-vdisp-ao
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
description:
Reset lines for PEXTP0/1 and UFS blocks.
mediatek,hardware-voter:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Phandle to the "Hardware Voter" (HWV), as named in the vendor
documentation for MT8196/MT6991.
The HWV is a SoC-internal fixed-function MCU used to collect votes from
both the Application Processor and other remote processors within the SoC.
It is intended to transparently enable or disable hardware resources (such
as power domains or clocks) based on internal vote aggregation handled by
the MCU's internal state machine.
However, in practice, this design is incomplete. While the HWV performs
some internal vote aggregation,software is still required to
- Manually enable power supplies externally, if present and if required
- Manually enable parent clocks via direct MMIO writes to clock controllers
- Enable the FENC after the clock has been ungated via direct MMIO
writes to clock controllers
As such, the HWV behaves more like a hardware-managed clock reference
counter than a true voter. Furthermore, it is not a separate
controller. It merely serves as an alternative interface to the same
underlying clock or power controller. Actual control still requires
direct access to the controller's own MMIO register space, in
addition to writing to the HWV's MMIO region.
For this reason, a custom phandle is used here - drivers need to directly
access the HWV MMIO region in a syscon-like fashion, due to how the
hardware is wired. This differs from true hardware voting systems, which
typically do not require custom phandles and rely instead on generic APIs
(clocks, power domains, interconnects).
The name "hardware-voter" is retained to match vendor documentation, but
this should not be reused or misunderstood as a proper voting mechanism.
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
pericfg_ao: clock-controller@16640000 {
compatible = "mediatek,mt8196-pericfg-ao", "syscon";
reg = <0x16640000 0x1000>;
mediatek,hardware-voter = <&scp_hwv>;
#clock-cells = <1>;
};
- |
pextp0cfg_ao: clock-controller@169b0000 {
compatible = "mediatek,mt8196-pextp0cfg-ao", "syscon";
reg = <0x169b0000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

107
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@ -0,0 +1,107 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8196
maintainers:
- Guangjie Song <guangjie.song@mediatek.com>
- Laura Nao <laura.nao@collabora.com>
description: |
The clock architecture in MediaTek SoCs is structured like below:
PLLs -->
dividers -->
muxes
-->
clock gate
The apmixedsys, apmixedsys_gp2, vlpckgen, armpll, ccipll, mfgpll and ptppll
provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator.
The topckgen, topckgen_gp2 and vlpckgen provide dividers and muxes which
provide the clock source to other IP blocks.
properties:
compatible:
items:
- enum:
- mediatek,mt8196-apmixedsys
- mediatek,mt8196-armpll-b-pll-ctrl
- mediatek,mt8196-armpll-bl-pll-ctrl
- mediatek,mt8196-armpll-ll-pll-ctrl
- mediatek,mt8196-apmixedsys-gp2
- mediatek,mt8196-ccipll-pll-ctrl
- mediatek,mt8196-mfgpll-pll-ctrl
- mediatek,mt8196-mfgpll-sc0-pll-ctrl
- mediatek,mt8196-mfgpll-sc1-pll-ctrl
- mediatek,mt8196-ptppll-pll-ctrl
- mediatek,mt8196-topckgen
- mediatek,mt8196-topckgen-gp2
- mediatek,mt8196-vlpckgen
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
mediatek,hardware-voter:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Phandle to the "Hardware Voter" (HWV), as named in the vendor
documentation for MT8196/MT6991.
The HWV is a SoC-internal fixed-function MCU used to collect votes from
both the Application Processor and other remote processors within the SoC.
It is intended to transparently enable or disable hardware resources (such
as power domains or clocks) based on internal vote aggregation handled by
the MCU's internal state machine.
However, in practice, this design is incomplete. While the HWV performs
some internal vote aggregation,software is still required to
- Manually enable power supplies externally, if present and if required
- Manually enable parent clocks via direct MMIO writes to clock controllers
- Enable the FENC after the clock has been ungated via direct MMIO
writes to clock controllers
As such, the HWV behaves more like a hardware-managed clock reference
counter than a true voter. Furthermore, it is not a separate
controller. It merely serves as an alternative interface to the same
underlying clock or power controller. Actual control still requires
direct access to the controller's own MMIO register space, in
addition to writing to the HWV's MMIO region.
For this reason, a custom phandle is used here - drivers need to directly
access the HWV MMIO region in a syscon-like fashion, due to how the
hardware is wired. This differs from true hardware voting systems, which
typically do not require custom phandles and rely instead on generic APIs
(clocks, power domains, interconnects).
The name "hardware-voter" is retained to match vendor documentation, but
this should not be reused or misunderstood as a proper voting mechanism.
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
apmixedsys_clk: syscon@10000800 {
compatible = "mediatek,mt8196-apmixedsys", "syscon";
reg = <0x10000800 0x1000>;
#clock-cells = <1>;
};
- |
topckgen: syscon@10000000 {
compatible = "mediatek,mt8196-topckgen", "syscon";
reg = <0x10000000 0x800>;
mediatek,hardware-voter = <&scp_hwv>;
#clock-cells = <1>;
};

15
dts/upstream/Bindings/clock/mediatek,syscon.yaml
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@ -76,6 +76,9 @@ properties:
- const: mediatek,mt2701-vdecsys - const: mediatek,mt2701-vdecsys
- const: syscon - const: syscon
power-domains:
maxItems: 1
reg: reg:
maxItems: 1 maxItems: 1
@ -86,6 +89,18 @@ required:
- compatible - compatible
- '#clock-cells' - '#clock-cells'
if:
properties:
compatible:
contains:
const: mediatek,mt8183-mfgcfg
then:
properties:
power-domains: true
else:
properties:
power-domains: false
additionalProperties: false additionalProperties: false
examples: examples:

11
dts/upstream/Bindings/clock/qcom,gcc-msm8953.yaml
View File

@ -9,16 +9,21 @@ title: Qualcomm Global Clock & Reset Controller on MSM8953
maintainers: maintainers:
- Adam Skladowski <a_skl39@protonmail.com> - Adam Skladowski <a_skl39@protonmail.com>
- Sireesh Kodali <sireeshkodali@protonmail.com> - Sireesh Kodali <sireeshkodali@protonmail.com>
- Barnabas Czeman <barnabas.czeman@mainlining.org>
description: | description: |
Qualcomm global clock control module provides the clocks, resets and power Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8953. domains on MSM8937 or MSM8953.
See also: include/dt-bindings/clock/qcom,gcc-msm8953.h See also::
include/dt-bindings/clock/qcom,gcc-msm8917.h
include/dt-bindings/clock/qcom,gcc-msm8953.h
properties: properties:
compatible: compatible:
const: qcom,gcc-msm8953 enum:
- qcom,gcc-msm8937
- qcom,gcc-msm8953
clocks: clocks:
items: items:

98
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@ -0,0 +1,98 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on GLYMUR
maintainers:
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains for the MDSS instances on GLYMUR SoC.
See also:
include/dt-bindings/clock/qcom,dispcc-glymur.h
properties:
compatible:
enum:
- qcom,glymur-dispcc
clocks:
items:
- description: Board CXO clock
- description: Board sleep clock
- description: DisplayPort 0 link clock
- description: DisplayPort 0 VCO div clock
- description: DisplayPort 1 link clock
- description: DisplayPort 1 VCO div clock
- description: DisplayPort 2 link clock
- description: DisplayPort 2 VCO div clock
- description: DisplayPort 3 link clock
- description: DisplayPort 3 VCO div clock
- description: DSI 0 PLL byte clock
- description: DSI 0 PLL DSI clock
- description: DSI 1 PLL byte clock
- description: DSI 1 PLL DSI clock
- description: Standalone PHY 0 PLL link clock
- description: Standalone PHY 0 VCO div clock
- description: Standalone PHY 1 PLL link clock
- description: Standalone PHY 1 VCO div clock
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,glymur-dispcc";
reg = <0x0af00000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&mdss_dp_phy0 0>,
<&mdss_dp_phy0 1>,
<&mdss_dp_phy1 0>,
<&mdss_dp_phy1 1>,
<&mdss_dp_phy2 0>,
<&mdss_dp_phy2 1>,
<&mdss_dp_phy3 0>,
<&mdss_dp_phy3 1>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>,
<&mdss_dsi1_phy 0>,
<&mdss_dsi1_phy 1>,
<&mdss_phy0_link 0>,
<&mdss_phy0_vco_div 0>,
<&mdss_phy1_link 1>,
<&mdss_phy1_vco_div 1>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

121
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@ -0,0 +1,121 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on Glymur SoC
maintainers:
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on Glymur SoC.
See also: include/dt-bindings/clock/qcom,glymur-gcc.h
properties:
compatible:
const: qcom,glymur-gcc
clocks:
items:
- description: Board XO source
- description: Board XO_A source
- description: Sleep clock source
- description: USB 0 Phy DP0 GMUX clock source
- description: USB 0 Phy DP1 GMUX clock source
- description: USB 0 Phy PCIE PIPEGMUX clock source
- description: USB 0 Phy PIPEGMUX clock source
- description: USB 0 Phy SYS PCIE PIPEGMUX clock source
- description: USB 1 Phy DP0 GMUX 2 clock source
- description: USB 1 Phy DP1 GMUX 2 clock source
- description: USB 1 Phy PCIE PIPEGMUX clock source
- description: USB 1 Phy PIPEGMUX clock source
- description: USB 1 Phy SYS PCIE PIPEGMUX clock source
- description: USB 2 Phy DP0 GMUX 2 clock source
- description: USB 2 Phy DP1 GMUX 2 clock source
- description: USB 2 Phy PCIE PIPEGMUX clock source
- description: USB 2 Phy PIPEGMUX clock source
- description: USB 2 Phy SYS PCIE PIPEGMUX clock source
- description: PCIe 3a pipe clock
- description: PCIe 3b pipe clock
- description: PCIe 4 pipe clock
- description: PCIe 5 pipe clock
- description: PCIe 6 pipe clock
- description: QUSB4 0 PHY RX 0 clock source
- description: QUSB4 0 PHY RX 1 clock source
- description: QUSB4 1 PHY RX 0 clock source
- description: QUSB4 1 PHY RX 1 clock source
- description: QUSB4 2 PHY RX 0 clock source
- description: QUSB4 2 PHY RX 1 clock source
- description: UFS PHY RX Symbol 0 clock source
- description: UFS PHY RX Symbol 1 clock source
- description: UFS PHY TX Symbol 0 clock source
- description: USB3 PHY 0 pipe clock source
- description: USB3 PHY 1 pipe clock source
- description: USB3 PHY 2 pipe clock source
- description: USB3 UNI PHY pipe 0 clock source
- description: USB3 UNI PHY pipe 1 clock source
- description: USB4 PHY 0 pcie pipe clock source
- description: USB4 PHY 0 Max pipe clock source
- description: USB4 PHY 1 pcie pipe clock source
- description: USB4 PHY 1 Max pipe clock source
- description: USB4 PHY 2 pcie pipe clock source
- description: USB4 PHY 2 Max pipe clock source
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,glymur-gcc";
reg = <0x100000 0x1f9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&usb_0_phy_dp0_gmux>,
<&usb_0_phy_dp1_gmux>,
<&usb_0_phy_pcie_pipegmux>,
<&usb_0_phy_pipegmux>,
<&usb_0_phy_sys_pcie_pipegmux>,
<&usb_1_phy_dp0_gmux_2>,
<&usb_1_phy_dp1_gmux_2>,
<&usb_1_phy_pcie_pipegmux>,
<&usb_1_phy_pipegmux>,
<&usb_1_phy_sys_pcie_pipegmux>,
<&usb_2_phy_dp0_gmux 2>,
<&usb_2_phy_dp1_gmux 2>,
<&usb_2_phy_pcie_pipegmux>,
<&usb_2_phy_pipegmux>,
<&usb_2_phy_sys_pcie_pipegmux>,
<&pcie_3a_pipe>, <&pcie_3b_pipe>,
<&pcie_4_pipe>, <&pcie_5_pipe>,
<&pcie_6_pipe>,
<&qusb4_0_phy_rx_0>, <&qusb4_0_phy_rx_1>,
<&qusb4_1_phy_rx_0>, <&qusb4_1_phy_rx_1>,
<&qusb4_2_phy_rx_0>, <&qusb4_2_phy_rx_1>,
<&ufs_phy_rx_symbol_0>, <&ufs_phy_rx_symbol_1>,
<&ufs_phy_tx_symbol_0>,
<&usb3_phy_0_pipe>, <&usb3_phy_1_pipe>,
<&usb3_phy_2_pipe>,
<&usb3_uni_phy_pipe_0>, <&usb3_uni_phy_pipe_1>,
<&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>,
<&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>,
<&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

55
dts/upstream/Bindings/clock/qcom,ipq5424-apss-clk.yaml Normal file
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@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm APSS IPQ5424 Clock Controller
maintainers:
- Varadarajan Narayanan <quic_varada@quicinc.com>
description:
The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
The RCG and PLL have a separate register space from the GCC.
properties:
compatible:
enum:
- qcom,ipq5424-apss-clk
reg:
maxItems: 1
clocks:
items:
- description: Reference to the XO clock.
- description: Reference to the GPLL0 clock.
'#clock-cells':
const: 1
'#interconnect-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#interconnect-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
apss_clk: clock-controller@fa80000 {
compatible = "qcom,ipq5424-apss-clk";
reg = <0x0fa80000 0x20000>;
clocks = <&xo_board>,
<&gcc GPLL0>;
#clock-cells = <1>;
#interconnect-cells = <1>;
};

1
dts/upstream/Bindings/clock/qcom,rpmhcc.yaml
View File

@ -17,6 +17,7 @@ description: |
properties: properties:
compatible: compatible:
enum: enum:
- qcom,glymur-rpmh-clk
- qcom,milos-rpmh-clk - qcom,milos-rpmh-clk
- qcom,qcs615-rpmh-clk - qcom,qcs615-rpmh-clk
- qcom,qdu1000-rpmh-clk - qcom,qdu1000-rpmh-clk

3
dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml
View File

@ -8,12 +8,14 @@ title: Qualcomm TCSR Clock Controller on SM8550
maintainers: maintainers:
- Bjorn Andersson <andersson@kernel.org> - Bjorn Andersson <andersson@kernel.org>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: | description: |
Qualcomm TCSR clock control module provides the clocks, resets and Qualcomm TCSR clock control module provides the clocks, resets and
power domains on SM8550 power domains on SM8550
See also: See also:
- include/dt-bindings/clock/qcom,glymur-tcsr.h
- include/dt-bindings/clock/qcom,sm8550-tcsr.h - include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h - include/dt-bindings/clock/qcom,sm8650-tcsr.h
- include/dt-bindings/clock/qcom,sm8750-tcsr.h - include/dt-bindings/clock/qcom,sm8750-tcsr.h
@ -22,6 +24,7 @@ properties:
compatible: compatible:
items: items:
- enum: - enum:
- qcom,glymur-tcsr
- qcom,milos-tcsr - qcom,milos-tcsr
- qcom,sar2130p-tcsr - qcom,sar2130p-tcsr
- qcom,sm8550-tcsr - qcom,sm8550-tcsr

23
dts/upstream/Bindings/clock/qcom,videocc.yaml
View File

@ -23,13 +23,17 @@ description: |
properties: properties:
compatible: compatible:
enum: oneOf:
- qcom,sc7180-videocc - enum:
- qcom,sc7280-videocc - qcom,sc7180-videocc
- qcom,sdm845-videocc - qcom,sc7280-videocc
- qcom,sm6350-videocc - qcom,sdm845-videocc
- qcom,sm8150-videocc - qcom,sm6350-videocc
- qcom,sm8250-videocc - qcom,sm8150-videocc
- qcom,sm8250-videocc
- items:
- const: qcom,sc8180x-videocc
- const: qcom,sm8150-videocc
clocks: clocks:
minItems: 1 minItems: 1
@ -110,8 +114,9 @@ allOf:
- if: - if:
properties: properties:
compatible: compatible:
enum: contains:
- qcom,sm8150-videocc enum:
- qcom,sm8150-videocc
then: then:
properties: properties:
clocks: clocks:

64
dts/upstream/Bindings/clock/riscv,rpmi-clock.yaml Normal file
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@ -0,0 +1,64 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/riscv,rpmi-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RISC-V RPMI clock service group based clock controller
maintainers:
- Anup Patel <anup@brainfault.org>
description: |
The RISC-V Platform Management Interface (RPMI) [1] defines a
messaging protocol which is modular and extensible. The supervisor
software can send/receive RPMI messages via SBI MPXY extension [2]
or some dedicated supervisor-mode RPMI transport.
The RPMI specification [1] defines clock service group for accessing
system clocks managed by a platform microcontroller. The supervisor
software can access RPMI clock service group via SBI MPXY channel or
some dedicated supervisor-mode RPMI transport.
===========================================
References
===========================================
[1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher)
https://github.com/riscv-non-isa/riscv-rpmi/releases
[2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher)
https://github.com/riscv-non-isa/riscv-sbi-doc/releases
properties:
compatible:
description:
Intended for use by the supervisor software.
const: riscv,rpmi-clock
mboxes:
maxItems: 1
description:
Mailbox channel of the underlying RPMI transport or SBI message proxy channel.
"#clock-cells":
const: 1
description:
Platform specific CLOCK_ID as defined by the RISC-V Platform Management
Interface (RPMI) specification.
required:
- compatible
- mboxes
- "#clock-cells"
additionalProperties: false
examples:
- |
clock-controller {
compatible = "riscv,rpmi-clock";
mboxes = <&mpxy_mbox 0x1000 0x0>;
#clock-cells = <1>;
};
...

64
dts/upstream/Bindings/clock/riscv,rpmi-mpxy-clock.yaml Normal file
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@ -0,0 +1,64 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/riscv,rpmi-mpxy-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RISC-V RPMI clock service group based message proxy
maintainers:
- Anup Patel <anup@brainfault.org>
description: |
The RISC-V Platform Management Interface (RPMI) [1] defines a
messaging protocol which is modular and extensible. The supervisor
software can send/receive RPMI messages via SBI MPXY extension [2]
or some dedicated supervisor-mode RPMI transport.
The RPMI specification [1] defines clock service group for accessing
system clocks managed by a platform microcontroller. The SBI implementation
(machine mode firmware or hypervisor) can implement an SBI MPXY channel
to allow RPMI clock service group access to the supervisor software.
===========================================
References
===========================================
[1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher)
https://github.com/riscv-non-isa/riscv-rpmi/releases
[2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher)
https://github.com/riscv-non-isa/riscv-sbi-doc/releases
properties:
compatible:
description:
Intended for use by the SBI implementation.
const: riscv,rpmi-mpxy-clock
mboxes:
maxItems: 1
description:
Mailbox channel of the underlying RPMI transport.
riscv,sbi-mpxy-channel-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The SBI MPXY channel id to be used for providing RPMI access to
the supervisor software.
required:
- compatible
- mboxes
- riscv,sbi-mpxy-channel-id
additionalProperties: false
examples:
- |
clock-service {
compatible = "riscv,rpmi-mpxy-clock";
mboxes = <&rpmi_shmem_mbox 0x8>;
riscv,sbi-mpxy-channel-id = <0x1000>;
};
...

24
dts/upstream/Bindings/clock/samsung,exynos990-clock.yaml
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@ -30,6 +30,8 @@ description: |
properties: properties:
compatible: compatible:
enum: enum:
- samsung,exynos990-cmu-peric1
- samsung,exynos990-cmu-peric0
- samsung,exynos990-cmu-hsi0 - samsung,exynos990-cmu-hsi0
- samsung,exynos990-cmu-peris - samsung,exynos990-cmu-peris
- samsung,exynos990-cmu-top - samsung,exynos990-cmu-top
@ -56,6 +58,28 @@ required:
- reg - reg
allOf: allOf:
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos990-cmu-peric1
- samsung,exynos990-cmu-peric0
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
- description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- const: ip
- if: - if:
properties: properties:
compatible: compatible:

1
dts/upstream/Bindings/clock/samsung,s2mps11.yaml
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@ -25,6 +25,7 @@ description: |
properties: properties:
compatible: compatible:
enum: enum:
- samsung,s2mpg10-clk
- samsung,s2mps11-clk - samsung,s2mps11-clk
- samsung,s2mps13-clk # S2MPS13 and S2MPS15 - samsung,s2mps13-clk # S2MPS13 and S2MPS15
- samsung,s2mps14-clk - samsung,s2mps14-clk

24
dts/upstream/Bindings/clock/silabs,si514.txt
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@ -1,24 +0,0 @@
Binding for Silicon Labs 514 programmable I2C clock generator.
Reference
This binding uses the common clock binding[1]. Details about the device can be
found in the datasheet[2].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Si514 datasheet
https://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf
Required properties:
- compatible: Shall be "silabs,si514"
- reg: I2C device address.
- #clock-cells: From common clock bindings: Shall be 0.
Optional properties:
- clock-output-names: From common clock bindings. Recommended to be "si514".
Example:
si514: clock-generator@55 {
reg = <0x55>;
#clock-cells = <0>;
compatible = "silabs,si514";
};

175
dts/upstream/Bindings/clock/silabs,si5341.txt
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@ -1,175 +0,0 @@
Binding for Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable
i2c clock generator.
Reference
[1] Si5341 Data Sheet
https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
[2] Si5341 Reference Manual
https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
[3] Si5345 Reference Manual
https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
in turn can be directed to any of the 10 (or 4) outputs through a divider.
The internal structure of the clock generators can be found in [2].
The Si5345 is similar to the Si5341 with the addition of fractional input
dividers and automatic input selection, as described in [3].
The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs.
The driver can be used in "as is" mode, reading the current settings from the
chip at boot, in case you have a (pre-)programmed device. If the PLL is not
configured when the driver probes, it assumes the driver must fully initialize
it.
The device type, speed grade and revision are determined runtime by probing.
The driver currently does not support any fancy input configurations. They can
still be programmed into the chip and the driver will leave them "as is".
==I2C device node==
Required properties:
- compatible: shall be one of the following:
"silabs,si5340" - Si5340 A/B/C/D
"silabs,si5341" - Si5341 A/B/C/D
"silabs,si5342" - Si5342 A/B/C/D
"silabs,si5344" - Si5344 A/B/C/D
"silabs,si5345" - Si5345 A/B/C/D
- reg: i2c device address, usually 0x74
- #clock-cells: from common clock binding; shall be set to 2.
The first value is "0" for outputs, "1" for synthesizers.
The second value is the output or synthesizer index.
- clocks: from common clock binding; list of parent clock handles,
corresponding to inputs. Use a fixed clock for the "xtal" input.
At least one must be present.
- clock-names: One of: "xtal", "in0", "in1", "in2"
Optional properties:
- vdd-supply: Regulator node for VDD
- vdda-supply: Regulator node for VDDA
- vdds-supply: Regulator node for VDDS
- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
feedback divider. Must be such that the PLL output is in the valid range. For
example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
the fraction matters, using 3500 and 12 will deliver the exact same result.
If these are not specified, and the PLL is not yet programmed when the driver
probes, the PLL will be set to 14GHz.
- silabs,reprogram: When present, the driver will always assume the device must
be initialized, and always performs the soft-reset routine. Since this will
temporarily stop all output clocks, don't do this if the chip is generating
the CPU clock for example.
- silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used
in EXTCLK (external reference clock) rather than XTAL (crystal) mode.
- interrupts: Interrupt for INTRb pin.
- silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V
rather than 1.8V thresholds.
- vddoX-supply (where X is an output index): Regulator node for VDDO for the
specified output. The driver selects the output VDD_SEL setting based on this
voltage.
- #address-cells: shall be set to 1.
- #size-cells: shall be set to 0.
== Child nodes: Outputs ==
The child nodes list the output clocks.
Each of the clock outputs can be overwritten individually by using a child node.
If a child node for a clock output is not set, the configuration remains
unchanged.
Required child node properties:
- reg: number of clock output.
Optional child node properties:
- silabs,format: Output format, one of:
1 = differential (defaults to LVDS levels)
2 = low-power (defaults to HCSL levels)
4 = LVCMOS
- silabs,common-mode: Manually override output common mode, see [2] for values
- silabs,amplitude: Manually override output amplitude, see [2] for values
- silabs,synth-master: boolean. If present, this output is allowed to change the
multisynth frequency dynamically.
- silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH
when disabled, otherwise it's driven LOW.
==Example==
/* 48MHz reference crystal */
ref48: ref48M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
i2c-master-node {
/* Programmable clock (for logic) */
si5341: clock-generator@74 {
reg = <0x74>;
compatible = "silabs,si5341";
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ref48>;
clock-names = "xtal";
silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
silabs,pll-m-den = <48>;
silabs,reprogram; /* Chips are not programmed, always reset */
out@0 {
reg = <0>;
silabs,format = <1>; /* LVDS 3v3 */
silabs,common-mode = <3>;
silabs,amplitude = <3>;
silabs,synth-master;
};
/*
* Output 6 configuration:
* LVDS 1v8
*/
out@6 {
reg = <6>;
silabs,format = <1>; /* LVDS 1v8 */
silabs,common-mode = <13>;
silabs,amplitude = <3>;
};
/*
* Output 8 configuration:
* HCSL 3v3
*/
out@8 {
reg = <8>;
silabs,format = <2>;
silabs,common-mode = <11>;
silabs,amplitude = <3>;
};
};
};
some-video-node {
/* Standard clock bindings */
clock-names = "pixel";
clocks = <&si5341 0 7>; /* Output 7 */
/* Set output 7 to use syntesizer 3 as its parent */
assigned-clocks = <&si5341 0 7>, <&si5341 1 3>;
assigned-clock-parents = <&si5341 1 3>;
/* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */
assigned-clock-rates = <148500000>, <594000000>;
};
some-audio-node {
clock-names = "i2s-clk";
clocks = <&si5341 0 0>;
/*
* since output 0 is a synth-master, the synth will be automatically set
* to an appropriate frequency when the audio driver requests another
* frequency. We give control over synth 2 to this output here.
*/
assigned-clocks = <&si5341 0 0>;
assigned-clock-parents = <&si5341 1 2>;
};

223
dts/upstream/Bindings/clock/silabs,si5341.yaml Normal file
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@ -0,0 +1,223 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/silabs,si5341.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Silicon Labs Si5340/1/2/4/5 programmable i2c clock generator
maintainers:
- Mike Looijmans <mike.looijmans@topic.nl>
description: >
Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable i2c clock
generator.
Reference
[1] Si5341 Data Sheet
https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
[2] Si5341 Reference Manual
https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
[3] Si5345 Reference Manual
https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
in turn can be directed to any of the 10 (or 4) outputs through a divider.
The internal structure of the clock generators can be found in [2].
The Si5345 is similar to the Si5341 with the addition of fractional input
dividers and automatic input selection, as described in [3].
The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs.
The driver can be used in "as is" mode, reading the current settings from the
chip at boot, in case you have a (pre-)programmed device. If the PLL is not
configured when the driver probes, it assumes the driver must fully initialize
it.
The device type, speed grade and revision are determined runtime by probing.
properties:
compatible:
enum:
- silabs,si5340
- silabs,si5341
- silabs,si5342
- silabs,si5344
- silabs,si5345
reg:
maxItems: 1
"#clock-cells":
const: 2
description: >
The first value is "0" for outputs, "1" for synthesizers.
The second value is the output or synthesizer index.
"#address-cells":
const: 1
"#size-cells":
const: 0
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
items:
- const: xtal
- const: in0
- const: in1
- const: in2
clock-output-names: true
interrupts:
maxItems: 1
description: Interrupt for INTRb pin
vdd-supply:
description: Regulator node for VDD
vdda-supply:
description: Regulator node for VDDA
vdds-supply:
description: Regulator node for VDDS
silabs,pll-m-num:
description:
Numerator for PLL feedback divider. Must be such that the PLL output is in
the valid range. For example, to create 14GHz from a 48MHz xtal, use
m-num=14000 and m-den=48. Only the fraction matters, using 3500 and 12
will deliver the exact same result. If these are not specified, and the
PLL is not yet programmed when the driver probes, the PLL will be set to
14GHz.
$ref: /schemas/types.yaml#/definitions/uint32
silabs,pll-m-den:
description: Denominator for PLL feedback divider
$ref: /schemas/types.yaml#/definitions/uint32
silabs,reprogram:
description: Always perform soft-reset and reinitialize PLL
type: boolean
silabs,xaxb-ext-clk:
description: Use XA/XB pins as external reference clock
type: boolean
silabs,iovdd-33:
description: I2C lines use 3.3V thresholds
type: boolean
patternProperties:
"^vddo[0-9]-supply$": true
"^out@[0-9]$":
description: >
Output-specific override nodes
Each of the clock outputs can be overwritten individually by using a child
node. If a child node for a clock output is not set, the configuration
remains unchanged.
type: object
additionalProperties: false
properties:
reg:
description: Number of clock output
maximum: 9
always-on:
description: Set to keep the clock output always running
type: boolean
silabs,format:
description: Output format
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 4]
silabs,common-mode:
description: Override output common mode
$ref: /schemas/types.yaml#/definitions/uint32
silabs,amplitude:
description: Override output amplitude
$ref: /schemas/types.yaml#/definitions/uint32
silabs,synth-master:
description: Allow dynamic multisynth rate control
type: boolean
silabs,disable-high:
description: Drive output HIGH when disabled
type: boolean
required:
- reg
required:
- compatible
- reg
- "#clock-cells"
- "#address-cells"
- "#size-cells"
- clocks
- clock-names
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
clock-generator@74 {
reg = <0x74>;
compatible = "silabs,si5341";
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ref48>;
clock-names = "xtal";
silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
silabs,pll-m-den = <48>;
silabs,reprogram; /* Chips are not programmed, always reset */
out@0 {
reg = <0>;
silabs,format = <1>; /* LVDS 3v3 */
silabs,common-mode = <3>;
silabs,amplitude = <3>;
silabs,synth-master;
};
/*
* Output 6 configuration:
* LVDS 1v8
*/
out@6 {
reg = <6>;
silabs,format = <1>; /* LVDS 1v8 */
silabs,common-mode = <13>;
silabs,amplitude = <3>;
};
/*
* Output 8 configuration:
* HCSL 3v3
*/
out@8 {
reg = <8>;
silabs,format = <2>;
silabs,common-mode = <11>;
silabs,amplitude = <3>;
};
};
};

25
dts/upstream/Bindings/clock/silabs,si544.txt
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@ -1,25 +0,0 @@
Binding for Silicon Labs 544 programmable I2C clock generator.
Reference
This binding uses the common clock binding[1]. Details about the device can be
found in the datasheet[2].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Si544 datasheet
https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
Required properties:
- compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according
to the speed grade of the chip.
- reg: I2C device address.
- #clock-cells: From common clock bindings: Shall be 0.
Optional properties:
- clock-output-names: From common clock bindings. Recommended to be "si544".
Example:
si544: clock-controller@55 {
reg = <0x55>;
#clock-cells = <0>;
compatible = "silabs,si544b";
};

54
dts/upstream/Bindings/clock/silabs,si544.yaml Normal file
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@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/silabs,si544.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Silicon Labs SI514/SI544 clock generator
maintainers:
- Mike Looijmans <mike.looijmans@topic.nl>
description: >
Silicon Labs 514/544 programmable I2C clock generator. Details about the device
can be found in the datasheet:
https://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf
https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
properties:
compatible:
enum:
- silabs,si514
- silabs,si544a
- silabs,si544b
- silabs,si544c
reg:
maxItems: 1
"#clock-cells":
const: 0
clock-output-names:
maxItems: 1
required:
- compatible
- reg
- "#clock-cells"
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
clock-controller@55 {
reg = <0x55>;
#clock-cells = <0>;
compatible = "silabs,si544b";
};
};

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