mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2025-08-14 19:26:58 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity

Revert "riscv: Select appropriate image type"

Browse Source 
This reverts commit 027a316828 as
discussed in [1].

[1] https://lists.denx.de/pipermail/u-boot/2025-May/590841.html

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Mayuresh Chitale 2025-05-29 03:30:50 +00:00 committed by Leo Yu-Chi Liang
parent 04fcd9a56b
commit 29a2025d77
2 changed files with 4 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/riscv/dts/binman.dtsi
View File

@ -5,12 +5,6 @@
#include <config.h> #include <config.h>
#ifdef CONFIG_64BIT
#define ARCH "riscv64"
#else
#define ARCH "riscv"
#endif
/ { / {
binman: binman { binman: binman {
multiple-images; multiple-images;
@ -37,7 +31,7 @@
description = "U-Boot"; description = "U-Boot";
type = "standalone"; type = "standalone";
os = "U-Boot"; os = "U-Boot";
arch = ARCH; arch = "riscv";
compression = "none"; compression = "none";
load = /bits/ 64 <CONFIG_TEXT_BASE>; load = /bits/ 64 <CONFIG_TEXT_BASE>;
@ -49,7 +43,7 @@
description = "Linux"; description = "Linux";
type = "standalone"; type = "standalone";
os = "Linux"; os = "Linux";
arch = ARCH; arch = "riscv";
compression = "none"; compression = "none";
load = /bits/ 64 <CONFIG_TEXT_BASE>; load = /bits/ 64 <CONFIG_TEXT_BASE>;
@ -62,7 +56,7 @@
tee { tee {
description = "OP-TEE"; description = "OP-TEE";
type = "tee"; type = "tee";
arch = ARCH; arch = "riscv";
compression = "none"; compression = "none";
os = "tee"; os = "tee";
load = /bits/ 64 <CONFIG_SPL_OPTEE_LOAD_ADDR>; load = /bits/ 64 <CONFIG_SPL_OPTEE_LOAD_ADDR>;
@ -76,7 +70,7 @@
description = "OpenSBI fw_dynamic Firmware"; description = "OpenSBI fw_dynamic Firmware";
type = "firmware"; type = "firmware";
os = "opensbi"; os = "opensbi";
arch = ARCH; arch = "riscv";
compression = "none"; compression = "none";
load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>; load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>; entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;

4
arch/riscv/include/asm/u-boot.h
View File

@ -23,10 +23,6 @@
#include <asm/u-boot-riscv.h> #include <asm/u-boot-riscv.h>
/* For image.h:image_check_target_arch() */ /* For image.h:image_check_target_arch() */
#ifdef CONFIG_64BIT
#define IH_ARCH_DEFAULT IH_ARCH_RISCV64
#else
#define IH_ARCH_DEFAULT IH_ARCH_RISCV #define IH_ARCH_DEFAULT IH_ARCH_RISCV
#endif
#endif /* _U_BOOT_H_ */ #endif /* _U_BOOT_H_ */