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arm: mediatek: consolidate ARMv8 memory maps

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Consolidate all mem_map definitions for MediaTek ARMv8 platforms into a
single file. The size of the DDR and MMIO regions can vary, so Kconfig
options are added to configure them by target.

Signed-off-by: David Lechner <dlechner@baylibre.com>
This commit is contained in:
David Lechner 2026-02-09 10:39:31 -06:00 committed by Tom Rini
parent 8b62140738
commit 24ffbb2aa1
16 changed files with 28 additions and 233 deletions
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21
arch/arm/mach-mediatek/Kconfig
View File

@ -130,6 +130,27 @@ config TARGET_MT8518
endchoice
if ARM64
config MTK_MEM_MAP_DDR_SIZE
hex "DDR .size in mem_map"
default 0x200000000 if TARGET_MT7987 || TARGET_MT7988 || TARGET_MT8188
default 0xc0000000 if TARGET_MT8365
default 0x80000000 if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT8183
default 0x40000000 if TARGET_MT7622 || TARGET_MT8512
default 0x20000000
help
Target-specific DDR region size in mem_map.
config MTK_MEM_MAP_MMIO_SIZE
hex "MMIO .size in mem_map"
default 0x40000000 if TARGET_MT7622 || TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7987 || TARGET_MT7988 || TARGET_MT8512
default 0x20000000
help
Target-specific MMIO region size in mem_map.
endif
config SYS_BOARD
string "Board name"
default "mt7622" if TARGET_MT7622

1
arch/arm/mach-mediatek/Makefile
View File

@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_ARM64) += armv8-mem-map.o
obj-y += cpu.o
obj-$(CONFIG_MTK_TZ_MOVABLE) += tzcfg.o
obj-$(CONFIG_XPL_BUILD) += spl.o

16
board/mediatek/mt8365_evk/mt8365_evk.c → arch/arm/mach-mediatek/armv8-mem-map.c
View File

@ -1,28 +1,24 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2023 BayLibre SAS
* Author: Julien Masson <jmasson@baylibre.com>
*/
// SPDX-License-Identifier: GPL-2.0-only
#include <asm/armv8/mmu.h>
static struct mm_region mt8365_evk_mem_map[] = {
static struct mm_region mediatek_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0xc0000000UL,
.size = CONFIG_MTK_MEM_MAP_DDR_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x20000000UL,
.size = CONFIG_MTK_MEM_MAP_MMIO_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
/* List terminator */
}
};
struct mm_region *mem_map = mt8365_evk_mem_map;
struct mm_region *mem_map = mediatek_mem_map;

20
arch/arm/mach-mediatek/mt7622/init.c
View File

@ -36,23 +36,3 @@ void reset_cpu(void)
{
psci_system_reset();
}
static struct mm_region mt7622_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt7622_mem_map;

21
arch/arm/mach-mediatek/mt7981/init.c
View File

@ -30,24 +30,3 @@ void reset_cpu(void)
{
psci_system_reset();
}
static struct mm_region mt7981_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt7981_mem_map;

21
arch/arm/mach-mediatek/mt7986/init.c
View File

@ -30,24 +30,3 @@ void reset_cpu(void)
{
psci_system_reset();
}
static struct mm_region mt7986_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt7986_mem_map;

21
arch/arm/mach-mediatek/mt7987/init.c
View File

@ -39,24 +39,3 @@ void reset_cpu(ulong addr)
{
psci_system_reset();
}
static struct mm_region mt7987_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x200000000ULL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt7987_mem_map;

21
arch/arm/mach-mediatek/mt7988/init.c
View File

@ -38,24 +38,3 @@ void reset_cpu(ulong addr)
{
psci_system_reset();
}
static struct mm_region mt7988_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x200000000ULL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt7988_mem_map;

20
arch/arm/mach-mediatek/mt8183/init.c
View File

@ -47,23 +47,3 @@ int print_cpuinfo(void)
printf("CPU: MediaTek MT8183\n");
return 0;
}
static struct mm_region mt8183_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt8183_mem_map;

21
arch/arm/mach-mediatek/mt8512/init.c
View File

@ -59,24 +59,3 @@ int print_cpuinfo(void)
debug("CPU: MediaTek MT8512\n");
return 0;
}
static struct mm_region mt8512_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt8512_mem_map;

20
arch/arm/mach-mediatek/mt8516/init.c
View File

@ -94,23 +94,3 @@ int print_cpuinfo(void)
printf("CPU: MediaTek MT8516\n");
return 0;
}
static struct mm_region mt8516_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt8516_mem_map;

21
arch/arm/mach-mediatek/mt8518/init.c
View File

@ -51,24 +51,3 @@ int print_cpuinfo(void)
printf("CPU: MediaTek MT8518\n");
return 0;
}
static struct mm_region mt8518_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt8518_mem_map;

2
board/mediatek/MAINTAINERS
View File

@ -1,12 +1,10 @@
MT8365 EVK
M: Julien Masson <jmasson@baylibre.com>
S: Maintained
F: board/mediatek/mt8365_evk/
F: configs/mt8365_evk_defconfig
MT8390 EVK
M: Julien Masson <jmasson@baylibre.com>
M: Macpaul Lin <Macpaul.Lin@mediatek.com>
S: Maintained
F: board/mediatek/mt8390_evk/
F: configs/mt8390_evk_defconfig

3
board/mediatek/mt8365_evk/Makefile
View File

@ -1,3 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += mt8365_evk.o

3
board/mediatek/mt8390_evk/Makefile
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@ -1,3 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += mt8390_evk.o

29
board/mediatek/mt8390_evk/mt8390_evk.c
View File

@ -1,29 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2026 BayLibre SAS
* Author: Julien Masson <jmasson@baylibre.com>
*/
#include <linux/types.h>
#include <asm/armv8/mmu.h>
static struct mm_region mt8390_evk_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x200000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt8390_evk_mem_map;