clk: altera: agilex: Exclude AGILEX_L4_SYS_FREE_CLK from enable/disable operations

AGILEX_L4_SYS_FREE_CLK is a free-running clock with no gate control in
hardware, therefore attempting to enable or disable it is not applicable.

Update the clock driver to explicitly exclude this clock ID from
enable/disable operations by returning -EOPNOTSUPP in bitmask_from_clk_id()
and treating this as a no-op in the socfpga_clk_enable() and
socfpga_clk_disable() functions.

This prevents unnecessary register access for clocks that cannot be gated
and ensures clean handling when the clock is present in the device tree.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

drivers/clk/altera/clk-agilex.c

@@ -729,6 +729,8 @@ static int bitmask_from_clk_id(struct clk *clk)
 		plat->pllgrp = CLKMGR_PERPLL_EN;
 		plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK;
 		break;
+	case AGILEX_L4_SYS_FREE_CLK:
+		return -EOPNOTSUPP;
 	default:
 		return -ENXIO;
 	}
@@ -743,6 +745,9 @@ static int socfpga_clk_enable(struct clk *clk)
 	int ret;
 
 	ret = bitmask_from_clk_id(clk);
+	if (ret == -EOPNOTSUPP)
+		return 0;
+
 	if (ret)
 		return ret;
 
@@ -758,6 +763,9 @@ static int socfpga_clk_disable(struct clk *clk)
 	int ret;
 
 	ret = bitmask_from_clk_id(clk);
+	if (ret == -EOPNOTSUPP)
+		return 0;
+
 	if (ret)
 		return ret;