From d983e503c4824d26c24365f96be2122f29bdff41 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 28 Mar 2022 19:25:26 +0200 Subject: [PATCH 01/40] stm32mp: stm32prog: fix comment Fix "partition" in comment. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 61cba157fdc..d513a60efbd 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -46,7 +46,7 @@ EFI_GUID(0xFD58F1C7, 0xBE0D, 0x4338, \ 0x88, 0xE9, 0xAD, 0x8F, 0x05, 0x0A, 0xEB, 0x18) -/* RAW parttion (binary / bootloader) used Linux - reserved UUID */ +/* RAW partition (binary / bootloader) used Linux - reserved UUID */ #define LINUX_RESERVED_UUID "8DA63339-0007-60C0-C436-083AC8230908" /* From 72450b4b35d0e5be72439a5c2fbcf7b813d90a9a Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 28 Mar 2022 19:25:27 +0200 Subject: [PATCH 02/40] stm32mp: stm32prog: add CONFIG_CMD_STM32PROG_OTP Add a configuration flag CONFIG_CMD_STM32PROG_OTP to enable the support of OTP update in stm32prog command. This new configuration allows to deactivate this feature for security reason and it is a preliminary step for support of OPT update with the OP-TEE provisioning TA. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig | 7 ++ .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 66 +++++++++++-------- 2 files changed, 46 insertions(+), 27 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig index dd166a1f918..81d2b870359 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig @@ -31,3 +31,10 @@ config CMD_STM32PROG_SERIAL activate the command "stm32prog serial" for STM32MP soc family with the tools STM32CubeProgrammer using U-Boot serial device and UART protocol. + +config CMD_STM32PROG_OTP + bool "support stm32prog for OTP update" + depends on CMD_STM32PROG + default y if ARM_SMCCC + help + Support the OTP update with the command "stm32prog" for STM32MP diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index d513a60efbd..3e9354b51d4 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -1154,7 +1154,9 @@ static int dfu_init_entities(struct stm32prog_data *data) struct dfu_entity *dfu; int alt_nb; - alt_nb = 2; /* number of virtual = CMD, OTP*/ + alt_nb = 1; /* number of virtual = CMD*/ + if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) + alt_nb++; /* OTP*/ if (CONFIG_IS_ENABLED(DM_PMIC)) alt_nb++; /* PMIC NVMEM*/ @@ -1205,7 +1207,7 @@ static int dfu_init_entities(struct stm32prog_data *data) if (!ret) ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, CMD_SIZE); - if (!ret) + if (!ret && IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, OTP_SIZE); if (!ret && CONFIG_IS_ENABLED(DM_PMIC)) @@ -1226,6 +1228,11 @@ int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer, { log_debug("%s: %x %lx\n", __func__, offset, *size); + if (!IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { + stm32prog_err("OTP update not supported"); + + return -EOPNOTSUPP; + } if (!data->otp_part) { data->otp_part = memalign(CONFIG_SYS_CACHELINE_SIZE, OTP_SIZE); if (!data->otp_part) @@ -1248,10 +1255,10 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer, { int result = 0; - if (!IS_ENABLED(CONFIG_ARM_SMCCC)) { + if (!IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { stm32prog_err("OTP update not supported"); - return -1; + return -EOPNOTSUPP; } log_debug("%s: %x %lx\n", __func__, offset, *size); @@ -1270,8 +1277,10 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer, memset(data->otp_part, 0, OTP_SIZE); /* call the service */ - result = stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_READ_ALL, - (u32)data->otp_part, 0); + result = -EOPNOTSUPP; + if (IS_ENABLED(CONFIG_ARM_SMCCC)) + result = stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_READ_ALL, + (u32)data->otp_part, 0); if (result) goto end_otp_read; } @@ -1296,10 +1305,10 @@ int stm32prog_otp_start(struct stm32prog_data *data) int result = 0; struct arm_smccc_res res; - if (!IS_ENABLED(CONFIG_ARM_SMCCC)) { + if (!IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { stm32prog_err("OTP update not supported"); - return -1; + return -EOPNOTSUPP; } if (!data->otp_part) { @@ -1307,28 +1316,31 @@ int stm32prog_otp_start(struct stm32prog_data *data) return -1; } - arm_smccc_smc(STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, - (u32)data->otp_part, 0, 0, 0, 0, 0, &res); + result = -EOPNOTSUPP; + if (IS_ENABLED(CONFIG_ARM_SMCCC)) { + arm_smccc_smc(STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, + (u32)data->otp_part, 0, 0, 0, 0, 0, &res); - if (!res.a0) { - switch (res.a1) { - case 0: - result = 0; - break; - case 1: - stm32prog_err("Provisioning"); - result = 0; - break; - default: - log_err("%s: OTP incorrect value (err = %ld)\n", - __func__, res.a1); + if (!res.a0) { + switch (res.a1) { + case 0: + result = 0; + break; + case 1: + stm32prog_err("Provisioning"); + result = 0; + break; + default: + log_err("%s: OTP incorrect value (err = %ld)\n", + __func__, res.a1); + result = -EINVAL; + break; + } + } else { + log_err("%s: Failed to exec svc=%x op=%x in secure mode (err = %ld)\n", + __func__, STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, res.a0); result = -EINVAL; - break; } - } else { - log_err("%s: Failed to exec svc=%x op=%x in secure mode (err = %ld)\n", - __func__, STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, res.a0); - result = -EINVAL; } free(data->otp_part); From e82ab4c8906fc2e1e42065e4207ff0c36f343553 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 28 Mar 2022 19:25:28 +0200 Subject: [PATCH 03/40] stm32mp: stm32prog: add TEE support in stm32prog command When OP-TEE is used, the SMC for BSEC management are not available and the PTA provisioning for OTP must be used. U-Boot opens the session to this PTA and use it for OTP access. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig | 2 +- .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 145 ++++++++++++++++-- .../mach-stm32mp/cmd_stm32prog/stm32prog.h | 7 +- .../cmd_stm32prog/stm32prog_usb.c | 2 +- 4 files changed, 142 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig index 81d2b870359..8f91db4b46b 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig @@ -35,6 +35,6 @@ config CMD_STM32PROG_SERIAL config CMD_STM32PROG_OTP bool "support stm32prog for OTP update" depends on CMD_STM32PROG - default y if ARM_SMCCC + default y if ARM_SMCCC || OPTEE help Support the OTP update with the command "stm32prog" for STM32MP diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 3e9354b51d4..5d53e6146fb 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -10,8 +10,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -79,8 +81,110 @@ struct fip_toc_header { u64 flags; }; +#define TA_NVMEM_UUID { 0x1a8342cc, 0x81a5, 0x4512, \ + { 0x99, 0xfe, 0x9e, 0x2b, 0x3e, 0x37, 0xd6, 0x26 } } + +/* + * Read NVMEM memory for STM32CubeProgrammer + * + * [in] value[0].a: Type (0 for OTP access) + * [out] memref[1].buffer Output buffer to return all read values + * [out] memref[1].size Size of buffer to be read + * + * Return codes: + * TEE_SUCCESS - Invoke command success + * TEE_ERROR_BAD_PARAMETERS - Incorrect input param + */ +#define TA_NVMEM_READ 0x0 + +/* + * Write NVMEM memory for STM32CubeProgrammer + * + * [in] value[0].a Type (0 for OTP access) + * [in] memref[1].buffer Input buffer with the values to write + * [in] memref[1].size Size of buffer to be written + * + * Return codes: + * TEE_SUCCESS - Invoke command success + * TEE_ERROR_BAD_PARAMETERS - Incorrect input param + */ +#define TA_NVMEM_WRITE 0x1 + +/* value of TA_NVMEM type = value[in] a */ +#define NVMEM_OTP 0 + DECLARE_GLOBAL_DATA_PTR; +/* OPTEE TA NVMEM open helper */ +static int optee_ta_open(struct stm32prog_data *data) +{ + const struct tee_optee_ta_uuid uuid = TA_NVMEM_UUID; + struct tee_open_session_arg arg; + struct udevice *tee = NULL; + int rc; + + if (data->tee) + return 0; + + tee = tee_find_device(NULL, NULL, NULL, NULL); + if (!tee) + return -ENODEV; + + memset(&arg, 0, sizeof(arg)); + tee_optee_ta_uuid_to_octets(arg.uuid, &uuid); + rc = tee_open_session(tee, &arg, 0, NULL); + if (rc < 0) + return -ENODEV; + + data->tee = tee; + data->tee_session = arg.session; + + return 0; +} + +/* OPTEE TA NVMEM invoke helper */ +static int optee_ta_invoke(struct stm32prog_data *data, int cmd, int type, + void *buff, ulong size) +{ + struct tee_invoke_arg arg; + struct tee_param param[2]; + struct tee_shm *buff_shm; + int rc; + + rc = tee_shm_register(data->tee, buff, size, 0, &buff_shm); + if (rc) + return rc; + + memset(&arg, 0, sizeof(arg)); + arg.func = cmd; + arg.session = data->tee_session; + + memset(param, 0, sizeof(param)); + param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INPUT; + param[0].u.value.a = type; + + if (cmd == TA_NVMEM_WRITE) + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + else + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_OUTPUT; + + param[1].u.memref.shm = buff_shm; + param[1].u.memref.size = size; + + rc = tee_invoke_func(data->tee, &arg, 2, param); + if (rc < 0 || arg.ret != 0) { + dev_err(data->tee, + "TA_NVMEM invoke failed TEE err: %x, err:%x\n", + arg.ret, rc); + if (!rc) + rc = -EIO; + } + + tee_shm_free(buff_shm); + + return rc; +} + /* partition handling routines : CONFIG_CMD_MTDPARTS */ int mtdparts_init(void); int find_dev_and_part(const char *id, struct mtd_device **dev, @@ -1208,7 +1312,11 @@ static int dfu_init_entities(struct stm32prog_data *data) ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, CMD_SIZE); if (!ret && IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { - ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, OTP_SIZE); + ret = optee_ta_open(data); + log_debug("optee_ta result %d\n", ret); + ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, + data->tee ? OTP_SIZE_TA : OTP_SIZE_SMC); + } if (!ret && CONFIG_IS_ENABLED(DM_PMIC)) ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, PMIC_SIZE); @@ -1226,6 +1334,7 @@ static int dfu_init_entities(struct stm32prog_data *data) int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer, long *size) { + u32 otp_size = data->tee ? OTP_SIZE_TA : OTP_SIZE_SMC; log_debug("%s: %x %lx\n", __func__, offset, *size); if (!IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { @@ -1233,17 +1342,18 @@ int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer, return -EOPNOTSUPP; } + if (!data->otp_part) { - data->otp_part = memalign(CONFIG_SYS_CACHELINE_SIZE, OTP_SIZE); + data->otp_part = memalign(CONFIG_SYS_CACHELINE_SIZE, otp_size); if (!data->otp_part) return -ENOMEM; } if (!offset) - memset(data->otp_part, 0, OTP_SIZE); + memset(data->otp_part, 0, otp_size); - if (offset + *size > OTP_SIZE) - *size = OTP_SIZE - offset; + if (offset + *size > otp_size) + *size = otp_size - offset; memcpy((void *)((u32)data->otp_part + offset), buffer, *size); @@ -1253,6 +1363,7 @@ int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer, int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer, long *size) { + u32 otp_size = data->tee ? OTP_SIZE_TA : OTP_SIZE_SMC; int result = 0; if (!IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { @@ -1266,7 +1377,7 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer, if (!offset) { if (!data->otp_part) data->otp_part = - memalign(CONFIG_SYS_CACHELINE_SIZE, OTP_SIZE); + memalign(CONFIG_SYS_CACHELINE_SIZE, otp_size); if (!data->otp_part) { result = -ENOMEM; @@ -1274,11 +1385,14 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer, } /* init struct with 0 */ - memset(data->otp_part, 0, OTP_SIZE); + memset(data->otp_part, 0, otp_size); /* call the service */ result = -EOPNOTSUPP; - if (IS_ENABLED(CONFIG_ARM_SMCCC)) + if (data->tee && CONFIG_IS_ENABLED(OPTEE)) + result = optee_ta_invoke(data, TA_NVMEM_READ, NVMEM_OTP, + data->otp_part, OTP_SIZE_TA); + else if (IS_ENABLED(CONFIG_ARM_SMCCC)) result = stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_READ_ALL, (u32)data->otp_part, 0); if (result) @@ -1290,8 +1404,8 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer, goto end_otp_read; } - if (offset + *size > OTP_SIZE) - *size = OTP_SIZE - offset; + if (offset + *size > otp_size) + *size = otp_size - offset; memcpy(buffer, (void *)((u32)data->otp_part + offset), *size); end_otp_read: @@ -1317,7 +1431,10 @@ int stm32prog_otp_start(struct stm32prog_data *data) } result = -EOPNOTSUPP; - if (IS_ENABLED(CONFIG_ARM_SMCCC)) { + if (data->tee && CONFIG_IS_ENABLED(OPTEE)) { + result = optee_ta_invoke(data, TA_NVMEM_WRITE, NVMEM_OTP, + data->otp_part, OTP_SIZE_TA); + } else if (IS_ENABLED(CONFIG_ARM_SMCCC)) { arm_smccc_smc(STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, (u32)data->otp_part, 0, 0, 0, 0, 0, &res); @@ -1751,6 +1868,12 @@ void stm32prog_clean(struct stm32prog_data *data) free(data->part_array); free(data->otp_part); free(data->buffer); + + if (CONFIG_IS_ENABLED(OPTEE) && data->tee) { + tee_close_session(data->tee, data->tee_session); + data->tee = NULL; + data->tee_session = 0x0; + } } /* DFU callback: used after serial and direct DFU USB access */ diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h index 240c5c44bcb..928b7b3a0e2 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -20,7 +20,8 @@ #define DEFAULT_ADDRESS 0xFFFFFFFF #define CMD_SIZE 512 -#define OTP_SIZE 1024 +#define OTP_SIZE_SMC 1024 +#define OTP_SIZE_TA 776 #define PMIC_SIZE 8 enum stm32prog_target { @@ -147,6 +148,10 @@ struct stm32prog_data { u32 dtb; u32 initrd; u32 initrd_size; + + /* OPTEE PTA NVMEM */ + struct udevice *tee; + u32 tee_session; }; extern struct stm32prog_data *stm32prog_data; diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c index e8acc302f9e..82b702f93b2 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c @@ -181,7 +181,7 @@ int stm32prog_get_medium_size_virt(struct dfu_entity *dfu, u64 *size) *size = CMD_SIZE; break; case PHASE_OTP: - *size = OTP_SIZE; + *size = stm32prog_data->tee ? OTP_SIZE_TA : OTP_SIZE_SMC; break; case PHASE_PMIC: *size = PMIC_SIZE; From 49d0ecb1231dd7f8558ede64cb724e43189cfcd3 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 28 Mar 2022 19:25:29 +0200 Subject: [PATCH 04/40] stm32mp: stm32prog: add support of STM32IMAGE version 2 Add support of new header for the STM32IMAGE version V2 in command stm32prog command for STM32MP13x family. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- .../cmd_stm32prog/cmd_stm32prog.c | 8 +- .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 131 ++++++++++++------ .../mach-stm32mp/cmd_stm32prog/stm32prog.h | 35 +++-- 3 files changed, 120 insertions(+), 54 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index 41452b5a290..3957e06e5d9 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -73,15 +73,15 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, /* check STM32IMAGE presence */ if (size == 0) { - stm32prog_header_check((struct raw_header_s *)addr, &header); + stm32prog_header_check(addr, &header); if (header.type == HEADER_STM32IMAGE) { - size = header.image_length + BL_HEADER_SIZE; + size = header.image_length + header.length; #if defined(CONFIG_LEGACY_IMAGE_FORMAT) /* uImage detected in STM32IMAGE, execute the script */ if (IMAGE_FORMAT_LEGACY == - genimg_get_format((void *)(addr + BL_HEADER_SIZE))) - return image_source_script(addr + BL_HEADER_SIZE, "script@1"); + genimg_get_format((void *)(addr + header.length))) + return image_source_script(addr + header.length, "script@1"); #endif } } diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 5d53e6146fb..3e1fdee5b38 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -205,52 +205,98 @@ static bool stm32prog_is_fip_header(struct fip_toc_header *header) return (header->name == FIP_TOC_HEADER_NAME) && header->serial_number; } -void stm32prog_header_check(struct raw_header_s *raw_header, - struct image_header_s *header) +static bool stm32prog_is_stm32_header_v1(struct stm32_header_v1 *header) { unsigned int i; + if (header->magic_number != + (('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) { + log_debug("%s:invalid magic number : 0x%x\n", + __func__, header->magic_number); + return false; + } + if (header->header_version != 0x00010000) { + log_debug("%s:invalid header version : 0x%x\n", + __func__, header->header_version); + return false; + } + + if (header->reserved1 || header->reserved2) { + log_debug("%s:invalid reserved field\n", __func__); + return false; + } + for (i = 0; i < sizeof(header->padding); i++) { + if (header->padding[i] != 0) { + log_debug("%s:invalid padding field\n", __func__); + return false; + } + } + + return true; +} + +static bool stm32prog_is_stm32_header_v2(struct stm32_header_v2 *header) +{ + unsigned int i; + + if (header->magic_number != + (('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) { + log_debug("%s:invalid magic number : 0x%x\n", + __func__, header->magic_number); + return false; + } + if (header->header_version != 0x00020000) { + log_debug("%s:invalid header version : 0x%x\n", + __func__, header->header_version); + return false; + } + if (header->reserved1 || header->reserved2) + return false; + + for (i = 0; i < sizeof(header->padding); i++) { + if (header->padding[i] != 0) { + log_debug("%s:invalid padding field\n", __func__); + return false; + } + } + + return true; +} + +void stm32prog_header_check(uintptr_t raw_header, struct image_header_s *header) +{ + struct stm32_header_v1 *v1_header = (struct stm32_header_v1 *)raw_header; + struct stm32_header_v2 *v2_header = (struct stm32_header_v2 *)raw_header; + if (!raw_header || !header) { log_debug("%s:no header data\n", __func__); return; } + if (stm32prog_is_fip_header((struct fip_toc_header *)raw_header)) { + header->type = HEADER_FIP; + header->length = 0; + return; + } + if (stm32prog_is_stm32_header_v1(v1_header)) { + header->type = HEADER_STM32IMAGE; + header->image_checksum = le32_to_cpu(v1_header->image_checksum); + header->image_length = le32_to_cpu(v1_header->image_length); + header->length = sizeof(struct stm32_header_v1); + return; + } + if (stm32prog_is_stm32_header_v2(v2_header)) { + header->type = HEADER_STM32IMAGE_V2; + header->image_checksum = le32_to_cpu(v2_header->image_checksum); + header->image_length = le32_to_cpu(v2_header->image_length); + header->length = sizeof(struct stm32_header_v1) + + v2_header->extension_headers_length; + return; + } + header->type = HEADER_NONE; header->image_checksum = 0x0; header->image_length = 0x0; - - if (stm32prog_is_fip_header((struct fip_toc_header *)raw_header)) { - header->type = HEADER_FIP; - return; - } - - if (raw_header->magic_number != - (('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) { - log_debug("%s:invalid magic number : 0x%x\n", - __func__, raw_header->magic_number); - return; - } - /* only header v1.0 supported */ - if (raw_header->header_version != 0x00010000) { - log_debug("%s:invalid header version : 0x%x\n", - __func__, raw_header->header_version); - return; - } - if (raw_header->reserved1 != 0x0 || raw_header->reserved2) { - log_debug("%s:invalid reserved field\n", __func__); - return; - } - for (i = 0; i < (sizeof(raw_header->padding) / 4); i++) { - if (raw_header->padding[i] != 0) { - log_debug("%s:invalid padding field\n", __func__); - return; - } - } - header->type = HEADER_STM32IMAGE; - header->image_checksum = le32_to_cpu(raw_header->image_checksum); - header->image_length = le32_to_cpu(raw_header->image_length); - - return; } static u32 stm32prog_header_checksum(u32 addr, struct image_header_s *header) @@ -480,11 +526,11 @@ static int parse_flash_layout(struct stm32prog_data *data, data->part_nb = 0; /* check if STM32image is detected */ - stm32prog_header_check((struct raw_header_s *)addr, &header); + stm32prog_header_check(addr, &header); if (header.type == HEADER_STM32IMAGE) { u32 checksum; - addr = addr + BL_HEADER_SIZE; + addr = addr + header.length; size = header.image_length; checksum = stm32prog_header_checksum(addr, &header); @@ -1560,7 +1606,7 @@ static int stm32prog_copy_fsbl(struct stm32prog_part_t *part) int ret, i; void *fsbl; struct image_header_s header; - struct raw_header_s raw_header; + struct stm32_header_v2 raw_header; /* V2 size > v1 size */ struct dfu_entity *dfu; long size, offset; @@ -1572,17 +1618,18 @@ static int stm32prog_copy_fsbl(struct stm32prog_part_t *part) /* read header */ dfu_transaction_cleanup(dfu); - size = BL_HEADER_SIZE; + size = sizeof(raw_header); ret = dfu->read_medium(dfu, 0, (void *)&raw_header, &size); if (ret) return ret; - stm32prog_header_check(&raw_header, &header); - if (header.type != HEADER_STM32IMAGE) + stm32prog_header_check((ulong)&raw_header, &header); + if (header.type != HEADER_STM32IMAGE && + header.type != HEADER_STM32IMAGE_V2) return -ENOENT; /* read header + payload */ - size = header.image_length + BL_HEADER_SIZE; + size = header.image_length + header.length; size = round_up(size, part->dev->mtd->erasesize); fsbl = calloc(1, size); if (!fsbl) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h index 928b7b3a0e2..90cdc2ba476 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -42,6 +42,7 @@ enum stm32prog_link_t { enum stm32prog_header_t { HEADER_NONE, HEADER_STM32IMAGE, + HEADER_STM32IMAGE_V2, HEADER_FIP, }; @@ -49,11 +50,12 @@ struct image_header_s { enum stm32prog_header_t type; u32 image_checksum; u32 image_length; + u32 length; }; -struct raw_header_s { +struct stm32_header_v1 { u32 magic_number; - u32 image_signature[64 / 4]; + u8 image_signature[64]; u32 image_checksum; u32 header_version; u32 image_length; @@ -64,12 +66,30 @@ struct raw_header_s { u32 version_number; u32 option_flags; u32 ecdsa_algorithm; - u32 ecdsa_public_key[64 / 4]; - u32 padding[83 / 4]; - u32 binary_type; + u8 ecdsa_public_key[64]; + u8 padding[83]; + u8 binary_type; }; -#define BL_HEADER_SIZE sizeof(struct raw_header_s) +struct stm32_header_v2 { + u32 magic_number; + u8 image_signature[64]; + u32 image_checksum; + u32 header_version; + u32 image_length; + u32 image_entry_point; + u32 reserved1; + u32 load_address; + u32 reserved2; + u32 version_number; + u32 extension_flags; + u32 extension_headers_length; + u32 binary_type; + u8 padding[16]; + u32 extension_header_type; + u32 extension_header_length; + u8 extension_padding[376]; +}; /* partition type in flashlayout file */ enum stm32prog_part_type { @@ -171,8 +191,7 @@ int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, int stm32prog_pmic_start(struct stm32prog_data *data); /* generic part*/ -void stm32prog_header_check(struct raw_header_s *raw_header, - struct image_header_s *header); +void stm32prog_header_check(uintptr_t raw_header, struct image_header_s *header); int stm32prog_dfu_init(struct stm32prog_data *data); void stm32prog_next_phase(struct stm32prog_data *data); void stm32prog_do_reset(struct stm32prog_data *data); From 2a4fe0ee48f83e63afcda146b85e23811e147393 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 28 Mar 2022 19:25:30 +0200 Subject: [PATCH 05/40] stm32mp: stm32prog: add support of UUID for FIP partition Add support of UUID for FIP parttion, required by Firmware update support in TF-A: - UUID TYPE for FIP partition: 19d5df83-11b0-457b-be2c-7559c13142a5 - "fip-a" partition UUID: 4fd84c93-54ef-463f-a7ef-ae25ff887087 - "fip-b" partition UUID: 09c54952-d5bf-45af-acee-335303766fb3 This check is done with a new partition type "FIP" associated at the FIP UUID. The A/B partition UUID is detected by the partition name: "fip-a", "fip-b". Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 76 ++++++++++++++----- .../mach-stm32mp/cmd_stm32prog/stm32prog.h | 3 +- 2 files changed, 59 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 3e1fdee5b38..d3b3e1ed727 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -62,6 +62,28 @@ static const efi_guid_t uuid_mmc[3] = { ROOTFS_MMC2_UUID }; +/* FIP type partition UUID used by TF-A*/ +#define FIP_TYPE_UUID "19D5DF83-11B0-457B-BE2C-7559C13142A5" + +/* unique partition guid (uuid) for FIP partitions A/B */ +#define FIP_A_UUID \ + EFI_GUID(0x4FD84C93, 0x54EF, 0x463F, \ + 0xA7, 0xEF, 0xAE, 0x25, 0xFF, 0x88, 0x70, 0x87) + +#define FIP_B_UUID \ + EFI_GUID(0x09C54952, 0xD5BF, 0x45AF, \ + 0xAC, 0xEE, 0x33, 0x53, 0x03, 0x76, 0x6F, 0xB3) + +static const char * const fip_part_name[] = { + "fip-a", + "fip-b" +}; + +static const efi_guid_t fip_part_uuid[] = { + FIP_A_UUID, + FIP_B_UUID +}; + /* order of column in flash layout file */ enum stm32prog_col_t { COL_OPTION, @@ -405,6 +427,8 @@ static int parse_type(struct stm32prog_data *data, part->bin_nb = dectoul(&p[7], NULL); } + } else if (!strcmp(p, "FIP")) { + part->part_type = PART_FIP; } else if (!strcmp(p, "System")) { part->part_type = PART_SYSTEM; } else if (!strcmp(p, "FileSystem")) { @@ -1056,9 +1080,10 @@ static int create_gpt_partitions(struct stm32prog_data *data) char uuid[UUID_STR_LEN + 1]; unsigned char *uuid_bin; unsigned int mmc_id; - int i; + int i, j; bool rootfs_found; struct stm32prog_part_t *part; + const char *type_str; buf = malloc(buflen); if (!buf) @@ -1100,33 +1125,46 @@ static int create_gpt_partitions(struct stm32prog_data *data) part->addr, part->size); - if (part->part_type == PART_BINARY) - offset += snprintf(buf + offset, - buflen - offset, - ",type=" - LINUX_RESERVED_UUID); - else - offset += snprintf(buf + offset, - buflen - offset, - ",type=linux"); + switch (part->part_type) { + case PART_BINARY: + type_str = LINUX_RESERVED_UUID; + break; + case PART_FIP: + type_str = FIP_TYPE_UUID; + break; + default: + type_str = "linux"; + break; + } + offset += snprintf(buf + offset, + buflen - offset, + ",type=%s", type_str); if (part->part_type == PART_SYSTEM) offset += snprintf(buf + offset, buflen - offset, ",bootable"); + /* partition UUID */ + uuid_bin = NULL; if (!rootfs_found && !strcmp(part->name, "rootfs")) { mmc_id = part->dev_id; rootfs_found = true; - if (mmc_id < ARRAY_SIZE(uuid_mmc)) { - uuid_bin = - (unsigned char *)uuid_mmc[mmc_id].b; - uuid_bin_to_str(uuid_bin, uuid, - UUID_STR_FORMAT_GUID); - offset += snprintf(buf + offset, - buflen - offset, - ",uuid=%s", uuid); - } + if (mmc_id < ARRAY_SIZE(uuid_mmc)) + uuid_bin = (unsigned char *)uuid_mmc[mmc_id].b; + } + if (part->part_type == PART_FIP) { + for (j = 0; j < ARRAY_SIZE(fip_part_name); j++) + if (!strcmp(part->name, fip_part_name[j])) { + uuid_bin = (unsigned char *)fip_part_uuid[j].b; + break; + } + } + if (uuid_bin) { + uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID); + offset += snprintf(buf + offset, + buflen - offset, + ",uuid=%s", uuid); } offset += snprintf(buf + offset, buflen - offset, ";"); diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h index 90cdc2ba476..b3e5c748105 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -94,9 +94,10 @@ struct stm32_header_v2 { /* partition type in flashlayout file */ enum stm32prog_part_type { PART_BINARY, + PART_FIP, PART_SYSTEM, PART_FILESYSTEM, - RAW_IMAGE + RAW_IMAGE, }; /* device information */ From 7f1121a85a5c68a0df137d0b161184a39a583ad2 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 28 Mar 2022 19:25:31 +0200 Subject: [PATCH 06/40] stm32mp: stm32prog: handle interruption during the first enumeration When an interruption is received during the first USB enumeration used to received the FlashLayout, with handle ctrl-c, the second enumeration is not needed and the result for stm32prog_usb_loop is false (reset is not needed). This patch avoids the need of a second ctrl to interrupt the command stm32prog. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c index 82b702f93b2..a8b57c4d8f0 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c @@ -206,9 +206,12 @@ bool stm32prog_usb_loop(struct stm32prog_data *data, int dev) g_dnl_set_product(product); if (stm32prog_data->phase == PHASE_FLASHLAYOUT) { + /* forget any previous Control C */ + clear_ctrlc(); ret = run_usb_dnl_gadget(dev, "usb_dnl_dfu"); - if (ret || stm32prog_data->phase != PHASE_FLASHLAYOUT) - return ret; + /* DFU reset received, no error or CtrlC */ + if (ret || stm32prog_data->phase != PHASE_FLASHLAYOUT || had_ctrlc()) + return ret; /* true = reset on DFU error */ /* prepare the second enumeration with the FlashLayout */ stm32prog_dfu_init(data); } From 152576a598cad749c80c589a51ea5bd342d6f2cc Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 28 Mar 2022 19:25:32 +0200 Subject: [PATCH 07/40] stm32mp: stm32prog: handle U-Boot script in flashlayout alternate Update the stm32prog command to allow the reception of U-Boot script in the FlashLayout alternate during the first USB enumeration. This patch is aligned with the last TF-A behavior: the Flashlayout is now loaded by U-Boot; it is no more present at STM32_DDR_BASE when the stm32prog is launched after a serial boot, on UART or on USB. The received script must be a U-Boot legacy image, no more need to add a stm32image header. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c | 9 ++------- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 9 +++++++++ arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h | 2 ++ 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index 3957e06e5d9..f59414e716f 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -76,13 +76,6 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, stm32prog_header_check(addr, &header); if (header.type == HEADER_STM32IMAGE) { size = header.image_length + header.length; - -#if defined(CONFIG_LEGACY_IMAGE_FORMAT) - /* uImage detected in STM32IMAGE, execute the script */ - if (IMAGE_FORMAT_LEGACY == - genimg_get_format((void *)(addr + header.length))) - return image_source_script(addr + header.length, "script@1"); -#endif } } @@ -160,6 +153,8 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, else if (CONFIG_IS_ENABLED(CMD_BOOTZ)) do_bootz(cmdtp, 0, 4, bootm_argv); } + if (data->script) + image_source_script(data->script, "script@stm32prog"); if (reset) { puts("Reset...\n"); diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index d3b3e1ed727..65655e25ca7 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -1697,6 +1698,14 @@ error: static void stm32prog_end_phase(struct stm32prog_data *data, u64 offset) { if (data->phase == PHASE_FLASHLAYOUT) { +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) + if (genimg_get_format((void *)STM32_DDR_BASE) == IMAGE_FORMAT_LEGACY) { + data->script = STM32_DDR_BASE; + data->phase = PHASE_END; + log_notice("U-Boot script received\n"); + return; + } +#endif if (parse_flash_layout(data, STM32_DDR_BASE, 0)) stm32prog_err("Layout: invalid FlashLayout"); return; diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h index b3e5c748105..ac300768ca0 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -170,6 +170,8 @@ struct stm32prog_data { u32 initrd; u32 initrd_size; + u32 script; + /* OPTEE PTA NVMEM */ struct udevice *tee; u32 tee_session; From a9fed5aac5c6da9763fdc5d10fd83299d63b7c24 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 28 Mar 2022 19:25:33 +0200 Subject: [PATCH 08/40] stm32mp: stm32prog: handle flashlayout without STM32 image header Accept flashlayout without header in alternate 0, to simplify the support of stm32prog command with dfu-util. By default the flashlayout file size is the size of the received binary, provided with the offset in the DFU alternate. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 65655e25ca7..b7111123ba9 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -1706,7 +1706,8 @@ static void stm32prog_end_phase(struct stm32prog_data *data, u64 offset) return; } #endif - if (parse_flash_layout(data, STM32_DDR_BASE, 0)) + log_notice("\nFlashLayout received, size = %lld\n", offset); + if (parse_flash_layout(data, STM32_DDR_BASE, offset)) stm32prog_err("Layout: invalid FlashLayout"); return; } From ef4ce6df3289f4ea8d55e093289bd39181385aac Mon Sep 17 00:00:00 2001 From: Yannick FERTRE Date: Wed, 6 Apr 2022 10:37:42 +0200 Subject: [PATCH 09/40] video: stm32: stm32_ltdc: fix data enable polarity Wrong DISPLAY_FLAGS used to set the data enable polarity. Signed-off-by: Yannick FERTRE Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- drivers/video/stm32/stm32_ltdc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index e741e74739c..9269d4bfb4c 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -255,7 +255,7 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv, val |= GCR_HSPOL; if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH) val |= GCR_VSPOL; - if (timings->flags & DISPLAY_FLAGS_DE_HIGH) + if (timings->flags & DISPLAY_FLAGS_DE_LOW) val |= GCR_DEPOL; if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) val |= GCR_PCPOL; From 13dc7562b67c82a31fa80f6e855018d803b7c7b3 Mon Sep 17 00:00:00 2001 From: Yannick Fertre Date: Wed, 6 Apr 2022 10:41:35 +0200 Subject: [PATCH 10/40] video: stm32: stm32_ltdc: support several hardware versions Register mapping & pixel formats depend on version of ltdc display controller. Signed-off-by: Yannick Fertre Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- drivers/video/stm32/stm32_ltdc.c | 245 +++++++++++++++++++++++++++---- 1 file changed, 216 insertions(+), 29 deletions(-) diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index 9269d4bfb4c..58b6434a485 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -25,8 +25,114 @@ struct stm32_ltdc_priv { void __iomem *regs; enum video_log2_bpp l2bpp; u32 bg_col_argb; + const u32 *layer_regs; + const u32 *pix_fmt_hw; u32 crop_x, crop_y, crop_w, crop_h; u32 alpha; + u32 hw_version; +}; + +/* Layer register offsets */ +static const u32 layer_regs_a0[] = { + 0x80, /* L1 configuration 0 */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x84, /* L1 control register */ + 0x88, /* L1 window horizontal position configuration */ + 0x8c, /* L1 window vertical position configuration */ + 0x90, /* L1 color keying configuration */ + 0x94, /* L1 pixel format configuration */ + 0x98, /* L1 constant alpha configuration */ + 0x9c, /* L1 default color configuration */ + 0xa0, /* L1 blending factors configuration */ + 0x00, /* not available */ + 0x00, /* not available */ + 0xac, /* L1 color frame buffer address */ + 0xb0, /* L1 color frame buffer length */ + 0xb4, /* L1 color frame buffer line number */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0xc4, /* L1 CLUT write */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00 /* not available */ +}; + +static const u32 layer_regs_a1[] = { + 0x80, /* L1 configuration 0 */ + 0x84, /* L1 configuration 1 */ + 0x00, /* L1 reload control */ + 0x88, /* L1 control register */ + 0x8c, /* L1 window horizontal position configuration */ + 0x90, /* L1 window vertical position configuration */ + 0x94, /* L1 color keying configuration */ + 0x98, /* L1 pixel format configuration */ + 0x9c, /* L1 constant alpha configuration */ + 0xa0, /* L1 default color configuration */ + 0xa4, /* L1 blending factors configuration */ + 0xa8, /* L1 burst length configuration */ + 0x00, /* not available */ + 0xac, /* L1 color frame buffer address */ + 0xb0, /* L1 color frame buffer length */ + 0xb4, /* L1 color frame buffer line number */ + 0xb8, /* L1 auxiliary frame buffer address 0 */ + 0xbc, /* L1 auxiliary frame buffer address 1 */ + 0xc0, /* L1 auxiliary frame buffer length */ + 0xc4, /* L1 auxiliary frame buffer line number */ + 0xc8, /* L1 CLUT write */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00 /* not available */ +}; + +static const u32 layer_regs_a2[] = { + 0x100, /* L1 configuration 0 */ + 0x104, /* L1 configuration 1 */ + 0x108, /* L1 reload control */ + 0x10c, /* L1 control register */ + 0x110, /* L1 window horizontal position configuration */ + 0x114, /* L1 window vertical position configuration */ + 0x118, /* L1 color keying configuration */ + 0x11c, /* L1 pixel format configuration */ + 0x120, /* L1 constant alpha configuration */ + 0x124, /* L1 default color configuration */ + 0x128, /* L1 blending factors configuration */ + 0x12c, /* L1 burst length configuration */ + 0x130, /* L1 planar configuration */ + 0x134, /* L1 color frame buffer address */ + 0x138, /* L1 color frame buffer length */ + 0x13c, /* L1 color frame buffer line number */ + 0x140, /* L1 auxiliary frame buffer address 0 */ + 0x144, /* L1 auxiliary frame buffer address 1 */ + 0x148, /* L1 auxiliary frame buffer length */ + 0x14c, /* L1 auxiliary frame buffer line number */ + 0x150, /* L1 CLUT write */ + 0x154, /* not available */ + 0x158, /* not available */ + 0x15c, /* not available */ + 0x160, /* not available */ + 0x164, /* not available */ + 0x168, /* not available */ + 0x16c, /* L1 Conversion YCbCr RGB 0 */ + 0x170, /* L1 Conversion YCbCr RGB 1 */ + 0x174, /* L1 Flexible Pixel Format 0 */ + 0x178 /* L1 Flexible Pixel Format 1 */ }; /* LTDC main registers */ @@ -49,26 +155,32 @@ struct stm32_ltdc_priv { #define LTDC_CPSR 0x44 /* Current Position Status */ #define LTDC_CDSR 0x48 /* Current Display Status */ -/* LTDC layer 1 registers */ -#define LTDC_L1LC1R 0x80 /* L1 Layer Configuration 1 */ -#define LTDC_L1LC2R 0x84 /* L1 Layer Configuration 2 */ -#define LTDC_L1CR 0x84 /* L1 Control */ -#define LTDC_L1WHPCR 0x88 /* L1 Window Hor Position Config */ -#define LTDC_L1WVPCR 0x8C /* L1 Window Vert Position Config */ -#define LTDC_L1CKCR 0x90 /* L1 Color Keying Configuration */ -#define LTDC_L1PFCR 0x94 /* L1 Pixel Format Configuration */ -#define LTDC_L1CACR 0x98 /* L1 Constant Alpha Config */ -#define LTDC_L1DCCR 0x9C /* L1 Default Color Configuration */ -#define LTDC_L1BFCR 0xA0 /* L1 Blend Factors Configuration */ -#define LTDC_L1FBBCR 0xA4 /* L1 FrameBuffer Bus Control */ -#define LTDC_L1AFBCR 0xA8 /* L1 AuxFB Control */ -#define LTDC_L1CFBAR 0xAC /* L1 Color FrameBuffer Address */ -#define LTDC_L1CFBLR 0xB0 /* L1 Color FrameBuffer Length */ -#define LTDC_L1CFBLNR 0xB4 /* L1 Color FrameBuffer Line Nb */ -#define LTDC_L1AFBAR 0xB8 /* L1 AuxFB Address */ -#define LTDC_L1AFBLR 0xBC /* L1 AuxFB Length */ -#define LTDC_L1AFBLNR 0xC0 /* L1 AuxFB Line Number */ -#define LTDC_L1CLUTWR 0xC4 /* L1 CLUT Write */ +/* Layer register offsets */ +#define LTDC_L1C0R (priv->layer_regs[0]) /* L1 configuration 0 */ +#define LTDC_L1C1R (priv->layer_regs[1]) /* L1 configuration 1 */ +#define LTDC_L1RCR (priv->layer_regs[2]) /* L1 reload control */ +#define LTDC_L1CR (priv->layer_regs[3]) /* L1 control register */ +#define LTDC_L1WHPCR (priv->layer_regs[4]) /* L1 window horizontal position configuration */ +#define LTDC_L1WVPCR (priv->layer_regs[5]) /* L1 window vertical position configuration */ +#define LTDC_L1CKCR (priv->layer_regs[6]) /* L1 color keying configuration */ +#define LTDC_L1PFCR (priv->layer_regs[7]) /* L1 pixel format configuration */ +#define LTDC_L1CACR (priv->layer_regs[8]) /* L1 constant alpha configuration */ +#define LTDC_L1DCCR (priv->layer_regs[9]) /* L1 default color configuration */ +#define LTDC_L1BFCR (priv->layer_regs[10]) /* L1 blending factors configuration */ +#define LTDC_L1BLCR (priv->layer_regs[11]) /* L1 burst length configuration */ +#define LTDC_L1PCR (priv->layer_regs[12]) /* L1 planar configuration */ +#define LTDC_L1CFBAR (priv->layer_regs[13]) /* L1 color frame buffer address */ +#define LTDC_L1CFBLR (priv->layer_regs[14]) /* L1 color frame buffer length */ +#define LTDC_L1CFBLNR (priv->layer_regs[15]) /* L1 color frame buffer line number */ +#define LTDC_L1AFBA0R (priv->layer_regs[16]) /* L1 auxiliary frame buffer address 0 */ +#define LTDC_L1AFBA1R (priv->layer_regs[17]) /* L1 auxiliary frame buffer address 1 */ +#define LTDC_L1AFBLR (priv->layer_regs[18]) /* L1 auxiliary frame buffer length */ +#define LTDC_L1AFBLNR (priv->layer_regs[19]) /* L1 auxiliary frame buffer line number */ +#define LTDC_L1CLUTWR (priv->layer_regs[20]) /* L1 CLUT write */ +#define LTDC_L1CYR0R (priv->layer_regs[27]) /* L1 Conversion YCbCr RGB 0 */ +#define LTDC_L1CYR1R (priv->layer_regs[28]) /* L1 Conversion YCbCr RGB 1 */ +#define LTDC_L1FPF0R (priv->layer_regs[29]) /* L1 Flexible Pixel Format 0 */ +#define LTDC_L1FPF1R (priv->layer_regs[30]) /* L1 Flexible Pixel Format 1 */ /* Bit definitions */ #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ @@ -144,15 +256,60 @@ struct stm32_ltdc_priv { #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ #define BF2_1CA 0x005 /* 1 - Constant Alpha */ +#define NB_PF 8 /* Max nb of HW pixel format */ + +#define HWVER_10200 0x010200 +#define HWVER_10300 0x010300 +#define HWVER_20101 0x020101 +#define HWVER_40100 0x040100 + enum stm32_ltdc_pix_fmt { - PF_ARGB8888 = 0, - PF_RGB888, - PF_RGB565, - PF_ARGB1555, - PF_ARGB4444, - PF_L8, - PF_AL44, - PF_AL88 + PF_ARGB8888 = 0, /* ARGB [32 bits] */ + PF_ABGR8888, /* ABGR [32 bits] */ + PF_BGRA8888, /* BGRA [32 bits] */ + PF_RGBA8888, /* RGBA [32 bits] */ + PF_RGB888, /* RGB [24 bits] */ + PF_BGR565, /* RGB [16 bits] */ + PF_RGB565, /* RGB [16 bits] */ + PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ + PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ + PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ + PF_AL88, /* Alpha:8 bits + indexed 8 bits [16 bits] */ + PF_L8, /* Indexed 8 bits [8 bits] */ + PF_NONE +}; + +static const enum stm32_ltdc_pix_fmt pix_fmt_a0[NB_PF] = { + PF_ARGB8888, /* 0x00 */ + PF_RGB888, /* 0x01 */ + PF_RGB565, /* 0x02 */ + PF_ARGB1555, /* 0x03 */ + PF_ARGB4444, /* 0x04 */ + PF_L8, /* 0x05 */ + PF_AL44, /* 0x06 */ + PF_AL88 /* 0x07 */ +}; + +static const enum stm32_ltdc_pix_fmt pix_fmt_a1[NB_PF] = { + PF_ARGB8888, /* 0x00 */ + PF_RGB888, /* 0x01 */ + PF_RGB565, /* 0x02 */ + PF_RGBA8888, /* 0x03 */ + PF_AL44, /* 0x04 */ + PF_L8, /* 0x05 */ + PF_ARGB1555, /* 0x06 */ + PF_ARGB4444 /* 0x07 */ +}; + +static const enum stm32_ltdc_pix_fmt pix_fmt_a2[NB_PF] = { + PF_ARGB8888, /* 0x00 */ + PF_ABGR8888, /* 0x01 */ + PF_RGBA8888, /* 0x02 */ + PF_BGRA8888, /* 0x03 */ + PF_RGB565, /* 0x04 */ + PF_BGR565, /* 0x05 */ + PF_RGB888, /* 0x06 */ + PF_NONE /* 0x07 (flexible pixel format) */ }; /* TODO add more color format support */ @@ -306,7 +463,16 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr) /* Pixel format */ format = stm32_ltdc_get_pixel_format(priv->l2bpp); - clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format); + for (val = 0; val < NB_PF; val++) + if (priv->pix_fmt_hw[val] == format) + break; + + if (val >= NB_PF) { + log_err("invalid pixel format\n"); + return; + } + + clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val); /* Constant alpha value */ clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha); @@ -359,6 +525,27 @@ static int stm32_ltdc_probe(struct udevice *dev) return ret; } + priv->hw_version = readl(priv->regs + LTDC_IDR); + debug("%s: LTDC hardware 0x%x\n", __func__, priv->hw_version); + + switch (priv->hw_version) { + case HWVER_10200: + case HWVER_10300: + priv->layer_regs = layer_regs_a0; + priv->pix_fmt_hw = pix_fmt_a0; + break; + case HWVER_20101: + priv->layer_regs = layer_regs_a1; + priv->pix_fmt_hw = pix_fmt_a1; + break; + case HWVER_40100: + priv->layer_regs = layer_regs_a2; + priv->pix_fmt_hw = pix_fmt_a2; + break; + default: + return -ENODEV; + } + ret = uclass_first_device_err(UCLASS_PANEL, &panel); if (ret) { if (ret != -ENODEV) From 1494e3758634a32a79484099ee9a86ff5e7d737a Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 15 Apr 2022 11:46:50 +0200 Subject: [PATCH 11/40] board: st: common: fix the error messages in stboard command Add missing \n at the end of the error trace Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- board/st/common/cmd_stboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/st/common/cmd_stboard.c b/board/st/common/cmd_stboard.c index c1ecd643b00..e12669b8628 100644 --- a/board/st/common/cmd_stboard.c +++ b/board/st/common/cmd_stboard.c @@ -92,14 +92,14 @@ static int do_stboard(struct cmd_tbl *cmdtp, int flag, int argc, &otp, sizeof(otp)); if (ret != sizeof(otp)) { - puts("OTP read error"); + puts("OTP read error\n"); return CMD_RET_FAILURE; } ret = misc_read(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD), &lock, sizeof(lock)); if (ret != sizeof(lock)) { - puts("LOCK read error"); + puts("LOCK read error\n"); return CMD_RET_FAILURE; } From 806c4dd31532708d30dd82a5173232dccc73c81b Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 15 Apr 2022 14:31:54 +0200 Subject: [PATCH 12/40] configs: stm32mp1: set the console variable for extlinux.conf Set the environment variable "console", used in extlinux.conf file when it is generated by YOCTO distribution with: UBOOT_EXTLINUX_CONSOLE ??= "console=${console},${baudrate}" With these 2 variables, U-Boot give dynamically the used console and baudrate in the Linux kernel bootargs. For the STMicroelectronics boards, the used console is ttySTM0. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- include/configs/stm32mp15_st_common.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 10248bffc14..e8dad004c61 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -8,6 +8,9 @@ #ifndef __CONFIG_STM32MP15_ST_COMMON_H__ #define __CONFIG_STM32MP15_ST_COMMON_H__ +#define STM32MP_BOARD_EXTRA_ENV \ + "console=ttySTM0\0" + #include #ifdef CONFIG_EXTRA_ENV_SETTINGS From 5367b67be4a3d26197fe5bf7baef2bf125997047 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 15 Apr 2022 14:31:55 +0200 Subject: [PATCH 13/40] configs: stm32mp1: Add support for baudrates higher than 115200 for st-link On STMicroelectronics boards, the UART can reliably go up to 2000000 bauds when connected to the on-board ST-LINK-V2 for STM32MP15 Unfortunately U-Boot will fall back to 115200 unless higher rates are declared via CONFIG_SYS_BAUDRATE_TABLE. This patch add the support of higher baudrates on STMicroelectronics boards with ST-LINK. Cc: Alexandru Gagniuc Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- include/configs/stm32mp15_st_common.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index e8dad004c61..3c0ffb8f56f 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -13,6 +13,11 @@ #include +/* uart with on-board st-link */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 460800, 921600, \ + 1000000, 2000000 } + #ifdef CONFIG_EXTRA_ENV_SETTINGS /* * default bootcmd for stm32mp1 STMicroelectronics boards: From 6a69eaf6f43840b05d7093c2728b2b6b011c31de Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 15 Apr 2022 14:43:23 +0200 Subject: [PATCH 14/40] ARM: stm32mp: skip ft_system_setup when the soc node is absent The function ft_system_setup shouldn't return an error when the /soc node is absent in the provided device tree but just skip the updates. This patch solves an issue when the U-Boot pytest is executed on board. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/mach-stm32mp/fdt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c index 91330a68a49..b1a4b765663 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/fdt.c @@ -260,6 +260,9 @@ int ft_system_setup(void *blob, struct bd_info *bd) char name[SOC_NAME_SIZE]; soc = fdt_path_offset(blob, "/soc"); + /* when absent, nothing to do */ + if (soc == -FDT_ERR_NOTFOUND) + return 0; if (soc < 0) return soc; From 655af9aa9c91303b76a9565df7292bf9ec3351a1 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 15 Apr 2022 15:00:43 +0200 Subject: [PATCH 15/40] ARM: stm32mp: correctly handle Silicon revision Handle correctly the silicon revision = REV_ID[15:0] of Device Version and the associated device marking, A to Z on STMicroelectronics STM32MP SOCs. This patch prepare the introduction of next STM32MP family, with STM32MP13x Rev.Z for REV_ID = 1.1. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/mach-stm32mp/cpu.c | 6 +++--- arch/arm/mach-stm32mp/include/mach/sys_proto.h | 9 +++++---- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 325d7101009..0ad5f307dba 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -432,13 +432,13 @@ static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, /* Revision */ switch (get_cpu_rev()) { - case CPU_REVA: + case CPU_REV1: *rev = 1; break; - case CPU_REVB: + case CPU_REV2: *rev = 2; break; - case CPU_REVZ: + case CPU_REV2_1: *rev = 3; break; default: diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 4149d3a1337..b91f98eb451 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -25,11 +25,12 @@ u32 get_cpu_type(void); /* return CPU_DEV constants */ u32 get_cpu_dev(void); -#define CPU_REVA 0x1000 -#define CPU_REVB 0x2000 -#define CPU_REVZ 0x2001 +#define CPU_REV1 0x1000 +#define CPU_REV1_1 0x1001 +#define CPU_REV2 0x2000 +#define CPU_REV2_1 0x2001 -/* return CPU_REV constants */ +/* return Silicon revision = REV_ID[15:0] of Device Version */ u32 get_cpu_rev(void); /* Get Package options from OTP */ From 189ec2fee6ef36f567640c61ccf4e04422cab70b Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 26 Apr 2022 15:38:05 +0200 Subject: [PATCH 16/40] arm: dts: stm32mp15: alignment with v5.18 Device tree alignment with Linux kernel v5.18-rc2: - ARM: dts: stm32: Add support for the emtrion emSBC-Argon (only the pincontrol part) - ARM: dts: stm32: Drop duplicate status okay from DHCOM gpioc node - ARM: dts: stm32: add st,stm32-sdmmc2 compatible on stm32mp151 - ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15 - ARM: dts: stm32: use exti 19 as main interrupt to support RTC wakeup on stm32mp157 - ARM: dts: stm32: add DMA configuration to UART nodes on stm32mp151 - ARM: dts: stm32: keep uart4 behavior on * - ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15 Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/dts/stm32mp15-pinctrl.dtsi | 92 +++++++++++++++++++ arch/arm/dts/stm32mp15-u-boot.dtsi | 12 --- arch/arm/dts/stm32mp151.dtsi | 37 ++++++-- arch/arm/dts/stm32mp153.dtsi | 7 ++ .../stm32mp157a-icore-stm32mp1-ctouch2.dts | 2 + .../stm32mp157a-icore-stm32mp1-edimm2.2.dts | 2 + ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 4 + ...32mp157a-microgea-stm32mp1-microdev2.0.dts | 4 + arch/arm/dts/stm32mp157c-ed1.dts | 2 + arch/arm/dts/stm32mp157c-odyssey.dts | 2 + arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi | 4 + arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi | 4 + arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi | 4 + arch/arm/dts/stm32mp15xx-dhcom-som.dtsi | 3 +- arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi | 6 ++ arch/arm/dts/stm32mp15xx-dkx.dtsi | 4 + 16 files changed, 168 insertions(+), 21 deletions(-) diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index 6161f5906ec..f0d66d8c6e3 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -338,6 +338,47 @@ }; }; + ethernet0_rmii_pins_b: rmii-1 { + pins1 { + pinmux = , /* ETH1_CLK */ + , /* ETH1_MDC */ + , /* ETH1_TXD0 */ + ; /* ETH1_TXD1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* ETH1_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH1_CRS_DV */ + , /* ETH1_RXD0 */ + ; /* ETH1_RXD1 */ + bias-disable; + }; + pins4 { + pinmux = ; /* ETH1_TX_EN */ + }; + }; + + ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { + pins1 { + pinmux = , /* ETH1_MDIO */ + , /* ETH1_CRS_DV */ + , /* ETH1_CLK */ + , /* ETH1_TX_EN */ + , /* ETH1_MDC */ + , /* ETH1_RXD0 */ + , /* ETH1_RXD1 */ + , /* ETH1_TXD0 */ + ; /* ETH1_TXD1 */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = , /* FMC_NOE */ @@ -927,6 +968,21 @@ }; }; + pwm1_pins_b: pwm1-1 { + pins { + pinmux = ; /* TIM1_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_b: pwm1-sleep-1 { + pins { + pinmux = ; /* TIM1_CH1 */ + }; + }; + pwm2_pins_a: pwm2-0 { pins { pinmux = ; /* TIM2_CH4 */ @@ -2042,6 +2098,42 @@ }; }; + usart3_pins_d: usart3-3 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + usart3_idle_pins_d: usart3-idle-3 { + pins1 { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + ; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_d: usart3-sleep-3 { + pins { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + , /* USART3_CTS_NSS */ + ; /* USART3_RX */ + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = ; /* OTG_ID */ diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index e23d6c7d7eb..d9d04743ac8 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -188,18 +188,6 @@ #size-cells = <0>; }; -&sdmmc1 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; -}; - -&sdmmc2 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; -}; - -&sdmmc3 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; -}; - &usart1 { resets = <&rcc USART1_R>; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 5a2be007586..e74a5faf4a3 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -63,10 +63,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-parent = <&intc>; }; @@ -473,6 +473,9 @@ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART2_K>; wakeup-source; + dmas = <&dmamux1 43 0x400 0x15>, + <&dmamux1 44 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -482,6 +485,9 @@ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART3_K>; wakeup-source; + dmas = <&dmamux1 45 0x400 0x15>, + <&dmamux1 46 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -491,6 +497,9 @@ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART4_K>; wakeup-source; + dmas = <&dmamux1 63 0x400 0x15>, + <&dmamux1 64 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -500,6 +509,9 @@ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART5_K>; wakeup-source; + dmas = <&dmamux1 65 0x400 0x15>, + <&dmamux1 66 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -606,6 +618,9 @@ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART7_K>; wakeup-source; + dmas = <&dmamux1 79 0x400 0x15>, + <&dmamux1 80 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -615,6 +630,9 @@ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART8_K>; wakeup-source; + dmas = <&dmamux1 81 0x400 0x15>, + <&dmamux1 82 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -696,6 +714,9 @@ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART6_K>; wakeup-source; + dmas = <&dmamux1 71 0x400 0x15>, + <&dmamux1 72 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1077,7 +1098,7 @@ }; sdmmc3: mmc@48004000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x48004000 0x400>; interrupts = ; @@ -1411,7 +1432,7 @@ }; sdmmc1: mmc@58005000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>; interrupts = ; @@ -1426,7 +1447,7 @@ }; sdmmc2: mmc@58007000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>; interrupts = ; @@ -1590,7 +1611,7 @@ reg = <0x5c004000 0x400>; clocks = <&rcc RTCAPB>, <&rcc RTC>; clock-names = "pclk", "rtc_ck"; - interrupts = ; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi index 1c1889b194c..486084e0b80 100644 --- a/arch/arm/dts/stm32mp153.dtsi +++ b/arch/arm/dts/stm32mp153.dtsi @@ -22,6 +22,13 @@ interrupt-affinity = <&cpu0>, <&cpu1>; }; + timer { + interrupts = , + , + , + ; + }; + soc { m_can1: can@4400e000 { compatible = "bosch,m_can"; diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts index d3058a036c7..1f75f1d4518 100644 --- a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts @@ -43,5 +43,7 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts index ec9f1d1cd50..3a1295cfa97 100644 --- a/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -43,5 +43,7 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts index 5670b23812a..fae656edd82 100644 --- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -143,6 +143,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -150,5 +152,7 @@ &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts index 7a75868164d..b9d0d3d6ad1 100644 --- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts @@ -44,6 +44,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -51,5 +53,7 @@ &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index f62b46b8dd5..fe5c8f25cec 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -392,6 +392,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 0e725498dd1..17bcf56f744 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -132,6 +132,8 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi index 4b10b013ffd..35b1034aa3c 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi @@ -131,6 +131,8 @@ &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -144,6 +146,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi index fbf3826933e..5f586f02406 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -287,6 +287,8 @@ &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -294,6 +296,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi index ba816ef8b9b..abc595350e7 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi @@ -105,12 +105,16 @@ &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi index 8c41f819f77..83e2c87713f 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi @@ -196,7 +196,6 @@ "", "", "DHCOM-E", "", "", "", "", "", "", "", "", ""; - status = "okay"; }; &gpiod { @@ -521,5 +520,7 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi index 6885948f302..61e17f44ce8 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -376,6 +376,8 @@ label = "LS-UART1"; pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -385,6 +387,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart7_pins_a>; uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -394,6 +398,8 @@ pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_sleep_pins_a>; st,hw-flow-ctrl; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; bluetooth { diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index f8130bf4451..3d36cac9ed0 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -658,6 +658,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -666,6 +668,8 @@ pinctrl-0 = <&uart7_pins_c>; pinctrl-1 = <&uart7_sleep_pins_c>; pinctrl-2 = <&uart7_idle_pins_c>; + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; }; From 221869efc3a4cf975c1bf068227f17ce10cd5597 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 26 Apr 2022 16:37:41 +0200 Subject: [PATCH 17/40] ram: stm32mp1: Conditionally enable ASR Enable DRAM ASR, auto self-refresh, conditionally, based on DT PWRCTL register bits. While ASR does save considerable amount of power at runtime automatically, it also causes LTDC underruns on large panels. Let user select whether or not ASR is required or not, generally ASR should be enabled on portable and battery operated devices. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrick Delaunay Signed-off-by: Patrice Chotard --- drivers/ram/stm32mp1/stm32mp1_ddr.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index 528a171b454..ab913a68761 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -653,10 +653,14 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, wait_sw_done_ack(ctl); } -static void stm32mp1_asr_enable(struct ddr_info *priv) +static void stm32mp1_asr_enable(struct ddr_info *priv, const u32 pwrctl) { struct stm32mp1_ddrctl *ctl = priv->ctl; + /* SSR is the best we can do. */ + if (!(pwrctl & DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE)) + return; + clrsetbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCKMOD_MASK, RCC_DDRITFCR_DDRCKMOD_ASR); @@ -666,8 +670,12 @@ static void stm32mp1_asr_enable(struct ddr_info *priv) writel(DDRCTRL_PWRTMG_POWERDOWN_TO_X32(0x10) | DDRCTRL_PWRTMG_SELFREF_TO_X32(0x01), &ctl->pwrtmg); + + /* HSR we can do. */ setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE); - setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN); + + if (pwrctl & DDRCTRL_PWRCTL_SELFREF_EN) /* ASR we can do. */ + setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN); setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); wait_sw_done_ack(ctl); @@ -845,7 +853,7 @@ start: config->c_reg.pwrctl); /* Enable auto-self-refresh, which saves a bit of power at runtime. */ - stm32mp1_asr_enable(priv); + stm32mp1_asr_enable(priv, config->c_reg.pwrctl); /* enable uMCTL2 AXI port 0 and 1 */ setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN); From d6ae1839650b6f4ea49c0ffbfcce6d50dce2f731 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 26 Apr 2022 16:38:05 +0200 Subject: [PATCH 18/40] stm32mp: psci: Retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend The SoC seems to lose the values of MCUDIVR, PLL3CR, PLL4CR, RCC_MSSCKSELR during suspend/resume cycle, cache them and reinstate their values on resume. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrick Delaunay Signed-off-by: Patrice Chotard --- arch/arm/mach-stm32mp/psci.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c index 86c160987a9..1e69673e88b 100644 --- a/arch/arm/mach-stm32mp/psci.c +++ b/arch/arm/mach-stm32mp/psci.c @@ -26,6 +26,7 @@ #define PWR_MPUCR_CSSF BIT(9) /* RCC */ +#define RCC_MSSCKSELR 0x48 #define RCC_DDRITFCR 0xd8 #define RCC_DDRITFCR_DDRC1EN BIT(0) @@ -49,6 +50,10 @@ #define RCC_MP_CIFR 0x418 #define RCC_MP_CIFR_WKUPF BIT(20) +#define RCC_MCUDIVR 0x830 +#define RCC_PLL3CR 0x880 +#define RCC_PLL4CR 0x894 + /* SYSCFG */ #define SYSCFG_CMPCR 0x20 #define SYSCFG_CMPCR_SW_CTRL BIT(2) @@ -690,6 +695,7 @@ static void __secure ddr_sw_self_refresh_exit(void) void __secure psci_system_suspend(u32 __always_unused function_id, u32 ep, u32 context_id) { + u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; u32 saved_pwrctl, reg; /* Disable IO compensation */ @@ -708,6 +714,11 @@ void __secure psci_system_suspend(u32 __always_unused function_id, setbits_le32(STM32_PWR_BASE + PWR_MPUCR, PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS); + saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR); + saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR); + saved_pll4cr = readl(STM32_RCC_BASE + RCC_PLL4CR); + saved_mssckselr = readl(STM32_RCC_BASE + RCC_MSSCKSELR); + psci_v7_flush_dcache_all(); ddr_sr_mode_ssr(&saved_pwrctl); ddr_sw_self_refresh_in(); @@ -724,6 +735,11 @@ void __secure psci_system_suspend(u32 __always_unused function_id, ddr_sw_self_refresh_exit(); ddr_sr_mode_restore(saved_pwrctl); + writel(saved_mcudivr, STM32_RCC_BASE + RCC_MCUDIVR); + writel(saved_pll3cr, STM32_RCC_BASE + RCC_PLL3CR); + writel(saved_pll4cr, STM32_RCC_BASE + RCC_PLL4CR); + writel(saved_mssckselr, STM32_RCC_BASE + RCC_MSSCKSELR); + writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); } From 9da04c17a36f10d9ab8702751e1412f2edc91236 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 1 May 2022 18:43:28 +0200 Subject: [PATCH 19/40] ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM The DHCOM does ship with KS8851 with 1.5 kiB packet buffer. The DHSOM may be extended with other MAC options connected to FMC2 bus, like the DM9000, wih similar limitations. Use default CONFIG_TFTP_BLOCKSIZE of 1468 Bytes instead of 1536 Bytes, which always avoids overflowing the packet buffers of such limited MACs, which leads to e.g. TFTP timeouts. This also avoids receiving a short packet fragment at the end of each TFTP block, which led to reduced performance. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Cc: Ramon Fried Reviewed-by: Ramon Fried Reviewed-by: Patrick Delaunay Signed-off-by: Patrice Chotard --- configs/stm32mp15_dhcom_basic_defconfig | 1 - configs/stm32mp15_dhcor_basic_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index ec955eae200..0ff015cae49 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -80,7 +80,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_ENV_IS_NOWHERE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y -CONFIG_TFTP_BLOCKSIZE=1536 CONFIG_STM32_ADC=y CONFIG_SPL_BLOCK_CACHE=y CONFIG_DFU_MMC=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 387e068155e..83614b9fc8e 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -77,7 +77,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_ENV_IS_NOWHERE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y -CONFIG_TFTP_BLOCKSIZE=1536 CONFIG_STM32_ADC=y CONFIG_SPL_BLOCK_CACHE=y CONFIG_DFU_MMC=y From 473c7d72e4da458ab0ff081cf5445c2c6239d8b9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 1 May 2022 18:43:29 +0200 Subject: [PATCH 20/40] ARM: stm32: Use CONFIG_TFTP_TSIZE on DHSOM Long TFTP transfers lead to a wall of # characters on UART, which in the end may slow down the transfer itself. Use CONFIG_TFTP_TSIZE to print progress in fewer # characters. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Cc: Ramon Fried Reviewed-by: Ramon Fried Reviewed-by: Patrick Delaunay Signed-off-by: Patrice Chotard --- configs/stm32mp15_dhcom_basic_defconfig | 1 + configs/stm32mp15_dhcor_basic_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 0ff015cae49..7f7aecf2510 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -80,6 +80,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_ENV_IS_NOWHERE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y +CONFIG_TFTP_TSIZE=y CONFIG_STM32_ADC=y CONFIG_SPL_BLOCK_CACHE=y CONFIG_DFU_MMC=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 83614b9fc8e..35e43a9a2fc 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -77,6 +77,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_ENV_IS_NOWHERE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y +CONFIG_TFTP_TSIZE=y CONFIG_STM32_ADC=y CONFIG_SPL_BLOCK_CACHE=y CONFIG_DFU_MMC=y From 6d4619f68cf1c9559fec32d72550cf76a745da6c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 4 May 2022 14:50:04 +0200 Subject: [PATCH 21/40] ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3 in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant which has extra Empirion DCDC converter in front of the 1V8 IO supply, or outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter. The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily high input voltage to the Empirion DCDC converter, so move it into matching DTSI to stop confusing users. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay Signed-off-by: Patrice Chotard --- arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi | 5 +++++ arch/arm/dts/stm32mp15xx-dhcor-som.dtsi | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi index 75172314d7a..9937b28548c 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi @@ -18,6 +18,11 @@ }; }; +&vdd { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; +}; + &pwr_regulators { vdd-supply = <&vdd_io>; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi index 44ecc470858..98033b51479 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi @@ -77,8 +77,8 @@ vdd: buck3 { regulator-name = "vdd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; regulator-initial-mode = <0>; regulator-over-current-protection; From 8202c958cfe24f0ffb6f6817fb3dc75ecaf8da12 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 5 May 2022 14:21:32 +0200 Subject: [PATCH 22/40] ARM: stm32: Use CONFIG_TFTP_TSIZE on STMicroelectronics boards Long TFTP transfers lead to a wall of # characters on UART, which in the end may slow down the transfer itself. Use CONFIG_TFTP_TSIZE to print progress in fewer # characters. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- configs/stm32mp15_basic_defconfig | 1 + configs/stm32mp15_defconfig | 1 + configs/stm32mp15_trusted_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 5d1b2e0fd7e..1b1c255b981 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -80,6 +80,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 # CONFIG_SPL_ENV_IS_NOWHERE is not set # CONFIG_SPL_ENV_IS_IN_SPI_FLASH is not set +CONFIG_TFTP_TSIZE=y CONFIG_STM32_ADC=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index f6e7fc81b08..02b37e14eae 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -61,6 +61,7 @@ CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_TFTP_TSIZE=y CONFIG_STM32_ADC=y CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 855a394893e..df31c0fbb10 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -62,6 +62,7 @@ CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_TFTP_TSIZE=y CONFIG_STM32_ADC=y CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y From 4382e55c428269c36777b20d7103afbf6be67041 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 22 Apr 2022 09:38:29 +0200 Subject: [PATCH 23/40] pinctrl: pinctrl_stm32: Update pinmux_mode definition pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c So reuse the same gpio_func_t enum value Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- drivers/pinctrl/pinctrl_stm32.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 5729799b122..5d8e156d62a 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -42,13 +42,12 @@ struct stm32_gpio_bank { #ifndef CONFIG_SPL_BUILD static char pin_name[PINNAME_SIZE]; -#define PINMUX_MODE_COUNT 5 -static const char * const pinmux_mode[PINMUX_MODE_COUNT] = { - "gpio input", - "gpio output", - "analog", - "unknown", - "alt function", +static const char * const pinmux_mode[GPIOF_COUNT] = { + [GPIOF_INPUT] = "gpio input", + [GPIOF_OUTPUT] = "gpio output", + [GPIOF_UNUSED] = "analog", + [GPIOF_UNKNOWN] = "unknown", + [GPIOF_FUNC] = "alt function", }; static const char * const pinmux_bias[] = { From 234b03f3a965b3e3ef5d7efb42c7d4c45bb401ef Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 22 Apr 2022 09:38:30 +0200 Subject: [PATCH 24/40] pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins GPIOF_UNKNOWN becomes a valid pin muxing information to indicate that a pin is not mapped. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- drivers/pinctrl/pinctrl_stm32.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 5d8e156d62a..373f51f0462 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -220,8 +220,6 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, switch (mode) { case GPIOF_UNKNOWN: - /* should never happen */ - return -EINVAL; case GPIOF_UNUSED: snprintf(buf, size, "%s", pinmux_mode[mode]); break; From 427f452cb94116b3f00215f87214e94b4aef9768 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 22 Apr 2022 09:38:31 +0200 Subject: [PATCH 25/40] gpio: stm32_gpio: Rework GPIO hole management On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank Example: If GPIO bank have 16 GPIO pins [0-15]. In particular SoC's package case, some GPIO bank can have less GPIO pins: - [0-10] => 11 pins; - [2-7] => 6 pins. Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management") proposed a first implementation by not counting GPIO "inside" hole. GPIO are not displaying correctly using gpio or pinmux command when GPIO holes are located at the beginning of GPIO bank. To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges struct to indicate if a GPIO is mapped or not. GPIO uclass offers several GPIO functions ("input", "output", "unused", "unknown" and "func"), use "unknown" GPIO function to indicate that a GPIO is not mapped. stm32_offset_to_index() is no more needed and removed. This must be reflected using the "gpio" command to indicate to user that a particular GPIO is not mapped (marked as "unknown") as shown below: Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins mapped): GPIOI0 : unknown GPIOI1 : unknown GPIOI2 : analog GPIOI3 : analog GPIOI4 : alt function 0 push-pull pull-down GPIOI5 : alt function 0 push-pull pull-down GPIOI6 : alt function 0 push-pull pull-down GPIOI7 : analog GPIOI8 : unknown GPIOI9 : unknown GPIOI10 : unknown GPIOI11 : unknown GPIOI12 : unknown GPIOI13 : unknown GPIOI14 : unknown GPIOI15 : unknown Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- drivers/gpio/stm32_gpio.c | 101 +++++++++++--------------------- drivers/gpio/stm32_gpio_priv.h | 2 - drivers/pinctrl/pinctrl_stm32.c | 5 +- 3 files changed, 36 insertions(+), 72 deletions(-) diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c index 8667ed3835c..7a2ca91c769 100644 --- a/drivers/gpio/stm32_gpio.c +++ b/drivers/gpio/stm32_gpio.c @@ -83,38 +83,22 @@ static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs, return (readl(®s->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK; } -/* - * convert gpio offset to gpio index taking into account gpio holes - * into gpio bank - */ -int stm32_offset_to_index(struct udevice *dev, unsigned int offset) +static bool stm32_gpio_is_mapped(struct udevice *dev, int offset) { struct stm32_gpio_priv *priv = dev_get_priv(dev); - unsigned int idx = 0; - int i; - for (i = 0; i < STM32_GPIOS_PER_BANK; i++) { - if (priv->gpio_range & BIT(i)) { - if (idx == offset) - return idx; - idx++; - } - } - /* shouldn't happen */ - return -EINVAL; + return !!(priv->gpio_range & BIT(offset)); } static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset) { struct stm32_gpio_priv *priv = dev_get_priv(dev); struct stm32_gpio_regs *regs = priv->regs; - int idx; - idx = stm32_offset_to_index(dev, offset); - if (idx < 0) - return idx; + if (!stm32_gpio_is_mapped(dev, offset)) + return -ENXIO; - stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN); + stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_IN); return 0; } @@ -124,15 +108,13 @@ static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset, { struct stm32_gpio_priv *priv = dev_get_priv(dev); struct stm32_gpio_regs *regs = priv->regs; - int idx; - idx = stm32_offset_to_index(dev, offset); - if (idx < 0) - return idx; + if (!stm32_gpio_is_mapped(dev, offset)) + return -ENXIO; - stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT); + stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_OUT); - writel(BSRR_BIT(idx, value), ®s->bsrr); + writel(BSRR_BIT(offset, value), ®s->bsrr); return 0; } @@ -141,26 +123,22 @@ static int stm32_gpio_get_value(struct udevice *dev, unsigned offset) { struct stm32_gpio_priv *priv = dev_get_priv(dev); struct stm32_gpio_regs *regs = priv->regs; - int idx; - idx = stm32_offset_to_index(dev, offset); - if (idx < 0) - return idx; + if (!stm32_gpio_is_mapped(dev, offset)) + return -ENXIO; - return readl(®s->idr) & BIT(idx) ? 1 : 0; + return readl(®s->idr) & BIT(offset) ? 1 : 0; } static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value) { struct stm32_gpio_priv *priv = dev_get_priv(dev); struct stm32_gpio_regs *regs = priv->regs; - int idx; - idx = stm32_offset_to_index(dev, offset); - if (idx < 0) - return idx; + if (!stm32_gpio_is_mapped(dev, offset)) + return -ENXIO; - writel(BSRR_BIT(idx, value), ®s->bsrr); + writel(BSRR_BIT(offset, value), ®s->bsrr); return 0; } @@ -171,14 +149,12 @@ static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset) struct stm32_gpio_regs *regs = priv->regs; int bits_index; int mask; - int idx; u32 mode; - idx = stm32_offset_to_index(dev, offset); - if (idx < 0) - return idx; + if (!stm32_gpio_is_mapped(dev, offset)) + return GPIOF_UNKNOWN; - bits_index = MODE_BITS(idx); + bits_index = MODE_BITS(offset); mask = MODE_BITS_MASK << bits_index; mode = (readl(®s->moder) & mask) >> bits_index; @@ -197,30 +173,28 @@ static int stm32_gpio_set_flags(struct udevice *dev, unsigned int offset, { struct stm32_gpio_priv *priv = dev_get_priv(dev); struct stm32_gpio_regs *regs = priv->regs; - int idx; - idx = stm32_offset_to_index(dev, offset); - if (idx < 0) - return idx; + if (!stm32_gpio_is_mapped(dev, offset)) + return -ENXIO; if (flags & GPIOD_IS_OUT) { bool value = flags & GPIOD_IS_OUT_ACTIVE; if (flags & GPIOD_OPEN_DRAIN) - stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD); + stm32_gpio_set_otype(regs, offset, STM32_GPIO_OTYPE_OD); else - stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP); + stm32_gpio_set_otype(regs, offset, STM32_GPIO_OTYPE_PP); - stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT); - writel(BSRR_BIT(idx, value), ®s->bsrr); + stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_OUT); + writel(BSRR_BIT(offset, value), ®s->bsrr); } else if (flags & GPIOD_IS_IN) { - stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN); + stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_IN); } if (flags & GPIOD_PULL_UP) - stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP); + stm32_gpio_set_pupd(regs, offset, STM32_GPIO_PUPD_UP); else if (flags & GPIOD_PULL_DOWN) - stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN); + stm32_gpio_set_pupd(regs, offset, STM32_GPIO_PUPD_DOWN); return 0; } @@ -230,19 +204,17 @@ static int stm32_gpio_get_flags(struct udevice *dev, unsigned int offset, { struct stm32_gpio_priv *priv = dev_get_priv(dev); struct stm32_gpio_regs *regs = priv->regs; - int idx; ulong dir_flags = 0; - idx = stm32_offset_to_index(dev, offset); - if (idx < 0) - return idx; + if (!stm32_gpio_is_mapped(dev, offset)) + return -ENXIO; - switch (stm32_gpio_get_moder(regs, idx)) { + switch (stm32_gpio_get_moder(regs, offset)) { case STM32_GPIO_MODE_OUT: dir_flags |= GPIOD_IS_OUT; - if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD) + if (stm32_gpio_get_otype(regs, offset) == STM32_GPIO_OTYPE_OD) dir_flags |= GPIOD_OPEN_DRAIN; - if (readl(®s->idr) & BIT(idx)) + if (readl(®s->idr) & BIT(offset)) dir_flags |= GPIOD_IS_OUT_ACTIVE; break; case STM32_GPIO_MODE_IN: @@ -251,7 +223,7 @@ static int stm32_gpio_get_flags(struct udevice *dev, unsigned int offset, default: break; } - switch (stm32_gpio_get_pupd(regs, idx)) { + switch (stm32_gpio_get_pupd(regs, offset)) { case STM32_GPIO_PUPD_UP: dir_flags |= GPIOD_PULL_UP; break; @@ -304,17 +276,14 @@ static int gpio_stm32_probe(struct udevice *dev) if (!ret && args.args_count < 3) return -EINVAL; - if (ret == -ENOENT) { - uc_priv->gpio_count = STM32_GPIOS_PER_BANK; + uc_priv->gpio_count = STM32_GPIOS_PER_BANK; + if (ret == -ENOENT) priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0); - } while (ret != -ENOENT) { priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1, args.args[0]); - uc_priv->gpio_count += args.args[2]; - ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, ++i, &args); if (!ret && args.args_count < 3) diff --git a/drivers/gpio/stm32_gpio_priv.h b/drivers/gpio/stm32_gpio_priv.h index d3d8f2ed5de..662a000fe73 100644 --- a/drivers/gpio/stm32_gpio_priv.h +++ b/drivers/gpio/stm32_gpio_priv.h @@ -81,6 +81,4 @@ struct stm32_gpio_priv { unsigned int gpio_range; }; -int stm32_offset_to_index(struct udevice *dev, unsigned int offset); - #endif /* _STM32_GPIO_PRIV_H_ */ diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 373f51f0462..56a20e8bd25 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -157,10 +157,7 @@ static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev, * we found the bank, convert pin selector to * gpio bank index */ - *idx = stm32_offset_to_index(gpio_bank->gpio_dev, - selector - pin_count); - if (IS_ERR_VALUE(*idx)) - return NULL; + *idx = selector - pin_count; return gpio_bank->gpio_dev; } From da6473c0d458c070c74a55c23f9fb26a1c8a0efd Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 22 Apr 2022 09:39:00 +0200 Subject: [PATCH 26/40] phy: stm32-usbphyc: stm32-usbphyc: Add DT phy tuning support Add support of phy-tuning properties for sm32-usbphyc's phy tuning aligned with v5.15 kernel bindings. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- drivers/phy/phy-stm32-usbphyc.c | 167 ++++++++++++++++++++++++++++++++ 1 file changed, 167 insertions(+) diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c index 9c1dcfae524..d7f7c37f919 100644 --- a/drivers/phy/phy-stm32-usbphyc.c +++ b/drivers/phy/phy-stm32-usbphyc.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include #include #include @@ -24,6 +26,7 @@ /* USBPHYC registers */ #define STM32_USBPHYC_PLL 0x0 #define STM32_USBPHYC_MISC 0x8 +#define STM32_USBPHYC_TUNE(X) (0x10C + ((X) * 0x100)) /* STM32_USBPHYC_PLL bit fields */ #define PLLNDIV GENMASK(6, 0) @@ -40,6 +43,26 @@ /* STM32_USBPHYC_MISC bit fields */ #define SWITHOST BIT(0) +/* STM32_USBPHYC_TUNE bit fields */ +#define INCURREN BIT(0) +#define INCURRINT BIT(1) +#define LFSCAPEN BIT(2) +#define HSDRVSLEW BIT(3) +#define HSDRVDCCUR BIT(4) +#define HSDRVDCLEV BIT(5) +#define HSDRVCURINCR BIT(6) +#define FSDRVRFADJ BIT(7) +#define HSDRVRFRED BIT(8) +#define HSDRVCHKITRM GENMASK(12, 9) +#define HSDRVCHKZTRM GENMASK(14, 13) +#define OTPCOMP GENMASK(19, 15) +#define SQLCHCTL GENMASK(21, 20) +#define HDRXGNEQEN BIT(22) +#define HSRXOFF GENMASK(24, 23) +#define HSFALLPREEM BIT(25) +#define SHTCCTCTLPROT BIT(26) +#define STAGSEL BIT(27) + #define MAX_PHYS 2 /* max 100 us for PLL lock and 100 us for PHY init */ @@ -49,6 +72,62 @@ #define PLL_INFF_MIN_RATE 19200000 /* in Hz */ #define PLL_INFF_MAX_RATE 38400000 /* in Hz */ +enum boosting_vals { + BOOST_1000_UA = 1000, + BOOST_2000_UA = 2000, +}; + +enum dc_level_vals { + DC_MINUS_5_TO_7_MV, + DC_PLUS_5_TO_7_MV, + DC_PLUS_10_TO_14_MV, + DC_MAX, +}; + +enum current_trim { + CUR_NOMINAL, + CUR_PLUS_1_56_PCT, + CUR_PLUS_3_12_PCT, + CUR_PLUS_4_68_PCT, + CUR_PLUS_6_24_PCT, + CUR_PLUS_7_8_PCT, + CUR_PLUS_9_36_PCT, + CUR_PLUS_10_92_PCT, + CUR_PLUS_12_48_PCT, + CUR_PLUS_14_04_PCT, + CUR_PLUS_15_6_PCT, + CUR_PLUS_17_16_PCT, + CUR_PLUS_19_01_PCT, + CUR_PLUS_20_58_PCT, + CUR_PLUS_22_16_PCT, + CUR_PLUS_23_73_PCT, + CUR_MAX, +}; + +enum impedance_trim { + IMP_NOMINAL, + IMP_MINUS_2_OHMS, + IMP_MINUS_4_OMHS, + IMP_MINUS_6_OHMS, + IMP_MAX, +}; + +enum squelch_level { + SQLCH_NOMINAL, + SQLCH_PLUS_7_MV, + SQLCH_MINUS_5_MV, + SQLCH_PLUS_14_MV, + SQLCH_MAX, +}; + +enum rx_offset { + NO_RX_OFFSET, + RX_OFFSET_PLUS_5_MV, + RX_OFFSET_PLUS_10_MV, + RX_OFFSET_MINUS_5_MV, + RX_OFFSET_MAX, +}; + struct pll_params { u8 ndiv; u16 frac; @@ -327,6 +406,90 @@ static int stm32_usbphyc_of_xlate(struct phy *phy, return 0; } +static void stm32_usbphyc_tuning(struct udevice *dev, ofnode node, u32 index) +{ + struct stm32_usbphyc *usbphyc = dev_get_priv(dev); + u32 reg = STM32_USBPHYC_TUNE(index); + u32 otpcomp, val, tune = 0; + int ret; + + /* Backup OTP compensation code */ + otpcomp = FIELD_GET(OTPCOMP, readl(usbphyc->base + reg)); + + ret = ofnode_read_u32(node, "st,current-boost-microamp", &val); + if (!ret && (val == BOOST_1000_UA || val == BOOST_2000_UA)) { + val = (val == BOOST_2000_UA) ? 1 : 0; + tune |= INCURREN | FIELD_PREP(INCURRINT, val); + } else if (ret != -EINVAL) { + dev_warn(dev, "phy%d: invalid st,current-boost-microamp value\n", index); + } + + if (!ofnode_read_bool(node, "st,no-lsfs-fb-cap")) + tune |= LFSCAPEN; + + if (ofnode_read_bool(node, "st,decrease-hs-slew-rate")) + tune |= HSDRVSLEW; + + ret = ofnode_read_u32(node, "st,tune-hs-dc-level", &val); + if (!ret && val < DC_MAX) { + if (val == DC_MINUS_5_TO_7_MV) { + tune |= HSDRVDCCUR; + } else { + val = (val == DC_PLUS_10_TO_14_MV) ? 1 : 0; + tune |= HSDRVCURINCR | FIELD_PREP(HSDRVDCLEV, val); + } + } else if (ret != -EINVAL) { + dev_warn(dev, "phy%d: invalid st,tune-hs-dc-level value\n", index); + } + + if (ofnode_read_bool(node, "st,enable-fs-rftime-tuning")) + tune |= FSDRVRFADJ; + + if (ofnode_read_bool(node, "st,enable-hs-rftime-reduction")) + tune |= HSDRVRFRED; + + ret = ofnode_read_u32(node, "st,trim-hs-current", &val); + if (!ret && val < CUR_MAX) + tune |= FIELD_PREP(HSDRVCHKITRM, val); + else if (ret != -EINVAL) + dev_warn(dev, "phy%d: invalid st,trim-hs-current value\n", index); + + ret = ofnode_read_u32(node, "st,trim-hs-impedance", &val); + if (!ret && val < IMP_MAX) + tune |= FIELD_PREP(HSDRVCHKZTRM, val); + else if (ret != -EINVAL) + dev_warn(dev, "phy%d: invalid trim-hs-impedance value\n", index); + + ret = ofnode_read_u32(node, "st,tune-squelch-level", &val); + if (!ret && val < SQLCH_MAX) + tune |= FIELD_PREP(SQLCHCTL, val); + else if (ret != -EINVAL) + dev_warn(dev, "phy%d: invalid st,tune-squelch-level value\n", index); + + if (ofnode_read_bool(node, "st,enable-hs-rx-gain-eq")) + tune |= HDRXGNEQEN; + + ret = ofnode_read_u32(node, "st,tune-hs-rx-offset", &val); + if (!ret && val < RX_OFFSET_MAX) + tune |= FIELD_PREP(HSRXOFF, val); + else if (ret != -EINVAL) + dev_warn(dev, "phy%d: invalid st,tune-hs-rx-offset value\n", index); + + if (ofnode_read_bool(node, "st,no-hs-ftime-ctrl")) + tune |= HSFALLPREEM; + + if (!ofnode_read_bool(node, "st,no-lsfs-sc")) + tune |= SHTCCTCTLPROT; + + if (ofnode_read_bool(node, "st,enable-hs-tx-staggering")) + tune |= STAGSEL; + + /* Restore OTP compensation code */ + tune |= FIELD_PREP(OTPCOMP, otpcomp); + + writel(tune, usbphyc->base + reg); +} + static const struct phy_ops stm32_usbphyc_phy_ops = { .init = stm32_usbphyc_phy_init, .exit = stm32_usbphyc_phy_exit, @@ -389,6 +552,10 @@ static int stm32_usbphyc_probe(struct udevice *dev) phy_id, ofnode_get_name(node)); return -ENOENT; } + + /* Configure phy tuning */ + stm32_usbphyc_tuning(dev, node, phy_id); + usbphyc_phy = usbphyc->phys + phy_id; usbphyc_phy->init = false; usbphyc_phy->powered = false; From 67899c2201a8009a1ea6bee55fe812fd298ca79e Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 22 Apr 2022 09:39:18 +0200 Subject: [PATCH 27/40] board: st: stm32mp1: Consider USB cable connected when boot device is USB Always consider USB cable is connected when USB boot device is detected. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- board/st/stm32mp1/stm32mp1.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 7466e1c732a..07b1a63db7d 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -199,6 +199,13 @@ int g_dnl_board_usb_cable_connected(void) if (!IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG)) return -ENODEV; + /* + * In case of USB boot device is detected, consider USB cable is + * connected + */ + if ((get_bootmode() & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_USB) + return true; + /* if typec stusb160x is present, means DK1 or DK2 board */ ret = stusb160x_cable_connected(); if (ret >= 0) From 05a3a028c127c7ca515b90a916cf3ac8c0264a61 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 22 Apr 2022 12:40:39 +0200 Subject: [PATCH 28/40] clk: stm32mp1: Add missing newline Add missing newline to this debug message, no functional change. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay Signed-off-by: Patrice Chotard --- drivers/clk/clk_stm32mp1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 83ab6b728ed..452550066e2 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -2205,7 +2205,7 @@ static void stm32mp1_osc_init(struct udevice *dev) for (i = 0; i < NB_OSC; i++) { if (clk_get_by_name(dev, name[i], &priv->osc_clk[i])) - dev_dbg(dev, "No source clock \"%s\"", name[i]); + dev_dbg(dev, "No source clock \"%s\"\n", name[i]); else dev_dbg(dev, "%s clock rate: %luHz\n", name[i], clk_get_rate(&priv->osc_clk[i])); From 480995b76b0ee61e473596e629dbc8ec754b0f84 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 27 Apr 2022 13:53:50 +0200 Subject: [PATCH 29/40] configs: stm32f746-disco: Concatenate spl and u-boot binaries This allows to concatenate spl and u-boot binaries together. Previously, both binaries has to be flashed separately at the correct offset (spl at offset 0 and u-boot at offset 0x8000). With this patch, only one binary is generated (u-boot-with-spl.bin) and has to be copied in flash at offset 0 using openocd for example or simply copied in exported mass storage. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32f746-disco_defconfig | 1 + include/configs/stm32f746-disco.h | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 130b90fae30..01338679425 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco" CONFIG_SPL_TEXT_BASE=0x8000000 CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y +CONFIG_BUILD_TARGET="u-boot-with-spl.bin" CONFIG_SYS_LOAD_ADDR=0x8008000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 8ad4bb99c83..b93acdcc1ff 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -49,6 +49,7 @@ #define CONFIG_SYS_UBOOT_START 0x080083FD #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ CONFIG_SYS_SPL_LEN) +#define CONFIG_SPL_PAD_TO 0x8000 /* DT blob (fdt) address */ #define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ From 0d4ef527da8e65770e3d870d32e45c115b246132 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 27 Apr 2022 13:53:51 +0200 Subject: [PATCH 30/40] configs: stm32f746-disco: Rename stm32f746-disco_defconfig to stm32f746-disco_spl_defconfig The current stm32f746-disco_defconfig file supports SPL, rename it to stm32f746-disco_spl_defconfig to reflect the supported configuration. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- board/st/stm32f746-disco/MAINTAINERS | 1 + .../{stm32f746-disco_defconfig => stm32f746-disco_spl_defconfig} | 0 2 files changed, 1 insertion(+) rename configs/{stm32f746-disco_defconfig => stm32f746-disco_spl_defconfig} (100%) diff --git a/board/st/stm32f746-disco/MAINTAINERS b/board/st/stm32f746-disco/MAINTAINERS index 3bbb513ad7a..06d366e8a20 100644 --- a/board/st/stm32f746-disco/MAINTAINERS +++ b/board/st/stm32f746-disco/MAINTAINERS @@ -4,4 +4,5 @@ S: Maintained F: board/st/stm32f746-disco F: include/configs/stm32f746-disco.h F: configs/stm32f746-disco_defconfig +F: configs/stm32f746-disco_spl_defconfig F: configs/stm32f769-disco_defconfig diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_spl_defconfig similarity index 100% rename from configs/stm32f746-disco_defconfig rename to configs/stm32f746-disco_spl_defconfig From 50f48340f0101ea5b13c1bc65af845e0abc9005d Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 27 Apr 2022 13:53:52 +0200 Subject: [PATCH 31/40] configs: stm32f746-disco: Add stm32f746-disco_defconfig Add stm32f746-disco_defconfig for stm32f746 discovery board to build U-Boot proper. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32f746-disco_defconfig | 64 +++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 configs/stm32f746-disco_defconfig diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig new file mode 100644 index 00000000000..2c70bac9cd3 --- /dev/null +++ b/configs/stm32f746-disco_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32=y +CONFIG_SYS_TEXT_BASE=0x08000000 +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SYS_MALLOC_F_LEN=0xE00 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco" +CONFIG_STM32F7=y +CONFIG_TARGET_STM32F746_DISCO=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x8008000 +CONFIG_BOOTDELAY=3 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_LATE_INIT=y +CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_ARM_PL180_MMCI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_STM32_FLASH=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +# CONFIG_PINCTRL_FULL is not set +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_STM32_QSPI=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_VIDEO_STM32=y +CONFIG_VIDEO_STM32_MAX_XRES=480 +CONFIG_VIDEO_STM32_MAX_YRES=640 +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_OF_LIBFDT_OVERLAY=y From 969bc0aecefdf58fc7467d862a8e0a49d05c0b21 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 27 Apr 2022 13:53:53 +0200 Subject: [PATCH 32/40] configs: stm32f769-disco: Rename stm32f769-disco_defconfig to stm32f769-disco_spl_defconfig The current stm32f769-disco_defconfig file supports SPL, rename it to stm32f769-disco_spl_defconfig to reflect the supported configuration. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- board/st/stm32f746-disco/MAINTAINERS | 1 + .../{stm32f769-disco_defconfig => stm32f769-disco_spl_defconfig} | 0 2 files changed, 1 insertion(+) rename configs/{stm32f769-disco_defconfig => stm32f769-disco_spl_defconfig} (100%) diff --git a/board/st/stm32f746-disco/MAINTAINERS b/board/st/stm32f746-disco/MAINTAINERS index 06d366e8a20..68f61fd5ff1 100644 --- a/board/st/stm32f746-disco/MAINTAINERS +++ b/board/st/stm32f746-disco/MAINTAINERS @@ -6,3 +6,4 @@ F: include/configs/stm32f746-disco.h F: configs/stm32f746-disco_defconfig F: configs/stm32f746-disco_spl_defconfig F: configs/stm32f769-disco_defconfig +F: configs/stm32f769-disco_spl_defconfig diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_spl_defconfig similarity index 100% rename from configs/stm32f769-disco_defconfig rename to configs/stm32f769-disco_spl_defconfig From bad1b7902850bf294c2c69114cca35d585dba7f1 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 27 Apr 2022 13:53:54 +0200 Subject: [PATCH 33/40] configs: stm32f769-disco: Add stm32f769-disco_defconfig Add stm32f769-disco_defconfig for stm32f769 discovery board to build U-Boot proper. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32f769-disco_defconfig | 65 +++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 configs/stm32f769-disco_defconfig diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig new file mode 100644 index 00000000000..3c112882cc3 --- /dev/null +++ b/configs/stm32f769-disco_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32=y +CONFIG_SYS_TEXT_BASE=0x08000000 +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SYS_MALLOC_F_LEN=0xE00 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco" +CONFIG_STM32F7=y +CONFIG_TARGET_STM32F746_DISCO=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x8008000 +CONFIG_BOOTDELAY=3 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_ARM_PL180_MMCI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_STM32_FLASH=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +# CONFIG_PINCTRL_FULL is not set +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_STM32_QSPI=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y +CONFIG_VIDEO_STM32=y +CONFIG_VIDEO_STM32_DSI=y +CONFIG_VIDEO_STM32_MAX_XRES=480 +CONFIG_VIDEO_STM32_MAX_YRES=800 +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_OF_LIBFDT_OVERLAY=y From 5ff7f0490d134bc52e8d654d2c4dfadaf60b5b8c Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 27 Apr 2022 13:53:55 +0200 Subject: [PATCH 34/40] configs: stm32f769-disco: Migrate SPL flags to defconfig Migrate SPL flags to stm32f769-disco_spl_defconfig Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32f769-disco_spl_defconfig | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index f151dab04fc..672c1ec065d 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -3,12 +3,19 @@ CONFIG_ARCH_STM32=y CONFIG_SYS_TEXT_BASE=0x08008000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_F_LEN=0xE00 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco" CONFIG_SPL_TEXT_BASE=0x8000000 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y +CONFIG_SPL=y +CONFIG_BUILD_TARGET="u-boot-with-spl.bin" CONFIG_SYS_LOAD_ADDR=0x8008000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 @@ -18,6 +25,11 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_XIP_SUPPORT=y +CONFIG_SPL_DM_RESET=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set @@ -29,15 +41,16 @@ CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y -# CONFIG_SPL_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y -# CONFIG_SPL_BLK is not set -# CONFIG_SPL_DM_MMC is not set +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_SPL_CLK=y CONFIG_ARM_PL180_MMCI=y CONFIG_MTD=y CONFIG_DM_MTD=y @@ -51,9 +64,13 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set +CONFIG_SPL_PINCTRL=y +CONFIG_SPL_RAM=y +CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y +CONFIG_SPL_TIMER=y CONFIG_DM_VIDEO=y CONFIG_BACKLIGHT_GPIO=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y From 35a15bc12ecb721449c300646d7aba4a1d8a7d7a Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 27 Apr 2022 13:53:56 +0200 Subject: [PATCH 35/40] configs: stm32f746-disco: Migrate SPL flags to defconfig Migrate SPL flags to stm32f746-disco_spl_defconfig Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/mach-stm32/Kconfig | 20 -------------------- configs/stm32f746-disco_spl_defconfig | 24 ++++++++++++++++++++---- 2 files changed, 20 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index a439dbd10f1..a44ebf25975 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -25,26 +25,6 @@ config STM32F7 select PINCTRL select PINCTRL_STM32 select RAM - select SPL - select SPL_BOARD_INIT - select SPL_CLK - select SPL_DM - select SPL_DM_RESET - select SPL_DM_SEQ_ALIAS - select SPL_DRIVERS_MISC - select SPL_GPIO - select SPL_LIBCOMMON_SUPPORT - select SPL_LIBGENERIC_SUPPORT - select SPL_MTD_SUPPORT - select SPL_OF_CONTROL - select SPL_OF_LIBFDT - select SPL_OF_TRANSLATE - select SPL_PINCTRL - select SPL_RAM - select SPL_SERIAL - select SPL_SYS_MALLOC_SIMPLE - select SPL_TIMER - select SPL_XIP_SUPPORT select STM32_RCC select STM32_RESET select STM32_SDRAM diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig index 01338679425..9fef65fa7b6 100644 --- a/configs/stm32f746-disco_spl_defconfig +++ b/configs/stm32f746-disco_spl_defconfig @@ -3,12 +3,18 @@ CONFIG_ARCH_STM32=y CONFIG_SYS_TEXT_BASE=0x08008000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_F_LEN=0xE00 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco" CONFIG_SPL_TEXT_BASE=0x8000000 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y +CONFIG_SPL=y CONFIG_BUILD_TARGET="u-boot-with-spl.bin" CONFIG_SYS_LOAD_ADDR=0x8008000 CONFIG_DISTRO_DEFAULTS=y @@ -20,6 +26,11 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_XIP_SUPPORT=y +CONFIG_SPL_DM_RESET=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set @@ -31,15 +42,16 @@ CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y -# CONFIG_SPL_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y -# CONFIG_SPL_BLK is not set -# CONFIG_SPL_DM_MMC is not set +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_SPL_CLK=y CONFIG_ARM_PL180_MMCI=y CONFIG_MTD=y CONFIG_DM_MTD=y @@ -53,9 +65,13 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set +CONFIG_SPL_PINCTRL=y +CONFIG_SPL_RAM=y +CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y +CONFIG_SPL_TIMER=y CONFIG_DM_VIDEO=y CONFIG_BACKLIGHT_GPIO=y CONFIG_VIDEO_STM32=y From 16613edbc1b59e906a41e84382f3e098f0ec946a Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 27 Apr 2022 13:53:57 +0200 Subject: [PATCH 36/40] board: stm32f746-disco: Fix dram_init() in none SPL config Replace CONFIG_SUPPORT_SPL by CONFIG_SPL_BUILD to allow dram_init() execution when using none SPL defconfig (stm32f746-disco_defconfig). Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- board/st/stm32f746-disco/stm32f746-disco.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 69f657c54b8..2ab23f2f4f7 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { -#ifndef CONFIG_SUPPORT_SPL +#ifndef CONFIG_SPL_BUILD int rv; struct udevice *dev; rv = uclass_get_device(UCLASS_RAM, 0, &dev); From 7aa4b4523f7c56b1b6407cbfb6ab3706f98e11c7 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 27 Apr 2022 13:53:58 +0200 Subject: [PATCH 37/40] configs: stm32f746-disco: use CONFIG_DEFAULT_DEVICE_TREE as fdtfile As stm32f46-disco, stm32f769-disco and stm32746g-eval are very similar except their respective device tree file. These 3 boards uses the same TARGET_STM32F746_DISCO flag (so same include/configs/stm32f746-disco.h and same board file board/st/stm32f746-disco/stm32f746-disco.c) To be able to compile these 3 boards, replace the hard-coded device-tree name in include/configs/stm32f746-disco.h by CONFIG_DEFAULT_DEVICE_TREE which is set in each board defconfig file with the correct value. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- include/configs/stm32f746-disco.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index b93acdcc1ff..cc3d4b4449d 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -34,7 +34,7 @@ #include #define CONFIG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0xC0008000\0" \ - "fdtfile=stm32f746-disco.dtb\0" \ + "fdtfile="CONFIG_DEFAULT_DEVICE_TREE".dtb\0" \ "fdt_addr_r=0xC0408000\0" \ "scriptaddr=0xC0418000\0" \ "pxefile_addr_r=0xC0428000\0" \ From e9881a1e750025a6614efa8428b6b4e393b55c8f Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 27 Apr 2022 13:53:59 +0200 Subject: [PATCH 38/40] configs: stm32746g-eval: Add stm32746g-eval_defconfig Add stm32746g-eval_defconfig for stm32746g evaluation board to build U-Boot proper. Full board description can be found here : https://www.st.com/en/evaluation-tools/stm32746g-eval.html Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- board/st/stm32f746-disco/MAINTAINERS | 1 + configs/stm32746g-eval_defconfig | 64 ++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 configs/stm32746g-eval_defconfig diff --git a/board/st/stm32f746-disco/MAINTAINERS b/board/st/stm32f746-disco/MAINTAINERS index 68f61fd5ff1..7f128a8b699 100644 --- a/board/st/stm32f746-disco/MAINTAINERS +++ b/board/st/stm32f746-disco/MAINTAINERS @@ -5,5 +5,6 @@ F: board/st/stm32f746-disco F: include/configs/stm32f746-disco.h F: configs/stm32f746-disco_defconfig F: configs/stm32f746-disco_spl_defconfig +F: configs/stm32746g-eval_defconfig F: configs/stm32f769-disco_defconfig F: configs/stm32f769-disco_spl_defconfig diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig new file mode 100644 index 00000000000..9f79b5a2b43 --- /dev/null +++ b/configs/stm32746g-eval_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32=y +CONFIG_SYS_TEXT_BASE=0x08000000 +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SYS_MALLOC_F_LEN=0xE00 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval" +CONFIG_STM32F7=y +CONFIG_TARGET_STM32F746_DISCO=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x8008000 +CONFIG_BOOTDELAY=3 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_LATE_INIT=y +CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_ARM_PL180_MMCI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_STM32_FLASH=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +# CONFIG_PINCTRL_FULL is not set +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_STM32_QSPI=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_VIDEO_STM32=y +CONFIG_VIDEO_STM32_MAX_XRES=480 +CONFIG_VIDEO_STM32_MAX_YRES=640 +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_OF_LIBFDT_OVERLAY=y From eda7b6a632bac9d150387080cc2ad6f9970bb311 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 27 Apr 2022 13:54:00 +0200 Subject: [PATCH 39/40] configs: stm32746g-eval: Add stm32746g-eval_spl_defconfig Add stm32746g-eval_spl_defconfig for stm32746g evaluation board to build SPL. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- board/st/stm32f746-disco/MAINTAINERS | 1 + configs/stm32746g-eval_spl_defconfig | 86 ++++++++++++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 configs/stm32746g-eval_spl_defconfig diff --git a/board/st/stm32f746-disco/MAINTAINERS b/board/st/stm32f746-disco/MAINTAINERS index 7f128a8b699..bc0952c5632 100644 --- a/board/st/stm32f746-disco/MAINTAINERS +++ b/board/st/stm32f746-disco/MAINTAINERS @@ -6,5 +6,6 @@ F: include/configs/stm32f746-disco.h F: configs/stm32f746-disco_defconfig F: configs/stm32f746-disco_spl_defconfig F: configs/stm32746g-eval_defconfig +F: configs/stm32746g-eval_spl_defconfig F: configs/stm32f769-disco_defconfig F: configs/stm32f769-disco_spl_defconfig diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig new file mode 100644 index 00000000000..169a9c5b239 --- /dev/null +++ b/configs/stm32746g-eval_spl_defconfig @@ -0,0 +1,86 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32=y +CONFIG_SYS_TEXT_BASE=0x08008000 +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SYS_MALLOC_F_LEN=0xE00 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval" +CONFIG_SPL_TEXT_BASE=0x8000000 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_STM32F7=y +CONFIG_TARGET_STM32F746_DISCO=y +CONFIG_SPL=y +CONFIG_BUILD_TARGET="u-boot-with-spl.bin" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x8008000 +CONFIG_BOOTDELAY=3 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_XIP_SUPPORT=y +CONFIG_SPL_DM_RESET=y +CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_SPL_CLK=y +CONFIG_ARM_PL180_MMCI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_STM32_FLASH=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +# CONFIG_PINCTRL_FULL is not set +CONFIG_SPL_PINCTRL=y +CONFIG_SPL_RAM=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_STM32_QSPI=y +CONFIG_SPL_TIMER=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_VIDEO_STM32=y +CONFIG_VIDEO_STM32_MAX_XRES=480 +CONFIG_VIDEO_STM32_MAX_YRES=640 +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_OF_LIBFDT_OVERLAY=y From e198d4fe7c34cbb97d7d3cbf31d3a78a5ecc43f7 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 27 Apr 2022 13:54:01 +0200 Subject: [PATCH 40/40] doc: Add documentation for STM32 MCUs Add documentation for STM32 MCUs (F4, F7 and H7 series). Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- board/st/stm32f429-discovery/MAINTAINERS | 1 + board/st/stm32f429-evaluation/MAINTAINERS | 1 + board/st/stm32f469-discovery/MAINTAINERS | 1 + board/st/stm32f746-disco/MAINTAINERS | 1 + board/st/stm32h743-disco/MAINTAINERS | 1 + board/st/stm32h743-eval/MAINTAINERS | 1 + board/st/stm32h750-art-pi/MAINTAINERS | 1 + doc/board/st/index.rst | 1 + doc/board/st/stm32_MCU.rst | 186 ++++++++++++++++++++++ 9 files changed, 194 insertions(+) create mode 100644 doc/board/st/stm32_MCU.rst diff --git a/board/st/stm32f429-discovery/MAINTAINERS b/board/st/stm32f429-discovery/MAINTAINERS index fdb62e98e89..7661a15fdde 100644 --- a/board/st/stm32f429-discovery/MAINTAINERS +++ b/board/st/stm32f429-discovery/MAINTAINERS @@ -1,6 +1,7 @@ STM32F429-DISCOVERY BOARD M: Kamil Lulko S: Maintained +F: doc/board/st/ F: board/st/stm32f429-discovery/ F: include/configs/stm32f429-discovery.h F: configs/stm32f429-discovery_defconfig diff --git a/board/st/stm32f429-evaluation/MAINTAINERS b/board/st/stm32f429-evaluation/MAINTAINERS index 29d00ef27ed..b272893ef7b 100644 --- a/board/st/stm32f429-evaluation/MAINTAINERS +++ b/board/st/stm32f429-evaluation/MAINTAINERS @@ -1,6 +1,7 @@ STM32F429-EVALUATION BOARD M: Patrice Chotard S: Maintained +F: doc/board/st/ F: board/st/stm32f429-evaluation/ F: include/configs/stm32f429-evaluation.h F: configs/stm32f429-evaluation_defconfig diff --git a/board/st/stm32f469-discovery/MAINTAINERS b/board/st/stm32f469-discovery/MAINTAINERS index 5a6a78b39ef..a95f93f6f6c 100644 --- a/board/st/stm32f469-discovery/MAINTAINERS +++ b/board/st/stm32f469-discovery/MAINTAINERS @@ -1,6 +1,7 @@ STM32F469-DISCOVERY BOARD M: Patrice Chotard S: Maintained +F: doc/board/st/ F: board/st/stm32f469-discovery/ F: include/configs/stm32f469-discovery.h F: configs/stm32f469-discovery_defconfig diff --git a/board/st/stm32f746-disco/MAINTAINERS b/board/st/stm32f746-disco/MAINTAINERS index bc0952c5632..18e4c99c4fb 100644 --- a/board/st/stm32f746-disco/MAINTAINERS +++ b/board/st/stm32f746-disco/MAINTAINERS @@ -1,6 +1,7 @@ STM32F746 DISCOVERY BOARD M: Vikas Manocha S: Maintained +F: doc/board/st/ F: board/st/stm32f746-disco F: include/configs/stm32f746-disco.h F: configs/stm32f746-disco_defconfig diff --git a/board/st/stm32h743-disco/MAINTAINERS b/board/st/stm32h743-disco/MAINTAINERS index 60fbe344f83..f4ecef3aa50 100644 --- a/board/st/stm32h743-disco/MAINTAINERS +++ b/board/st/stm32h743-disco/MAINTAINERS @@ -1,6 +1,7 @@ STM32H743 DISCOVERY BOARD M: Patrice Chotard S: Maintained +F: doc/board/st/ F: board/st/stm32h743-disco F: include/configs/stm32h743-disco.h F: configs/stm32h743-disco_defconfig diff --git a/board/st/stm32h743-eval/MAINTAINERS b/board/st/stm32h743-eval/MAINTAINERS index fda93db7774..b69e0d4abbb 100644 --- a/board/st/stm32h743-eval/MAINTAINERS +++ b/board/st/stm32h743-eval/MAINTAINERS @@ -1,6 +1,7 @@ STM32H743 EVALUATION BOARD M: Patrice Chotard S: Maintained +F: doc/board/st/ F: board/st/stm32h743-eval F: include/configs/stm32h743-eval.h F: configs/stm32h743-eval_defconfig diff --git a/board/st/stm32h750-art-pi/MAINTAINERS b/board/st/stm32h750-art-pi/MAINTAINERS index 9578833068b..2fd69e6d1ca 100644 --- a/board/st/stm32h750-art-pi/MAINTAINERS +++ b/board/st/stm32h750-art-pi/MAINTAINERS @@ -1,6 +1,7 @@ STM32H750 ART PI BOARD M: Dillon Min S: Maintained +F: doc/board/st/ F: board/st/stm32h750-art-pi F: include/configs/stm32h750-art-pi.h F: configs/stm32h750-art-pi_defconfig diff --git a/doc/board/st/index.rst b/doc/board/st/index.rst index 9bba42f1dae..2a8a4ef3b84 100644 --- a/doc/board/st/index.rst +++ b/doc/board/st/index.rst @@ -8,3 +8,4 @@ STMicroelectronics st-dt stm32mp1 + stm32_MCU diff --git a/doc/board/st/stm32_MCU.rst b/doc/board/st/stm32_MCU.rst new file mode 100644 index 00000000000..7ff7c730fae --- /dev/null +++ b/doc/board/st/stm32_MCU.rst @@ -0,0 +1,186 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Patrice Chotard + +STM32 MCU boards +================= + +This is a quick instruction for setup STM32 MCU boards. + +Supported devices +----------------- + +U-Boot supports the following STMP32 MCU SoCs: + + - STM32F429 + - STM32F469 + - STM32F746 + - STM32F769 + - STM32H743 + - STM32H750 + +SoCs information: +----------------- +STM32F4 series are Cortex-M4 MCU. +STM32F7 and STM32H7 series are Cortex-M7 MCU. + + + STM32F4 series: https://www.st.com/en/microcontrollers-microprocessors/stm32f4-series.html + + STM32F7 series: https://www.st.com/en/microcontrollers-microprocessors/stm32f7-series.html + + STM32H7 series: https://www.st.com/en/microcontrollers-microprocessors/stm32h7-series.html + +Currently the following boards are supported: + + + stm32f429-discovery + + stm32f469-discovery + + stm32746g-evaluation + + stm32f746-discovery + + stm32f769-discovery + + stm32h743i-discovery + + stm32h743i-evaluation + + stm32h750i-art-pi + +Boot Sequences +-------------- + +For STM32F7 series, 2 boot configurations are supported with and without SPL + ++------------------------+-------------------------+--------------+ +| **FSBL** | **SSBL** | **OS** | ++------------------------+-------------------------+--------------+ +| First Stage Bootloader | Second Stage Bootloader | Linux Kernel | ++------------------------+-------------------------+--------------+ +| embedded Flash | DDR | ++------------------------+-------------------------+--------------+ + +The boot chain with SPL +``````````````````````` + +defconfig_file : + + **stm32746g-eval_spl_defconfig** + + **stm32f746-disco_spl_defconfig** + + **stm32f769-disco_spl_defconfig** + ++------------+------------+-------+ +| FSBL | SSBL | OS | ++------------+------------+-------+ +|U-Boot SPL | U-Boot | Linux | ++------------+------------+-------+ + +The boot chain without SPL +`````````````````````````` + +defconfig_file : + + **stm32f429-discovery_defconfig** + + **stm32f429-evaluation_defconfig** + + **stm32f469-discovery_defconfig** + + **stm32746g-eval_defconfig** + + **stm32f746-disco_defconfig** + + **stm32f769-disco_defconfig** + + **stm32h743-disco_defconfig** + + **stm32h743-eval_defconfig** + + **stm32h750-art-pi_defconfig** + ++-----------+-------+ +| FSBL | OS | ++-----------+-------+ +|U-Boot | Linux | ++-----------+-------+ + +Build Procedure +--------------- + +1. Install the required tools for U-Boot + + * install package needed in U-Boot makefile + (libssl-dev, swig, libpython-dev...) + + * install ARMv7 toolchain for 32bit Cortex-A (from Linaro, + from SDK for STM32MP15x, or any crosstoolchains from your distribution) + (you can use any gcc cross compiler compatible with U-Boot) + +2. Set the cross compiler:: + + # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi- + +3. Select the output directory (optional):: + + # export KBUILD_OUTPUT=/path/to/output + + for example: use one output directory for each configuration:: + + # export KBUILD_OUTPUT=stm32f4 + # export KBUILD_OUTPUT=stm32f7 + # export KBUILD_OUTPUT=stm32h7 + + you can build outside of code directory:: + + # export KBUILD_OUTPUT=../build/stm32f4 + +4. Configure U-Boot:: + + # make + + For example with : + + - For **stm32f429 discovery** board : **stm32f429-discovery_defconfig** + - For **stm32f769 discovery** board with SPL: **stm32f769-disco_spl_defconfig** + - For **stm32f769 discovery** board without SPL: **stm32f769-disco_defconfig** + +5. Configure the device-tree and build the U-Boot image:: + + # make DEVICE_TREE= all + + Examples: + + a) boot with SPL on stm32f746 discovery board:: + + # export KBUILD_OUTPUT=stm32f746-disco + # make stm32f746-disco_spl_defconfig + # make all + + b) boot without SPL on stm32f746 discovery board:: + + # export KBUILD_OUTPUT=stm32f746-disco + # make stm32f746-disco_defconfig + # make all + + c) boot on stm32h743 discovery board:: + + # export KBUILD_OUTPUT=stm32h743-disco + # make stm32h743-disco_defconfig + # make all + + d) boot on stm32h743 evaluation board:: + + # export KBUILD_OUTPUT=stm32h743-disco + # make stm32h743-eval_defconfig + # make all + +6. U-Boot Output files + + So in the output directory (selected by KBUILD_OUTPUT), + you can found the needed U-Boot files, for example:: + + - stm32f746-disco_defconfig = **u-boot-dtb.bin** and **u-boot.dtb** + + - FSBL = u-boot-dtb.bin + + - stm32f746-disco_spl_defconfig = **u-boot-dtb.bin**, **u-boot.dtb** and **u-boot-with-spl.bin** + + - FSBL + SSBL = u-boot-with-spl.bin + - SSBL = u-boot-dtb.bin + +7. Flash U-Boot files + +Plug STM32 MCUs board using the USB ST-Link connector, hence it will expose +the flash area as a mass-storage. In this mass-storage you will find the +following files: + +- DETAILS.TXT: give the bootrom version and build +- MBED.HTM: shortcul to the hardware board description web page from st.com. + +Copy/paste the u-boot.bin or u-boot-with-spl.bin (in case of bootchain with SPL) +to this mass-storage. The "COM" LED will blink alternatively red and green during +the flash process. When done the board will reboot automatically. + +In case of boot with SPL, by default SPL will try to load either a Linux +kernel (falcon mode) or, if the key "c" is maintained pressed, the main U-Boot.