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mmc: Migrate MMC_SUPPORTS_TUNING to Kconfig

Browse Source 
The constraints on the MMC_SUPPORTS_TUNING symbol can easily be
expressed in Kconfig (with the addition of SPL_MMC_SUPPORTS_TUNING).
Furthermore, in order to remove <common.h> from the MMC subsystem, the
way this symbol is used today needs to be changed in order to continue
functioning.

Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2024-05-01 19:30:18 -06:00
parent 797cea685b
commit 2143a11e61
17 changed files with 43 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-mediatek/Kconfig
View File

@ -23,6 +23,7 @@ config TARGET_MT7622
config TARGET_MT7623
bool "MediaTek MT7623 SoC"
select CPU_V7A
select MMC_SUPPORTS_TUNING
help
The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7
including NEON and GPU, Mali-450 graphics, several DDR3 options,

1
arch/mips/mach-mtmips/Kconfig
View File

@ -80,6 +80,7 @@ config SOC_MT7621
bool "MT7621"
select MIPS_CM
select MIPS_L2_CACHE
select MMC_SUPPORTS_TUNING
select SYS_CACHE_SHIFT_5
select SYS_MIPS_CACHE_INIT_RAM_LOAD
select PINCTRL_MT7621

11
drivers/mmc/Kconfig
View File

@ -147,9 +147,16 @@ config SPL_MMC_IO_VOLTAGE
support. For eMMC this not mandatory, but not enabling this option may
prevent the driver of using the faster modes.
config MMC_SUPPORTS_TUNING
bool
config SPL_MMC_SUPPORTS_TUNING
bool
config MMC_UHS_SUPPORT
bool "enable UHS support"
depends on MMC_IO_VOLTAGE
select MMC_SUPPORTS_TUNING
help
The Ultra High Speed (UHS) bus is available on some SDHC and SDXC
cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus
@ -158,6 +165,7 @@ config MMC_UHS_SUPPORT
config SPL_MMC_UHS_SUPPORT
bool "enable UHS support in SPL"
depends on SPL_MMC_IO_VOLTAGE
select SPL_MMC_SUPPORTS_TUNING
help
The Ultra High Speed (UHS) bus is available on some SDHC and SDXC
cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus
@ -193,6 +201,7 @@ config SPL_MMC_HS400_SUPPORT
config MMC_HS200_SUPPORT
bool "enable HS200 support"
select MMC_SUPPORTS_TUNING
help
The HS200 mode is support by some eMMC. The bus frequency is up to
200MHz. This mode requires tuning the IO.
@ -200,6 +209,7 @@ config MMC_HS200_SUPPORT
config SPL_MMC_HS200_SUPPORT
bool "enable HS200 support in SPL"
depends on SPL_MMC
select SPL_MMC_SUPPORTS_TUNING
help
The HS200 mode is support by some eMMC. The bus frequency is up to
200MHz. This mode requires tuning the IO.
@ -347,6 +357,7 @@ config MMC_OCTEONTX
bool "Marvell Octeon Multimedia Card Interface support"
depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2)
depends on DM_MMC
select MMC_SUPPORTS_TUNING if ARCH_OCTEONTX2
help
This selects the Octeon Multimedia card Interface.
If you have an OcteonTX/TX2 or MIPS Octeon board with a

6
drivers/mmc/am654_sdhci.c
View File

@ -397,7 +397,7 @@ static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg)
writeb(val, host->ioaddr + reg);
}
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
#define ITAPDLY_LENGTH 32
#define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1)
@ -500,7 +500,7 @@ static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
}
#endif
const struct sdhci_ops am654_sdhci_ops = {
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
.platform_execute_tuning = am654_sdhci_execute_tuning,
#endif
.deferred_probe = am654_sdhci_deferred_probe,
@ -560,7 +560,7 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
}
const struct sdhci_ops j721e_4bit_sdhci_ops = {
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
.platform_execute_tuning = am654_sdhci_execute_tuning,
#endif
.deferred_probe = am654_sdhci_deferred_probe,

4
drivers/mmc/fsl_esdhc.c
View File

@ -1102,7 +1102,7 @@ static int fsl_esdhc_reinit(struct udevice *dev)
return esdhc_init_common(priv, &plat->mmc);
}
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
{
struct fsl_esdhc_plat *plat = dev_get_plat(dev);
@ -1175,7 +1175,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = {
.get_cd = fsl_esdhc_get_cd,
.send_cmd = fsl_esdhc_send_cmd,
.set_ios = fsl_esdhc_set_ios,
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
.execute_tuning = fsl_esdhc_execute_tuning,
#endif
.reinit = fsl_esdhc_reinit,

8
drivers/mmc/fsl_esdhc_imx.c
View File

@ -635,7 +635,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
priv->clock = clock;
}
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
static int esdhc_change_pinstate(struct udevice *dev)
{
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
@ -913,7 +913,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
int ret __maybe_unused;
u32 clock;
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
/*
* call esdhc_set_timing() before update the clock rate,
* This is because current we support DDR and SDR mode,
@ -951,7 +951,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
}
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
/*
* For HS400/HS400ES mode, make sure set the strobe dll in the
* target clock rate. So call esdhc_set_strobe_dll() after the
@ -1618,7 +1618,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = {
.get_cd = fsl_esdhc_get_cd,
.send_cmd = fsl_esdhc_send_cmd,
.set_ios = fsl_esdhc_set_ios,
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
.execute_tuning = fsl_esdhc_execute_tuning,
#endif
#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)

2
drivers/mmc/mmc-uclass.c
View File

@ -112,7 +112,7 @@ int mmc_getcd(struct mmc *mmc)
return dm_mmc_get_cd(mmc->dev);
}
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
static int dm_mmc_execute_tuning(struct udevice *dev, uint opcode)
{
struct dm_mmc_ops *ops = mmc_get_ops(dev);

12
drivers/mmc/mmc.c
View File

@ -329,7 +329,7 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
MMC_QUIRK_RETRY_SET_BLOCKLEN, 4);
}
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
static const u8 tuning_blk_pattern_4bit[] = {
0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
@ -1621,7 +1621,7 @@ static inline int bus_width(uint cap)
}
#if !CONFIG_IS_ENABLED(DM_MMC)
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
{
return -ENOTSUPP;
@ -1702,7 +1702,7 @@ void mmc_dump_capabilities(const char *text, uint caps)
struct mode_width_tuning {
enum bus_mode mode;
uint widths;
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
uint tuning;
#endif
};
@ -1743,7 +1743,7 @@ static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
#if !CONFIG_IS_ENABLED(MMC_TINY)
static const struct mode_width_tuning sd_modes_by_pref[] = {
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
{
.mode = UHS_SDR104,
.widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
@ -1846,7 +1846,7 @@ static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
mmc_set_clock(mmc, mmc->tran_speed,
MMC_CLK_ENABLE);
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
/* execute tuning if needed */
if (mwt->tuning && !mmc_host_is_spi(mmc)) {
err = mmc_execute_tuning(mmc,
@ -2224,7 +2224,7 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
mmc_select_mode(mmc, mwt->mode);
mmc_set_clock(mmc, mmc->tran_speed,
MMC_CLK_ENABLE);
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
/* execute tuning if needed */
if (mwt->tuning) {

4
drivers/mmc/mtk-sd.c
View File

@ -1011,7 +1011,7 @@ static int msdc_ops_get_wp(struct udevice *dev)
#endif
}
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
static u32 test_delay_bit(u32 delay, u32 bit)
{
bit %= PAD_DELAY_MAX;
@ -1760,7 +1760,7 @@ static const struct dm_mmc_ops msdc_ops = {
.set_ios = msdc_ops_set_ios,
.get_cd = msdc_ops_get_cd,
.get_wp = msdc_ops_get_wp,
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
.execute_tuning = msdc_execute_tuning,
#endif
.wait_dat0 = msdc_ops_wait_dat0,

12
drivers/mmc/octeontx_hsmmc.c
View File

@ -794,7 +794,7 @@ octeontx_mmc_get_cr_mods(struct mmc *mmc, const struct mmc_cmd *cmd,
u8 desired_ctype = 0;
if (IS_MMC(mmc)) {
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
if (cmd->resp_type == MMC_RSP_R1)
cr.rtype_xor = 1;
@ -1631,7 +1631,7 @@ static int octeontx_mmc_dev_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
return octeontx_mmc_send_cmd(dev_to_mmc(dev), cmd, data);
}
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
static int octeontx_mmc_test_cmd(struct mmc *mmc, u32 opcode, int *statp)
{
struct mmc_cmd cmd;
@ -2421,12 +2421,12 @@ static int octeontx_mmc_execute_tuning(struct udevice *dev, u32 opcode)
return 0;
}
#else /* MMC_SUPPORTS_TUNING */
#else /* CONFIG_MMC_SUPPORTS_TUNING */
static void octeontx_mmc_set_emm_timing(struct mmc *mmc,
union mio_emm_timing emm_timing)
{
}
#endif /* MMC_SUPPORTS_TUNING */
#endif /* CONFIG_MMC_SUPPORTS_TUNING */
/**
* Calculate the clock period with rounding up
@ -2573,7 +2573,7 @@ static int octeontx_mmc_set_ios(struct udevice *dev)
err = octeontx_mmc_configure_delay(mmc);
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
if (!err && mmc->selected_mode == MMC_HS_400 && !slot->hs400_tuned) {
debug("%s: Tuning HS400 mode\n", __func__);
err = octeontx_tune_hs400(mmc);
@ -3776,7 +3776,7 @@ static const struct dm_mmc_ops octeontx_hsmmc_ops = {
.set_ios = octeontx_mmc_set_ios,
.get_cd = octeontx_mmc_get_cd,
.get_wp = octeontx_mmc_get_wp,
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
.execute_tuning = octeontx_mmc_execute_tuning,
#endif
};

4
drivers/mmc/omap_hsmmc.c
View File

@ -577,7 +577,7 @@ static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
return val;
}
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
static void omap_hsmmc_disable_tuning(struct mmc *mmc)
{
struct hsmmc *mmc_base;
@ -1518,7 +1518,7 @@ static const struct dm_mmc_ops omap_hsmmc_ops = {
.get_cd = omap_hsmmc_getcd,
.get_wp = omap_hsmmc_getwp,
#endif
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
.execute_tuning = omap_hsmmc_execute_tuning,
#endif
.wait_dat0 = omap_hsmmc_wait_dat0,

2
drivers/mmc/sdhci-cadence.c
View File

@ -274,7 +274,7 @@ static int sdhci_cdns_probe(struct udevice *dev)
host->ops = &sdhci_cdns_ops;
host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
sdhci_cdns_mmc_ops = sdhci_ops;
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning;
#endif

4
drivers/mmc/sdhci.c
View File

@ -351,7 +351,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
return -ECOMM;
}
#if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
#if defined(CONFIG_DM_MMC) && CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
{
int err;
@ -848,7 +848,7 @@ const struct dm_mmc_ops sdhci_ops = {
.set_ios = sdhci_set_ios,
.get_cd = sdhci_get_cd,
.deferred_probe = sdhci_deferred_probe,
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
.execute_tuning = sdhci_execute_tuning,
#endif
.wait_dat0 = sdhci_wait_dat0,

3
include/configs/mt7621.h
View File

@ -14,9 +14,6 @@
#define CFG_SYS_INIT_SP_OFFSET 0x800000
/* MMC */
#define MMC_SUPPORTS_TUNING
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
#define CFG_SYS_NS16550_CLK 50000000

3
include/configs/mt7623.h
View File

@ -11,9 +11,6 @@
#include <linux/sizes.h>
/* MMC */
#define MMC_SUPPORTS_TUNING
/* DRAM */
#define CFG_SYS_SDRAM_BASE 0x80000000

5
include/configs/octeontx2_common.h
View File

@ -19,9 +19,4 @@
"loadaddr=20080000\0" \
"ethrotate=yes\0"
#if defined(CONFIG_MMC_OCTEONTX)
#define MMC_SUPPORTS_TUNING
/** EMMC specific defines */
#endif
#endif /* __OCTEONTX2_COMMON_H__ */

9
include/mmc.h
View File

@ -18,13 +18,6 @@
struct bd_info;
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
#define MMC_SUPPORTS_TUNING
#endif
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
#define MMC_SUPPORTS_TUNING
#endif
/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
#define SD_VERSION_SD (1U << 31)
#define MMC_VERSION_MMC (1U << 30)
@ -485,7 +478,7 @@ struct dm_mmc_ops {
*/
int (*get_wp)(struct udevice *dev);
#ifdef MMC_SUPPORTS_TUNING
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
/**
* execute_tuning() - Start the tuning process
*