mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-08-28 01:51:25 +02:00
Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra into next
This PR contains 4 patchsets: 1. PMIC GPIO cells bringup. Created drivers for MAX7663 and Palmas PMICs and gpio-uclass patch isolated behind configs for these 2 drivers. No unintentional size increase on any board. (proposed 2023-11-06 without any reaction) 2. Simple PLL clocks support in common tegra clock code which allows use of simple PLL the same way main PLLs are used (before only clock_start_pll was available). PLLD2 is an example of simple PLL, it is used as a video subsystem parent clock and was used to test this code. So far everything worked as expected. (proposed 2023-11-16 without any reaction) 3. A small patch for tegra emmc to allow pass max frequency from device tree since some devices may not support full speed. 4. Pinmux DM conversion. Patchset consists of commit with DM wrapper for existing pinmux code for t20/t30/t114, pinmux and funcmux files relocation into a dedicated folder inside pinctrl, conversion of some tegra boards to device tree pinmux setup.
This commit is contained in:
Tom Rini
commit
1f115bdeb8
@ -522,8 +522,8 @@
|
||||
power-supply = <&vdd_bl_reg>;
|
||||
pwms = <&pwm 0 5000000>;
|
||||
|
||||
brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
|
||||
default-brightness-level = <10>;
|
||||
brightness-levels = <1 35 70 105 140 175 210 255>;
|
||||
default-brightness-level = <2>;
|
||||
|
||||
backlight-boot-off;
|
||||
};
|
||||
|
||||
@ -44,6 +44,718 @@
|
||||
};
|
||||
};
|
||||
|
||||
pinmux@70000868 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
clk_32k_out_pa0 {
|
||||
nvidia,pins = "clk_32k_out_pa0";
|
||||
nvidia,function = "blink";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
uart3_cts_n_pa1 {
|
||||
nvidia,pins = "uart3_cts_n_pa1",
|
||||
"uart3_rxd_pw7";
|
||||
nvidia,function = "uartc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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||||
};
|
||||
dap2_fs_pa2 {
|
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nvidia,pins = "dap2_fs_pa2",
|
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"dap2_sclk_pa3",
|
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"dap2_din_pa4",
|
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"dap2_dout_pa5";
|
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nvidia,function = "i2s1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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||||
};
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sdmmc3_clk_pa6 {
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nvidia,pins = "sdmmc3_clk_pa6";
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nvidia,function = "sdmmc3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc3_cmd_pa7 {
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nvidia,pins = "sdmmc3_cmd_pa7",
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"sdmmc3_dat3_pb4",
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"sdmmc3_dat2_pb5",
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"sdmmc3_dat1_pb6",
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"sdmmc3_dat0_pb7",
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"sdmmc3_dat4_pd1",
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"sdmmc3_dat6_pd3",
|
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"sdmmc3_dat7_pd4";
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nvidia,function = "sdmmc3";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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gmi_a17_pb0 {
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nvidia,pins = "gmi_a17_pb0",
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"gmi_a18_pb1";
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nvidia,function = "uartd";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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lcd_pwr0_pb2 {
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nvidia,pins = "lcd_pwr0_pb2",
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"lcd_pwr1_pc1",
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"lcd_m1_pw1";
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nvidia,function = "displaya";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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||||
};
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lcd_pclk_pb3 {
|
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nvidia,pins = "lcd_pclk_pb3",
|
||||
"lcd_d0_pe0",
|
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"lcd_d1_pe1",
|
||||
"lcd_d2_pe2",
|
||||
"lcd_d3_pe3",
|
||||
"lcd_d4_pe4",
|
||||
"lcd_d5_pe5",
|
||||
"lcd_d6_pe6",
|
||||
"lcd_d7_pe7",
|
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"lcd_d8_pf0",
|
||||
"lcd_d9_pf1",
|
||||
"lcd_d10_pf2",
|
||||
"lcd_d11_pf3",
|
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"lcd_d12_pf4",
|
||||
"lcd_d13_pf5",
|
||||
"lcd_d14_pf6",
|
||||
"lcd_d15_pf7",
|
||||
"lcd_de_pj1",
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||||
"lcd_hsync_pj3",
|
||||
"lcd_vsync_pj4",
|
||||
"lcd_d16_pm0",
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||||
"lcd_d17_pm1",
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||||
"lcd_d18_pm2",
|
||||
"lcd_d19_pm3",
|
||||
"lcd_d20_pm4",
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||||
"lcd_d21_pm5",
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||||
"lcd_d22_pm6",
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||||
"lcd_d23_pm7",
|
||||
"lcd_cs0_n_pn4",
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||||
"lcd_sdout_pn5",
|
||||
"lcd_dc0_pn6",
|
||||
"lcd_cs1_n_pw0",
|
||||
"lcd_sdin_pz2",
|
||||
"lcd_sck_pz4";
|
||||
nvidia,function = "displaya";
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||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
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uart3_rts_n_pc0 {
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||||
nvidia,pins = "uart3_rts_n_pc0",
|
||||
"uart3_txd_pw6";
|
||||
nvidia,function = "uartc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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||||
};
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uart2_txd_pc2 {
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||||
nvidia,pins = "uart2_txd_pc2",
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||||
"uart2_rts_n_pj6";
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nvidia,function = "uartb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
uart2_rxd_pc3 {
|
||||
nvidia,pins = "uart2_rxd_pc3",
|
||||
"uart2_cts_n_pj5";
|
||||
nvidia,function = "uartb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
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||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
gen1_i2c_scl_pc4 {
|
||||
nvidia,pins = "gen1_i2c_scl_pc4",
|
||||
"gen1_i2c_sda_pc5";
|
||||
nvidia,function = "i2c1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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||||
};
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gmi_wp_n_pc7 {
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||||
nvidia,pins = "gmi_wp_n_pc7",
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"gmi_wait_pi7",
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"gmi_cs4_n_pk2",
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"gmi_cs3_n_pk4";
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||||
nvidia,function = "rsvd1";
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||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
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||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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||||
};
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||||
gmi_ad12_ph4 {
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||||
nvidia,pins = "gmi_ad12_ph4",
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"gmi_cs0_n_pj0",
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"gmi_cs1_n_pj2",
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||||
"gmi_cs2_n_pk3";
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nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc3_dat5_pd0 {
|
||||
nvidia,pins = "sdmmc3_dat5_pd0";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
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||||
gmi_ad0_pg0 {
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||||
nvidia,pins = "gmi_ad0_pg0",
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||||
"gmi_ad1_pg1",
|
||||
"gmi_ad14_ph6",
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||||
"pu1";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_ad2_pg2 {
|
||||
nvidia,pins = "gmi_ad2_pg2",
|
||||
"gmi_ad3_pg3",
|
||||
"gmi_ad6_pg6",
|
||||
"gmi_ad7_pg7";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_ad4_pg4 {
|
||||
nvidia,pins = "gmi_ad4_pg4",
|
||||
"gmi_ad5_pg5";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
gmi_ad8_ph0 {
|
||||
nvidia,pins = "gmi_ad8_ph0";
|
||||
nvidia,function = "pwm0";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_ad9_ph1 {
|
||||
nvidia,pins = "gmi_ad9_ph1";
|
||||
nvidia,function = "rsvd4";
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||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_ad10_ph2 {
|
||||
nvidia,pins = "gmi_ad10_ph2";
|
||||
nvidia,function = "pwm2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_ad11_ph3 {
|
||||
nvidia,pins = "gmi_ad11_ph3";
|
||||
nvidia,function = "pwm3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_ad13_ph5 {
|
||||
nvidia,pins = "gmi_ad13_ph5",
|
||||
"gmi_wr_n_pi0",
|
||||
"gmi_oe_n_pi1",
|
||||
"gmi_adv_n_pk0";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_ad15_ph7 {
|
||||
nvidia,pins = "gmi_ad15_ph7";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_dqs_pi2 {
|
||||
nvidia,pins = "gmi_dqs_pi2",
|
||||
"pu2",
|
||||
"pv1";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
gmi_rst_n_pi4 {
|
||||
nvidia,pins = "gmi_rst_n_pi4";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_iordy_pi5 {
|
||||
nvidia,pins = "gmi_iordy_pi5";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
gmi_cs7_n_pi6 {
|
||||
nvidia,pins = "gmi_cs7_n_pi6",
|
||||
"gmi_clk_pk1";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_a16_pj7 {
|
||||
nvidia,pins = "gmi_a16_pj7",
|
||||
"gmi_a19_pk7";
|
||||
nvidia,function = "uartd";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
spdif_out_pk5 {
|
||||
nvidia,pins = "spdif_out_pk5";
|
||||
nvidia,function = "spdif";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
spdif_in_pk6 {
|
||||
nvidia,pins = "spdif_in_pk6";
|
||||
nvidia,function = "spdif";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap1_fs_pn0 {
|
||||
nvidia,pins = "dap1_fs_pn0",
|
||||
"dap1_din_pn1",
|
||||
"dap1_dout_pn2",
|
||||
"dap1_sclk_pn3";
|
||||
nvidia,function = "i2s0";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
hdmi_int_pn7 {
|
||||
nvidia,pins = "hdmi_int_pn7";
|
||||
nvidia,function = "hdmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ulpi_data7_po0 {
|
||||
nvidia,pins = "ulpi_data7_po0";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
ulpi_data3_po4 {
|
||||
nvidia,pins = "ulpi_data3_po4";
|
||||
nvidia,function = "ulpi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap3_fs_pp0 {
|
||||
nvidia,pins = "dap3_fs_pp0";
|
||||
nvidia,function = "i2s2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
dap4_fs_pp4 {
|
||||
nvidia,pins = "dap4_fs_pp4",
|
||||
"dap4_din_pp5",
|
||||
"dap4_dout_pp6",
|
||||
"dap4_sclk_pp7";
|
||||
nvidia,function = "i2s3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
kb_col0_pq0 {
|
||||
nvidia,pins = "kb_col0_pq0",
|
||||
"kb_col1_pq1",
|
||||
"kb_row1_pr1";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
kb_col2_pq2 {
|
||||
nvidia,pins = "kb_col2_pq2",
|
||||
"kb_col3_pq3";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
kb_col4_pq4 {
|
||||
nvidia,pins = "kb_col4_pq4",
|
||||
"kb_col5_pq5",
|
||||
"kb_col7_pq7",
|
||||
"kb_row2_pr2",
|
||||
"kb_row4_pr4",
|
||||
"kb_row5_pr5",
|
||||
"kb_row14_ps6";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
kb_row0_pr0 {
|
||||
nvidia,pins = "kb_row0_pr0";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
kb_row6_pr6 {
|
||||
nvidia,pins = "kb_row6_pr6",
|
||||
"kb_row8_ps0",
|
||||
"kb_row9_ps1",
|
||||
"kb_row10_ps2";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
kb_row11_ps3 {
|
||||
nvidia,pins = "kb_row11_ps3",
|
||||
"kb_row12_ps4";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
gen2_i2c_scl_pt5 {
|
||||
nvidia,pins = "gen2_i2c_scl_pt5",
|
||||
"gen2_i2c_sda_pt6";
|
||||
nvidia,function = "i2c2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc4_cmd_pt7 {
|
||||
nvidia,pins = "sdmmc4_cmd_pt7",
|
||||
"sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pu0 {
|
||||
nvidia,pins = "pu0",
|
||||
"pu6";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
jtag_rtck_pu7 {
|
||||
nvidia,pins = "jtag_rtck_pu7";
|
||||
nvidia,function = "rtck";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pv0 {
|
||||
nvidia,pins = "pv0";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ddc_scl_pv4 {
|
||||
nvidia,pins = "ddc_scl_pv4",
|
||||
"ddc_sda_pv5";
|
||||
nvidia,function = "i2c4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
crt_hsync_pv6 {
|
||||
nvidia,pins = "crt_hsync_pv6",
|
||||
"crt_vsync_pv7";
|
||||
nvidia,function = "crt";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
spi2_cs1_n_pw2 {
|
||||
nvidia,pins = "spi2_cs1_n_pw2",
|
||||
"spi2_miso_px1",
|
||||
"spi2_sck_px2";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
clk1_out_pw4 {
|
||||
nvidia,pins = "clk1_out_pw4";
|
||||
nvidia,function = "extperiph1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
clk2_out_pw5 {
|
||||
nvidia,pins = "clk2_out_pw5";
|
||||
nvidia,function = "extperiph2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
spi2_cs0_n_px3 {
|
||||
nvidia,pins = "spi2_cs0_n_px3";
|
||||
nvidia,function = "spi6";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
spi1_mosi_px4 {
|
||||
nvidia,pins = "spi1_mosi_px4",
|
||||
"spi1_cs0_n_px6";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ulpi_clk_py0 {
|
||||
nvidia,pins = "ulpi_clk_py0",
|
||||
"ulpi_dir_py1";
|
||||
nvidia,function = "ulpi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sdmmc1_dat3_py4 {
|
||||
nvidia,pins = "sdmmc1_dat3_py4",
|
||||
"sdmmc1_dat2_py5",
|
||||
"sdmmc1_dat1_py6",
|
||||
"sdmmc1_dat0_py7",
|
||||
"sdmmc1_cmd_pz1";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc1_clk_pz0 {
|
||||
nvidia,pins = "sdmmc1_clk_pz0";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
lcd_wr_n_pz3 {
|
||||
nvidia,pins = "lcd_wr_n_pz3";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sys_clk_req_pz5 {
|
||||
nvidia,pins = "sys_clk_req_pz5";
|
||||
nvidia,function = "sysclk";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pwr_i2c_scl_pz6 {
|
||||
nvidia,pins = "pwr_i2c_scl_pz6",
|
||||
"pwr_i2c_sda_pz7";
|
||||
nvidia,function = "i2cpwr";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pbb0 {
|
||||
nvidia,pins = "pbb0",
|
||||
"pcc1";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
cam_i2c_scl_pbb1 {
|
||||
nvidia,pins = "cam_i2c_scl_pbb1",
|
||||
"cam_i2c_sda_pbb2";
|
||||
nvidia,function = "i2c3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pbb3 {
|
||||
nvidia,pins = "pbb3";
|
||||
nvidia,function = "vgp3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pbb4 {
|
||||
nvidia,pins = "pbb4";
|
||||
nvidia,function = "vgp4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pbb5 {
|
||||
nvidia,pins = "pbb5";
|
||||
nvidia,function = "vgp5";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pbb6 {
|
||||
nvidia,pins = "pbb6";
|
||||
nvidia,function = "vgp6";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pbb7 {
|
||||
nvidia,pins = "pbb7",
|
||||
"pcc2";
|
||||
nvidia,function = "i2s4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
cam_mclk_pcc0 {
|
||||
nvidia,pins = "cam_mclk_pcc0";
|
||||
nvidia,function = "vi_alt3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc4_rst_n_pcc3 {
|
||||
nvidia,pins = "sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
clk2_req_pcc5 {
|
||||
nvidia,pins = "clk2_req_pcc5";
|
||||
nvidia,function = "dap";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pex_l2_rst_n_pcc6 {
|
||||
nvidia,pins = "pex_l2_rst_n_pcc6",
|
||||
"pex_l2_clkreq_n_pcc7";
|
||||
nvidia,function = "pcie";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pex_wake_n_pdd3 {
|
||||
nvidia,pins = "pex_wake_n_pdd3",
|
||||
"pex_l2_prsnt_n_pdd7";
|
||||
nvidia,function = "pcie";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
clk3_out_pee0 {
|
||||
nvidia,pins = "clk3_out_pee0";
|
||||
nvidia,function = "extperiph3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
clk1_req_pee2 {
|
||||
nvidia,pins = "clk1_req_pee2";
|
||||
nvidia,function = "dap";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
hdmi_cec_pee3 {
|
||||
nvidia,pins = "hdmi_cec_pee3";
|
||||
nvidia,function = "cec";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
owr {
|
||||
nvidia,pins = "owr";
|
||||
nvidia,function = "owr";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
drive_dap1 {
|
||||
nvidia,pins = "drive_dap1",
|
||||
"drive_dap2",
|
||||
"drive_dbg",
|
||||
"drive_at5",
|
||||
"drive_gme",
|
||||
"drive_ddc",
|
||||
"drive_ao1",
|
||||
"drive_uart3";
|
||||
nvidia,high-speed-mode = <0>;
|
||||
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
||||
nvidia,pull-down-strength = <31>;
|
||||
nvidia,pull-up-strength = <31>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
};
|
||||
drive_sdio1 {
|
||||
nvidia,pins = "drive_sdio1",
|
||||
"drive_sdio3";
|
||||
nvidia,high-speed-mode = <0>;
|
||||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull-down-strength = <46>;
|
||||
nvidia,pull-up-strength = <42>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
|
||||
};
|
||||
drive_gma {
|
||||
nvidia,pins = "drive_gma",
|
||||
"drive_gmb",
|
||||
"drive_gmc",
|
||||
"drive_gmd";
|
||||
nvidia,pull-down-strength = <9>;
|
||||
nvidia,pull-up-strength = <9>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uarta: serial@70006000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -7,6 +7,119 @@
|
||||
model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) E1565";
|
||||
compatible = "asus,grouper", "nvidia,tegra30";
|
||||
|
||||
pinmux@70000868 {
|
||||
state_default: pinmux {
|
||||
lcd_dc1_pd2 {
|
||||
nvidia,pins = "lcd_dc1_pd2";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
lcd_pwr2_pc6 {
|
||||
nvidia,pins = "lcd_pwr2_pc6";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
spi2_cs2_n_pw3 {
|
||||
nvidia,pins = "spi2_cs2_n_pw3";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
spi1_sck_px5 {
|
||||
nvidia,pins = "spi1_sck_px5";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pu5 {
|
||||
nvidia,pins = "pu5";
|
||||
nvidia,function = "pwm2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
spi1_miso_px7 {
|
||||
nvidia,pins = "spi1_miso_px7";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
spi2_mosi_px0 {
|
||||
nvidia,pins = "spi2_mosi_px0";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
kb_row7_pr7 {
|
||||
nvidia,pins = "kb_row7_pr7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pu3 {
|
||||
nvidia,pins = "pu3";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pu4 {
|
||||
nvidia,pins = "pu4";
|
||||
nvidia,function = "pwm1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
kb_row15_ps7 {
|
||||
nvidia,pins = "kb_row15_ps7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
kb_row3_pr3 {
|
||||
nvidia,pins = "kb_row3_pr3";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
kb_row13_ps5 {
|
||||
nvidia,pins = "kb_row13_ps5";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_wp_n_pc7 {
|
||||
nvidia,pins = "gmi_wp_n_pc7",
|
||||
"gmi_wait_pi7",
|
||||
"gmi_cs4_n_pk2",
|
||||
"gmi_cs3_n_pk4";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_cs6_n_pi3 {
|
||||
nvidia,pins = "gmi_cs6_n_pi3";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000d000 {
|
||||
pmic: max77663@3c {
|
||||
compatible = "maxim,max77663";
|
||||
|
||||
@ -7,6 +7,119 @@
|
||||
model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269";
|
||||
compatible = "asus,grouper", "nvidia,tegra30";
|
||||
|
||||
pinmux@70000868 {
|
||||
state_default: pinmux {
|
||||
lcd_dc1_pd2 {
|
||||
nvidia,pins = "lcd_dc1_pd2";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
lcd_pwr2_pc6 {
|
||||
nvidia,pins = "lcd_pwr2_pc6";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
spi2_cs2_n_pw3 {
|
||||
nvidia,pins = "spi2_cs2_n_pw3";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
spi1_sck_px5 {
|
||||
nvidia,pins = "spi1_sck_px5";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pu5 {
|
||||
nvidia,pins = "pu5";
|
||||
nvidia,function = "pwm2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
spi1_miso_px7 {
|
||||
nvidia,pins = "spi1_miso_px7";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
spi2_mosi_px0 {
|
||||
nvidia,pins = "spi2_mosi_px0";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
kb_row7_pr7 {
|
||||
nvidia,pins = "kb_row7_pr7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pu3 {
|
||||
nvidia,pins = "pu3";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pu4 {
|
||||
nvidia,pins = "pu4";
|
||||
nvidia,function = "pwm1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
kb_row15_ps7 {
|
||||
nvidia,pins = "kb_row15_ps7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
kb_row3_pr3 {
|
||||
nvidia,pins = "kb_row3_pr3";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
kb_row13_ps5 {
|
||||
nvidia,pins = "kb_row13_ps5";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_wp_n_pc7 {
|
||||
nvidia,pins = "gmi_wp_n_pc7",
|
||||
"gmi_wait_pi7",
|
||||
"gmi_cs4_n_pk2",
|
||||
"gmi_cs3_n_pk4";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_cs6_n_pi3 {
|
||||
nvidia,pins = "gmi_cs6_n_pi3";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000d000 {
|
||||
/* Texas Instruments TPS659110 PMIC */
|
||||
pmic: tps65911@2d {
|
||||
|
||||
@ -7,6 +7,155 @@
|
||||
model = "ASUS Google Nexus 7 (Project Bach / ME370TG) E1565";
|
||||
compatible = "asus,tilapia", "nvidia,tegra30";
|
||||
|
||||
pinmux@70000868 {
|
||||
state_default: pinmux {
|
||||
lcd_dc1_pd2 {
|
||||
nvidia,pins = "lcd_dc1_pd2";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
lcd_pwr2_pc6 {
|
||||
nvidia,pins = "lcd_pwr2_pc6";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
spi2_cs2_n_pw3 {
|
||||
nvidia,pins = "spi2_cs2_n_pw3";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap3_din_pp1 {
|
||||
nvidia,pins = "dap3_din_pp1";
|
||||
nvidia,function = "i2s2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
spi1_sck_px5 {
|
||||
nvidia,pins = "spi1_sck_px5";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pu5 {
|
||||
nvidia,pins = "pu5";
|
||||
nvidia,function = "pwm2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
spi1_miso_px7 {
|
||||
nvidia,pins = "spi1_miso_px7";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
spi2_mosi_px0 {
|
||||
nvidia,pins = "spi2_mosi_px0";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
clk3_req_pee1 {
|
||||
nvidia,pins = "clk3_req_pee1";
|
||||
nvidia,function = "dev3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ulpi_nxt_py2 {
|
||||
nvidia,pins = "ulpi_nxt_py2";
|
||||
nvidia,function = "uartd";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
ulpi_stp_py3 {
|
||||
nvidia,pins = "ulpi_stp_py3";
|
||||
nvidia,function = "uartd";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
kb_row7_pr7 {
|
||||
nvidia,pins = "kb_row7_pr7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pu4 {
|
||||
nvidia,pins = "pu4";
|
||||
nvidia,function = "pwm1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pu3 {
|
||||
nvidia,pins = "pu3";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
kb_row15_ps7 {
|
||||
nvidia,pins = "kb_row15_ps7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap3_sclk_pp3 {
|
||||
nvidia,pins = "dap3_sclk_pp3";
|
||||
nvidia,function = "i2s2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
kb_row3_pr3 {
|
||||
nvidia,pins = "kb_row3_pr3",
|
||||
"kb_row13_ps5";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
kb_row13_ps5 {
|
||||
nvidia,pins = "kb_row13_ps5";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
gmi_wp_n_pc7 {
|
||||
nvidia,pins = "gmi_wp_n_pc7",
|
||||
"gmi_wait_pi7",
|
||||
"gmi_cs4_n_pk2",
|
||||
"gmi_cs3_n_pk4";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
gmi_cs6_n_pi3 {
|
||||
nvidia,pins = "gmi_cs6_n_pi3";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000d000 {
|
||||
pmic: max77663@3c {
|
||||
compatible = "maxim,max77663";
|
||||
|
||||
@ -60,6 +60,988 @@
|
||||
};
|
||||
};
|
||||
|
||||
pinmux@70000868 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
/* SDMMC1 pinmux */
|
||||
sdmmc1_clk {
|
||||
nvidia,pins = "sdmmc1_clk_pz0";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc1_cmd {
|
||||
nvidia,pins = "sdmmc1_dat3_py4",
|
||||
"sdmmc1_dat2_py5",
|
||||
"sdmmc1_dat1_py6",
|
||||
"sdmmc1_dat0_py7",
|
||||
"sdmmc1_cmd_pz1";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc1_cd {
|
||||
nvidia,pins = "gmi_iordy_pi5";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc1_wp {
|
||||
nvidia,pins = "vi_d11_pt3";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* SDMMC2 pinmux */
|
||||
vi_d1_pd5 {
|
||||
nvidia,pins = "vi_d1_pd5",
|
||||
"vi_d2_pl0",
|
||||
"vi_d3_pl1",
|
||||
"vi_d5_pl3",
|
||||
"vi_d7_pl5";
|
||||
nvidia,function = "sdmmc2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
vi_d8_pl6 {
|
||||
nvidia,pins = "vi_d8_pl6",
|
||||
"vi_d9_pl7";
|
||||
nvidia,function = "sdmmc2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
nvidia,ioreset = <0>;
|
||||
};
|
||||
|
||||
/* SDMMC3 pinmux */
|
||||
sdmmc3_clk {
|
||||
nvidia,pins = "sdmmc3_clk_pa6";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc3_cmd {
|
||||
nvidia,pins = "sdmmc3_cmd_pa7",
|
||||
"sdmmc3_dat0_pb7",
|
||||
"sdmmc3_dat1_pb6",
|
||||
"sdmmc3_dat2_pb5",
|
||||
"sdmmc3_dat3_pb4",
|
||||
"sdmmc3_dat4_pd1",
|
||||
"sdmmc3_dat5_pd0",
|
||||
"sdmmc3_dat6_pd3",
|
||||
"sdmmc3_dat7_pd4";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* SDMMC4 pinmux */
|
||||
sdmmc4_clk {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc4_cmd {
|
||||
nvidia,pins = "sdmmc4_cmd_pt7",
|
||||
"sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc4_rst_n {
|
||||
nvidia,pins = "sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
cam_mclk {
|
||||
nvidia,pins = "cam_mclk_pcc0";
|
||||
nvidia,function = "vi_alt3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
drive_sdmmc4 {
|
||||
nvidia,pins = "drive_gma",
|
||||
"drive_gmb",
|
||||
"drive_gmc",
|
||||
"drive_gmd";
|
||||
nvidia,pull-down-strength = <9>;
|
||||
nvidia,pull-up-strength = <9>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
||||
};
|
||||
|
||||
/* I2C pinmux */
|
||||
gen1_i2c {
|
||||
nvidia,pins = "gen1_i2c_scl_pc4",
|
||||
"gen1_i2c_sda_pc5";
|
||||
nvidia,function = "i2c1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
gen2_i2c {
|
||||
nvidia,pins = "gen2_i2c_scl_pt5",
|
||||
"gen2_i2c_sda_pt6";
|
||||
nvidia,function = "i2c2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
cam_i2c {
|
||||
nvidia,pins = "cam_i2c_scl_pbb1",
|
||||
"cam_i2c_sda_pbb2";
|
||||
nvidia,function = "i2c3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
ddc_i2c {
|
||||
nvidia,pins = "ddc_scl_pv4",
|
||||
"ddc_sda_pv5";
|
||||
nvidia,function = "i2c4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
pwr_i2c {
|
||||
nvidia,pins = "pwr_i2c_scl_pz6",
|
||||
"pwr_i2c_sda_pz7";
|
||||
nvidia,function = "i2cpwr";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
hotplug_i2c {
|
||||
nvidia,pins = "pu4";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* HDMI pinmux */
|
||||
hdmi_cec {
|
||||
nvidia,pins = "hdmi_cec_pee3";
|
||||
nvidia,function = "cec";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
hdmi_hpd {
|
||||
nvidia,pins = "hdmi_int_pn7";
|
||||
nvidia,function = "hdmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* UART-A */
|
||||
ulpi_data0_po1 {
|
||||
nvidia,pins = "ulpi_data0_po1";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
ulpi_data1_po2 {
|
||||
nvidia,pins = "ulpi_data1_po2";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ulpi_data5_po6 {
|
||||
nvidia,pins = "ulpi_data5_po6";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ulpi_data7_po0 {
|
||||
nvidia,pins = "ulpi_data7_po0",
|
||||
"ulpi_data2_po3",
|
||||
"ulpi_data3_po4",
|
||||
"ulpi_data4_po5",
|
||||
"ulpi_data6_po7";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* UART-B */
|
||||
uartb_txd_rts {
|
||||
nvidia,pins = "uart2_txd_pc2",
|
||||
"uart2_rts_n_pj6";
|
||||
nvidia,function = "uartb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
uartb_rxd_cts {
|
||||
nvidia,pins = "uart2_rxd_pc3",
|
||||
"uart2_cts_n_pj5";
|
||||
nvidia,function = "uartb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* UART-C */
|
||||
uartc_rxd_cts {
|
||||
nvidia,pins = "uart3_cts_n_pa1",
|
||||
"uart3_rxd_pw7";
|
||||
nvidia,function = "uartc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
uartc_txd_rts {
|
||||
nvidia,pins = "uart3_rts_n_pc0",
|
||||
"uart3_txd_pw6";
|
||||
nvidia,function = "uartc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* UART-D */
|
||||
ulpi_nxt_py2 {
|
||||
nvidia,pins = "ulpi_nxt_py2";
|
||||
nvidia,function = "uartd";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ulpi_clk_py0 {
|
||||
nvidia,pins = "ulpi_clk_py0",
|
||||
"ulpi_dir_py1",
|
||||
"ulpi_stp_py3";
|
||||
nvidia,function = "uartd";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* I2S pinmux */
|
||||
dap_i2s0 {
|
||||
nvidia,pins = "dap1_fs_pn0",
|
||||
"dap1_din_pn1",
|
||||
"dap1_dout_pn2",
|
||||
"dap1_sclk_pn3";
|
||||
nvidia,function = "i2s0";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap_i2s1 {
|
||||
nvidia,pins = "dap2_fs_pa2",
|
||||
"dap2_sclk_pa3",
|
||||
"dap2_din_pa4",
|
||||
"dap2_dout_pa5";
|
||||
nvidia,function = "i2s1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap3_fs {
|
||||
nvidia,pins = "dap3_fs_pp0",
|
||||
"dap3_din_pp1";
|
||||
nvidia,function = "i2s2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap3_dout {
|
||||
nvidia,pins = "dap3_dout_pp2",
|
||||
"dap3_sclk_pp3";
|
||||
nvidia,function = "i2s2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap_i2s3 {
|
||||
nvidia,pins = "dap4_fs_pp4",
|
||||
"dap4_din_pp5",
|
||||
"dap4_dout_pp6",
|
||||
"dap4_sclk_pp7";
|
||||
nvidia,function = "i2s3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* sensors pinmux */
|
||||
nct_irq {
|
||||
nvidia,pins = "pcc2";
|
||||
nvidia,function = "i2s4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Asus EC pinmux */
|
||||
ec_irqs {
|
||||
nvidia,pins = "kb_row10_ps2",
|
||||
"kb_row15_ps7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ec_reqs {
|
||||
nvidia,pins = "kb_col1_pq1";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* memory type bootstrap */
|
||||
mem_boostraps {
|
||||
nvidia,pins = "gmi_ad4_pg4",
|
||||
"gmi_ad5_pg5";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* PCI-e pinmux */
|
||||
pex_l2_rst_n {
|
||||
nvidia,pins = "pex_l2_rst_n_pcc6",
|
||||
"pex_l0_rst_n_pdd1",
|
||||
"pex_l1_rst_n_pdd5";
|
||||
nvidia,function = "pcie";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pex_l2_clkreq_n {
|
||||
nvidia,pins = "pex_l2_clkreq_n_pcc7",
|
||||
"pex_l0_prsnt_n_pdd0",
|
||||
"pex_l0_clkreq_n_pdd2",
|
||||
"pex_wake_n_pdd3",
|
||||
"pex_l1_prsnt_n_pdd4",
|
||||
"pex_l1_clkreq_n_pdd6",
|
||||
"pex_l2_prsnt_n_pdd7";
|
||||
nvidia,function = "pcie";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* SPI pinmux */
|
||||
spi1_mosi_px4 {
|
||||
nvidia,pins = "spi1_mosi_px4",
|
||||
"spi1_sck_px5",
|
||||
"spi1_cs0_n_px6",
|
||||
"spi1_miso_px7";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
spi2_cs1_n_pw2 {
|
||||
nvidia,pins = "spi2_cs1_n_pw2";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
spi2_sck_px2 {
|
||||
nvidia,pins = "spi2_sck_px2";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
gmi_a17_pb0 {
|
||||
nvidia,pins = "gmi_a17_pb0",
|
||||
"gmi_a16_pj7";
|
||||
nvidia,function = "spi4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_a18_pb1 {
|
||||
nvidia,pins = "gmi_a18_pb1";
|
||||
nvidia,function = "spi4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
gmi_a19_pk7 {
|
||||
nvidia,pins = "gmi_a19_pk7";
|
||||
nvidia,function = "spi4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Display A pinmux */
|
||||
lcd_pwr0_pb2 {
|
||||
nvidia,pins = "lcd_pwr0_pb2",
|
||||
"lcd_pclk_pb3",
|
||||
"lcd_pwr1_pc1",
|
||||
"lcd_d0_pe0",
|
||||
"lcd_d1_pe1",
|
||||
"lcd_d2_pe2",
|
||||
"lcd_d3_pe3",
|
||||
"lcd_d4_pe4",
|
||||
"lcd_d5_pe5",
|
||||
"lcd_d6_pe6",
|
||||
"lcd_d7_pe7",
|
||||
"lcd_d8_pf0",
|
||||
"lcd_d9_pf1",
|
||||
"lcd_d10_pf2",
|
||||
"lcd_d11_pf3",
|
||||
"lcd_d12_pf4",
|
||||
"lcd_d13_pf5",
|
||||
"lcd_d14_pf6",
|
||||
"lcd_d15_pf7",
|
||||
"lcd_de_pj1",
|
||||
"lcd_hsync_pj3",
|
||||
"lcd_vsync_pj4",
|
||||
"lcd_d16_pm0",
|
||||
"lcd_d17_pm1",
|
||||
"lcd_d18_pm2",
|
||||
"lcd_d19_pm3",
|
||||
"lcd_d20_pm4",
|
||||
"lcd_d21_pm5",
|
||||
"lcd_d22_pm6",
|
||||
"lcd_d23_pm7",
|
||||
"lcd_cs1_n_pw0",
|
||||
"lcd_dc0_pn6",
|
||||
"lcd_sck_pz4",
|
||||
"lcd_sdin_pz2";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
lcd_cs0_n_pn4 {
|
||||
nvidia,pins = "lcd_cs0_n_pn4",
|
||||
"lcd_sdout_pn5",
|
||||
"lcd_wr_n_pz3";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
blink {
|
||||
nvidia,pins = "clk_32k_out_pa0";
|
||||
nvidia,function = "blink";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* KBC keys */
|
||||
kb_col0_pq0 {
|
||||
nvidia,pins = "kb_col0_pq0";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
kb_col1_pq1 {
|
||||
nvidia,pins = "kb_row1_pr1",
|
||||
"kb_row3_pr3",
|
||||
"kb_row9_ps1",
|
||||
"kb_row11_ps3",
|
||||
"kb_row14_ps6",
|
||||
"kb_col6_pq6";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
kb_col4_pq4 {
|
||||
nvidia,pins = "kb_col4_pq4",
|
||||
"kb_col5_pq5",
|
||||
"kb_col7_pq7",
|
||||
"kb_row2_pr2",
|
||||
"kb_row4_pr4",
|
||||
"kb_row5_pr5",
|
||||
"kb_row12_ps4",
|
||||
"kb_row13_ps5";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
gmi_wp_n_pc7 {
|
||||
nvidia,pins = "gmi_wp_n_pc7",
|
||||
"gmi_wait_pi7",
|
||||
"gmi_cs3_n_pk4";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_cs0_n_pj0 {
|
||||
nvidia,pins = "gmi_cs0_n_pj0",
|
||||
"gmi_cs1_n_pj2",
|
||||
"gmi_cs2_n_pk3";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
vi_pclk_pt0 {
|
||||
nvidia,pins = "vi_pclk_pt0";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
nvidia,ioreset = <0>;
|
||||
};
|
||||
|
||||
/* GPIO keys pinmux */
|
||||
power_key {
|
||||
nvidia,pins = "pv0";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
vol_keys {
|
||||
nvidia,pins = "kb_col2_pq2",
|
||||
"kb_col3_pq3";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Bluetooth */
|
||||
bt_shutdown {
|
||||
nvidia,pins = "pu0";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
bt_dev_wake {
|
||||
nvidia,pins = "pu1";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
bt_host_wake {
|
||||
nvidia,pins = "pu6";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pu2 {
|
||||
nvidia,pins = "pu2";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pu3 {
|
||||
nvidia,pins = "pu3";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pcc1 {
|
||||
nvidia,pins = "pcc1";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pv2 {
|
||||
nvidia,pins = "pv2";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pv3 {
|
||||
nvidia,pins = "pv3";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
vi_vsync_pd6 {
|
||||
nvidia,pins = "vi_vsync_pd6",
|
||||
"vi_hsync_pd7";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
nvidia,ioreset = <0>;
|
||||
};
|
||||
vi_d10_pt2 {
|
||||
nvidia,pins = "vi_d10_pt2",
|
||||
"vi_d0_pt4", "pbb0";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
kb_row0_pr0 {
|
||||
nvidia,pins = "kb_row0_pr0";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
gmi_ad0_pg0 {
|
||||
nvidia,pins = "gmi_ad0_pg0",
|
||||
"gmi_ad1_pg1",
|
||||
"gmi_ad2_pg2",
|
||||
"gmi_ad3_pg3",
|
||||
"gmi_ad6_pg6",
|
||||
"gmi_ad7_pg7",
|
||||
"gmi_wr_n_pi0",
|
||||
"gmi_oe_n_pi1",
|
||||
"gmi_dqs_pi2",
|
||||
"gmi_adv_n_pk0",
|
||||
"gmi_clk_pk1";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_ad13_ph5 {
|
||||
nvidia,pins = "gmi_ad13_ph5";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
gmi_ad10_ph2 {
|
||||
nvidia,pins = "gmi_ad10_ph2",
|
||||
"gmi_ad11_ph3",
|
||||
"gmi_ad14_ph6";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_ad12_ph4 {
|
||||
nvidia,pins = "gmi_ad12_ph4",
|
||||
"gmi_rst_n_pi4";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
/* USB2 VBUS control */
|
||||
usb2_vbus_control {
|
||||
nvidia,pins = "gmi_ad15_ph7";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
/* PWM pinmux */
|
||||
pwm_0 {
|
||||
nvidia,pins = "gmi_ad8_ph0";
|
||||
nvidia,function = "pwm0";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pwm_1 {
|
||||
nvidia,pins = "gmi_ad9_ph1";
|
||||
nvidia,function = "pwm1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pwm_2 {
|
||||
nvidia,pins = "pu5";
|
||||
nvidia,function = "pwm2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* S/PDIF pinmux */
|
||||
spdif_out {
|
||||
nvidia,pins = "spdif_out_pk5";
|
||||
nvidia,function = "spdif";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
spdif_in {
|
||||
nvidia,pins = "spdif_in_pk6";
|
||||
nvidia,function = "spdif";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
vi_d4_pl2 {
|
||||
nvidia,pins = "vi_d4_pl2";
|
||||
nvidia,function = "vi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
vi_d6_pl4 {
|
||||
nvidia,pins = "vi_d6_pl4";
|
||||
nvidia,function = "vi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,lock = <0>;
|
||||
nvidia,ioreset = <0>;
|
||||
};
|
||||
vi_mclk_pt1 {
|
||||
nvidia,pins = "vi_mclk_pt1";
|
||||
nvidia,function = "vi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
jtag_rtck {
|
||||
nvidia,pins = "jtag_rtck_pu7";
|
||||
nvidia,function = "rtck";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
crt_hsync_pv6 {
|
||||
nvidia,pins = "crt_hsync_pv6",
|
||||
"crt_vsync_pv7";
|
||||
nvidia,function = "crt";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
clk1_out {
|
||||
nvidia,pins = "clk1_out_pw4";
|
||||
nvidia,function = "extperiph1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
clk2_out {
|
||||
nvidia,pins = "clk2_out_pw5";
|
||||
nvidia,function = "extperiph2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
clk3_out {
|
||||
nvidia,pins = "clk3_out_pee0";
|
||||
nvidia,function = "extperiph3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sys_clk_req {
|
||||
nvidia,pins = "sys_clk_req_pz5";
|
||||
nvidia,function = "sysclk";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pbb4 {
|
||||
nvidia,pins = "pbb4";
|
||||
nvidia,function = "vgp4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pbb5 {
|
||||
nvidia,pins = "pbb5";
|
||||
nvidia,function = "vgp5";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pbb6 {
|
||||
nvidia,pins = "pbb6";
|
||||
nvidia,function = "vgp6";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
clk2_req_pcc5 {
|
||||
nvidia,pins = "clk2_req_pcc5",
|
||||
"clk1_req_pee2";
|
||||
nvidia,function = "dap";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
clk3_req_pee1 {
|
||||
nvidia,pins = "clk3_req_pee1";
|
||||
nvidia,function = "dev3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
owr {
|
||||
nvidia,pins = "owr";
|
||||
nvidia,function = "owr";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* P1801-T specific pinmux */
|
||||
lcd_pwr2 {
|
||||
nvidia,pins = "lcd_pwr2_pc6",
|
||||
"lcd_dc1_pd2";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
lcd_m1 {
|
||||
nvidia,pins = "lcd_m1_pw1";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
key_mode {
|
||||
nvidia,pins = "gmi_cs4_n_pk2";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
splashtop {
|
||||
nvidia,pins = "gmi_cs6_n_pi3";
|
||||
nvidia,function = "nand_alt";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
w8_detect {
|
||||
nvidia,pins = "gmi_cs7_n_pi6";
|
||||
nvidia,function = "nand_alt";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pbb3 {
|
||||
nvidia,pins = "pbb3";
|
||||
nvidia,function = "vgp3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pbb7 {
|
||||
nvidia,pins = "pbb7";
|
||||
nvidia,function = "i2s4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
spi2_mosi_px0 {
|
||||
nvidia,pins = "spi2_mosi_px0";
|
||||
nvidia,function = "spi6";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
tp_vendor {
|
||||
nvidia,pins = "kb_row6_pr6",
|
||||
"kb_row7_pr7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
tp_power {
|
||||
nvidia,pins = "kb_row8_ps0";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* GPIO power/drive control */
|
||||
drive_dap1 {
|
||||
nvidia,pins = "drive_dap1",
|
||||
"drive_dap2",
|
||||
"drive_dbg",
|
||||
"drive_at5",
|
||||
"drive_gme",
|
||||
"drive_ddc",
|
||||
"drive_ao1",
|
||||
"drive_uart3";
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
||||
nvidia,pull-down-strength = <31>;
|
||||
nvidia,pull-up-strength = <31>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
};
|
||||
drive_sdio1 {
|
||||
nvidia,pins = "drive_sdio1",
|
||||
"drive_sdio3";
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull-down-strength = <46>;
|
||||
nvidia,pull-up-strength = <42>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uarta: serial@70006000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -7,6 +7,51 @@
|
||||
model = "ASUS Transformer Prime TF201";
|
||||
compatible = "asus,tf201", "nvidia,tegra30";
|
||||
|
||||
pinmux@70000868 {
|
||||
state_default: pinmux {
|
||||
lcd_pwr2_pc6 {
|
||||
nvidia,pins = "lcd_pwr2_pc6",
|
||||
"lcd_dc1_pd2";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pbb3 {
|
||||
nvidia,pins = "pbb3";
|
||||
nvidia,function = "vgp3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pbb7 {
|
||||
nvidia,pins = "pbb7";
|
||||
nvidia,function = "i2s4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
kb_row7_pr7 {
|
||||
nvidia,pins = "kb_row7_pr7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
gmi_cs4_n_pk2 {
|
||||
nvidia,pins = "gmi_cs4_n_pk2";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb-phy@7d008000 {
|
||||
/delete-property/ nvidia,xcvr-setup-use-fuses;
|
||||
nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */
|
||||
|
||||
@ -15,4 +15,49 @@
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
pinmux@70000868 {
|
||||
state_default: pinmux {
|
||||
lcd_pwr2_pc6 {
|
||||
nvidia,pins = "lcd_pwr2_pc6",
|
||||
"lcd_dc1_pd2";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pbb3 {
|
||||
nvidia,pins = "pbb3";
|
||||
nvidia,function = "vgp3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pbb7 {
|
||||
nvidia,pins = "pbb7";
|
||||
nvidia,function = "i2s4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
kb_row7_pr7 {
|
||||
nvidia,pins = "kb_row7_pr7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
gmi_cs4_n_pk2 {
|
||||
nvidia,pins = "gmi_cs4_n_pk2";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -6,4 +6,132 @@
|
||||
/ {
|
||||
model = "ASUS Transformer Pad 3G TF300TG";
|
||||
compatible = "asus,tf300tg", "nvidia,tegra30";
|
||||
|
||||
pinmux@70000868 {
|
||||
state_default: pinmux {
|
||||
pbb3 {
|
||||
nvidia,pins = "pbb3";
|
||||
nvidia,function = "vgp3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pbb7 {
|
||||
nvidia,pins = "pbb7";
|
||||
nvidia,function = "i2s4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
gmi_cs4_n_pk2 {
|
||||
nvidia,pins = "gmi_cs4_n_pk2";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
lcd_pwr2_pc6 {
|
||||
nvidia,pins = "lcd_pwr2_pc6",
|
||||
"lcd_dc1_pd2";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
kb_row7_pr7 {
|
||||
nvidia,pins = "kb_row7_pr7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
spi2_cs2_n_pw3 {
|
||||
nvidia,pins = "spi2_cs2_n_pw3";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
dap3_din_pp1 {
|
||||
nvidia,pins = "dap3_din_pp1";
|
||||
nvidia,function = "i2s2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
spi1_sck_px5 {
|
||||
nvidia,pins = "spi1_sck_px5";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pu5 {
|
||||
nvidia,pins = "pu5";
|
||||
nvidia,function = "pwm2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
spi2_mosi_px0 {
|
||||
nvidia,pins = "spi2_mosi_px0";
|
||||
nvidia,function = "spi2";
|
||||
};
|
||||
|
||||
spi1_miso_px7 {
|
||||
nvidia,pins = "spi1_miso_px7";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
clk3_req_pee1 {
|
||||
nvidia,pins = "clk3_req_pee1";
|
||||
nvidia,function = "dev3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
ulpi_nxt_py2 {
|
||||
nvidia,pins = "ulpi_nxt_py2";
|
||||
nvidia,function = "uartd";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
ulpi_stp_py3 {
|
||||
nvidia,pins = "ulpi_stp_py3";
|
||||
nvidia,function = "uartd";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pu3 {
|
||||
nvidia,pins = "pu3";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
dap1_din_pn1 {
|
||||
nvidia,pins = "dap1_din_pn1";
|
||||
nvidia,function = "i2s0";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -6,4 +6,167 @@
|
||||
/ {
|
||||
model = "ASUS Transformer Pad LTE TF300TL";
|
||||
compatible = "asus,tf300tl", "nvidia,tegra30";
|
||||
|
||||
pinmux@70000868 {
|
||||
state_default: pinmux {
|
||||
lcd_pwr2_pc6 {
|
||||
nvidia,pins = "lcd_pwr2_pc6",
|
||||
"lcd_dc1_pd2";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
pbb3 {
|
||||
nvidia,pins = "pbb3";
|
||||
nvidia,function = "vgp3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pbb7 {
|
||||
nvidia,pins = "pbb7";
|
||||
nvidia,function = "i2s4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
kb_row7_pr7 {
|
||||
nvidia,pins = "kb_row7_pr7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
gmi_cs4_n_pk2 {
|
||||
nvidia,pins = "gmi_cs4_n_pk2";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* TF300TL specific pinmux reconfiguration */
|
||||
|
||||
ulpi_data5_po6 {
|
||||
nvidia,pins = "ulpi_data5_po6";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
dap3_din_pp1 {
|
||||
nvidia,pins = "dap3_din_pp1";
|
||||
nvidia,function = "i2s2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
crt_hsync_pv6 {
|
||||
nvidia,pins = "crt_hsync_pv6";
|
||||
nvidia,function = "crt";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
crt_vsync_pv7 {
|
||||
nvidia,pins = "crt_vsync_pv7";
|
||||
nvidia,function = "crt";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
pu5 {
|
||||
nvidia,pins = "pu5";
|
||||
nvidia,function = "pwm2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
clk3_out_pee0 {
|
||||
nvidia,pins = "clk3_out_pee0";
|
||||
nvidia,function = "extperiph3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
clk3_req_pee1 {
|
||||
nvidia,pins = "clk3_req_pee1";
|
||||
nvidia,function = "dev3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
dap1_fs_pn0 {
|
||||
nvidia,pins = "dap1_fs_pn0",
|
||||
"dap1_sclk_pn3";
|
||||
nvidia,function = "i2s0";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
dap1_din_pn1 {
|
||||
nvidia,pins = "dap1_din_pn1";
|
||||
nvidia,function = "i2s0";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
dap1_dout_pn2 {
|
||||
nvidia,pins = "dap1_dout_pn2";
|
||||
nvidia,function = "i2s0";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
clk1_req_pee2 {
|
||||
nvidia,pins = "clk1_req_pee2";
|
||||
nvidia,function = "dap";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
spi2_mosi_px0 {
|
||||
nvidia,pins = "spi2_mosi_px0";
|
||||
nvidia,function = "spi2";
|
||||
};
|
||||
|
||||
spi1_sck_px5 {
|
||||
nvidia,pins = "spi1_sck_px5";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
spi1_miso_px7 {
|
||||
nvidia,pins = "spi1_miso_px7";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
spi2_cs2_n_pw3 {
|
||||
nvidia,pins = "spi2_cs2_n_pw3";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -53,6 +53,895 @@
|
||||
};
|
||||
};
|
||||
|
||||
pinmux@70000868 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
/* SDMMC1 pinmux */
|
||||
sdmmc1_clk {
|
||||
nvidia,pins = "sdmmc1_clk_pz0";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc1_cmd {
|
||||
nvidia,pins = "sdmmc1_dat3_py4",
|
||||
"sdmmc1_dat2_py5",
|
||||
"sdmmc1_dat1_py6",
|
||||
"sdmmc1_dat0_py7",
|
||||
"sdmmc1_cmd_pz1";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc1_cd {
|
||||
nvidia,pins = "gmi_iordy_pi5";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc1_wp {
|
||||
nvidia,pins = "vi_d11_pt3";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* SDMMC2 pinmux */
|
||||
vi_d1_pd5 {
|
||||
nvidia,pins = "vi_d1_pd5",
|
||||
"vi_d2_pl0",
|
||||
"vi_d3_pl1",
|
||||
"vi_d5_pl3",
|
||||
"vi_d7_pl5";
|
||||
nvidia,function = "sdmmc2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
vi_d8_pl6 {
|
||||
nvidia,pins = "vi_d8_pl6",
|
||||
"vi_d9_pl7";
|
||||
nvidia,function = "sdmmc2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
nvidia,ioreset = <0>;
|
||||
};
|
||||
|
||||
/* SDMMC3 pinmux */
|
||||
sdmmc3_clk {
|
||||
nvidia,pins = "sdmmc3_clk_pa6";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc3_cmd {
|
||||
nvidia,pins = "sdmmc3_cmd_pa7",
|
||||
"sdmmc3_dat0_pb7",
|
||||
"sdmmc3_dat1_pb6",
|
||||
"sdmmc3_dat2_pb5",
|
||||
"sdmmc3_dat3_pb4",
|
||||
"sdmmc3_dat4_pd1",
|
||||
"sdmmc3_dat5_pd0",
|
||||
"sdmmc3_dat6_pd3",
|
||||
"sdmmc3_dat7_pd4";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* SDMMC4 pinmux */
|
||||
sdmmc4_clk {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc4_cmd {
|
||||
nvidia,pins = "sdmmc4_cmd_pt7",
|
||||
"sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc4_rst_n {
|
||||
nvidia,pins = "sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
cam_mclk {
|
||||
nvidia,pins = "cam_mclk_pcc0";
|
||||
nvidia,function = "vi_alt3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* I2C pinmux */
|
||||
gen1_i2c {
|
||||
nvidia,pins = "gen1_i2c_scl_pc4",
|
||||
"gen1_i2c_sda_pc5";
|
||||
nvidia,function = "i2c1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
gen2_i2c {
|
||||
nvidia,pins = "gen2_i2c_scl_pt5",
|
||||
"gen2_i2c_sda_pt6";
|
||||
nvidia,function = "i2c2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
cam_i2c {
|
||||
nvidia,pins = "cam_i2c_scl_pbb1",
|
||||
"cam_i2c_sda_pbb2";
|
||||
nvidia,function = "i2c3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
ddc_i2c {
|
||||
nvidia,pins = "ddc_scl_pv4",
|
||||
"ddc_sda_pv5";
|
||||
nvidia,function = "i2c4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
pwr_i2c {
|
||||
nvidia,pins = "pwr_i2c_scl_pz6",
|
||||
"pwr_i2c_sda_pz7";
|
||||
nvidia,function = "i2cpwr";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
hotplug_i2c {
|
||||
nvidia,pins = "pu4";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* HDMI pinmux */
|
||||
hdmi_cec {
|
||||
nvidia,pins = "hdmi_cec_pee3";
|
||||
nvidia,function = "cec";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
hdmi_hpd {
|
||||
nvidia,pins = "hdmi_int_pn7";
|
||||
nvidia,function = "hdmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* UART-A */
|
||||
ulpi_data0_po1 {
|
||||
nvidia,pins = "ulpi_data0_po1";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
ulpi_data1_po2 {
|
||||
nvidia,pins = "ulpi_data1_po2";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ulpi_data5_po6 {
|
||||
nvidia,pins = "ulpi_data5_po6";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ulpi_data7_po0 {
|
||||
nvidia,pins = "ulpi_data7_po0",
|
||||
"ulpi_data2_po3",
|
||||
"ulpi_data3_po4",
|
||||
"ulpi_data4_po5",
|
||||
"ulpi_data6_po7";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* UART-B */
|
||||
uartb_txd_rts {
|
||||
nvidia,pins = "uart2_txd_pc2",
|
||||
"uart2_rts_n_pj6";
|
||||
nvidia,function = "uartb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
uartb_rxd_cts {
|
||||
nvidia,pins = "uart2_rxd_pc3",
|
||||
"uart2_cts_n_pj5";
|
||||
nvidia,function = "uartb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* UART-C */
|
||||
uartc_rxd_cts {
|
||||
nvidia,pins = "uart3_cts_n_pa1",
|
||||
"uart3_rxd_pw7";
|
||||
nvidia,function = "uartc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
uartc_txd_rts {
|
||||
nvidia,pins = "uart3_rts_n_pc0",
|
||||
"uart3_txd_pw6";
|
||||
nvidia,function = "uartc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* UART-D */
|
||||
ulpi_nxt_py2 {
|
||||
nvidia,pins = "ulpi_nxt_py2";
|
||||
nvidia,function = "uartd";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ulpi_clk_py0 {
|
||||
nvidia,pins = "ulpi_clk_py0",
|
||||
"ulpi_dir_py1",
|
||||
"ulpi_stp_py3";
|
||||
nvidia,function = "uartd";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* I2S pinmux */
|
||||
dap_i2s0 {
|
||||
nvidia,pins = "dap1_fs_pn0",
|
||||
"dap1_din_pn1",
|
||||
"dap1_dout_pn2",
|
||||
"dap1_sclk_pn3";
|
||||
nvidia,function = "i2s0";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap_i2s1 {
|
||||
nvidia,pins = "dap2_fs_pa2",
|
||||
"dap2_sclk_pa3",
|
||||
"dap2_din_pa4",
|
||||
"dap2_dout_pa5";
|
||||
nvidia,function = "i2s1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap3_fs {
|
||||
nvidia,pins = "dap3_fs_pp0";
|
||||
nvidia,function = "i2s2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap3_din {
|
||||
nvidia,pins = "dap3_din_pp1";
|
||||
nvidia,function = "i2s2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap3_dout {
|
||||
nvidia,pins = "dap3_dout_pp2",
|
||||
"dap3_sclk_pp3";
|
||||
nvidia,function = "i2s2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap_i2s3 {
|
||||
nvidia,pins = "dap4_fs_pp4",
|
||||
"dap4_din_pp5",
|
||||
"dap4_dout_pp6",
|
||||
"dap4_sclk_pp7";
|
||||
nvidia,function = "i2s3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
i2s4 {
|
||||
nvidia,pins = "pbb7";
|
||||
nvidia,function = "i2s4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Sensors pinmux */
|
||||
nct_irq {
|
||||
nvidia,pins = "pcc2";
|
||||
nvidia,function = "i2s4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
hall {
|
||||
nvidia,pins = "pbb6";
|
||||
nvidia,function = "vgp6";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Asus EC pinmux */
|
||||
ec_irqs {
|
||||
nvidia,pins = "kb_row10_ps2",
|
||||
"kb_row15_ps7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ec_reqs {
|
||||
nvidia,pins = "kb_col1_pq1";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Memory type bootstrap */
|
||||
mem_boostraps {
|
||||
nvidia,pins = "gmi_ad4_pg4",
|
||||
"gmi_ad5_pg5";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* PCI-e pinmux */
|
||||
pex_l2_rst_n {
|
||||
nvidia,pins = "pex_l2_rst_n_pcc6",
|
||||
"pex_l0_rst_n_pdd1",
|
||||
"pex_l1_rst_n_pdd5";
|
||||
nvidia,function = "pcie";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pex_l2_clkreq_n {
|
||||
nvidia,pins = "pex_l2_clkreq_n_pcc7",
|
||||
"pex_l0_prsnt_n_pdd0",
|
||||
"pex_l0_clkreq_n_pdd2",
|
||||
"pex_wake_n_pdd3",
|
||||
"pex_l1_prsnt_n_pdd4",
|
||||
"pex_l1_clkreq_n_pdd6",
|
||||
"pex_l2_prsnt_n_pdd7";
|
||||
nvidia,function = "pcie";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Display A pinmux */
|
||||
lcd_pwr0_pb2 {
|
||||
nvidia,pins = "lcd_pwr0_pb2",
|
||||
"lcd_pclk_pb3",
|
||||
"lcd_pwr1_pc1",
|
||||
"lcd_d0_pe0",
|
||||
"lcd_d1_pe1",
|
||||
"lcd_d2_pe2",
|
||||
"lcd_d3_pe3",
|
||||
"lcd_d4_pe4",
|
||||
"lcd_d5_pe5",
|
||||
"lcd_d6_pe6",
|
||||
"lcd_d7_pe7",
|
||||
"lcd_d8_pf0",
|
||||
"lcd_d9_pf1",
|
||||
"lcd_d10_pf2",
|
||||
"lcd_d11_pf3",
|
||||
"lcd_d12_pf4",
|
||||
"lcd_d13_pf5",
|
||||
"lcd_d14_pf6",
|
||||
"lcd_d15_pf7",
|
||||
"lcd_de_pj1",
|
||||
"lcd_hsync_pj3",
|
||||
"lcd_vsync_pj4",
|
||||
"lcd_d16_pm0",
|
||||
"lcd_d17_pm1",
|
||||
"lcd_d18_pm2",
|
||||
"lcd_d19_pm3",
|
||||
"lcd_d20_pm4",
|
||||
"lcd_d21_pm5",
|
||||
"lcd_d22_pm6",
|
||||
"lcd_d23_pm7",
|
||||
"lcd_cs1_n_pw0",
|
||||
"lcd_m1_pw1",
|
||||
"lcd_dc0_pn6",
|
||||
"lcd_sck_pz4",
|
||||
"lcd_sdin_pz2";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
lcd_cs0_n_pn4 {
|
||||
nvidia,pins = "lcd_sdout_pn5",
|
||||
"lcd_wr_n_pz3",
|
||||
"lcd_pwr2_pc6",
|
||||
"lcd_dc1_pd2";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
blink {
|
||||
nvidia,pins = "clk_32k_out_pa0";
|
||||
nvidia,function = "blink";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* KBC keys */
|
||||
kb_col0 {
|
||||
nvidia,pins = "kb_col0_pq0",
|
||||
"kb_row1_pr1",
|
||||
"kb_row3_pr3",
|
||||
"kb_row6_pr6",
|
||||
"kb_row8_ps0",
|
||||
"kb_row9_ps1",
|
||||
"kb_row11_ps3",
|
||||
"kb_row14_ps6",
|
||||
"kb_col6_pq6";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
kb_col5 {
|
||||
nvidia,pins = "kb_col5_pq5",
|
||||
"kb_col7_pq7",
|
||||
"kb_row2_pr2",
|
||||
"kb_row4_pr4",
|
||||
"kb_row5_pr5",
|
||||
"kb_row13_ps5";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
gmi_cs0_n_pj0 {
|
||||
nvidia,pins = "gmi_wp_n_pc7",
|
||||
"gmi_wait_pi7",
|
||||
"gmi_cs0_n_pj0",
|
||||
"gmi_cs1_n_pj2",
|
||||
"gmi_cs2_n_pk3",
|
||||
"gmi_cs3_n_pk4";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
vi_pclk_pt0 {
|
||||
nvidia,pins = "vi_pclk_pt0";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
nvidia,ioreset = <0>;
|
||||
};
|
||||
|
||||
/* GPIO keys pinmux */
|
||||
power_key {
|
||||
nvidia,pins = "pv0";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
vol_keys {
|
||||
nvidia,pins = "kb_col3_pq3",
|
||||
"kb_col4_pq4";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Bluetooth */
|
||||
bt_shutdown {
|
||||
nvidia,pins = "pu0";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
bt_dev_wake {
|
||||
nvidia,pins = "pu1";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
bt_host_wake {
|
||||
nvidia,pins = "pu6";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pu2 {
|
||||
nvidia,pins = "pu2";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pu3 {
|
||||
nvidia,pins = "pu3";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pcc1 {
|
||||
nvidia,pins = "pcc1";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pv2 {
|
||||
nvidia,pins = "pv2";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pv3 {
|
||||
nvidia,pins = "pv3";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
vi_vsync_pd6 {
|
||||
nvidia,pins = "vi_vsync_pd6",
|
||||
"vi_hsync_pd7";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
nvidia,ioreset = <0>;
|
||||
};
|
||||
vi_d10_pt2 {
|
||||
nvidia,pins = "vi_d10_pt2",
|
||||
"vi_d0_pt4", "pbb0";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
kb_row0_pr0 {
|
||||
nvidia,pins = "kb_row0_pr0";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
gmi_ad0_pg0 {
|
||||
nvidia,pins = "gmi_ad0_pg0",
|
||||
"gmi_ad1_pg1",
|
||||
"gmi_ad2_pg2",
|
||||
"gmi_ad3_pg3",
|
||||
"gmi_ad6_pg6",
|
||||
"gmi_ad7_pg7",
|
||||
"gmi_wr_n_pi0",
|
||||
"gmi_oe_n_pi1",
|
||||
"gmi_dqs_pi2",
|
||||
"gmi_adv_n_pk0",
|
||||
"gmi_clk_pk1";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_ad13_ph5 {
|
||||
nvidia,pins = "gmi_ad13_ph5";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
gmi_ad10_ph2 {
|
||||
nvidia,pins = "gmi_ad10_ph2",
|
||||
"gmi_ad11_ph3",
|
||||
"gmi_ad14_ph6";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gmi_ad12_ph4 {
|
||||
nvidia,pins = "gmi_ad12_ph4",
|
||||
"gmi_rst_n_pi4",
|
||||
"gmi_cs7_n_pi6";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Vibrator control */
|
||||
vibrator {
|
||||
nvidia,pins = "gmi_ad11_ph3";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* PWM pinmux */
|
||||
pwm_0 {
|
||||
nvidia,pins = "gmi_ad8_ph0";
|
||||
nvidia,function = "pwm0";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pwm_1 {
|
||||
nvidia,pins = "gmi_ad9_ph1";
|
||||
nvidia,function = "pwm1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pwm_2 {
|
||||
nvidia,pins = "pu5";
|
||||
nvidia,function = "pwm2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
gmi_cs_n {
|
||||
nvidia,pins = "gmi_cs4_n_pk2",
|
||||
"gmi_cs6_n_pi3";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Spdif pinmux */
|
||||
spdif_out {
|
||||
nvidia,pins = "spdif_out_pk5";
|
||||
nvidia,function = "spdif";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
spdif_in {
|
||||
nvidia,pins = "spdif_in_pk6";
|
||||
nvidia,function = "spdif";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
vi_d4_pl2 {
|
||||
nvidia,pins = "vi_d4_pl2";
|
||||
nvidia,function = "vi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
vi_d6_pl4 {
|
||||
nvidia,pins = "vi_d6_pl4";
|
||||
nvidia,function = "vi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,lock = <0>;
|
||||
nvidia,ioreset = <0>;
|
||||
};
|
||||
vi_mclk_pt1 {
|
||||
nvidia,pins = "vi_mclk_pt1";
|
||||
nvidia,function = "vi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
jtag {
|
||||
nvidia,pins = "jtag_rtck_pu7";
|
||||
nvidia,function = "rtck";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
crt_sync {
|
||||
nvidia,pins = "crt_hsync_pv6",
|
||||
"crt_vsync_pv7";
|
||||
nvidia,function = "crt";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
clk1_out {
|
||||
nvidia,pins = "clk1_out_pw4";
|
||||
nvidia,function = "extperiph1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
clk2_out {
|
||||
nvidia,pins = "clk2_out_pw5";
|
||||
nvidia,function = "extperiph2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
clk3_out {
|
||||
nvidia,pins = "clk3_out_pee0";
|
||||
nvidia,function = "extperiph3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
sys_clk_req {
|
||||
nvidia,pins = "sys_clk_req_pz5";
|
||||
nvidia,function = "sysclk";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
pbb3 {
|
||||
nvidia,pins = "pbb3";
|
||||
nvidia,function = "vgp3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pbb4 {
|
||||
nvidia,pins = "pbb4";
|
||||
nvidia,function = "vgp4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pbb5 {
|
||||
nvidia,pins = "pbb5";
|
||||
nvidia,function = "vgp5";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
clk2_req_pcc5 {
|
||||
nvidia,pins = "clk2_req_pcc5",
|
||||
"clk1_req_pee2";
|
||||
nvidia,function = "dap";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
clk3_req_pee1 {
|
||||
nvidia,pins = "clk3_req_pee1";
|
||||
nvidia,function = "dev3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
owr {
|
||||
nvidia,pins = "owr";
|
||||
nvidia,function = "owr";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* GPIO power/drive control */
|
||||
drive_dap1 {
|
||||
nvidia,pins = "drive_dap1",
|
||||
"drive_dap2",
|
||||
"drive_dbg",
|
||||
"drive_at5",
|
||||
"drive_gme",
|
||||
"drive_ddc",
|
||||
"drive_ao1",
|
||||
"drive_uart3";
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
||||
nvidia,pull-down-strength = <31>;
|
||||
nvidia,pull-up-strength = <31>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
};
|
||||
drive_sdio1 {
|
||||
nvidia,pins = "drive_sdio1",
|
||||
"drive_sdio3";
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull-down-strength = <46>;
|
||||
nvidia,pull-up-strength = <42>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
|
||||
};
|
||||
drive_sdmmc4 {
|
||||
nvidia,pins = "drive_gma",
|
||||
"drive_gmb",
|
||||
"drive_gmc",
|
||||
"drive_gmd";
|
||||
nvidia,pull-down-strength = <9>;
|
||||
nvidia,pull-up-strength = <9>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uarta: serial@70006000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -9,5 +9,58 @@
|
||||
|
||||
/delete-node/ host1x@50000000;
|
||||
|
||||
pinmux@70000868 {
|
||||
state_default: pinmux {
|
||||
lcd_pwr2_pc6 {
|
||||
nvidia,pins = "lcd_pwr2_pc6",
|
||||
"lcd_dc1_pd2";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
pbb3 {
|
||||
nvidia,pins = "pbb3";
|
||||
nvidia,function = "vgp3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
spi2_mosi_px0 {
|
||||
nvidia,pins = "spi2_mosi_px0";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
pbb7 {
|
||||
nvidia,pins = "pbb7";
|
||||
nvidia,function = "i2s4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
kb_row7_pr7 {
|
||||
nvidia,pins = "kb_row7_pr7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
gmi_cs4_n_pk2 {
|
||||
nvidia,pins = "gmi_cs4_n_pk2";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/delete-node/ panel;
|
||||
};
|
||||
|
||||
@ -37,6 +37,990 @@
|
||||
};
|
||||
};
|
||||
|
||||
pinmux@70000868 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
/* SDMMC1 pinmux */
|
||||
sdmmc1_clk {
|
||||
nvidia,pins = "sdmmc1_clk_pz0";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
sdmmc1_cmd {
|
||||
nvidia,pins = "sdmmc1_dat3_py4",
|
||||
"sdmmc1_dat2_py5",
|
||||
"sdmmc1_dat1_py6",
|
||||
"sdmmc1_dat0_py7",
|
||||
"sdmmc1_cmd_pz1";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
sdmmc1_cd {
|
||||
nvidia,pins = "gmi_iordy_pi5";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
sdmmc1_wp {
|
||||
nvidia,pins = "vi_d11_pt3";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* SDMMC2 pinmux */
|
||||
vi_d1_pd5 {
|
||||
nvidia,pins = "vi_d1_pd5",
|
||||
"vi_d2_pl0",
|
||||
"vi_d3_pl1",
|
||||
"vi_d5_pl3",
|
||||
"vi_d7_pl5";
|
||||
nvidia,function = "sdmmc2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
vi_d8_pl6 {
|
||||
nvidia,pins = "vi_d8_pl6",
|
||||
"vi_d9_pl7";
|
||||
nvidia,function = "sdmmc2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
nvidia,io-reset = <0>;
|
||||
};
|
||||
|
||||
/* SDMMC3 pinmux */
|
||||
sdmmc3_clk {
|
||||
nvidia,pins = "sdmmc3_clk_pa6";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
sdmmc3_cmd {
|
||||
nvidia,pins = "sdmmc3_cmd_pa7",
|
||||
"sdmmc3_dat0_pb7",
|
||||
"sdmmc3_dat1_pb6",
|
||||
"sdmmc3_dat2_pb5",
|
||||
"sdmmc3_dat3_pb4",
|
||||
"sdmmc3_dat4_pd1",
|
||||
"sdmmc3_dat5_pd0",
|
||||
"sdmmc3_dat6_pd3",
|
||||
"sdmmc3_dat7_pd4";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* SDMMC4 pinmux */
|
||||
sdmmc4_clk {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
sdmmc4_cmd {
|
||||
nvidia,pins = "sdmmc4_cmd_pt7",
|
||||
"sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
sdmmc4_rst_n {
|
||||
nvidia,pins = "sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
cam_mclk {
|
||||
nvidia,pins = "cam_mclk_pcc0";
|
||||
nvidia,function = "vi_alt3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
drive_sdmmc4 {
|
||||
nvidia,pins = "drive_gma",
|
||||
"drive_gmb",
|
||||
"drive_gmc",
|
||||
"drive_gmd";
|
||||
nvidia,pull-down-strength = <9>;
|
||||
nvidia,pull-up-strength = <9>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
||||
};
|
||||
|
||||
/* I2C pinmux */
|
||||
gen1_i2c {
|
||||
nvidia,pins = "gen1_i2c_scl_pc4",
|
||||
"gen1_i2c_sda_pc5";
|
||||
nvidia,function = "i2c1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
|
||||
gen2_i2c {
|
||||
nvidia,pins = "gen2_i2c_scl_pt5",
|
||||
"gen2_i2c_sda_pt6";
|
||||
nvidia,function = "i2c2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
|
||||
cam_i2c {
|
||||
nvidia,pins = "cam_i2c_scl_pbb1",
|
||||
"cam_i2c_sda_pbb2";
|
||||
nvidia,function = "i2c3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
|
||||
ddc_i2c {
|
||||
nvidia,pins = "ddc_scl_pv4",
|
||||
"ddc_sda_pv5";
|
||||
nvidia,function = "i2c4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
|
||||
pwr_i2c {
|
||||
nvidia,pins = "pwr_i2c_scl_pz6",
|
||||
"pwr_i2c_sda_pz7";
|
||||
nvidia,function = "i2cpwr";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
};
|
||||
|
||||
hotplug_i2c {
|
||||
nvidia,pins = "pu4";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* HDMI pinmux */
|
||||
hdmi_cec {
|
||||
nvidia,pins = "hdmi_cec_pee3";
|
||||
nvidia,function = "cec";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
hdmi_hpd {
|
||||
nvidia,pins = "hdmi_int_pn7";
|
||||
nvidia,function = "hdmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* UART-A */
|
||||
ulpi_data0_po1 {
|
||||
nvidia,pins = "ulpi_data0_po1";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
ulpi_data1_po2 {
|
||||
nvidia,pins = "ulpi_data1_po2";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
ulpi_data5_po6 {
|
||||
nvidia,pins = "ulpi_data5_po6";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
ulpi_data7_po0 {
|
||||
nvidia,pins = "ulpi_data7_po0",
|
||||
"ulpi_data2_po3",
|
||||
"ulpi_data3_po4",
|
||||
"ulpi_data4_po5",
|
||||
"ulpi_data6_po7";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* UART-B */
|
||||
uartb_txd_rts {
|
||||
nvidia,pins = "uart2_txd_pc2",
|
||||
"uart2_rts_n_pj6";
|
||||
nvidia,function = "uartb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
uartb_rxd_cts {
|
||||
nvidia,pins = "uart2_rxd_pc3",
|
||||
"uart2_cts_n_pj5";
|
||||
nvidia,function = "uartb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* UART-C */
|
||||
uartc_rxd_cts {
|
||||
nvidia,pins = "uart3_cts_n_pa1",
|
||||
"uart3_rxd_pw7";
|
||||
nvidia,function = "uartc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
uartc_txd_rts {
|
||||
nvidia,pins = "uart3_rts_n_pc0",
|
||||
"uart3_txd_pw6";
|
||||
nvidia,function = "uartc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* UART-D */
|
||||
ulpi_nxt_py2 {
|
||||
nvidia,pins = "ulpi_nxt_py2";
|
||||
nvidia,function = "uartd";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
ulpi_clk_py0 {
|
||||
nvidia,pins = "ulpi_clk_py0",
|
||||
"ulpi_dir_py1",
|
||||
"ulpi_stp_py3";
|
||||
nvidia,function = "uartd";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* I2S pinmux */
|
||||
dap_i2s0 {
|
||||
nvidia,pins = "dap1_fs_pn0",
|
||||
"dap1_din_pn1",
|
||||
"dap1_dout_pn2",
|
||||
"dap1_sclk_pn3";
|
||||
nvidia,function = "i2s0";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
dap_i2s1 {
|
||||
nvidia,pins = "dap2_fs_pa2",
|
||||
"dap2_sclk_pa3",
|
||||
"dap2_din_pa4",
|
||||
"dap2_dout_pa5";
|
||||
nvidia,function = "i2s1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
dap3_fs {
|
||||
nvidia,pins = "dap3_fs_pp0",
|
||||
"dap3_din_pp1";
|
||||
nvidia,function = "i2s2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
dap3_dout {
|
||||
nvidia,pins = "dap3_dout_pp2",
|
||||
"dap3_sclk_pp3";
|
||||
nvidia,function = "i2s2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
dap_i2s3 {
|
||||
nvidia,pins = "dap4_fs_pp4",
|
||||
"dap4_din_pp5",
|
||||
"dap4_dout_pp6",
|
||||
"dap4_sclk_pp7";
|
||||
nvidia,function = "i2s3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Sensors pinmux */
|
||||
nct_irq {
|
||||
nvidia,pins = "pcc2";
|
||||
nvidia,function = "i2s4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Asus EC pinmux */
|
||||
ec_irqs {
|
||||
nvidia,pins = "kb_row10_ps2",
|
||||
"kb_row15_ps7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
ec_reqs {
|
||||
nvidia,pins = "kb_col1_pq1";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Memory type bootstrap */
|
||||
mem_boostraps {
|
||||
nvidia,pins = "gmi_ad4_pg4",
|
||||
"gmi_ad5_pg5";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* PCI-e pinmux */
|
||||
pex_l2_rst_n {
|
||||
nvidia,pins = "pex_l2_rst_n_pcc6",
|
||||
"pex_l0_rst_n_pdd1",
|
||||
"pex_l1_rst_n_pdd5";
|
||||
nvidia,function = "pcie";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
pex_l2_clkreq_n {
|
||||
nvidia,pins = "pex_l2_clkreq_n_pcc7",
|
||||
"pex_l0_prsnt_n_pdd0",
|
||||
"pex_l0_clkreq_n_pdd2",
|
||||
"pex_wake_n_pdd3",
|
||||
"pex_l1_prsnt_n_pdd4",
|
||||
"pex_l1_clkreq_n_pdd6",
|
||||
"pex_l2_prsnt_n_pdd7";
|
||||
nvidia,function = "pcie";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* SPI pinmux */
|
||||
spi1_mosi_px4 {
|
||||
nvidia,pins = "spi1_mosi_px4",
|
||||
"spi1_sck_px5",
|
||||
"spi1_cs0_n_px6",
|
||||
"spi1_miso_px7";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
hp_detect {
|
||||
nvidia,pins = "spi2_cs1_n_pw2";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
mic_detect {
|
||||
nvidia,pins = "spi2_sck_px2";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
gmi_a17_pb0 {
|
||||
nvidia,pins = "gmi_a17_pb0",
|
||||
"gmi_a16_pj7";
|
||||
nvidia,function = "spi4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
gmi_a18_pb1 {
|
||||
nvidia,pins = "gmi_a18_pb1";
|
||||
nvidia,function = "spi4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
gmi_a19_pk7 {
|
||||
nvidia,pins = "gmi_a19_pk7";
|
||||
nvidia,function = "spi4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Display A pinmux */
|
||||
lcd_pwr0_pb2 {
|
||||
nvidia,pins = "lcd_pwr0_pb2",
|
||||
"lcd_pclk_pb3",
|
||||
"lcd_pwr1_pc1",
|
||||
"lcd_d0_pe0",
|
||||
"lcd_d1_pe1",
|
||||
"lcd_d2_pe2",
|
||||
"lcd_d3_pe3",
|
||||
"lcd_d4_pe4",
|
||||
"lcd_d5_pe5",
|
||||
"lcd_d6_pe6",
|
||||
"lcd_d7_pe7",
|
||||
"lcd_d8_pf0",
|
||||
"lcd_d9_pf1",
|
||||
"lcd_d10_pf2",
|
||||
"lcd_d11_pf3",
|
||||
"lcd_d12_pf4",
|
||||
"lcd_d13_pf5",
|
||||
"lcd_d14_pf6",
|
||||
"lcd_d15_pf7",
|
||||
"lcd_de_pj1",
|
||||
"lcd_hsync_pj3",
|
||||
"lcd_vsync_pj4",
|
||||
"lcd_d16_pm0",
|
||||
"lcd_d17_pm1",
|
||||
"lcd_d18_pm2",
|
||||
"lcd_d19_pm3",
|
||||
"lcd_d20_pm4",
|
||||
"lcd_d21_pm5",
|
||||
"lcd_d22_pm6",
|
||||
"lcd_d23_pm7",
|
||||
"lcd_cs1_n_pw0",
|
||||
"lcd_m1_pw1",
|
||||
"lcd_dc0_pn6",
|
||||
"lcd_sck_pz4",
|
||||
"lcd_sdin_pz2";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
lcd_cs0_n_pn4 {
|
||||
nvidia,pins = "lcd_cs0_n_pn4",
|
||||
"lcd_sdout_pn5",
|
||||
"lcd_wr_n_pz3";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
blink {
|
||||
nvidia,pins = "clk_32k_out_pa0";
|
||||
nvidia,function = "blink";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* KBC keys */
|
||||
kb_col0_pq0 {
|
||||
nvidia,pins = "kb_col0_pq0";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
kb_col1_pq1 {
|
||||
nvidia,pins = "kb_row1_pr1",
|
||||
"kb_row3_pr3",
|
||||
"kb_row6_pr6",
|
||||
"kb_row8_ps0",
|
||||
"kb_row9_ps1",
|
||||
"kb_row11_ps3",
|
||||
"kb_row14_ps6",
|
||||
"kb_col6_pq6";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
kb_col4_pq4 {
|
||||
nvidia,pins = "kb_col4_pq4",
|
||||
"kb_col5_pq5",
|
||||
"kb_col7_pq7",
|
||||
"kb_row2_pr2",
|
||||
"kb_row4_pr4",
|
||||
"kb_row5_pr5",
|
||||
"kb_row12_ps4",
|
||||
"kb_row13_ps5";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
gmi_wp_n_pc7 {
|
||||
nvidia,pins = "gmi_wp_n_pc7",
|
||||
"gmi_wait_pi7",
|
||||
"gmi_cs3_n_pk4";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
gmi_cs0_n_pj0 {
|
||||
nvidia,pins = "gmi_cs0_n_pj0",
|
||||
"gmi_cs1_n_pj2",
|
||||
"gmi_cs2_n_pk3";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
vi_pclk_pt0 {
|
||||
nvidia,pins = "vi_pclk_pt0";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
nvidia,io-reset = <0>;
|
||||
};
|
||||
|
||||
/* GPIO keys pinmux */
|
||||
power_key {
|
||||
nvidia,pins = "pv0";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
vol_keys {
|
||||
nvidia,pins = "kb_col2_pq2",
|
||||
"kb_col3_pq3";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Bluetooth */
|
||||
bt_shutdown {
|
||||
nvidia,pins = "pu0";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
bt_dev_wake {
|
||||
nvidia,pins = "pu1";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
bt_host_wake {
|
||||
nvidia,pins = "pu6";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pu2 {
|
||||
nvidia,pins = "pu2";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pu3 {
|
||||
nvidia,pins = "pu3";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
pcc1 {
|
||||
nvidia,pins = "pcc1";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pv2 {
|
||||
nvidia,pins = "pv2";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
pv3 {
|
||||
nvidia,pins = "pv3";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
vi_vsync_pd6 {
|
||||
nvidia,pins = "vi_vsync_pd6",
|
||||
"vi_hsync_pd7";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <0>;
|
||||
nvidia,io-reset = <0>;
|
||||
};
|
||||
|
||||
vi_d10_pt2 {
|
||||
nvidia,pins = "vi_d10_pt2",
|
||||
"vi_d0_pt4", "pbb0";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
kb_row0_pr0 {
|
||||
nvidia,pins = "kb_row0_pr0";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
gmi_ad0_pg0 {
|
||||
nvidia,pins = "gmi_ad0_pg0",
|
||||
"gmi_ad1_pg1",
|
||||
"gmi_ad2_pg2",
|
||||
"gmi_ad3_pg3",
|
||||
"gmi_ad6_pg6",
|
||||
"gmi_ad7_pg7",
|
||||
"gmi_wr_n_pi0",
|
||||
"gmi_oe_n_pi1",
|
||||
"gmi_dqs_pi2",
|
||||
"gmi_adv_n_pk0",
|
||||
"gmi_clk_pk1";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
gmi_ad13_ph5 {
|
||||
nvidia,pins = "gmi_ad13_ph5";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
gmi_ad10_ph2 {
|
||||
nvidia,pins = "gmi_ad10_ph2",
|
||||
"gmi_ad11_ph3",
|
||||
"gmi_ad14_ph6";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
gmi_ad12_ph4 {
|
||||
nvidia,pins = "gmi_ad12_ph4",
|
||||
"gmi_rst_n_pi4",
|
||||
"gmi_cs7_n_pi6";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Vibrator control */
|
||||
vibrator {
|
||||
nvidia,pins = "gmi_ad15_ph7";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* PWM pimnmux */
|
||||
pwm_0 {
|
||||
nvidia,pins = "gmi_ad8_ph0";
|
||||
nvidia,function = "pwm0";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pwm_1 {
|
||||
nvidia,pins = "gmi_ad9_ph1";
|
||||
nvidia,function = "pwm1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pwm_2 {
|
||||
nvidia,pins = "pu5";
|
||||
nvidia,function = "pwm2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
gmi_cs6_n_pi3 {
|
||||
nvidia,pins = "gmi_cs6_n_pi3";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* Spdif pinmux */
|
||||
spdif_out {
|
||||
nvidia,pins = "spdif_out_pk5";
|
||||
nvidia,function = "spdif";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
spdif_in {
|
||||
nvidia,pins = "spdif_in_pk6";
|
||||
nvidia,function = "spdif";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
vi_d4_pl2 {
|
||||
nvidia,pins = "vi_d4_pl2";
|
||||
nvidia,function = "vi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
vi_d6_pl4 {
|
||||
nvidia,pins = "vi_d6_pl4";
|
||||
nvidia,function = "vi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,lock = <0>;
|
||||
nvidia,io-reset = <0>;
|
||||
};
|
||||
|
||||
vi_mclk_pt1 {
|
||||
nvidia,pins = "vi_mclk_pt1";
|
||||
nvidia,function = "vi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
jtag_rtck {
|
||||
nvidia,pins = "jtag_rtck_pu7";
|
||||
nvidia,function = "rtck";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
crt_hsync_pv6 {
|
||||
nvidia,pins = "crt_hsync_pv6",
|
||||
"crt_vsync_pv7";
|
||||
nvidia,function = "crt";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
clk1_out {
|
||||
nvidia,pins = "clk1_out_pw4";
|
||||
nvidia,function = "extperiph1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
clk2_out {
|
||||
nvidia,pins = "clk2_out_pw5";
|
||||
nvidia,function = "extperiph2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
clk3_out {
|
||||
nvidia,pins = "clk3_out_pee0";
|
||||
nvidia,function = "extperiph3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
sys_clk_req {
|
||||
nvidia,pins = "sys_clk_req_pz5";
|
||||
nvidia,function = "sysclk";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
pbb4 {
|
||||
nvidia,pins = "pbb4";
|
||||
nvidia,function = "vgp4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pbb5 {
|
||||
nvidia,pins = "pbb5";
|
||||
nvidia,function = "vgp5";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
pbb6 {
|
||||
nvidia,pins = "pbb6";
|
||||
nvidia,function = "vgp6";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
clk2_req_pcc5 {
|
||||
nvidia,pins = "clk2_req_pcc5",
|
||||
"clk1_req_pee2";
|
||||
nvidia,function = "dap";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
clk3_req_pee1 {
|
||||
nvidia,pins = "clk3_req_pee1";
|
||||
nvidia,function = "dev3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
owr {
|
||||
nvidia,pins = "owr";
|
||||
nvidia,function = "owr";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* GPIO power/drive control */
|
||||
drive_dap1 {
|
||||
nvidia,pins = "drive_dap1",
|
||||
"drive_dap2",
|
||||
"drive_dbg",
|
||||
"drive_at5",
|
||||
"drive_gme",
|
||||
"drive_ddc",
|
||||
"drive_ao1",
|
||||
"drive_uart3";
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
||||
nvidia,pull-down-strength = <31>;
|
||||
nvidia,pull-up-strength = <31>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
};
|
||||
|
||||
drive_sdio1 {
|
||||
nvidia,pins = "drive_sdio1",
|
||||
"drive_sdio3";
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull-down-strength = <46>;
|
||||
nvidia,pull-up-strength = <42>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uarta: serial@70006000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -11,6 +11,96 @@
|
||||
mmc1 = &sdmmc3; /* uSD slot */
|
||||
};
|
||||
|
||||
pinmux@70000868 {
|
||||
state_default: pinmux {
|
||||
/* WLAN SDIO pinmux */
|
||||
host_wlan_wake {
|
||||
nvidia,pins = "pu4";
|
||||
nvidia,function = "pwm1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* GNSS UART-B pinmux */
|
||||
uartb_rxd {
|
||||
nvidia,pins = "uart2_rxd_pc3";
|
||||
nvidia,function = "uartb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
uartb_txd {
|
||||
nvidia,pins = "uart2_txd_pc2";
|
||||
nvidia,function = "uartb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gps_reset {
|
||||
nvidia,pins = "kb_row7_pr7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* MicroSD pinmux */
|
||||
sdmmc3_clk {
|
||||
nvidia,pins = "sdmmc3_clk_pa6";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc3_data {
|
||||
nvidia,pins = "sdmmc3_cmd_pa7",
|
||||
"sdmmc3_dat0_pb7",
|
||||
"sdmmc3_dat1_pb6",
|
||||
"sdmmc3_dat2_pb5",
|
||||
"sdmmc3_dat3_pb4";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
microsd_detect {
|
||||
nvidia,pins = "clk2_out_pw5";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* GPIO keys pinmux */
|
||||
volume_up {
|
||||
nvidia,pins = "ulpi_data6_po7";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Sensors pinmux */
|
||||
current_alert_irq {
|
||||
nvidia,pins = "uart2_rts_n_pj6";
|
||||
nvidia,function = "uartb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* AUDIO pinmux */
|
||||
sub_mic_ldo {
|
||||
nvidia,pins = "gmi_cs7_n_pi6";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc3: sdhci@78000400 {
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
|
||||
@ -15,6 +15,99 @@
|
||||
};
|
||||
};
|
||||
|
||||
pinmux@70000868 {
|
||||
state_default: pinmux {
|
||||
/* GNSS UART-B pinmux */
|
||||
uartb_cts_rxd {
|
||||
nvidia,pins = "uart2_cts_n_pj5",
|
||||
"uart2_rxd_pc3";
|
||||
nvidia,function = "uartb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
uartb_rts_txd {
|
||||
nvidia,pins = "uart2_rts_n_pj6",
|
||||
"uart2_txd_pc2";
|
||||
nvidia,function = "uartb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gps_reset {
|
||||
nvidia,pins = "spdif_out_pk5";
|
||||
nvidia,function = "spdif";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* GPIO keys pinmux */
|
||||
volume_up {
|
||||
nvidia,pins = "gmi_cs7_n_pi6";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
memo_key {
|
||||
nvidia,pins = "sdmmc3_dat1_pb6";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Sensors pinmux */
|
||||
current_alert_irq {
|
||||
nvidia,pins = "spi1_cs0_n_px6";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Panel pinmux */
|
||||
panel_vdd {
|
||||
nvidia,pins = "pbb0";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* AUDIO pinmux */
|
||||
sub_mic_ldo {
|
||||
nvidia,pins = "gmi_dqs_pi2";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* Modem pinmux */
|
||||
usim_detect {
|
||||
nvidia,pins = "clk2_out_pw5";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* GPIO power/drive control */
|
||||
drive_sdmmc4 {
|
||||
nvidia,pins = "drive_gma",
|
||||
"drive_gmb",
|
||||
"drive_gmc",
|
||||
"drive_gmd";
|
||||
nvidia,pull-down-strength = <9>;
|
||||
nvidia,pull-up-strength = <9>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel: panel {
|
||||
compatible = "hitachi,tx13d100vm0eaa";
|
||||
|
||||
|
||||
@ -37,6 +37,851 @@
|
||||
};
|
||||
};
|
||||
|
||||
pinmux@70000868 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
/* WLAN SDIO pinmux */
|
||||
sdmmc1_clk {
|
||||
nvidia,pins = "sdmmc1_clk_pz0";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc1_cmd {
|
||||
nvidia,pins = "sdmmc1_cmd_pz1",
|
||||
"sdmmc1_dat3_py4",
|
||||
"sdmmc1_dat2_py5",
|
||||
"sdmmc1_dat1_py6",
|
||||
"sdmmc1_dat0_py7";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
wlan_reset {
|
||||
nvidia,pins = "pv3";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
wlan_host_wake {
|
||||
nvidia,pins = "pu6";
|
||||
nvidia,function = "pwm3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* GNSS UART-B pinmux */
|
||||
gps_pwr_en {
|
||||
nvidia,pins = "kb_row6_pr6";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gps_ldo_en {
|
||||
nvidia,pins = "ulpi_dir_py1";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gps_clk_ref {
|
||||
nvidia,pins = "gmi_ad8_ph0";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* Bluetooth UART-C pinmux */
|
||||
uartc_cts_rxd {
|
||||
nvidia,pins = "uart3_cts_n_pa1",
|
||||
"uart3_rxd_pw7";
|
||||
nvidia,function = "uartc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
uartc_rts_txd {
|
||||
nvidia,pins = "uart3_rts_n_pc0",
|
||||
"uart3_txd_pw6";
|
||||
nvidia,function = "uartc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
bt_reset {
|
||||
nvidia,pins = "clk2_req_pcc5";
|
||||
nvidia,function = "dap";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
bt_dev_wake {
|
||||
nvidia,pins = "kb_row11_ps3";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
bt_host_wake {
|
||||
nvidia,pins = "kb_row12_ps4";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
bt_pcm_dap4 {
|
||||
nvidia,pins = "dap4_fs_pp4",
|
||||
"dap4_din_pp5",
|
||||
"dap4_dout_pp6",
|
||||
"dap4_sclk_pp7";
|
||||
nvidia,function = "i2s3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* EMMC pinmux */
|
||||
sdmmc4_clk {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc4_data {
|
||||
nvidia,pins = "sdmmc4_cmd_pt7",
|
||||
"sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdmmc4_reset {
|
||||
nvidia,pins = "sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* I2C pinmux */
|
||||
gen1_i2c {
|
||||
nvidia,pins = "gen1_i2c_scl_pc4",
|
||||
"gen1_i2c_sda_pc5";
|
||||
nvidia,function = "i2c1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
gen2_i2c {
|
||||
nvidia,pins = "gen2_i2c_scl_pt5",
|
||||
"gen2_i2c_sda_pt6";
|
||||
nvidia,function = "i2c2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
cam_i2c {
|
||||
nvidia,pins = "cam_i2c_scl_pbb1",
|
||||
"cam_i2c_sda_pbb2";
|
||||
nvidia,function = "i2c3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
ddc_i2c {
|
||||
nvidia,pins = "ddc_scl_pv4",
|
||||
"ddc_sda_pv5";
|
||||
nvidia,function = "i2c4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
pwr_i2c {
|
||||
nvidia,pins = "pwr_i2c_scl_pz6",
|
||||
"pwr_i2c_sda_pz7";
|
||||
nvidia,function = "i2cpwr";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
mhl_i2c {
|
||||
nvidia,pins = "kb_col6_pq6",
|
||||
"kb_col7_pq7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* GPIO keys pinmux */
|
||||
power_key {
|
||||
nvidia,pins = "gmi_wp_n_pc7";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
volume_down {
|
||||
nvidia,pins = "ulpi_data3_po4";
|
||||
nvidia,function = "spi3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Sensors pinmux */
|
||||
sen_vdd {
|
||||
nvidia,pins = "spi1_miso_px7";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
proxi_vdd {
|
||||
nvidia,pins = "spi2_miso_px1";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sen_vio {
|
||||
nvidia,pins = "lcd_dc1_pd2";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
nct_irq {
|
||||
nvidia,pins = "gmi_iordy_pi5";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
bat_irq {
|
||||
nvidia,pins = "kb_row8_ps0";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
charger_irq {
|
||||
nvidia,pins = "gmi_cs1_n_pj2";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
mpu_irq {
|
||||
nvidia,pins = "gmi_ad12_ph4";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
compass_irq {
|
||||
nvidia,pins = "gmi_ad13_ph5";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
light_irq {
|
||||
nvidia,pins = "gmi_cs4_n_pk2";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* LED pinmux */
|
||||
backlight_en {
|
||||
nvidia,pins = "lcd_dc0_pn6";
|
||||
nvidia,function = "rsvd3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
flash_led_en {
|
||||
nvidia,pins = "pbb3";
|
||||
nvidia,function = "vgp3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
keypad_led {
|
||||
nvidia,pins = "kb_row2_pr2",
|
||||
"kb_row3_pr3";
|
||||
nvidia,function = "rsvd3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* NFC pinmux */
|
||||
nfc_irq {
|
||||
nvidia,pins = "spi2_cs1_n_pw2";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
nfc_ven {
|
||||
nvidia,pins = "spi1_sck_px5";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
nfc_firm {
|
||||
nvidia,pins = "kb_row0_pr0";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* DC pinmux */
|
||||
lcd_pwr {
|
||||
nvidia,pins = "lcd_pwr0_pb2",
|
||||
"lcd_pwr1_pc1";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
lcd_wr_n {
|
||||
nvidia,pins = "lcd_wr_n_pz3";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
lcd_id {
|
||||
nvidia,pins = "lcd_m1_pw1";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
lcd_pclk {
|
||||
nvidia,pins = "lcd_pclk_pb3",
|
||||
"lcd_de_pj1",
|
||||
"lcd_hsync_pj3",
|
||||
"lcd_vsync_pj4";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
lcd_rgb_blue {
|
||||
nvidia,pins = "lcd_d0_pe0",
|
||||
"lcd_d1_pe1",
|
||||
"lcd_d2_pe2",
|
||||
"lcd_d3_pe3",
|
||||
"lcd_d4_pe4",
|
||||
"lcd_d5_pe5",
|
||||
"lcd_d18_pm2",
|
||||
"lcd_d19_pm3";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
lcd_rgb_green {
|
||||
nvidia,pins = "lcd_d6_pe6",
|
||||
"lcd_d7_pe7",
|
||||
"lcd_d8_pf0",
|
||||
"lcd_d9_pf1",
|
||||
"lcd_d10_pf2",
|
||||
"lcd_d11_pf3",
|
||||
"lcd_d20_pm4",
|
||||
"lcd_d21_pm5";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
lcd_rgb_red {
|
||||
nvidia,pins = "lcd_d12_pf4",
|
||||
"lcd_d13_pf5",
|
||||
"lcd_d14_pf6",
|
||||
"lcd_d15_pf7",
|
||||
"lcd_d16_pm0",
|
||||
"lcd_d17_pm1",
|
||||
"lcd_d22_pm6",
|
||||
"lcd_d23_pm7";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Bridge pinmux */
|
||||
bridge_reset {
|
||||
nvidia,pins = "ulpi_data1_po2";
|
||||
nvidia,function = "spi3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
rgb_ic_en {
|
||||
nvidia,pins = "gmi_a18_pb1";
|
||||
nvidia,function = "uartd";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
bridge_clk {
|
||||
nvidia,pins = "clk3_out_pee0";
|
||||
nvidia,function = "extperiph3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
rgb_bridge {
|
||||
nvidia,pins = "lcd_sdin_pz2",
|
||||
"lcd_sdout_pn5",
|
||||
"lcd_cs0_n_pn4",
|
||||
"lcd_sck_pz4";
|
||||
nvidia,function = "spi5";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Panel pinmux */
|
||||
panel_reset {
|
||||
nvidia,pins = "lcd_cs1_n_pw0";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
panel_vio {
|
||||
nvidia,pins = "ulpi_clk_py0";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* Touchscreen pinmux */
|
||||
touch_vdd {
|
||||
nvidia,pins = "kb_col1_pq1";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
touch_vio {
|
||||
nvidia,pins = "spi1_mosi_px4";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
touch_int_n {
|
||||
nvidia,pins = "kb_col3_pq3";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
touch_rst_n {
|
||||
nvidia,pins = "ulpi_data0_po1";
|
||||
nvidia,function = "spi3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
touch_maker_id {
|
||||
nvidia,pins = "kb_col2_pq2";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* MHL pinmux */
|
||||
mhl_vio {
|
||||
nvidia,pins = "pv2";
|
||||
nvidia,function = "owr";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
mhl_rst_n {
|
||||
nvidia,pins = "clk3_req_pee1";
|
||||
nvidia,function = "dev3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
mhl_int {
|
||||
nvidia,pins = "crt_vsync_pv7";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
mhl_sel {
|
||||
nvidia,pins = "kb_row10_ps2";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
hdmi_hpd {
|
||||
nvidia,pins = "hdmi_int_pn7";
|
||||
nvidia,function = "hdmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* AUDIO pinmux */
|
||||
hp_detect {
|
||||
nvidia,pins = "pbb6";
|
||||
nvidia,function = "vgp6";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
hp_hook {
|
||||
nvidia,pins = "ulpi_data4_po5";
|
||||
nvidia,function = "ulpi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ear_mic_en {
|
||||
nvidia,pins = "spi2_mosi_px0";
|
||||
nvidia,function = "spi2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
audio_irq {
|
||||
nvidia,pins = "spi2_cs2_n_pw3";
|
||||
nvidia,function = "spi3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
audio_mclk {
|
||||
nvidia,pins = "clk1_out_pw4";
|
||||
nvidia,function = "extperiph1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap_i2s0 {
|
||||
nvidia,pins = "dap1_fs_pn0",
|
||||
"dap1_din_pn1",
|
||||
"dap1_dout_pn2",
|
||||
"dap1_sclk_pn3";
|
||||
nvidia,function = "i2s0";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap_i2s1 {
|
||||
nvidia,pins = "dap2_fs_pa2",
|
||||
"dap2_sclk_pa3",
|
||||
"dap2_din_pa4",
|
||||
"dap2_dout_pa5";
|
||||
nvidia,function = "i2s1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* MUIC pinmux */
|
||||
muic_irq {
|
||||
nvidia,pins = "gmi_cs0_n_pj0";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
muic_dp2t {
|
||||
nvidia,pins = "pcc2";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
muic_usif {
|
||||
nvidia,pins = "ulpi_stp_py3";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
ifx_usb_vbus_en {
|
||||
nvidia,pins = "kb_row4_pr4";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pcb_rev {
|
||||
nvidia,pins = "gmi_wait_pi7",
|
||||
"gmi_rst_n_pi4";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
jtag_rtck {
|
||||
nvidia,pins = "jtag_rtck_pu7";
|
||||
nvidia,function = "rtck";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* Camera pinmux */
|
||||
cam_mclk {
|
||||
nvidia,pins = "cam_mclk_pcc0";
|
||||
nvidia,function = "vi_alt3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
cam_pmic_en {
|
||||
nvidia,pins = "pbb4";
|
||||
nvidia,function = "vgp4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
front_cam_rst {
|
||||
nvidia,pins = "pbb5";
|
||||
nvidia,function = "vgp5";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
front_cam_vio {
|
||||
nvidia,pins = "ulpi_nxt_py2";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
rear_cam_rst {
|
||||
nvidia,pins = "gmi_cs3_n_pk4";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
rear_cam_eprom_pr {
|
||||
nvidia,pins = "gmi_cs2_n_pk3";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
rear_cam_vcm_pwdn {
|
||||
nvidia,pins = "kb_row1_pr1";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* Haptic pinmux */
|
||||
haptic_en {
|
||||
nvidia,pins = "gmi_ad9_ph1";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
haptic_osc {
|
||||
nvidia,pins = "gmi_ad11_ph3";
|
||||
nvidia,function = "pwm3";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
/* Modem pinmux */
|
||||
cp2ap_ack1_host_active {
|
||||
nvidia,pins = "pu5";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
cp2ap_ack2_host_wakeup {
|
||||
nvidia,pins = "pv0";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ap2cp_ack2_suspend_req {
|
||||
nvidia,pins = "kb_row14_ps6";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ap2cp_ack1_slave_wakeup {
|
||||
nvidia,pins = "kb_row15_ps7";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
cp_kkp {
|
||||
nvidia,pins = "kb_col0_pq0";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
cp_crash_irq {
|
||||
nvidia,pins = "kb_row13_ps5";
|
||||
nvidia,function = "kbc";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
ap2cp_uarta_tx_ipc {
|
||||
nvidia,pins = "pu0";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
ap2cp_uarta_rx_ipc {
|
||||
nvidia,pins = "pu1";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
fota_ap_cts_cp_rts {
|
||||
nvidia,pins = "pu2";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
fota_ap_rts_cp_cts {
|
||||
nvidia,pins = "pu3";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
modem_enable {
|
||||
nvidia,pins = "ulpi_data7_po0";
|
||||
nvidia,function = "hsi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
modem_reset {
|
||||
nvidia,pins = "pv1";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
dap_i2s2 {
|
||||
nvidia,pins = "dap3_fs_pp0",
|
||||
"dap3_din_pp1",
|
||||
"dap3_dout_pp2",
|
||||
"dap3_sclk_pp3";
|
||||
nvidia,function = "i2s2";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
||||
/* GPIO power/drive control */
|
||||
drive_i2c {
|
||||
nvidia,pins = "drive_dbg",
|
||||
"drive_at5",
|
||||
"drive_gme",
|
||||
"drive_ddc",
|
||||
"drive_ao1";
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
||||
nvidia,pull-down-strength = <31>;
|
||||
nvidia,pull-up-strength = <31>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
};
|
||||
|
||||
drive_uart3 {
|
||||
nvidia,pins = "drive_uart3";
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
||||
nvidia,pull-down-strength = <31>;
|
||||
nvidia,pull-up-strength = <31>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
};
|
||||
|
||||
drive_gmi {
|
||||
nvidia,pins = "drive_at3";
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
||||
nvidia,pull-down-strength = <31>;
|
||||
nvidia,pull-up-strength = <31>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uartd: serial@70006300 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -174,8 +174,7 @@ struct clk_rst_ctlr {
|
||||
uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
|
||||
uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
|
||||
|
||||
uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */
|
||||
uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */
|
||||
struct clk_pll_simple plld2; /* _PLLD2_BASE_0, 0x4B8 */
|
||||
uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */
|
||||
uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */
|
||||
uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */
|
||||
|
||||
@ -23,6 +23,7 @@ enum clock_id {
|
||||
CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
|
||||
CLOCK_ID_EPCI,
|
||||
CLOCK_ID_SFROM32KHZ,
|
||||
CLOCK_ID_DISPLAY2,
|
||||
|
||||
/* These are the base clocks (inputs to the Tegra SOC) */
|
||||
CLOCK_ID_32KHZ,
|
||||
@ -30,7 +31,6 @@ enum clock_id {
|
||||
CLOCK_ID_CLK_M,
|
||||
|
||||
CLOCK_ID_COUNT, /* number of PLLs */
|
||||
CLOCK_ID_DISPLAY2, /* placeholder */
|
||||
CLOCK_ID_NONE = -1,
|
||||
};
|
||||
|
||||
|
||||
@ -312,6 +312,309 @@ enum pmux_func {
|
||||
PMUX_FUNC_COUNT,
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_pingrp[] = {
|
||||
[PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1",
|
||||
[PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2",
|
||||
[PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3",
|
||||
[PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4",
|
||||
[PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5",
|
||||
[PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6",
|
||||
[PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7",
|
||||
[PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0",
|
||||
[PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0",
|
||||
[PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1",
|
||||
[PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2",
|
||||
[PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3",
|
||||
[PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0",
|
||||
[PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1",
|
||||
[PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2",
|
||||
[PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3",
|
||||
[PMUX_PINGRP_PV0] = "pv0",
|
||||
[PMUX_PINGRP_PV1] = "pv1",
|
||||
[PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0",
|
||||
[PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1",
|
||||
[PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4",
|
||||
[PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5",
|
||||
[PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6",
|
||||
[PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7",
|
||||
[PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5",
|
||||
[PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5",
|
||||
[PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7",
|
||||
[PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4",
|
||||
[PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5",
|
||||
[PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3",
|
||||
[PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2",
|
||||
[PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6",
|
||||
[PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5",
|
||||
[PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6",
|
||||
[PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7",
|
||||
[PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1",
|
||||
[PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0",
|
||||
[PMUX_PINGRP_PU0] = "pu0",
|
||||
[PMUX_PINGRP_PU1] = "pu1",
|
||||
[PMUX_PINGRP_PU2] = "pu2",
|
||||
[PMUX_PINGRP_PU3] = "pu3",
|
||||
[PMUX_PINGRP_PU4] = "pu4",
|
||||
[PMUX_PINGRP_PU5] = "pu5",
|
||||
[PMUX_PINGRP_PU6] = "pu6",
|
||||
[PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5",
|
||||
[PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4",
|
||||
[PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4",
|
||||
[PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5",
|
||||
[PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6",
|
||||
[PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7",
|
||||
[PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0",
|
||||
[PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1",
|
||||
[PMUX_PINGRP_GMI_WP_N_PC7] = "gmi_wp_n_pc7",
|
||||
[PMUX_PINGRP_GMI_IORDY_PI5] = "gmi_iordy_pi5",
|
||||
[PMUX_PINGRP_GMI_WAIT_PI7] = "gmi_wait_pi7",
|
||||
[PMUX_PINGRP_GMI_ADV_N_PK0] = "gmi_adv_n_pk0",
|
||||
[PMUX_PINGRP_GMI_CLK_PK1] = "gmi_clk_pk1",
|
||||
[PMUX_PINGRP_GMI_CS0_N_PJ0] = "gmi_cs0_n_pj0",
|
||||
[PMUX_PINGRP_GMI_CS1_N_PJ2] = "gmi_cs1_n_pj2",
|
||||
[PMUX_PINGRP_GMI_CS2_N_PK3] = "gmi_cs2_n_pk3",
|
||||
[PMUX_PINGRP_GMI_CS3_N_PK4] = "gmi_cs3_n_pk4",
|
||||
[PMUX_PINGRP_GMI_CS4_N_PK2] = "gmi_cs4_n_pk2",
|
||||
[PMUX_PINGRP_GMI_CS6_N_PI3] = "gmi_cs6_n_pi3",
|
||||
[PMUX_PINGRP_GMI_CS7_N_PI6] = "gmi_cs7_n_pi6",
|
||||
[PMUX_PINGRP_GMI_AD0_PG0] = "gmi_ad0_pg0",
|
||||
[PMUX_PINGRP_GMI_AD1_PG1] = "gmi_ad1_pg1",
|
||||
[PMUX_PINGRP_GMI_AD2_PG2] = "gmi_ad2_pg2",
|
||||
[PMUX_PINGRP_GMI_AD3_PG3] = "gmi_ad3_pg3",
|
||||
[PMUX_PINGRP_GMI_AD4_PG4] = "gmi_ad4_pg4",
|
||||
[PMUX_PINGRP_GMI_AD5_PG5] = "gmi_ad5_pg5",
|
||||
[PMUX_PINGRP_GMI_AD6_PG6] = "gmi_ad6_pg6",
|
||||
[PMUX_PINGRP_GMI_AD7_PG7] = "gmi_ad7_pg7",
|
||||
[PMUX_PINGRP_GMI_AD8_PH0] = "gmi_ad8_ph0",
|
||||
[PMUX_PINGRP_GMI_AD9_PH1] = "gmi_ad9_ph1",
|
||||
[PMUX_PINGRP_GMI_AD10_PH2] = "gmi_ad10_ph2",
|
||||
[PMUX_PINGRP_GMI_AD11_PH3] = "gmi_ad11_ph3",
|
||||
[PMUX_PINGRP_GMI_AD12_PH4] = "gmi_ad12_ph4",
|
||||
[PMUX_PINGRP_GMI_AD13_PH5] = "gmi_ad13_ph5",
|
||||
[PMUX_PINGRP_GMI_AD14_PH6] = "gmi_ad14_ph6",
|
||||
[PMUX_PINGRP_GMI_AD15_PH7] = "gmi_ad15_ph7",
|
||||
[PMUX_PINGRP_GMI_A16_PJ7] = "gmi_a16_pj7",
|
||||
[PMUX_PINGRP_GMI_A17_PB0] = "gmi_a17_pb0",
|
||||
[PMUX_PINGRP_GMI_A18_PB1] = "gmi_a18_pb1",
|
||||
[PMUX_PINGRP_GMI_A19_PK7] = "gmi_a19_pk7",
|
||||
[PMUX_PINGRP_GMI_WR_N_PI0] = "gmi_wr_n_pi0",
|
||||
[PMUX_PINGRP_GMI_OE_N_PI1] = "gmi_oe_n_pi1",
|
||||
[PMUX_PINGRP_GMI_DQS_P_PJ3] = "gmi_dqs_p_pj3",
|
||||
[PMUX_PINGRP_GMI_RST_N_PI4] = "gmi_rst_n_pi4",
|
||||
[PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5",
|
||||
[PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6",
|
||||
[PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4",
|
||||
[PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7",
|
||||
[PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0",
|
||||
[PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1",
|
||||
[PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2",
|
||||
[PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3",
|
||||
[PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4",
|
||||
[PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5",
|
||||
[PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6",
|
||||
[PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7",
|
||||
[PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0",
|
||||
[PMUX_PINGRP_PCC1] = "pcc1",
|
||||
[PMUX_PINGRP_PBB0] = "pbb0",
|
||||
[PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1",
|
||||
[PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2",
|
||||
[PMUX_PINGRP_PBB3] = "pbb3",
|
||||
[PMUX_PINGRP_PBB4] = "pbb4",
|
||||
[PMUX_PINGRP_PBB5] = "pbb5",
|
||||
[PMUX_PINGRP_PBB6] = "pbb6",
|
||||
[PMUX_PINGRP_PBB7] = "pbb7",
|
||||
[PMUX_PINGRP_PCC2] = "pcc2",
|
||||
[PMUX_PINGRP_JTAG_RTCK] = "jtag_rtck",
|
||||
[PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6",
|
||||
[PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7",
|
||||
[PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0",
|
||||
[PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1",
|
||||
[PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2",
|
||||
[PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3",
|
||||
[PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4",
|
||||
[PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5",
|
||||
[PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6",
|
||||
[PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7",
|
||||
[PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0",
|
||||
[PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1",
|
||||
[PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2",
|
||||
[PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0",
|
||||
[PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1",
|
||||
[PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2",
|
||||
[PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3",
|
||||
[PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4",
|
||||
[PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5",
|
||||
[PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6",
|
||||
[PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7",
|
||||
[PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0",
|
||||
[PMUX_PINGRP_SYS_CLK_REQ_PZ5] = "sys_clk_req_pz5",
|
||||
[PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req",
|
||||
[PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req",
|
||||
[PMUX_PINGRP_PWR_INT_N] = "pwr_int_n",
|
||||
[PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in",
|
||||
[PMUX_PINGRP_OWR] = "owr",
|
||||
[PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0",
|
||||
[PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1",
|
||||
[PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2",
|
||||
[PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3",
|
||||
[PMUX_PINGRP_CLK1_REQ_PEE2] = "clk1_req_pee2",
|
||||
[PMUX_PINGRP_CLK1_OUT_PW4] = "clk1_out_pw4",
|
||||
[PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6",
|
||||
[PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5",
|
||||
[PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2",
|
||||
[PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4",
|
||||
[PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5",
|
||||
[PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3",
|
||||
[PMUX_PINGRP_DVFS_PWM_PX0] = "dvfs_pwm_px0",
|
||||
[PMUX_PINGRP_GPIO_X1_AUD_PX1] = "gpio_x1_aud_px1",
|
||||
[PMUX_PINGRP_GPIO_X3_AUD_PX3] = "gpio_x3_aud_px3",
|
||||
[PMUX_PINGRP_DVFS_CLK_PX2] = "dvfs_clk_px2",
|
||||
[PMUX_PINGRP_GPIO_X4_AUD_PX4] = "gpio_x4_aud_px4",
|
||||
[PMUX_PINGRP_GPIO_X5_AUD_PX5] = "gpio_x5_aud_px5",
|
||||
[PMUX_PINGRP_GPIO_X6_AUD_PX6] = "gpio_x6_aud_px6",
|
||||
[PMUX_PINGRP_GPIO_X7_AUD_PX7] = "gpio_x7_aud_px7",
|
||||
[PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6",
|
||||
[PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7",
|
||||
[PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7",
|
||||
[PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6",
|
||||
[PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5",
|
||||
[PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4",
|
||||
[PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3",
|
||||
[PMUX_PINGRP_SDMMC1_WP_N_PV3] = "sdmmc1_wp_n_pv3",
|
||||
[PMUX_PINGRP_SDMMC3_CD_N_PV2] = "sdmmc3_cd_n_pv2",
|
||||
[PMUX_PINGRP_GPIO_W2_AUD_PW2] = "gpio_w2_aud_pw2",
|
||||
[PMUX_PINGRP_GPIO_W3_AUD_PW3] = "gpio_w3_aud_pw3",
|
||||
[PMUX_PINGRP_USB_VBUS_EN0_PN4] = "usb_vbus_en0_pn4",
|
||||
[PMUX_PINGRP_USB_VBUS_EN1_PN5] = "usb_vbus_en1_pn5",
|
||||
[PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5] = "sdmmc3_clk_lb_in_pee5",
|
||||
[PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4] = "sdmmc3_clk_lb_out_pee4",
|
||||
[PMUX_PINGRP_GMI_CLK_LB] = "gmi_clk_lb",
|
||||
[PMUX_PINGRP_RESET_OUT_N] = "reset_out_n",
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_drvgrp[] = {
|
||||
[PMUX_DRVGRP_AO1] = "drive_ao1",
|
||||
[PMUX_DRVGRP_AO2] = "drive_ao2",
|
||||
[PMUX_DRVGRP_AT1] = "drive_at1",
|
||||
[PMUX_DRVGRP_AT2] = "drive_at2",
|
||||
[PMUX_DRVGRP_AT3] = "drive_at3",
|
||||
[PMUX_DRVGRP_AT4] = "drive_at4",
|
||||
[PMUX_DRVGRP_AT5] = "drive_at5",
|
||||
[PMUX_DRVGRP_CDEV1] = "drive_cdev1",
|
||||
[PMUX_DRVGRP_CDEV2] = "drive_cdev2",
|
||||
[PMUX_DRVGRP_DAP1] = "drive_dap1",
|
||||
[PMUX_DRVGRP_DAP2] = "drive_dap2",
|
||||
[PMUX_DRVGRP_DAP3] = "drive_dap3",
|
||||
[PMUX_DRVGRP_DAP4] = "drive_dap4",
|
||||
[PMUX_DRVGRP_DBG] = "drive_dbg",
|
||||
[PMUX_DRVGRP_SDIO3] = "drive_sdio3",
|
||||
[PMUX_DRVGRP_SPI] = "drive_spi",
|
||||
[PMUX_DRVGRP_UAA] = "drive_uaa",
|
||||
[PMUX_DRVGRP_UAB] = "drive_uab",
|
||||
[PMUX_DRVGRP_UART2] = "drive_uart2",
|
||||
[PMUX_DRVGRP_UART3] = "drive_uart3",
|
||||
[PMUX_DRVGRP_SDIO1] = "drive_sdio1",
|
||||
[PMUX_DRVGRP_DDC] = "drive_ddc",
|
||||
[PMUX_DRVGRP_GMA] = "drive_gma",
|
||||
[PMUX_DRVGRP_GME] = "drive_gme",
|
||||
[PMUX_DRVGRP_GMF] = "drive_gmf",
|
||||
[PMUX_DRVGRP_GMG] = "drive_gmg",
|
||||
[PMUX_DRVGRP_GMH] = "drive_gmh",
|
||||
[PMUX_DRVGRP_OWR] = "drive_owr",
|
||||
[PMUX_DRVGRP_UDA] = "drive_uda",
|
||||
[PMUX_DRVGRP_DEV3] = "drive_dev3",
|
||||
[PMUX_DRVGRP_CEC] = "drive_cec",
|
||||
[PMUX_DRVGRP_AT6] = "drive_at6",
|
||||
[PMUX_DRVGRP_DAP5] = "drive_dap5",
|
||||
[PMUX_DRVGRP_USB_VBUS_EN] = "drive_usb_vbus_en",
|
||||
[PMUX_DRVGRP_AO3] = "drive_ao3",
|
||||
[PMUX_DRVGRP_HV0] = "drive_hv0",
|
||||
[PMUX_DRVGRP_SDIO4] = "drive_sdio4",
|
||||
[PMUX_DRVGRP_AO0] = "drive_ao0",
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_func[] = {
|
||||
[PMUX_FUNC_DEFAULT] = "default",
|
||||
[PMUX_FUNC_BLINK] = "blink",
|
||||
[PMUX_FUNC_CEC] = "cec",
|
||||
[PMUX_FUNC_CLDVFS] = "cldvfs",
|
||||
[PMUX_FUNC_CLK] = "clk",
|
||||
[PMUX_FUNC_CLK12] = "clk12",
|
||||
[PMUX_FUNC_CPU] = "cpu",
|
||||
[PMUX_FUNC_DAP] = "dap",
|
||||
[PMUX_FUNC_DAP1] = "dap1",
|
||||
[PMUX_FUNC_DAP2] = "dap2",
|
||||
[PMUX_FUNC_DEV3] = "dev3",
|
||||
[PMUX_FUNC_DISPLAYA] = "displaya",
|
||||
[PMUX_FUNC_DISPLAYA_ALT] = "displaya_alt",
|
||||
[PMUX_FUNC_DISPLAYB] = "displayb",
|
||||
[PMUX_FUNC_DTV] = "dtv",
|
||||
[PMUX_FUNC_EMC_DLL] = "emc_dll",
|
||||
[PMUX_FUNC_EXTPERIPH1] = "extperiph1",
|
||||
[PMUX_FUNC_EXTPERIPH2] = "extperiph2",
|
||||
[PMUX_FUNC_EXTPERIPH3] = "extperiph3",
|
||||
[PMUX_FUNC_GMI] = "gmi",
|
||||
[PMUX_FUNC_GMI_ALT] = "gmi_alt",
|
||||
[PMUX_FUNC_HDA] = "hda",
|
||||
[PMUX_FUNC_HSI] = "hsi",
|
||||
[PMUX_FUNC_I2C1] = "i2c1",
|
||||
[PMUX_FUNC_I2C2] = "i2c2",
|
||||
[PMUX_FUNC_I2C3] = "i2c3",
|
||||
[PMUX_FUNC_I2C4] = "i2c4",
|
||||
[PMUX_FUNC_I2CPWR] = "i2cpwr",
|
||||
[PMUX_FUNC_I2S0] = "i2s0",
|
||||
[PMUX_FUNC_I2S1] = "i2s1",
|
||||
[PMUX_FUNC_I2S2] = "i2s2",
|
||||
[PMUX_FUNC_I2S3] = "i2s3",
|
||||
[PMUX_FUNC_I2S4] = "i2s4",
|
||||
[PMUX_FUNC_IRDA] = "irda",
|
||||
[PMUX_FUNC_KBC] = "kbc",
|
||||
[PMUX_FUNC_NAND] = "nand",
|
||||
[PMUX_FUNC_NAND_ALT] = "nand_alt",
|
||||
[PMUX_FUNC_OWR] = "owr",
|
||||
[PMUX_FUNC_PMI] = "pmi",
|
||||
[PMUX_FUNC_PWM0] = "pwm0",
|
||||
[PMUX_FUNC_PWM1] = "pwm1",
|
||||
[PMUX_FUNC_PWM2] = "pwm2",
|
||||
[PMUX_FUNC_PWM3] = "pwm3",
|
||||
[PMUX_FUNC_PWRON] = "pwron",
|
||||
[PMUX_FUNC_RESET_OUT_N] = "reset_out_n",
|
||||
[PMUX_FUNC_RTCK] = "rtck",
|
||||
[PMUX_FUNC_SDMMC1] = "sdmmc1",
|
||||
[PMUX_FUNC_SDMMC2] = "sdmmc2",
|
||||
[PMUX_FUNC_SDMMC3] = "sdmmc3",
|
||||
[PMUX_FUNC_SDMMC4] = "sdmmc4",
|
||||
[PMUX_FUNC_SOC] = "soc",
|
||||
[PMUX_FUNC_SPDIF] = "spdif",
|
||||
[PMUX_FUNC_SPI1] = "spi1",
|
||||
[PMUX_FUNC_SPI2] = "spi2",
|
||||
[PMUX_FUNC_SPI3] = "spi3",
|
||||
[PMUX_FUNC_SPI4] = "spi4",
|
||||
[PMUX_FUNC_SPI5] = "spi5",
|
||||
[PMUX_FUNC_SPI6] = "spi6",
|
||||
[PMUX_FUNC_SYSCLK] = "sysclk",
|
||||
[PMUX_FUNC_TRACE] = "trace",
|
||||
[PMUX_FUNC_UARTA] = "uarta",
|
||||
[PMUX_FUNC_UARTB] = "uartb",
|
||||
[PMUX_FUNC_UARTC] = "uartc",
|
||||
[PMUX_FUNC_UARTD] = "uartd",
|
||||
[PMUX_FUNC_ULPI] = "ulpi",
|
||||
[PMUX_FUNC_USB] = "usb",
|
||||
[PMUX_FUNC_VGP1] = "vgp1",
|
||||
[PMUX_FUNC_VGP2] = "vgp2",
|
||||
[PMUX_FUNC_VGP3] = "vgp3",
|
||||
[PMUX_FUNC_VGP4] = "vgp4",
|
||||
[PMUX_FUNC_VGP5] = "vgp5",
|
||||
[PMUX_FUNC_VGP6] = "vgp6",
|
||||
[PMUX_FUNC_VI] = "vi",
|
||||
[PMUX_FUNC_VI_ALT1] = "vi_alt1",
|
||||
[PMUX_FUNC_VI_ALT3] = "vi_alt3",
|
||||
[PMUX_FUNC_RSVD1] = "rsvd1",
|
||||
[PMUX_FUNC_RSVD2] = "rsvd2",
|
||||
[PMUX_FUNC_RSVD3] = "rsvd3",
|
||||
[PMUX_FUNC_RSVD4] = "rsvd4",
|
||||
};
|
||||
|
||||
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
|
||||
#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
|
||||
#define TEGRA_PMX_SOC_HAS_DRVGRPS
|
||||
|
||||
@ -341,6 +341,333 @@ enum pmux_func {
|
||||
PMUX_FUNC_COUNT,
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_pingrp[] = {
|
||||
[PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1",
|
||||
[PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2",
|
||||
[PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3",
|
||||
[PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4",
|
||||
[PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5",
|
||||
[PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6",
|
||||
[PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7",
|
||||
[PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0",
|
||||
[PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0",
|
||||
[PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1",
|
||||
[PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2",
|
||||
[PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3",
|
||||
[PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0",
|
||||
[PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1",
|
||||
[PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2",
|
||||
[PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3",
|
||||
[PMUX_PINGRP_PV0] = "pv0",
|
||||
[PMUX_PINGRP_PV1] = "pv1",
|
||||
[PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0",
|
||||
[PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1",
|
||||
[PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4",
|
||||
[PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5",
|
||||
[PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6",
|
||||
[PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7",
|
||||
[PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5",
|
||||
[PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5",
|
||||
[PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7",
|
||||
[PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4",
|
||||
[PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5",
|
||||
[PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3",
|
||||
[PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2",
|
||||
[PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6",
|
||||
[PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5",
|
||||
[PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6",
|
||||
[PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7",
|
||||
[PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1",
|
||||
[PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0",
|
||||
[PMUX_PINGRP_PU0] = "pu0",
|
||||
[PMUX_PINGRP_PU1] = "pu1",
|
||||
[PMUX_PINGRP_PU2] = "pu2",
|
||||
[PMUX_PINGRP_PU3] = "pu3",
|
||||
[PMUX_PINGRP_PU4] = "pu4",
|
||||
[PMUX_PINGRP_PU5] = "pu5",
|
||||
[PMUX_PINGRP_PU6] = "pu6",
|
||||
[PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5",
|
||||
[PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4",
|
||||
[PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4",
|
||||
[PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5",
|
||||
[PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6",
|
||||
[PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7",
|
||||
[PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0",
|
||||
[PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1",
|
||||
[PMUX_PINGRP_PC7] = "pc7",
|
||||
[PMUX_PINGRP_PI5] = "pi5",
|
||||
[PMUX_PINGRP_PI7] = "pi7",
|
||||
[PMUX_PINGRP_PK0] = "pk0",
|
||||
[PMUX_PINGRP_PK1] = "pk1",
|
||||
[PMUX_PINGRP_PJ0] = "pj0",
|
||||
[PMUX_PINGRP_PJ2] = "pj2",
|
||||
[PMUX_PINGRP_PK3] = "pk3",
|
||||
[PMUX_PINGRP_PK4] = "pk4",
|
||||
[PMUX_PINGRP_PK2] = "pk2",
|
||||
[PMUX_PINGRP_PI3] = "pi3",
|
||||
[PMUX_PINGRP_PI6] = "pi6",
|
||||
[PMUX_PINGRP_PG0] = "pg0",
|
||||
[PMUX_PINGRP_PG1] = "pg1",
|
||||
[PMUX_PINGRP_PG2] = "pg2",
|
||||
[PMUX_PINGRP_PG3] = "pg3",
|
||||
[PMUX_PINGRP_PG4] = "pg4",
|
||||
[PMUX_PINGRP_PG5] = "pg5",
|
||||
[PMUX_PINGRP_PG6] = "pg6",
|
||||
[PMUX_PINGRP_PG7] = "pg7",
|
||||
[PMUX_PINGRP_PH0] = "ph0",
|
||||
[PMUX_PINGRP_PH1] = "ph1",
|
||||
[PMUX_PINGRP_PH2] = "ph2",
|
||||
[PMUX_PINGRP_PH3] = "ph3",
|
||||
[PMUX_PINGRP_PH4] = "ph4",
|
||||
[PMUX_PINGRP_PH5] = "ph5",
|
||||
[PMUX_PINGRP_PH6] = "ph6",
|
||||
[PMUX_PINGRP_PH7] = "ph7",
|
||||
[PMUX_PINGRP_PJ7] = "pj7",
|
||||
[PMUX_PINGRP_PB0] = "pb0",
|
||||
[PMUX_PINGRP_PB1] = "pb1",
|
||||
[PMUX_PINGRP_PK7] = "pk7",
|
||||
[PMUX_PINGRP_PI0] = "pi0",
|
||||
[PMUX_PINGRP_PI1] = "pi1",
|
||||
[PMUX_PINGRP_PI2] = "pi2",
|
||||
[PMUX_PINGRP_PI4] = "pi4",
|
||||
[PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5",
|
||||
[PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6",
|
||||
[PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4",
|
||||
[PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7",
|
||||
[PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0",
|
||||
[PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1",
|
||||
[PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2",
|
||||
[PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3",
|
||||
[PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4",
|
||||
[PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5",
|
||||
[PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6",
|
||||
[PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7",
|
||||
[PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0",
|
||||
[PMUX_PINGRP_PCC1] = "pcc1",
|
||||
[PMUX_PINGRP_PBB0] = "pbb0",
|
||||
[PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1",
|
||||
[PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2",
|
||||
[PMUX_PINGRP_PBB3] = "pbb3",
|
||||
[PMUX_PINGRP_PBB4] = "pbb4",
|
||||
[PMUX_PINGRP_PBB5] = "pbb5",
|
||||
[PMUX_PINGRP_PBB6] = "pbb6",
|
||||
[PMUX_PINGRP_PBB7] = "pbb7",
|
||||
[PMUX_PINGRP_PCC2] = "pcc2",
|
||||
[PMUX_PINGRP_JTAG_RTCK] = "jtag_rtck",
|
||||
[PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6",
|
||||
[PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7",
|
||||
[PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0",
|
||||
[PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1",
|
||||
[PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2",
|
||||
[PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3",
|
||||
[PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4",
|
||||
[PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5",
|
||||
[PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6",
|
||||
[PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7",
|
||||
[PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0",
|
||||
[PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1",
|
||||
[PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2",
|
||||
[PMUX_PINGRP_KB_ROW11_PS3] = "kb_row11_ps3",
|
||||
[PMUX_PINGRP_KB_ROW12_PS4] = "kb_row12_ps4",
|
||||
[PMUX_PINGRP_KB_ROW13_PS5] = "kb_row13_ps5",
|
||||
[PMUX_PINGRP_KB_ROW14_PS6] = "kb_row14_ps6",
|
||||
[PMUX_PINGRP_KB_ROW15_PS7] = "kb_row15_ps7",
|
||||
[PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0",
|
||||
[PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1",
|
||||
[PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2",
|
||||
[PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3",
|
||||
[PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4",
|
||||
[PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5",
|
||||
[PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6",
|
||||
[PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7",
|
||||
[PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0",
|
||||
[PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req",
|
||||
[PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req",
|
||||
[PMUX_PINGRP_PWR_INT_N] = "pwr_int_n",
|
||||
[PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in",
|
||||
[PMUX_PINGRP_OWR] = "owr",
|
||||
[PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0",
|
||||
[PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1",
|
||||
[PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2",
|
||||
[PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3",
|
||||
[PMUX_PINGRP_DAP_MCLK1_REQ_PEE2] = "dap_mclk1_req_pee2",
|
||||
[PMUX_PINGRP_DAP_MCLK1_PW4] = "dap_mclk1_pw4",
|
||||
[PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6",
|
||||
[PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5",
|
||||
[PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2",
|
||||
[PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4",
|
||||
[PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5",
|
||||
[PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3",
|
||||
[PMUX_PINGRP_DVFS_PWM_PX0] = "dvfs_pwm_px0",
|
||||
[PMUX_PINGRP_GPIO_X1_AUD_PX1] = "gpio_x1_aud_px1",
|
||||
[PMUX_PINGRP_GPIO_X3_AUD_PX3] = "gpio_x3_aud_px3",
|
||||
[PMUX_PINGRP_DVFS_CLK_PX2] = "dvfs_clk_px2",
|
||||
[PMUX_PINGRP_GPIO_X4_AUD_PX4] = "gpio_x4_aud_px4",
|
||||
[PMUX_PINGRP_GPIO_X5_AUD_PX5] = "gpio_x5_aud_px5",
|
||||
[PMUX_PINGRP_GPIO_X6_AUD_PX6] = "gpio_x6_aud_px6",
|
||||
[PMUX_PINGRP_GPIO_X7_AUD_PX7] = "gpio_x7_aud_px7",
|
||||
[PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6",
|
||||
[PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7",
|
||||
[PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7",
|
||||
[PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6",
|
||||
[PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5",
|
||||
[PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4",
|
||||
[PMUX_PINGRP_PEX_L0_RST_N_PDD1] = "pex_l0_rst_n_pdd1",
|
||||
[PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2] = "pex_l0_clkreq_n_pdd2",
|
||||
[PMUX_PINGRP_PEX_WAKE_N_PDD3] = "pex_wake_n_pdd3",
|
||||
[PMUX_PINGRP_PEX_L1_RST_N_PDD5] = "pex_l1_rst_n_pdd5",
|
||||
[PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6] = "pex_l1_clkreq_n_pdd6",
|
||||
[PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3",
|
||||
[PMUX_PINGRP_SDMMC1_WP_N_PV3] = "sdmmc1_wp_n_pv3",
|
||||
[PMUX_PINGRP_SDMMC3_CD_N_PV2] = "sdmmc3_cd_n_pv2",
|
||||
[PMUX_PINGRP_GPIO_W2_AUD_PW2] = "gpio_w2_aud_pw2",
|
||||
[PMUX_PINGRP_GPIO_W3_AUD_PW3] = "gpio_w3_aud_pw3",
|
||||
[PMUX_PINGRP_USB_VBUS_EN0_PN4] = "usb_vbus_en0_pn4",
|
||||
[PMUX_PINGRP_USB_VBUS_EN1_PN5] = "usb_vbus_en1_pn5",
|
||||
[PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5] = "sdmmc3_clk_lb_in_pee5",
|
||||
[PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4] = "sdmmc3_clk_lb_out_pee4",
|
||||
[PMUX_PINGRP_GMI_CLK_LB] = "gmi_clk_lb",
|
||||
[PMUX_PINGRP_RESET_OUT_N] = "reset_out_n",
|
||||
[PMUX_PINGRP_KB_ROW16_PT0] = "kb_row16_pt0",
|
||||
[PMUX_PINGRP_KB_ROW17_PT1] = "kb_row17_pt1",
|
||||
[PMUX_PINGRP_USB_VBUS_EN2_PFF1] = "usb_vbus_en2_pff1",
|
||||
[PMUX_PINGRP_PFF2] = "pff2",
|
||||
[PMUX_PINGRP_DP_HPD_PFF0] = "dp_hpd_pff0",
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_drvgrp[] = {
|
||||
[PMUX_DRVGRP_AO1] = "ao1",
|
||||
[PMUX_DRVGRP_AO2] = "ao2",
|
||||
[PMUX_DRVGRP_AT1] = "at1",
|
||||
[PMUX_DRVGRP_AT2] = "at2",
|
||||
[PMUX_DRVGRP_AT3] = "at3",
|
||||
[PMUX_DRVGRP_AT4] = "at4",
|
||||
[PMUX_DRVGRP_AT5] = "at5",
|
||||
[PMUX_DRVGRP_CDEV1] = "cdev1",
|
||||
[PMUX_DRVGRP_CDEV2] = "cdev2",
|
||||
[PMUX_DRVGRP_DAP1] = "dap1",
|
||||
[PMUX_DRVGRP_DAP2] = "dap2",
|
||||
[PMUX_DRVGRP_DAP3] = "dap3",
|
||||
[PMUX_DRVGRP_DAP4] = "dap4",
|
||||
[PMUX_DRVGRP_DBG] = "dbg",
|
||||
[PMUX_DRVGRP_SDIO3] = "sdio3",
|
||||
[PMUX_DRVGRP_SPI] = "spi",
|
||||
[PMUX_DRVGRP_UAA] = "uaa",
|
||||
[PMUX_DRVGRP_UAB] = "uab",
|
||||
[PMUX_DRVGRP_UART2] = "uart2",
|
||||
[PMUX_DRVGRP_UART3] = "uart3",
|
||||
[PMUX_DRVGRP_SDIO1] = "sdio1",
|
||||
[PMUX_DRVGRP_DDC] = "ddc",
|
||||
[PMUX_DRVGRP_GMA] = "gma",
|
||||
[PMUX_DRVGRP_GME] = "gme",
|
||||
[PMUX_DRVGRP_GMF] = "gmf",
|
||||
[PMUX_DRVGRP_GMG] = "gmg",
|
||||
[PMUX_DRVGRP_GMH] = "gmh",
|
||||
[PMUX_DRVGRP_OWR] = "owr",
|
||||
[PMUX_DRVGRP_UDA] = "uda",
|
||||
[PMUX_DRVGRP_GPV] = "gpv",
|
||||
[PMUX_DRVGRP_DEV3] = "dev3",
|
||||
[PMUX_DRVGRP_CEC] = "cec",
|
||||
[PMUX_DRVGRP_AT6] = "at6",
|
||||
[PMUX_DRVGRP_DAP5] = "dap5",
|
||||
[PMUX_DRVGRP_USB_VBUS_EN] = "usb_vbus_en",
|
||||
[PMUX_DRVGRP_AO3] = "ao3",
|
||||
[PMUX_DRVGRP_AO0] = "ao0",
|
||||
[PMUX_DRVGRP_HV0] = "hv0",
|
||||
[PMUX_DRVGRP_SDIO4] = "sdio4",
|
||||
[PMUX_DRVGRP_AO4] = "ao4",
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_func[] = {
|
||||
[PMUX_FUNC_DEFAULT] = "default",
|
||||
[PMUX_FUNC_BLINK] = "blink",
|
||||
[PMUX_FUNC_CCLA] = "ccla",
|
||||
[PMUX_FUNC_CEC] = "cec",
|
||||
[PMUX_FUNC_CLDVFS] = "cldvfs",
|
||||
[PMUX_FUNC_CLK] = "clk",
|
||||
[PMUX_FUNC_CLK12] = "clk12",
|
||||
[PMUX_FUNC_CPU] = "cpu",
|
||||
[PMUX_FUNC_CSI] = "csi",
|
||||
[PMUX_FUNC_DAP] = "dap",
|
||||
[PMUX_FUNC_DAP1] = "dap1",
|
||||
[PMUX_FUNC_DAP2] = "dap2",
|
||||
[PMUX_FUNC_DEV3] = "dev3",
|
||||
[PMUX_FUNC_DISPLAYA] = "displaya",
|
||||
[PMUX_FUNC_DISPLAYA_ALT] = "displaya_alt",
|
||||
[PMUX_FUNC_DISPLAYB] = "displayb",
|
||||
[PMUX_FUNC_DP] = "dp",
|
||||
[PMUX_FUNC_DSI_B] = "dsi_b",
|
||||
[PMUX_FUNC_DTV] = "dtv",
|
||||
[PMUX_FUNC_EXTPERIPH1] = "extperiph1",
|
||||
[PMUX_FUNC_EXTPERIPH2] = "extperiph2",
|
||||
[PMUX_FUNC_EXTPERIPH3] = "extperiph3",
|
||||
[PMUX_FUNC_GMI] = "gmi",
|
||||
[PMUX_FUNC_GMI_ALT] = "gmi_alt",
|
||||
[PMUX_FUNC_HDA] = "hda",
|
||||
[PMUX_FUNC_HSI] = "hsi",
|
||||
[PMUX_FUNC_I2C1] = "i2c1",
|
||||
[PMUX_FUNC_I2C2] = "i2c2",
|
||||
[PMUX_FUNC_I2C3] = "i2c3",
|
||||
[PMUX_FUNC_I2C4] = "i2c4",
|
||||
[PMUX_FUNC_I2CPWR] = "i2cpwr",
|
||||
[PMUX_FUNC_I2S0] = "i2s0",
|
||||
[PMUX_FUNC_I2S1] = "i2s1",
|
||||
[PMUX_FUNC_I2S2] = "i2s2",
|
||||
[PMUX_FUNC_I2S3] = "i2s3",
|
||||
[PMUX_FUNC_I2S4] = "i2s4",
|
||||
[PMUX_FUNC_IRDA] = "irda",
|
||||
[PMUX_FUNC_KBC] = "kbc",
|
||||
[PMUX_FUNC_OWR] = "owr",
|
||||
[PMUX_FUNC_PE] = "pe",
|
||||
[PMUX_FUNC_PE0] = "pe0",
|
||||
[PMUX_FUNC_PE1] = "pe1",
|
||||
[PMUX_FUNC_PMI] = "pmi",
|
||||
[PMUX_FUNC_PWM0] = "pwm0",
|
||||
[PMUX_FUNC_PWM1] = "pwm1",
|
||||
[PMUX_FUNC_PWM2] = "pwm2",
|
||||
[PMUX_FUNC_PWM3] = "pwm3",
|
||||
[PMUX_FUNC_PWRON] = "pwron",
|
||||
[PMUX_FUNC_RESET_OUT_N] = "reset_out_n",
|
||||
[PMUX_FUNC_RTCK] = "rtck",
|
||||
[PMUX_FUNC_SATA] = "sata",
|
||||
[PMUX_FUNC_SDMMC1] = "sdmmc1",
|
||||
[PMUX_FUNC_SDMMC2] = "sdmmc2",
|
||||
[PMUX_FUNC_SDMMC3] = "sdmmc3",
|
||||
[PMUX_FUNC_SDMMC4] = "sdmmc4",
|
||||
[PMUX_FUNC_SOC] = "soc",
|
||||
[PMUX_FUNC_SPDIF] = "spdif",
|
||||
[PMUX_FUNC_SPI1] = "spi1",
|
||||
[PMUX_FUNC_SPI2] = "spi2",
|
||||
[PMUX_FUNC_SPI3] = "spi3",
|
||||
[PMUX_FUNC_SPI4] = "spi4",
|
||||
[PMUX_FUNC_SPI5] = "spi5",
|
||||
[PMUX_FUNC_SPI6] = "spi6",
|
||||
[PMUX_FUNC_SYS] = "sys",
|
||||
[PMUX_FUNC_TMDS] = "tmds",
|
||||
[PMUX_FUNC_TRACE] = "trace",
|
||||
[PMUX_FUNC_UARTA] = "uarta",
|
||||
[PMUX_FUNC_UARTB] = "uartb",
|
||||
[PMUX_FUNC_UARTC] = "uartc",
|
||||
[PMUX_FUNC_UARTD] = "uartd",
|
||||
[PMUX_FUNC_ULPI] = "ulpi",
|
||||
[PMUX_FUNC_USB] = "usb",
|
||||
[PMUX_FUNC_VGP1] = "vgp1",
|
||||
[PMUX_FUNC_VGP2] = "vgp2",
|
||||
[PMUX_FUNC_VGP3] = "vgp3",
|
||||
[PMUX_FUNC_VGP4] = "vgp4",
|
||||
[PMUX_FUNC_VGP5] = "vgp5",
|
||||
[PMUX_FUNC_VGP6] = "vgp6",
|
||||
[PMUX_FUNC_VI] = "vi",
|
||||
[PMUX_FUNC_VI_ALT1] = "vi_alt1",
|
||||
[PMUX_FUNC_VI_ALT3] = "vi_alt3",
|
||||
[PMUX_FUNC_VIMCLK2] = "vimclk2",
|
||||
[PMUX_FUNC_VIMCLK2_ALT] = "vimclk2_alt",
|
||||
[PMUX_FUNC_RSVD1] = "rsvd1",
|
||||
[PMUX_FUNC_RSVD2] = "rsvd2",
|
||||
[PMUX_FUNC_RSVD3] = "rsvd3",
|
||||
[PMUX_FUNC_RSVD4] = "rsvd4",
|
||||
};
|
||||
|
||||
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
|
||||
#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820
|
||||
#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
|
||||
|
||||
@ -159,6 +159,47 @@ enum pmux_pingrp {
|
||||
PMUX_PINGRP_COUNT,
|
||||
};
|
||||
|
||||
enum pmux_drvgrp {
|
||||
PMUX_DRVGRP_AO1,
|
||||
PMUX_DRVGRP_AO2,
|
||||
PMUX_DRVGRP_AT1,
|
||||
PMUX_DRVGRP_AT2,
|
||||
PMUX_DRVGRP_CDEV1,
|
||||
PMUX_DRVGRP_CDEV2,
|
||||
PMUX_DRVGRP_CSUS,
|
||||
PMUX_DRVGRP_DAP1,
|
||||
PMUX_DRVGRP_DAP2,
|
||||
PMUX_DRVGRP_DAP3,
|
||||
PMUX_DRVGRP_DAP4,
|
||||
PMUX_DRVGRP_DBG,
|
||||
PMUX_DRVGRP_LCD1,
|
||||
PMUX_DRVGRP_LCD2,
|
||||
PMUX_DRVGRP_SDIO2,
|
||||
PMUX_DRVGRP_SDIO3,
|
||||
PMUX_DRVGRP_SPI,
|
||||
PMUX_DRVGRP_UAA,
|
||||
PMUX_DRVGRP_UAB,
|
||||
PMUX_DRVGRP_UART2,
|
||||
PMUX_DRVGRP_UART3,
|
||||
PMUX_DRVGRP_VI1,
|
||||
PMUX_DRVGRP_VI2,
|
||||
PMUX_DRVGRP_XM2A,
|
||||
PMUX_DRVGRP_XM2C,
|
||||
PMUX_DRVGRP_XM2D,
|
||||
PMUX_DRVGRP_XM2CLK,
|
||||
PMUX_DRVGRP_SDIO1 = (0x78 / 4),
|
||||
PMUX_DRVGRP_CRT = (0x84 / 4),
|
||||
PMUX_DRVGRP_DDC,
|
||||
PMUX_DRVGRP_GMA,
|
||||
PMUX_DRVGRP_GMB,
|
||||
PMUX_DRVGRP_GMC,
|
||||
PMUX_DRVGRP_GMD,
|
||||
PMUX_DRVGRP_GME,
|
||||
PMUX_DRVGRP_OWR,
|
||||
PMUX_DRVGRP_UDA,
|
||||
PMUX_DRVGRP_COUNT,
|
||||
};
|
||||
|
||||
/*
|
||||
* Functions which can be assigned to each of the pin groups. The values here
|
||||
* bear no relation to the values programmed into pinmux registers and are
|
||||
@ -232,6 +273,256 @@ enum pmux_func {
|
||||
PMUX_FUNC_COUNT,
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_pingrp[] = {
|
||||
/* APB_MISC_PP_TRISTATE_REG_A_0 */
|
||||
[PMUX_PINGRP_ATA] = "ata",
|
||||
[PMUX_PINGRP_ATB] = "atb",
|
||||
[PMUX_PINGRP_ATC] = "atc",
|
||||
[PMUX_PINGRP_ATD] = "atd",
|
||||
[PMUX_PINGRP_CDEV1] = "cdev1",
|
||||
[PMUX_PINGRP_CDEV2] = "cdev2",
|
||||
[PMUX_PINGRP_CSUS] = "csus",
|
||||
[PMUX_PINGRP_DAP1] = "dap1",
|
||||
|
||||
[PMUX_PINGRP_DAP2] = "dap2",
|
||||
[PMUX_PINGRP_DAP3] = "dap3",
|
||||
[PMUX_PINGRP_DAP4] = "dap4",
|
||||
[PMUX_PINGRP_DTA] = "dta",
|
||||
[PMUX_PINGRP_DTB] = "dtb",
|
||||
[PMUX_PINGRP_DTC] = "dtc",
|
||||
[PMUX_PINGRP_DTD] = "dtd",
|
||||
[PMUX_PINGRP_DTE] = "dte",
|
||||
|
||||
[PMUX_PINGRP_GPU] = "gpu",
|
||||
[PMUX_PINGRP_GPV] = "gpv",
|
||||
[PMUX_PINGRP_I2CP] = "i2cp",
|
||||
[PMUX_PINGRP_IRTX] = "irtx",
|
||||
[PMUX_PINGRP_IRRX] = "irrx",
|
||||
[PMUX_PINGRP_KBCB] = "kbcb",
|
||||
[PMUX_PINGRP_KBCA] = "kbca",
|
||||
[PMUX_PINGRP_PMC] = "pmc",
|
||||
|
||||
[PMUX_PINGRP_PTA] = "pta",
|
||||
[PMUX_PINGRP_RM] = "rm",
|
||||
[PMUX_PINGRP_KBCE] = "kbce",
|
||||
[PMUX_PINGRP_KBCF] = "kbcf",
|
||||
[PMUX_PINGRP_GMA] = "gma",
|
||||
[PMUX_PINGRP_GMC] = "gmc",
|
||||
[PMUX_PINGRP_SDIO1] = "sdio1",
|
||||
[PMUX_PINGRP_OWC] = "owc",
|
||||
|
||||
/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
|
||||
[PMUX_PINGRP_GME] = "gme",
|
||||
[PMUX_PINGRP_SDC] = "sdc",
|
||||
[PMUX_PINGRP_SDD] = "sdd",
|
||||
[PMUX_PINGRP_RESERVED0] = "reserved0",
|
||||
[PMUX_PINGRP_SLXA] = "slxa",
|
||||
[PMUX_PINGRP_SLXC] = "slxc",
|
||||
[PMUX_PINGRP_SLXD] = "slxd",
|
||||
[PMUX_PINGRP_SLXK] = "slxk",
|
||||
|
||||
[PMUX_PINGRP_SPDI] = "spdi",
|
||||
[PMUX_PINGRP_SPDO] = "spdo",
|
||||
[PMUX_PINGRP_SPIA] = "spia",
|
||||
[PMUX_PINGRP_SPIB] = "spib",
|
||||
[PMUX_PINGRP_SPIC] = "spic",
|
||||
[PMUX_PINGRP_SPID] = "spid",
|
||||
[PMUX_PINGRP_SPIE] = "spie",
|
||||
[PMUX_PINGRP_SPIF] = "spif",
|
||||
|
||||
[PMUX_PINGRP_SPIG] = "spig",
|
||||
[PMUX_PINGRP_SPIH] = "spih",
|
||||
[PMUX_PINGRP_UAA] = "uaa",
|
||||
[PMUX_PINGRP_UAB] = "uab",
|
||||
[PMUX_PINGRP_UAC] = "uac",
|
||||
[PMUX_PINGRP_UAD] = "uad",
|
||||
[PMUX_PINGRP_UCA] = "uca",
|
||||
[PMUX_PINGRP_UCB] = "ucb",
|
||||
|
||||
[PMUX_PINGRP_RESERVED1] = "reserved1",
|
||||
[PMUX_PINGRP_ATE] = "ate",
|
||||
[PMUX_PINGRP_KBCC] = "kbcc",
|
||||
[PMUX_PINGRP_RESERVED2] = "reserved2",
|
||||
[PMUX_PINGRP_RESERVED3] = "reserved3",
|
||||
[PMUX_PINGRP_GMB] = "gmb",
|
||||
[PMUX_PINGRP_GMD] = "gmd",
|
||||
[PMUX_PINGRP_DDC] = "ddc",
|
||||
|
||||
/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
|
||||
[PMUX_PINGRP_LD0] = "ld0",
|
||||
[PMUX_PINGRP_LD1] = "ld1",
|
||||
[PMUX_PINGRP_LD2] = "ld2",
|
||||
[PMUX_PINGRP_LD3] = "ld3",
|
||||
[PMUX_PINGRP_LD4] = "ld4",
|
||||
[PMUX_PINGRP_LD5] = "ld5",
|
||||
[PMUX_PINGRP_LD6] = "ld6",
|
||||
[PMUX_PINGRP_LD7] = "ld7",
|
||||
|
||||
[PMUX_PINGRP_LD8] = "ld8",
|
||||
[PMUX_PINGRP_LD9] = "ld9",
|
||||
[PMUX_PINGRP_LD10] = "ld10",
|
||||
[PMUX_PINGRP_LD11] = "ld11",
|
||||
[PMUX_PINGRP_LD12] = "ld12",
|
||||
[PMUX_PINGRP_LD13] = "ld13",
|
||||
[PMUX_PINGRP_LD14] = "ld14",
|
||||
[PMUX_PINGRP_LD15] = "ld15",
|
||||
|
||||
[PMUX_PINGRP_LD16] = "ld16",
|
||||
[PMUX_PINGRP_LD17] = "ld17",
|
||||
[PMUX_PINGRP_LHP0] = "lhp0",
|
||||
[PMUX_PINGRP_LHP1] = "lhp1",
|
||||
[PMUX_PINGRP_LHP2] = "lhp2",
|
||||
[PMUX_PINGRP_LVP0] = "lvp0",
|
||||
[PMUX_PINGRP_LVP1] = "lvp1",
|
||||
[PMUX_PINGRP_HDINT] = "hdint",
|
||||
|
||||
[PMUX_PINGRP_LM0] = "lm0",
|
||||
[PMUX_PINGRP_LM1] = "lm1",
|
||||
[PMUX_PINGRP_LVS] = "lvs",
|
||||
[PMUX_PINGRP_LSC0] = "lsc0",
|
||||
[PMUX_PINGRP_LSC1] = "lsc1",
|
||||
[PMUX_PINGRP_LSCK] = "lsck",
|
||||
[PMUX_PINGRP_LDC] = "ldc",
|
||||
[PMUX_PINGRP_LCSN] = "lcsn",
|
||||
|
||||
/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
|
||||
[PMUX_PINGRP_LSPI] = "lspi",
|
||||
[PMUX_PINGRP_LSDA] = "lsda",
|
||||
[PMUX_PINGRP_LSDI] = "lsdi",
|
||||
[PMUX_PINGRP_LPW0] = "lpw0",
|
||||
[PMUX_PINGRP_LPW1] = "lpw1",
|
||||
[PMUX_PINGRP_LPW2] = "lpw2",
|
||||
[PMUX_PINGRP_LDI] = "ldi",
|
||||
[PMUX_PINGRP_LHS] = "lhs",
|
||||
|
||||
[PMUX_PINGRP_LPP] = "lpp",
|
||||
[PMUX_PINGRP_RESERVED4] = "reserved4",
|
||||
[PMUX_PINGRP_KBCD] = "kbcd",
|
||||
[PMUX_PINGRP_GPU7] = "gpu7",
|
||||
[PMUX_PINGRP_DTF] = "dtf",
|
||||
[PMUX_PINGRP_UDA] = "uda",
|
||||
[PMUX_PINGRP_CRTP] = "crtp",
|
||||
[PMUX_PINGRP_SDB] = "sdb",
|
||||
|
||||
/* these pin groups only have pullup and pull down control */
|
||||
[PMUX_PINGRP_CK32] = "ck32",
|
||||
[PMUX_PINGRP_DDRC] = "ddrc",
|
||||
[PMUX_PINGRP_PMCA] = "pmca",
|
||||
[PMUX_PINGRP_PMCB] = "pmcb",
|
||||
[PMUX_PINGRP_PMCC] = "pmcc",
|
||||
[PMUX_PINGRP_PMCD] = "pmcd",
|
||||
[PMUX_PINGRP_PMCE] = "pmce",
|
||||
[PMUX_PINGRP_XM2C] = "xm2c",
|
||||
[PMUX_PINGRP_XM2D] = "xm2d",
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_drvgrp[] = {
|
||||
[PMUX_DRVGRP_AO1] = "drive_ao1",
|
||||
[PMUX_DRVGRP_AO2] = "drive_ao2",
|
||||
[PMUX_DRVGRP_AT1] = "drive_at1",
|
||||
[PMUX_DRVGRP_AT2] = "drive_at2",
|
||||
[PMUX_DRVGRP_CDEV1] = "drive_cdev1",
|
||||
[PMUX_DRVGRP_CDEV2] = "drive_cdev2",
|
||||
[PMUX_DRVGRP_CSUS] = "drive_csus",
|
||||
[PMUX_DRVGRP_DAP1] = "drive_dap1",
|
||||
[PMUX_DRVGRP_DAP2] = "drive_dap2",
|
||||
[PMUX_DRVGRP_DAP3] = "drive_dap3",
|
||||
[PMUX_DRVGRP_DAP4] = "drive_dap4",
|
||||
[PMUX_DRVGRP_DBG] = "drive_dbg",
|
||||
[PMUX_DRVGRP_LCD1] = "drive_lcd1",
|
||||
[PMUX_DRVGRP_LCD2] = "drive_lcd2",
|
||||
[PMUX_DRVGRP_SDIO2] = "drive_sdio2",
|
||||
[PMUX_DRVGRP_SDIO3] = "drive_sdio3",
|
||||
[PMUX_DRVGRP_SPI] = "drive_spi",
|
||||
[PMUX_DRVGRP_UAA] = "drive_uaa",
|
||||
[PMUX_DRVGRP_UAB] = "drive_uab",
|
||||
[PMUX_DRVGRP_UART2] = "drive_uart2",
|
||||
[PMUX_DRVGRP_UART3] = "drive_uart3",
|
||||
[PMUX_DRVGRP_VI1] = "drive_vi1",
|
||||
[PMUX_DRVGRP_VI2] = "drive_vi2",
|
||||
[PMUX_DRVGRP_XM2A] = "drive_xm2a",
|
||||
[PMUX_DRVGRP_XM2C] = "drive_xm2c",
|
||||
[PMUX_DRVGRP_XM2D] = "drive_xm2d",
|
||||
[PMUX_DRVGRP_XM2CLK] = "drive_xm2clk",
|
||||
[PMUX_DRVGRP_SDIO1] = "drive_sdio1",
|
||||
[PMUX_DRVGRP_CRT] = "drive_crt",
|
||||
[PMUX_DRVGRP_DDC] = "drive_ddc",
|
||||
[PMUX_DRVGRP_GMA] = "drive_gma",
|
||||
[PMUX_DRVGRP_GMB] = "drive_gmb",
|
||||
[PMUX_DRVGRP_GMC] = "drive_gmc",
|
||||
[PMUX_DRVGRP_GMD] = "drive_gmd",
|
||||
[PMUX_DRVGRP_GME] = "drive_gme",
|
||||
[PMUX_DRVGRP_OWR] = "drive_owr",
|
||||
[PMUX_DRVGRP_UDA] = "drive_uda",
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_func[] = {
|
||||
[PMUX_FUNC_DEFAULT] = "default",
|
||||
[PMUX_FUNC_AHB_CLK] = "ahb_clk",
|
||||
[PMUX_FUNC_APB_CLK] = "apb_clk",
|
||||
[PMUX_FUNC_AUDIO_SYNC] = "audio_sync",
|
||||
[PMUX_FUNC_CRT] = "crt",
|
||||
[PMUX_FUNC_DAP1] = "dap1",
|
||||
[PMUX_FUNC_DAP2] = "dap2",
|
||||
[PMUX_FUNC_DAP3] = "dap3",
|
||||
[PMUX_FUNC_DAP4] = "dap4",
|
||||
[PMUX_FUNC_DAP5] = "dap5",
|
||||
[PMUX_FUNC_DISPA] = "dispa",
|
||||
[PMUX_FUNC_DISPB] = "dispb",
|
||||
[PMUX_FUNC_EMC_TEST0_DLL] = "emc_test0_dll",
|
||||
[PMUX_FUNC_EMC_TEST1_DLL] = "emc_test1_dll",
|
||||
[PMUX_FUNC_GMI] = "gmi",
|
||||
[PMUX_FUNC_GMI_INT] = "gmi_int",
|
||||
[PMUX_FUNC_HDMI] = "hdmi",
|
||||
[PMUX_FUNC_I2C] = "i2c",
|
||||
[PMUX_FUNC_I2C2] = "i2c2",
|
||||
[PMUX_FUNC_I2C3] = "i2c3",
|
||||
[PMUX_FUNC_IDE] = "ide",
|
||||
[PMUX_FUNC_KBC] = "kbc",
|
||||
[PMUX_FUNC_MIO] = "mio",
|
||||
[PMUX_FUNC_MIPI_HS] = "mipi_hs",
|
||||
[PMUX_FUNC_NAND] = "nand",
|
||||
[PMUX_FUNC_OSC] = "osc",
|
||||
[PMUX_FUNC_OWR] = "owr",
|
||||
[PMUX_FUNC_PCIE] = "pcie",
|
||||
[PMUX_FUNC_PLLA_OUT] = "plla_out",
|
||||
[PMUX_FUNC_PLLC_OUT1] = "pllc_out1",
|
||||
[PMUX_FUNC_PLLM_OUT1] = "pllm_out1",
|
||||
[PMUX_FUNC_PLLP_OUT2] = "pllp_out2",
|
||||
[PMUX_FUNC_PLLP_OUT3] = "pllp_out3",
|
||||
[PMUX_FUNC_PLLP_OUT4] = "pllp_out4",
|
||||
[PMUX_FUNC_PWM] = "pwm",
|
||||
[PMUX_FUNC_PWR_INTR] = "pwr_intr",
|
||||
[PMUX_FUNC_PWR_ON] = "pwr_on",
|
||||
[PMUX_FUNC_RTCK] = "rtck",
|
||||
[PMUX_FUNC_SDIO1] = "sdio1",
|
||||
[PMUX_FUNC_SDIO2] = "sdio2",
|
||||
[PMUX_FUNC_SDIO3] = "sdio3",
|
||||
[PMUX_FUNC_SDIO4] = "sdio4",
|
||||
[PMUX_FUNC_SFLASH] = "sflash",
|
||||
[PMUX_FUNC_SPDIF] = "spdif",
|
||||
[PMUX_FUNC_SPI1] = "spi1",
|
||||
[PMUX_FUNC_SPI2] = "spi2",
|
||||
[PMUX_FUNC_SPI2_ALT] = "spi2_alt",
|
||||
[PMUX_FUNC_SPI3] = "spi3",
|
||||
[PMUX_FUNC_SPI4] = "spi4",
|
||||
[PMUX_FUNC_TRACE] = "trace",
|
||||
[PMUX_FUNC_TWC] = "twc",
|
||||
[PMUX_FUNC_UARTA] = "uarta",
|
||||
[PMUX_FUNC_UARTB] = "uartb",
|
||||
[PMUX_FUNC_UARTC] = "uartc",
|
||||
[PMUX_FUNC_UARTD] = "uartd",
|
||||
[PMUX_FUNC_UARTE] = "uarte",
|
||||
[PMUX_FUNC_ULPI] = "ulpi",
|
||||
[PMUX_FUNC_VI] = "vi",
|
||||
[PMUX_FUNC_VI_SENSOR_CLK] = "vi_sensor_clk",
|
||||
[PMUX_FUNC_XIO] = "xio",
|
||||
[PMUX_FUNC_RSVD1] = "rsvd1",
|
||||
[PMUX_FUNC_RSVD2] = "rsvd2",
|
||||
[PMUX_FUNC_RSVD3] = "rsvd3",
|
||||
[PMUX_FUNC_RSVD4] = "rsvd4",
|
||||
};
|
||||
|
||||
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
|
||||
#include <asm/arch-tegra/pinmux.h>
|
||||
|
||||
|
||||
@ -403,6 +403,400 @@ enum pmux_func {
|
||||
PMUX_FUNC_COUNT,
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_pingrp[] = {
|
||||
[PMUX_PINGRP_SDMMC1_CLK_PM0] = "sdmmc1_clk_pm0",
|
||||
[PMUX_PINGRP_SDMMC1_CMD_PM1] = "sdmmc1_cmd_pm1",
|
||||
[PMUX_PINGRP_SDMMC1_DAT3_PM2] = "sdmmc1_dat3_pm2",
|
||||
[PMUX_PINGRP_SDMMC1_DAT2_PM3] = "sdmmc1_dat2_pm3",
|
||||
[PMUX_PINGRP_SDMMC1_DAT1_PM4] = "sdmmc1_dat1_pm4",
|
||||
[PMUX_PINGRP_SDMMC1_DAT0_PM5] = "sdmmc1_dat0_pm5",
|
||||
[PMUX_PINGRP_SDMMC3_CLK_PP0] = "sdmmc3_clk_pp0",
|
||||
[PMUX_PINGRP_SDMMC3_CMD_PP1] = "sdmmc3_cmd_pp1",
|
||||
[PMUX_PINGRP_SDMMC3_DAT0_PP5] = "sdmmc3_dat0_pp5",
|
||||
[PMUX_PINGRP_SDMMC3_DAT1_PP4] = "sdmmc3_dat1_pp4",
|
||||
[PMUX_PINGRP_SDMMC3_DAT2_PP3] = "sdmmc3_dat2_pp3",
|
||||
[PMUX_PINGRP_SDMMC3_DAT3_PP2] = "sdmmc3_dat3_pp2",
|
||||
[PMUX_PINGRP_PEX_L0_RST_N_PA0] = "pex_l0_rst_n_pa0",
|
||||
[PMUX_PINGRP_PEX_L0_CLKREQ_N_PA1] = "pex_l0_clkreq_n_pa1",
|
||||
[PMUX_PINGRP_PEX_WAKE_N_PA2] = "pex_wake_n_pa2",
|
||||
[PMUX_PINGRP_PEX_L1_RST_N_PA3] = "pex_l1_rst_n_pa3",
|
||||
[PMUX_PINGRP_PEX_L1_CLKREQ_N_PA4] = "pex_l1_clkreq_n_pa4",
|
||||
[PMUX_PINGRP_SATA_LED_ACTIVE_PA5] = "sata_led_active_pa5",
|
||||
[PMUX_PINGRP_SPI1_MOSI_PC0] = "spi1_mosi_pc0",
|
||||
[PMUX_PINGRP_SPI1_MISO_PC1] = "spi1_miso_pc1",
|
||||
[PMUX_PINGRP_SPI1_SCK_PC2] = "spi1_sck_pc2",
|
||||
[PMUX_PINGRP_SPI1_CS0_PC3] = "spi1_cs0_pc3",
|
||||
[PMUX_PINGRP_SPI1_CS1_PC4] = "spi1_cs1_pc4",
|
||||
[PMUX_PINGRP_SPI2_MOSI_PB4] = "spi2_mosi_pb4",
|
||||
[PMUX_PINGRP_SPI2_MISO_PB5] = "spi2_miso_pb5",
|
||||
[PMUX_PINGRP_SPI2_SCK_PB6] = "spi2_sck_pb6",
|
||||
[PMUX_PINGRP_SPI2_CS0_PB7] = "spi2_cs0_pb7",
|
||||
[PMUX_PINGRP_SPI2_CS1_PDD0] = "spi2_cs1_pdd0",
|
||||
[PMUX_PINGRP_SPI4_MOSI_PC7] = "spi4_mosi_pc7",
|
||||
[PMUX_PINGRP_SPI4_MISO_PD0] = "spi4_miso_pd0",
|
||||
[PMUX_PINGRP_SPI4_SCK_PC5] = "spi4_sck_pc5",
|
||||
[PMUX_PINGRP_SPI4_CS0_PC6] = "spi4_cs0_pc6",
|
||||
[PMUX_PINGRP_QSPI_SCK_PEE0] = "qspi_sck_pee0",
|
||||
[PMUX_PINGRP_QSPI_CS_N_PEE1] = "qspi_cs_n_pee1",
|
||||
[PMUX_PINGRP_QSPI_IO0_PEE2] = "qspi_io0_pee2",
|
||||
[PMUX_PINGRP_QSPI_IO1_PEE3] = "qspi_io1_pee3",
|
||||
[PMUX_PINGRP_QSPI_IO2_PEE4] = "qspi_io2_pee4",
|
||||
[PMUX_PINGRP_QSPI_IO3_PEE5] = "qspi_io3_pee5",
|
||||
[PMUX_PINGRP_DMIC1_CLK_PE0] = "dmic1_clk_pe0",
|
||||
[PMUX_PINGRP_DMIC1_DAT_PE1] = "dmic1_dat_pe1",
|
||||
[PMUX_PINGRP_DMIC2_CLK_PE2] = "dmic2_clk_pe2",
|
||||
[PMUX_PINGRP_DMIC2_DAT_PE3] = "dmic2_dat_pe3",
|
||||
[PMUX_PINGRP_DMIC3_CLK_PE4] = "dmic3_clk_pe4",
|
||||
[PMUX_PINGRP_DMIC3_DAT_PE5] = "dmic3_dat_pe5",
|
||||
[PMUX_PINGRP_GEN1_I2C_SCL_PJ1] = "gen1_i2c_scl_pj1",
|
||||
[PMUX_PINGRP_GEN1_I2C_SDA_PJ0] = "gen1_i2c_sda_pj0",
|
||||
[PMUX_PINGRP_GEN2_I2C_SCL_PJ2] = "gen2_i2c_scl_pj2",
|
||||
[PMUX_PINGRP_GEN2_I2C_SDA_PJ3] = "gen2_i2c_sda_pj3",
|
||||
[PMUX_PINGRP_GEN3_I2C_SCL_PF0] = "gen3_i2c_scl_pf0",
|
||||
[PMUX_PINGRP_GEN3_I2C_SDA_PF1] = "gen3_i2c_sda_pf1",
|
||||
[PMUX_PINGRP_CAM_I2C_SCL_PS2] = "cam_i2c_scl_ps2",
|
||||
[PMUX_PINGRP_CAM_I2C_SDA_PS3] = "cam_i2c_sda_ps3",
|
||||
[PMUX_PINGRP_PWR_I2C_SCL_PY3] = "pwr_i2c_scl_py3",
|
||||
[PMUX_PINGRP_PWR_I2C_SDA_PY4] = "pwr_i2c_sda_py4",
|
||||
[PMUX_PINGRP_UART1_TX_PU0] = "uart1_tx_pu0",
|
||||
[PMUX_PINGRP_UART1_RX_PU1] = "uart1_rx_pu1",
|
||||
[PMUX_PINGRP_UART1_RTS_PU2] = "uart1_rts_pu2",
|
||||
[PMUX_PINGRP_UART1_CTS_PU3] = "uart1_cts_pu3",
|
||||
[PMUX_PINGRP_UART2_TX_PG0] = "uart2_tx_pg0",
|
||||
[PMUX_PINGRP_UART2_RX_PG1] = "uart2_rx_pg1",
|
||||
[PMUX_PINGRP_UART2_RTS_PG2] = "uart2_rts_pg2",
|
||||
[PMUX_PINGRP_UART2_CTS_PG3] = "uart2_cts_pg3",
|
||||
[PMUX_PINGRP_UART3_TX_PD1] = "uart3_tx_pd1",
|
||||
[PMUX_PINGRP_UART3_RX_PD2] = "uart3_rx_pd2",
|
||||
[PMUX_PINGRP_UART3_RTS_PD3] = "uart3_rts_pd3",
|
||||
[PMUX_PINGRP_UART3_CTS_PD4] = "uart3_cts_pd4",
|
||||
[PMUX_PINGRP_UART4_TX_PI4] = "uart4_tx_pi4",
|
||||
[PMUX_PINGRP_UART4_RX_PI5] = "uart4_rx_pi5",
|
||||
[PMUX_PINGRP_UART4_RTS_PI6] = "uart4_rts_pi6",
|
||||
[PMUX_PINGRP_UART4_CTS_PI7] = "uart4_cts_pi7",
|
||||
[PMUX_PINGRP_DAP1_FS_PB0] = "dap1_fs_pb0",
|
||||
[PMUX_PINGRP_DAP1_DIN_PB1] = "dap1_din_pb1",
|
||||
[PMUX_PINGRP_DAP1_DOUT_PB2] = "dap1_dout_pb2",
|
||||
[PMUX_PINGRP_DAP1_SCLK_PB3] = "dap1_sclk_pb3",
|
||||
[PMUX_PINGRP_DAP2_FS_PAA0] = "dap2_fs_paa0",
|
||||
[PMUX_PINGRP_DAP2_DIN_PAA2] = "dap2_din_paa2",
|
||||
[PMUX_PINGRP_DAP2_DOUT_PAA3] = "dap2_dout_paa3",
|
||||
[PMUX_PINGRP_DAP2_SCLK_PAA1] = "dap2_sclk_paa1",
|
||||
[PMUX_PINGRP_DAP4_FS_PJ4] = "dap4_fs_pj4",
|
||||
[PMUX_PINGRP_DAP4_DIN_PJ5] = "dap4_din_pj5",
|
||||
[PMUX_PINGRP_DAP4_DOUT_PJ6] = "dap4_dout_pj6",
|
||||
[PMUX_PINGRP_DAP4_SCLK_PJ7] = "dap4_sclk_pj7",
|
||||
[PMUX_PINGRP_CAM1_MCLK_PS0] = "cam1_mclk_ps0",
|
||||
[PMUX_PINGRP_CAM2_MCLK_PS1] = "cam2_mclk_ps1",
|
||||
[PMUX_PINGRP_JTAG_RTCK] = "jtag_rtck",
|
||||
[PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in",
|
||||
[PMUX_PINGRP_CLK_32K_OUT_PY5] = "clk_32k_out_py5",
|
||||
[PMUX_PINGRP_BATT_BCL] = "batt_bcl",
|
||||
[PMUX_PINGRP_CLK_REQ] = "clk_req",
|
||||
[PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req",
|
||||
[PMUX_PINGRP_PWR_INT_N] = "pwr_int_n",
|
||||
[PMUX_PINGRP_SHUTDOWN] = "shutdown",
|
||||
[PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req",
|
||||
[PMUX_PINGRP_AUD_MCLK_PBB0] = "aud_mclk_pbb0",
|
||||
[PMUX_PINGRP_DVFS_PWM_PBB1] = "dvfs_pwm_pbb1",
|
||||
[PMUX_PINGRP_DVFS_CLK_PBB2] = "dvfs_clk_pbb2",
|
||||
[PMUX_PINGRP_GPIO_X1_AUD_PBB3] = "gpio_x1_aud_pbb3",
|
||||
[PMUX_PINGRP_GPIO_X3_AUD_PBB4] = "gpio_x3_aud_pbb4",
|
||||
[PMUX_PINGRP_PCC7] = "pcc7",
|
||||
[PMUX_PINGRP_HDMI_CEC_PCC0] = "hdmi_cec_pcc0",
|
||||
[PMUX_PINGRP_HDMI_INT_DP_HPD_PCC1] = "hdmi_int_dp_hpd_pcc1",
|
||||
[PMUX_PINGRP_SPDIF_OUT_PCC2] = "spdif_out_pcc2",
|
||||
[PMUX_PINGRP_SPDIF_IN_PCC3] = "spdif_in_pcc3",
|
||||
[PMUX_PINGRP_USB_VBUS_EN0_PCC4] = "usb_vbus_en0_pcc4",
|
||||
[PMUX_PINGRP_USB_VBUS_EN1_PCC5] = "usb_vbus_en1_pcc5",
|
||||
[PMUX_PINGRP_DP_HPD0_PCC6] = "dp_hpd0_pcc6",
|
||||
[PMUX_PINGRP_WIFI_EN_PH0] = "wifi_en_ph0",
|
||||
[PMUX_PINGRP_WIFI_RST_PH1] = "wifi_rst_ph1",
|
||||
[PMUX_PINGRP_WIFI_WAKE_AP_PH2] = "wifi_wake_ap_ph2",
|
||||
[PMUX_PINGRP_AP_WAKE_BT_PH3] = "ap_wake_bt_ph3",
|
||||
[PMUX_PINGRP_BT_RST_PH4] = "bt_rst_ph4",
|
||||
[PMUX_PINGRP_BT_WAKE_AP_PH5] = "bt_wake_ap_ph5",
|
||||
[PMUX_PINGRP_AP_WAKE_NFC_PH7] = "ap_wake_nfc_ph7",
|
||||
[PMUX_PINGRP_NFC_EN_PI0] = "nfc_en_pi0",
|
||||
[PMUX_PINGRP_NFC_INT_PI1] = "nfc_int_pi1",
|
||||
[PMUX_PINGRP_GPS_EN_PI2] = "gps_en_pi2",
|
||||
[PMUX_PINGRP_GPS_RST_PI3] = "gps_rst_pi3",
|
||||
[PMUX_PINGRP_CAM_RST_PS4] = "cam_rst_ps4",
|
||||
[PMUX_PINGRP_CAM_AF_EN_PS5] = "cam_af_en_ps5",
|
||||
[PMUX_PINGRP_CAM_FLASH_EN_PS6] = "cam_flash_en_ps6",
|
||||
[PMUX_PINGRP_CAM1_PWDN_PS7] = "cam1_pwdn_ps7",
|
||||
[PMUX_PINGRP_CAM2_PWDN_PT0] = "cam2_pwdn_pt0",
|
||||
[PMUX_PINGRP_CAM1_STROBE_PT1] = "cam1_strobe_pt1",
|
||||
[PMUX_PINGRP_LCD_TE_PY2] = "lcd_te_py2",
|
||||
[PMUX_PINGRP_LCD_BL_PWM_PV0] = "lcd_bl_pwm_pv0",
|
||||
[PMUX_PINGRP_LCD_BL_EN_PV1] = "lcd_bl_en_pv1",
|
||||
[PMUX_PINGRP_LCD_RST_PV2] = "lcd_rst_pv2",
|
||||
[PMUX_PINGRP_LCD_GPIO1_PV3] = "lcd_gpio1_pv3",
|
||||
[PMUX_PINGRP_LCD_GPIO2_PV4] = "lcd_gpio2_pv4",
|
||||
[PMUX_PINGRP_AP_READY_PV5] = "ap_ready_pv5",
|
||||
[PMUX_PINGRP_TOUCH_RST_PV6] = "touch_rst_pv6",
|
||||
[PMUX_PINGRP_TOUCH_CLK_PV7] = "touch_clk_pv7",
|
||||
[PMUX_PINGRP_MODEM_WAKE_AP_PX0] = "modem_wake_ap_px0",
|
||||
[PMUX_PINGRP_TOUCH_INT_PX1] = "touch_int_px1",
|
||||
[PMUX_PINGRP_MOTION_INT_PX2] = "motion_int_px2",
|
||||
[PMUX_PINGRP_ALS_PROX_INT_PX3] = "als_prox_int_px3",
|
||||
[PMUX_PINGRP_TEMP_ALERT_PX4] = "temp_alert_px4",
|
||||
[PMUX_PINGRP_BUTTON_POWER_ON_PX5] = "button_power_on_px5",
|
||||
[PMUX_PINGRP_BUTTON_VOL_UP_PX6] = "button_vol_up_px6",
|
||||
[PMUX_PINGRP_BUTTON_VOL_DOWN_PX7] = "button_vol_down_px7",
|
||||
[PMUX_PINGRP_BUTTON_SLIDE_SW_PY0] = "button_slide_sw_py0",
|
||||
[PMUX_PINGRP_BUTTON_HOME_PY1] = "button_home_py1",
|
||||
[PMUX_PINGRP_PA6] = "pa6",
|
||||
[PMUX_PINGRP_PE6] = "pe6",
|
||||
[PMUX_PINGRP_PE7] = "pe7",
|
||||
[PMUX_PINGRP_PH6] = "ph6",
|
||||
[PMUX_PINGRP_PK0] = "pk0",
|
||||
[PMUX_PINGRP_PK1] = "pk1",
|
||||
[PMUX_PINGRP_PK2] = "pk2",
|
||||
[PMUX_PINGRP_PK3] = "pk3",
|
||||
[PMUX_PINGRP_PK4] = "pk4",
|
||||
[PMUX_PINGRP_PK5] = "pk5",
|
||||
[PMUX_PINGRP_PK6] = "pk6",
|
||||
[PMUX_PINGRP_PK7] = "pk7",
|
||||
[PMUX_PINGRP_PL0] = "pl0",
|
||||
[PMUX_PINGRP_PL1] = "pl1",
|
||||
[PMUX_PINGRP_PZ0] = "pz0",
|
||||
[PMUX_PINGRP_PZ1] = "pz1",
|
||||
[PMUX_PINGRP_PZ2] = "pz2",
|
||||
[PMUX_PINGRP_PZ3] = "pz3",
|
||||
[PMUX_PINGRP_PZ4] = "pz4",
|
||||
[PMUX_PINGRP_PZ5] = "pz5",
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_drvgrp[] = {
|
||||
[PMUX_DRVGRP_ALS_PROX_INT] = "als_prox_int",
|
||||
[PMUX_DRVGRP_AP_READY] = "ap_ready",
|
||||
[PMUX_DRVGRP_AP_WAKE_BT] = "ap_wake_bt",
|
||||
[PMUX_DRVGRP_AP_WAKE_NFC] = "ap_wake_nfc",
|
||||
[PMUX_DRVGRP_AUD_MCLK] = "aud_mclk",
|
||||
[PMUX_DRVGRP_BATT_BCL] = "batt_bcl",
|
||||
[PMUX_DRVGRP_BT_RST] = "bt_rst",
|
||||
[PMUX_DRVGRP_BT_WAKE_AP] = "bt_wake_ap",
|
||||
[PMUX_DRVGRP_BUTTON_HOME] = "button_home",
|
||||
[PMUX_DRVGRP_BUTTON_POWER_ON] = "button_power_on",
|
||||
[PMUX_DRVGRP_BUTTON_SLIDE_SW] = "button_slide_sw",
|
||||
[PMUX_DRVGRP_BUTTON_VOL_DOWN] = "button_vol_down",
|
||||
[PMUX_DRVGRP_BUTTON_VOL_UP] = "button_vol_up",
|
||||
[PMUX_DRVGRP_CAM1_MCLK] = "cam1_mclk",
|
||||
[PMUX_DRVGRP_CAM1_PWDN] = "cam1_pwdn",
|
||||
[PMUX_DRVGRP_CAM1_STROBE] = "cam1_strobe",
|
||||
[PMUX_DRVGRP_CAM2_MCLK] = "cam2_mclk",
|
||||
[PMUX_DRVGRP_CAM2_PWDN] = "cam2_pwdn",
|
||||
[PMUX_DRVGRP_CAM_AF_EN] = "cam_af_en",
|
||||
[PMUX_DRVGRP_CAM_FLASH_EN] = "cam_flash_en",
|
||||
[PMUX_DRVGRP_CAM_I2C_SCL] = "cam_i2c_scl",
|
||||
[PMUX_DRVGRP_CAM_I2C_SDA] = "cam_i2c_sda",
|
||||
[PMUX_DRVGRP_CAM_RST] = "cam_rst",
|
||||
[PMUX_DRVGRP_CLK_32K_IN] = "clk_32k_in",
|
||||
[PMUX_DRVGRP_CLK_32K_OUT] = "clk_32k_out",
|
||||
[PMUX_DRVGRP_CLK_REQ] = "clk_req",
|
||||
[PMUX_DRVGRP_CORE_PWR_REQ] = "core_pwr_req",
|
||||
[PMUX_DRVGRP_CPU_PWR_REQ] = "cpu_pwr_req",
|
||||
[PMUX_DRVGRP_DAP1_DIN] = "dap1_din",
|
||||
[PMUX_DRVGRP_DAP1_DOUT] = "dap1_dout",
|
||||
[PMUX_DRVGRP_DAP1_FS] = "dap1_fs",
|
||||
[PMUX_DRVGRP_DAP1_SCLK] = "dap1_sclk",
|
||||
[PMUX_DRVGRP_DAP2_DIN] = "dap2_din",
|
||||
[PMUX_DRVGRP_DAP2_DOUT] = "dap2_dout",
|
||||
[PMUX_DRVGRP_DAP2_FS] = "dap2_fs",
|
||||
[PMUX_DRVGRP_DAP2_SCLK] = "dap2_sclk",
|
||||
[PMUX_DRVGRP_DAP4_DIN] = "dap4_din",
|
||||
[PMUX_DRVGRP_DAP4_DOUT] = "dap4_dout",
|
||||
[PMUX_DRVGRP_DAP4_FS] = "dap4_fs",
|
||||
[PMUX_DRVGRP_DAP4_SCLK] = "dap4_sclk",
|
||||
[PMUX_DRVGRP_DMIC1_CLK] = "dmic1_clk",
|
||||
[PMUX_DRVGRP_DMIC1_DAT] = "dmic1_dat",
|
||||
[PMUX_DRVGRP_DMIC2_CLK] = "dmic2_clk",
|
||||
[PMUX_DRVGRP_DMIC2_DAT] = "dmic2_dat",
|
||||
[PMUX_DRVGRP_DMIC3_CLK] = "dmic3_clk",
|
||||
[PMUX_DRVGRP_DMIC3_DAT] = "dmic3_dat",
|
||||
[PMUX_DRVGRP_DP_HPD0] = "dp_hpd0",
|
||||
[PMUX_DRVGRP_DVFS_CLK] = "dvfs_clk",
|
||||
[PMUX_DRVGRP_DVFS_PWM] = "dvfs_pwm",
|
||||
[PMUX_DRVGRP_GEN1_I2C_SCL] = "gen1_i2c_scl",
|
||||
[PMUX_DRVGRP_GEN1_I2C_SDA] = "gen1_i2c_sda",
|
||||
[PMUX_DRVGRP_GEN2_I2C_SCL] = "gen2_i2c_scl",
|
||||
[PMUX_DRVGRP_GEN2_I2C_SDA] = "gen2_i2c_sda",
|
||||
[PMUX_DRVGRP_GEN3_I2C_SCL] = "gen3_i2c_scl",
|
||||
[PMUX_DRVGRP_GEN3_I2C_SDA] = "gen3_i2c_sda",
|
||||
[PMUX_DRVGRP_PA6] = "pa6",
|
||||
[PMUX_DRVGRP_PCC7] = "pcc7",
|
||||
[PMUX_DRVGRP_PE6] = "pe6",
|
||||
[PMUX_DRVGRP_PE7] = "pe7",
|
||||
[PMUX_DRVGRP_PH6] = "ph6",
|
||||
[PMUX_DRVGRP_PK0] = "pk0",
|
||||
[PMUX_DRVGRP_PK1] = "pk1",
|
||||
[PMUX_DRVGRP_PK2] = "pk2",
|
||||
[PMUX_DRVGRP_PK3] = "pk3",
|
||||
[PMUX_DRVGRP_PK4] = "pk4",
|
||||
[PMUX_DRVGRP_PK5] = "pk5",
|
||||
[PMUX_DRVGRP_PK6] = "pk6",
|
||||
[PMUX_DRVGRP_PK7] = "pk7",
|
||||
[PMUX_DRVGRP_PL0] = "pl0",
|
||||
[PMUX_DRVGRP_PL1] = "pl1",
|
||||
[PMUX_DRVGRP_PZ0] = "pz0",
|
||||
[PMUX_DRVGRP_PZ1] = "pz1",
|
||||
[PMUX_DRVGRP_PZ2] = "pz2",
|
||||
[PMUX_DRVGRP_PZ3] = "pz3",
|
||||
[PMUX_DRVGRP_PZ4] = "pz4",
|
||||
[PMUX_DRVGRP_PZ5] = "pz5",
|
||||
[PMUX_DRVGRP_GPIO_X1_AUD] = "gpio_x1_aud",
|
||||
[PMUX_DRVGRP_GPIO_X3_AUD] = "gpio_x3_aud",
|
||||
[PMUX_DRVGRP_GPS_EN] = "gps_en",
|
||||
[PMUX_DRVGRP_GPS_RST] = "gps_rst",
|
||||
[PMUX_DRVGRP_HDMI_CEC] = "hdmi_cec",
|
||||
[PMUX_DRVGRP_HDMI_INT_DP_HPD] = "hdmi_int_dp_hpd",
|
||||
[PMUX_DRVGRP_JTAG_RTCK] = "jtag_rtck",
|
||||
[PMUX_DRVGRP_LCD_BL_EN] = "lcd_bl_en",
|
||||
[PMUX_DRVGRP_LCD_BL_PWM] = "lcd_bl_pwm",
|
||||
[PMUX_DRVGRP_LCD_GPIO1] = "lcd_gpio1",
|
||||
[PMUX_DRVGRP_LCD_GPIO2] = "lcd_gpio2",
|
||||
[PMUX_DRVGRP_LCD_RST] = "lcd_rst",
|
||||
[PMUX_DRVGRP_LCD_TE] = "lcd_te",
|
||||
[PMUX_DRVGRP_MODEM_WAKE_AP] = "modem_wake_ap",
|
||||
[PMUX_DRVGRP_MOTION_INT] = "motion_int",
|
||||
[PMUX_DRVGRP_NFC_EN] = "nfc_en",
|
||||
[PMUX_DRVGRP_NFC_INT] = "nfc_int",
|
||||
[PMUX_DRVGRP_PEX_L0_CLKREQ_N] = "pex_l0_clkreq_n",
|
||||
[PMUX_DRVGRP_PEX_L0_RST_N] = "pex_l0_rst_n",
|
||||
[PMUX_DRVGRP_PEX_L1_CLKREQ_N] = "pex_l1_clkreq_n",
|
||||
[PMUX_DRVGRP_PEX_L1_RST_N] = "pex_l1_rst_n",
|
||||
[PMUX_DRVGRP_PEX_WAKE_N] = "pex_wake_n",
|
||||
[PMUX_DRVGRP_PWR_I2C_SCL] = "pwr_i2c_scl",
|
||||
[PMUX_DRVGRP_PWR_I2C_SDA] = "pwr_i2c_sda",
|
||||
[PMUX_DRVGRP_PWR_INT_N] = "pwr_int_n",
|
||||
[PMUX_DRVGRP_QSPI_SCK] = "qspi_sck",
|
||||
[PMUX_DRVGRP_SATA_LED_ACTIVE] = "sata_led_active",
|
||||
[PMUX_DRVGRP_SDMMC1] = "sdmmc1",
|
||||
[PMUX_DRVGRP_SDMMC2] = "sdmmc2",
|
||||
[PMUX_DRVGRP_SDMMC3] = "sdmmc3",
|
||||
[PMUX_DRVGRP_SDMMC4] = "sdmmc4",
|
||||
[PMUX_DRVGRP_SHUTDOWN] = "shutdown",
|
||||
[PMUX_DRVGRP_SPDIF_IN] = "spdif_in",
|
||||
[PMUX_DRVGRP_SPDIF_OUT] = "spdif_out",
|
||||
[PMUX_DRVGRP_SPI1_CS0] = "spi1_cs0",
|
||||
[PMUX_DRVGRP_SPI1_CS1] = "spi1_cs1",
|
||||
[PMUX_DRVGRP_SPI1_MISO] = "spi1_miso",
|
||||
[PMUX_DRVGRP_SPI1_MOSI] = "spi1_mosi",
|
||||
[PMUX_DRVGRP_SPI1_SCK] = "spi1_sck",
|
||||
[PMUX_DRVGRP_SPI2_CS0] = "spi2_cs0",
|
||||
[PMUX_DRVGRP_SPI2_CS1] = "spi2_cs1",
|
||||
[PMUX_DRVGRP_SPI2_MISO] = "spi2_miso",
|
||||
[PMUX_DRVGRP_SPI2_MOSI] = "spi2_mosi",
|
||||
[PMUX_DRVGRP_SPI2_SCK] = "spi2_sck",
|
||||
[PMUX_DRVGRP_SPI4_CS0] = "spi4_cs0",
|
||||
[PMUX_DRVGRP_SPI4_MISO] = "spi4_miso",
|
||||
[PMUX_DRVGRP_SPI4_MOSI] = "spi4_mosi",
|
||||
[PMUX_DRVGRP_SPI4_SCK] = "spi4_sck",
|
||||
[PMUX_DRVGRP_TEMP_ALERT] = "temp_alert",
|
||||
[PMUX_DRVGRP_TOUCH_CLK] = "touch_clk",
|
||||
[PMUX_DRVGRP_TOUCH_INT] = "touch_int",
|
||||
[PMUX_DRVGRP_TOUCH_RST] = "touch_rst",
|
||||
[PMUX_DRVGRP_UART1_CTS] = "uart1_cts",
|
||||
[PMUX_DRVGRP_UART1_RTS] = "uart1_rts",
|
||||
[PMUX_DRVGRP_UART1_RX] = "uart1_rx",
|
||||
[PMUX_DRVGRP_UART1_TX] = "uart1_tx",
|
||||
[PMUX_DRVGRP_UART2_CTS] = "uart2_cts",
|
||||
[PMUX_DRVGRP_UART2_RTS] = "uart2_rts",
|
||||
[PMUX_DRVGRP_UART2_RX] = "uart2_rx",
|
||||
[PMUX_DRVGRP_UART2_TX] = "uart2_tx",
|
||||
[PMUX_DRVGRP_UART3_CTS] = "uart3_cts",
|
||||
[PMUX_DRVGRP_UART3_RTS] = "uart3_rts",
|
||||
[PMUX_DRVGRP_UART3_RX] = "uart3_rx",
|
||||
[PMUX_DRVGRP_UART3_TX] = "uart3_tx",
|
||||
[PMUX_DRVGRP_UART4_CTS] = "uart4_cts",
|
||||
[PMUX_DRVGRP_UART4_RTS] = "uart4_rts",
|
||||
[PMUX_DRVGRP_UART4_RX] = "uart4_rx",
|
||||
[PMUX_DRVGRP_UART4_TX] = "uart4_tx",
|
||||
[PMUX_DRVGRP_USB_VBUS_EN0] = "usb_vbus_en0",
|
||||
[PMUX_DRVGRP_USB_VBUS_EN1] = "usb_vbus_en1",
|
||||
[PMUX_DRVGRP_WIFI_EN] = "wifi_en",
|
||||
[PMUX_DRVGRP_WIFI_RST] = "wifi_rst",
|
||||
[PMUX_DRVGRP_WIFI_WAKE_AP] = "wifi_wake_ap",
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_func[] = {
|
||||
[PMUX_FUNC_DEFAULT] = "default",
|
||||
[PMUX_FUNC_AUD] = "aud",
|
||||
[PMUX_FUNC_BCL] = "bcl",
|
||||
[PMUX_FUNC_BLINK] = "blink",
|
||||
[PMUX_FUNC_CCLA] = "ccla",
|
||||
[PMUX_FUNC_CEC] = "cec",
|
||||
[PMUX_FUNC_CLDVFS] = "cldvfs",
|
||||
[PMUX_FUNC_CLK] = "clk",
|
||||
[PMUX_FUNC_CORE] = "core",
|
||||
[PMUX_FUNC_CPU] = "cpu",
|
||||
[PMUX_FUNC_DISPLAYA] = "displaya",
|
||||
[PMUX_FUNC_DISPLAYB] = "displayb",
|
||||
[PMUX_FUNC_DMIC1] = "dmic1",
|
||||
[PMUX_FUNC_DMIC2] = "dmic2",
|
||||
[PMUX_FUNC_DMIC3] = "dmic3",
|
||||
[PMUX_FUNC_DP] = "dp",
|
||||
[PMUX_FUNC_DTV] = "dtv",
|
||||
[PMUX_FUNC_EXTPERIPH3] = "extperiph3",
|
||||
[PMUX_FUNC_I2C1] = "i2c1",
|
||||
[PMUX_FUNC_I2C2] = "i2c2",
|
||||
[PMUX_FUNC_I2C3] = "i2c3",
|
||||
[PMUX_FUNC_I2CPMU] = "i2cpmu",
|
||||
[PMUX_FUNC_I2CVI] = "i2cvi",
|
||||
[PMUX_FUNC_I2S1] = "i2s1",
|
||||
[PMUX_FUNC_I2S2] = "i2s2",
|
||||
[PMUX_FUNC_I2S3] = "i2s3",
|
||||
[PMUX_FUNC_I2S4A] = "i2s4a",
|
||||
[PMUX_FUNC_I2S4B] = "i2s4b",
|
||||
[PMUX_FUNC_I2S5A] = "i2s5a",
|
||||
[PMUX_FUNC_I2S5B] = "i2s5b",
|
||||
[PMUX_FUNC_IQC0] = "iqc0",
|
||||
[PMUX_FUNC_IQC1] = "iqc1",
|
||||
[PMUX_FUNC_JTAG] = "jtag",
|
||||
[PMUX_FUNC_PE] = "pe",
|
||||
[PMUX_FUNC_PE0] = "pe0",
|
||||
[PMUX_FUNC_PE1] = "pe1",
|
||||
[PMUX_FUNC_PMI] = "pmi",
|
||||
[PMUX_FUNC_PWM0] = "pwm0",
|
||||
[PMUX_FUNC_PWM1] = "pwm1",
|
||||
[PMUX_FUNC_PWM2] = "pwm2",
|
||||
[PMUX_FUNC_PWM3] = "pwm3",
|
||||
[PMUX_FUNC_QSPI] = "qspi",
|
||||
[PMUX_FUNC_SATA] = "sata",
|
||||
[PMUX_FUNC_SDMMC1] = "sdmmc1",
|
||||
[PMUX_FUNC_SDMMC3] = "sdmmc3",
|
||||
[PMUX_FUNC_SHUTDOWN] = "shutdown",
|
||||
[PMUX_FUNC_SOC] = "soc",
|
||||
[PMUX_FUNC_SOR0] = "sor0",
|
||||
[PMUX_FUNC_SOR1] = "sor1",
|
||||
[PMUX_FUNC_SPDIF] = "spdif",
|
||||
[PMUX_FUNC_SPI1] = "spi1",
|
||||
[PMUX_FUNC_SPI2] = "spi2",
|
||||
[PMUX_FUNC_SPI3] = "spi3",
|
||||
[PMUX_FUNC_SPI4] = "spi4",
|
||||
[PMUX_FUNC_SYS] = "sys",
|
||||
[PMUX_FUNC_TOUCH] = "touch",
|
||||
[PMUX_FUNC_UART] = "uart",
|
||||
[PMUX_FUNC_UARTA] = "uarta",
|
||||
[PMUX_FUNC_UARTB] = "uartb",
|
||||
[PMUX_FUNC_UARTC] = "uartc",
|
||||
[PMUX_FUNC_UARTD] = "uartd",
|
||||
[PMUX_FUNC_USB] = "usb",
|
||||
[PMUX_FUNC_VGP1] = "vgp1",
|
||||
[PMUX_FUNC_VGP2] = "vgp2",
|
||||
[PMUX_FUNC_VGP3] = "vgp3",
|
||||
[PMUX_FUNC_VGP4] = "vgp4",
|
||||
[PMUX_FUNC_VGP5] = "vgp5",
|
||||
[PMUX_FUNC_VGP6] = "vgp6",
|
||||
[PMUX_FUNC_VIMCLK] = "vimclk",
|
||||
[PMUX_FUNC_VIMCLK2] = "vimclk2",
|
||||
[PMUX_FUNC_RSVD0] = "rsvd0",
|
||||
[PMUX_FUNC_RSVD1] = "rsvd1",
|
||||
[PMUX_FUNC_RSVD2] = "rsvd2",
|
||||
[PMUX_FUNC_RSVD3] = "rsvd3",
|
||||
};
|
||||
|
||||
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4
|
||||
#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
|
||||
#define TEGRA_PMX_SOC_HAS_DRVGRPS
|
||||
|
||||
@ -23,6 +23,7 @@ enum clock_id {
|
||||
CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
|
||||
CLOCK_ID_EPCI,
|
||||
CLOCK_ID_SFROM32KHZ,
|
||||
CLOCK_ID_DISPLAY2,
|
||||
|
||||
/* These are the base clocks (inputs to the Tegra SOC) */
|
||||
CLOCK_ID_32KHZ,
|
||||
@ -30,7 +31,6 @@ enum clock_id {
|
||||
CLOCK_ID_CLK_M,
|
||||
|
||||
CLOCK_ID_COUNT, /* number of PLLs */
|
||||
CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */
|
||||
CLOCK_ID_NONE = -1,
|
||||
};
|
||||
|
||||
|
||||
@ -390,6 +390,387 @@ enum pmux_func {
|
||||
PMUX_FUNC_COUNT,
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_pingrp[] = {
|
||||
[PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1",
|
||||
[PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2",
|
||||
[PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3",
|
||||
[PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4",
|
||||
[PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5",
|
||||
[PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6",
|
||||
[PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7",
|
||||
[PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0",
|
||||
[PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0",
|
||||
[PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1",
|
||||
[PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2",
|
||||
[PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3",
|
||||
[PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0",
|
||||
[PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1",
|
||||
[PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2",
|
||||
[PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3",
|
||||
[PMUX_PINGRP_PV0] = "pv0",
|
||||
[PMUX_PINGRP_PV1] = "pv1",
|
||||
[PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0",
|
||||
[PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1",
|
||||
[PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4",
|
||||
[PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5",
|
||||
[PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6",
|
||||
[PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7",
|
||||
[PMUX_PINGRP_PV2] = "pv2",
|
||||
[PMUX_PINGRP_PV3] = "pv3",
|
||||
[PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5",
|
||||
[PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5",
|
||||
[PMUX_PINGRP_LCD_PWR1_PC1] = "lcd_pwr1_pc1",
|
||||
[PMUX_PINGRP_LCD_PWR2_PC6] = "lcd_pwr2_pc6",
|
||||
[PMUX_PINGRP_LCD_SDIN_PZ2] = "lcd_sdin_pz2",
|
||||
[PMUX_PINGRP_LCD_SDOUT_PN5] = "lcd_sdout_pn5",
|
||||
[PMUX_PINGRP_LCD_WR_N_PZ3] = "lcd_wr_n_pz3",
|
||||
[PMUX_PINGRP_LCD_CS0_N_PN4] = "lcd_cs0_n_pn4",
|
||||
[PMUX_PINGRP_LCD_DC0_PN6] = "lcd_dc0_pn6",
|
||||
[PMUX_PINGRP_LCD_SCK_PZ4] = "lcd_sck_pz4",
|
||||
[PMUX_PINGRP_LCD_PWR0_PB2] = "lcd_pwr0_pb2",
|
||||
[PMUX_PINGRP_LCD_PCLK_PB3] = "lcd_pclk_pb3",
|
||||
[PMUX_PINGRP_LCD_DE_PJ1] = "lcd_de_pj1",
|
||||
[PMUX_PINGRP_LCD_HSYNC_PJ3] = "lcd_hsync_pj3",
|
||||
[PMUX_PINGRP_LCD_VSYNC_PJ4] = "lcd_vsync_pj4",
|
||||
[PMUX_PINGRP_LCD_D0_PE0] = "lcd_d0_pe0",
|
||||
[PMUX_PINGRP_LCD_D1_PE1] = "lcd_d1_pe1",
|
||||
[PMUX_PINGRP_LCD_D2_PE2] = "lcd_d2_pe2",
|
||||
[PMUX_PINGRP_LCD_D3_PE3] = "lcd_d3_pe3",
|
||||
[PMUX_PINGRP_LCD_D4_PE4] = "lcd_d4_pe4",
|
||||
[PMUX_PINGRP_LCD_D5_PE5] = "lcd_d5_pe5",
|
||||
[PMUX_PINGRP_LCD_D6_PE6] = "lcd_d6_pe6",
|
||||
[PMUX_PINGRP_LCD_D7_PE7] = "lcd_d7_pe7",
|
||||
[PMUX_PINGRP_LCD_D8_PF0] = "lcd_d8_pf0",
|
||||
[PMUX_PINGRP_LCD_D9_PF1] = "lcd_d9_pf1",
|
||||
[PMUX_PINGRP_LCD_D10_PF2] = "lcd_d10_pf2",
|
||||
[PMUX_PINGRP_LCD_D11_PF3] = "lcd_d11_pf3",
|
||||
[PMUX_PINGRP_LCD_D12_PF4] = "lcd_d12_pf4",
|
||||
[PMUX_PINGRP_LCD_D13_PF5] = "lcd_d13_pf5",
|
||||
[PMUX_PINGRP_LCD_D14_PF6] = "lcd_d14_pf6",
|
||||
[PMUX_PINGRP_LCD_D15_PF7] = "lcd_d15_pf7",
|
||||
[PMUX_PINGRP_LCD_D16_PM0] = "lcd_d16_pm0",
|
||||
[PMUX_PINGRP_LCD_D17_PM1] = "lcd_d17_pm1",
|
||||
[PMUX_PINGRP_LCD_D18_PM2] = "lcd_d18_pm2",
|
||||
[PMUX_PINGRP_LCD_D19_PM3] = "lcd_d19_pm3",
|
||||
[PMUX_PINGRP_LCD_D20_PM4] = "lcd_d20_pm4",
|
||||
[PMUX_PINGRP_LCD_D21_PM5] = "lcd_d21_pm5",
|
||||
[PMUX_PINGRP_LCD_D22_PM6] = "lcd_d22_pm6",
|
||||
[PMUX_PINGRP_LCD_D23_PM7] = "lcd_d23_pm7",
|
||||
[PMUX_PINGRP_LCD_CS1_N_PW0] = "lcd_cs1_n_pw0",
|
||||
[PMUX_PINGRP_LCD_M1_PW1] = "lcd_m1_pw1",
|
||||
[PMUX_PINGRP_LCD_DC1_PD2] = "lcd_dc1_pd2",
|
||||
[PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7",
|
||||
[PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4",
|
||||
[PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5",
|
||||
[PMUX_PINGRP_CRT_HSYNC_PV6] = "crt_hsync_pv6",
|
||||
[PMUX_PINGRP_CRT_VSYNC_PV7] = "crt_vsync_pv7",
|
||||
[PMUX_PINGRP_VI_D0_PT4] = "vi_d0_pt4",
|
||||
[PMUX_PINGRP_VI_D1_PD5] = "vi_d1_pd5",
|
||||
[PMUX_PINGRP_VI_D2_PL0] = "vi_d2_pl0",
|
||||
[PMUX_PINGRP_VI_D3_PL1] = "vi_d3_pl1",
|
||||
[PMUX_PINGRP_VI_D4_PL2] = "vi_d4_pl2",
|
||||
[PMUX_PINGRP_VI_D5_PL3] = "vi_d5_pl3",
|
||||
[PMUX_PINGRP_VI_D6_PL4] = "vi_d6_pl4",
|
||||
[PMUX_PINGRP_VI_D7_PL5] = "vi_d7_pl5",
|
||||
[PMUX_PINGRP_VI_D8_PL6] = "vi_d8_pl6",
|
||||
[PMUX_PINGRP_VI_D9_PL7] = "vi_d9_pl7",
|
||||
[PMUX_PINGRP_VI_D10_PT2] = "vi_d10_pt2",
|
||||
[PMUX_PINGRP_VI_D11_PT3] = "vi_d11_pt3",
|
||||
[PMUX_PINGRP_VI_PCLK_PT0] = "vi_pclk_pt0",
|
||||
[PMUX_PINGRP_VI_MCLK_PT1] = "vi_mclk_pt1",
|
||||
[PMUX_PINGRP_VI_VSYNC_PD6] = "vi_vsync_pd6",
|
||||
[PMUX_PINGRP_VI_HSYNC_PD7] = "vi_hsync_pd7",
|
||||
[PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3",
|
||||
[PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2",
|
||||
[PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6",
|
||||
[PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5",
|
||||
[PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6",
|
||||
[PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7",
|
||||
[PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1",
|
||||
[PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0",
|
||||
[PMUX_PINGRP_PU0] = "pu0",
|
||||
[PMUX_PINGRP_PU1] = "pu1",
|
||||
[PMUX_PINGRP_PU2] = "pu2",
|
||||
[PMUX_PINGRP_PU3] = "pu3",
|
||||
[PMUX_PINGRP_PU4] = "pu4",
|
||||
[PMUX_PINGRP_PU5] = "pu5",
|
||||
[PMUX_PINGRP_PU6] = "pu6",
|
||||
[PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5",
|
||||
[PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4",
|
||||
[PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4",
|
||||
[PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5",
|
||||
[PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6",
|
||||
[PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7",
|
||||
[PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0",
|
||||
[PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1",
|
||||
[PMUX_PINGRP_GMI_WP_N_PC7] = "gmi_wp_n_pc7",
|
||||
[PMUX_PINGRP_GMI_IORDY_PI5] = "gmi_iordy_pi5",
|
||||
[PMUX_PINGRP_GMI_WAIT_PI7] = "gmi_wait_pi7",
|
||||
[PMUX_PINGRP_GMI_ADV_N_PK0] = "gmi_adv_n_pk0",
|
||||
[PMUX_PINGRP_GMI_CLK_PK1] = "gmi_clk_pk1",
|
||||
[PMUX_PINGRP_GMI_CS0_N_PJ0] = "gmi_cs0_n_pj0",
|
||||
[PMUX_PINGRP_GMI_CS1_N_PJ2] = "gmi_cs1_n_pj2",
|
||||
[PMUX_PINGRP_GMI_CS2_N_PK3] = "gmi_cs2_n_pk3",
|
||||
[PMUX_PINGRP_GMI_CS3_N_PK4] = "gmi_cs3_n_pk4",
|
||||
[PMUX_PINGRP_GMI_CS4_N_PK2] = "gmi_cs4_n_pk2",
|
||||
[PMUX_PINGRP_GMI_CS6_N_PI3] = "gmi_cs6_n_pi3",
|
||||
[PMUX_PINGRP_GMI_CS7_N_PI6] = "gmi_cs7_n_pi6",
|
||||
[PMUX_PINGRP_GMI_AD0_PG0] = "gmi_ad0_pg0",
|
||||
[PMUX_PINGRP_GMI_AD1_PG1] = "gmi_ad1_pg1",
|
||||
[PMUX_PINGRP_GMI_AD2_PG2] = "gmi_ad2_pg2",
|
||||
[PMUX_PINGRP_GMI_AD3_PG3] = "gmi_ad3_pg3",
|
||||
[PMUX_PINGRP_GMI_AD4_PG4] = "gmi_ad4_pg4",
|
||||
[PMUX_PINGRP_GMI_AD5_PG5] = "gmi_ad5_pg5",
|
||||
[PMUX_PINGRP_GMI_AD6_PG6] = "gmi_ad6_pg6",
|
||||
[PMUX_PINGRP_GMI_AD7_PG7] = "gmi_ad7_pg7",
|
||||
[PMUX_PINGRP_GMI_AD8_PH0] = "gmi_ad8_ph0",
|
||||
[PMUX_PINGRP_GMI_AD9_PH1] = "gmi_ad9_ph1",
|
||||
[PMUX_PINGRP_GMI_AD10_PH2] = "gmi_ad10_ph2",
|
||||
[PMUX_PINGRP_GMI_AD11_PH3] = "gmi_ad11_ph3",
|
||||
[PMUX_PINGRP_GMI_AD12_PH4] = "gmi_ad12_ph4",
|
||||
[PMUX_PINGRP_GMI_AD13_PH5] = "gmi_ad13_ph5",
|
||||
[PMUX_PINGRP_GMI_AD14_PH6] = "gmi_ad14_ph6",
|
||||
[PMUX_PINGRP_GMI_AD15_PH7] = "gmi_ad15_ph7",
|
||||
[PMUX_PINGRP_GMI_A16_PJ7] = "gmi_a16_pj7",
|
||||
[PMUX_PINGRP_GMI_A17_PB0] = "gmi_a17_pb0",
|
||||
[PMUX_PINGRP_GMI_A18_PB1] = "gmi_a18_pb1",
|
||||
[PMUX_PINGRP_GMI_A19_PK7] = "gmi_a19_pk7",
|
||||
[PMUX_PINGRP_GMI_WR_N_PI0] = "gmi_wr_n_pi0",
|
||||
[PMUX_PINGRP_GMI_OE_N_PI1] = "gmi_oe_n_pi1",
|
||||
[PMUX_PINGRP_GMI_DQS_PI2] = "gmi_dqs_pi2",
|
||||
[PMUX_PINGRP_GMI_RST_N_PI4] = "gmi_rst_n_pi4",
|
||||
[PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5",
|
||||
[PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6",
|
||||
[PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4",
|
||||
[PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7",
|
||||
[PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0",
|
||||
[PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1",
|
||||
[PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2",
|
||||
[PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3",
|
||||
[PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4",
|
||||
[PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5",
|
||||
[PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6",
|
||||
[PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7",
|
||||
[PMUX_PINGRP_SDMMC4_RST_N_PCC3] = "sdmmc4_rst_n_pcc3",
|
||||
[PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0",
|
||||
[PMUX_PINGRP_PCC1] = "pcc1",
|
||||
[PMUX_PINGRP_PBB0] = "pbb0",
|
||||
[PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1",
|
||||
[PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2",
|
||||
[PMUX_PINGRP_PBB3] = "pbb3",
|
||||
[PMUX_PINGRP_PBB4] = "pbb4",
|
||||
[PMUX_PINGRP_PBB5] = "pbb5",
|
||||
[PMUX_PINGRP_PBB6] = "pbb6",
|
||||
[PMUX_PINGRP_PBB7] = "pbb7",
|
||||
[PMUX_PINGRP_PCC2] = "pcc2",
|
||||
[PMUX_PINGRP_JTAG_RTCK_PU7] = "jtag_rtck_pu7",
|
||||
[PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6",
|
||||
[PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7",
|
||||
[PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0",
|
||||
[PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1",
|
||||
[PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2",
|
||||
[PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3",
|
||||
[PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4",
|
||||
[PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5",
|
||||
[PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6",
|
||||
[PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7",
|
||||
[PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0",
|
||||
[PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1",
|
||||
[PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2",
|
||||
[PMUX_PINGRP_KB_ROW11_PS3] = "kb_row11_ps3",
|
||||
[PMUX_PINGRP_KB_ROW12_PS4] = "kb_row12_ps4",
|
||||
[PMUX_PINGRP_KB_ROW13_PS5] = "kb_row13_ps5",
|
||||
[PMUX_PINGRP_KB_ROW14_PS6] = "kb_row14_ps6",
|
||||
[PMUX_PINGRP_KB_ROW15_PS7] = "kb_row15_ps7",
|
||||
[PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0",
|
||||
[PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1",
|
||||
[PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2",
|
||||
[PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3",
|
||||
[PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4",
|
||||
[PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5",
|
||||
[PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6",
|
||||
[PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7",
|
||||
[PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0",
|
||||
[PMUX_PINGRP_SYS_CLK_REQ_PZ5] = "sys_clk_req_pz5",
|
||||
[PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req",
|
||||
[PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req",
|
||||
[PMUX_PINGRP_PWR_INT_N] = "pwr_int_n",
|
||||
[PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in",
|
||||
[PMUX_PINGRP_OWR] = "owr",
|
||||
[PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0",
|
||||
[PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1",
|
||||
[PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2",
|
||||
[PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3",
|
||||
[PMUX_PINGRP_CLK1_REQ_PEE2] = "clk1_req_pee2",
|
||||
[PMUX_PINGRP_CLK1_OUT_PW4] = "clk1_out_pw4",
|
||||
[PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6",
|
||||
[PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5",
|
||||
[PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2",
|
||||
[PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4",
|
||||
[PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5",
|
||||
[PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3",
|
||||
[PMUX_PINGRP_SPI2_MOSI_PX0] = "spi2_mosi_px0",
|
||||
[PMUX_PINGRP_SPI2_MISO_PX1] = "spi2_miso_px1",
|
||||
[PMUX_PINGRP_SPI2_CS0_N_PX3] = "spi2_cs0_n_px3",
|
||||
[PMUX_PINGRP_SPI2_SCK_PX2] = "spi2_sck_px2",
|
||||
[PMUX_PINGRP_SPI1_MOSI_PX4] = "spi1_mosi_px4",
|
||||
[PMUX_PINGRP_SPI1_SCK_PX5] = "spi1_sck_px5",
|
||||
[PMUX_PINGRP_SPI1_CS0_N_PX6] = "spi1_cs0_n_px6",
|
||||
[PMUX_PINGRP_SPI1_MISO_PX7] = "spi1_miso_px7",
|
||||
[PMUX_PINGRP_SPI2_CS1_N_PW2] = "spi2_cs1_n_pw2",
|
||||
[PMUX_PINGRP_SPI2_CS2_N_PW3] = "spi2_cs2_n_pw3",
|
||||
[PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6",
|
||||
[PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7",
|
||||
[PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7",
|
||||
[PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6",
|
||||
[PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5",
|
||||
[PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4",
|
||||
[PMUX_PINGRP_SDMMC3_DAT4_PD1] = "sdmmc3_dat4_pd1",
|
||||
[PMUX_PINGRP_SDMMC3_DAT5_PD0] = "sdmmc3_dat5_pd0",
|
||||
[PMUX_PINGRP_SDMMC3_DAT6_PD3] = "sdmmc3_dat6_pd3",
|
||||
[PMUX_PINGRP_SDMMC3_DAT7_PD4] = "sdmmc3_dat7_pd4",
|
||||
[PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0] = "pex_l0_prsnt_n_pdd0",
|
||||
[PMUX_PINGRP_PEX_L0_RST_N_PDD1] = "pex_l0_rst_n_pdd1",
|
||||
[PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2] = "pex_l0_clkreq_n_pdd2",
|
||||
[PMUX_PINGRP_PEX_WAKE_N_PDD3] = "pex_wake_n_pdd3",
|
||||
[PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4] = "pex_l1_prsnt_n_pdd4",
|
||||
[PMUX_PINGRP_PEX_L1_RST_N_PDD5] = "pex_l1_rst_n_pdd5",
|
||||
[PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6] = "pex_l1_clkreq_n_pdd6",
|
||||
[PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7] = "pex_l2_prsnt_n_pdd7",
|
||||
[PMUX_PINGRP_PEX_L2_RST_N_PCC6] = "pex_l2_rst_n_pcc6",
|
||||
[PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7] = "pex_l2_clkreq_n_pcc7",
|
||||
[PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3",
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_drvgrp[] = {
|
||||
[PMUX_DRVGRP_AO1] = "drive_ao1",
|
||||
[PMUX_DRVGRP_AO2] = "drive_ao2",
|
||||
[PMUX_DRVGRP_AT1] = "drive_at1",
|
||||
[PMUX_DRVGRP_AT2] = "drive_at2",
|
||||
[PMUX_DRVGRP_AT3] = "drive_at3",
|
||||
[PMUX_DRVGRP_AT4] = "drive_at4",
|
||||
[PMUX_DRVGRP_AT5] = "drive_at5",
|
||||
[PMUX_DRVGRP_CDEV1] = "drive_cdev1",
|
||||
[PMUX_DRVGRP_CDEV2] = "drive_cdev2",
|
||||
[PMUX_DRVGRP_CSUS] = "drive_csus",
|
||||
[PMUX_DRVGRP_DAP1] = "drive_dap1",
|
||||
[PMUX_DRVGRP_DAP2] = "drive_dap2",
|
||||
[PMUX_DRVGRP_DAP3] = "drive_dap3",
|
||||
[PMUX_DRVGRP_DAP4] = "drive_dap4",
|
||||
[PMUX_DRVGRP_DBG] = "drive_dbg",
|
||||
[PMUX_DRVGRP_LCD1] = "drive_lcd1",
|
||||
[PMUX_DRVGRP_LCD2] = "drive_lcd2",
|
||||
[PMUX_DRVGRP_SDIO2] = "drive_sdio2",
|
||||
[PMUX_DRVGRP_SDIO3] = "drive_sdio3",
|
||||
[PMUX_DRVGRP_SPI] = "drive_spi",
|
||||
[PMUX_DRVGRP_UAA] = "drive_uaa",
|
||||
[PMUX_DRVGRP_UAB] = "drive_uab",
|
||||
[PMUX_DRVGRP_UART2] = "drive_uart2",
|
||||
[PMUX_DRVGRP_UART3] = "drive_uart3",
|
||||
[PMUX_DRVGRP_VI1] = "drive_vi1",
|
||||
[PMUX_DRVGRP_SDIO1] = "drive_sdio1",
|
||||
[PMUX_DRVGRP_CRT] = "drive_crt",
|
||||
[PMUX_DRVGRP_DDC] = "drive_ddc",
|
||||
[PMUX_DRVGRP_GMA] = "drive_gma",
|
||||
[PMUX_DRVGRP_GMB] = "drive_gmb",
|
||||
[PMUX_DRVGRP_GMC] = "drive_gmc",
|
||||
[PMUX_DRVGRP_GMD] = "drive_gmd",
|
||||
[PMUX_DRVGRP_GME] = "drive_gme",
|
||||
[PMUX_DRVGRP_GMF] = "drive_gmf",
|
||||
[PMUX_DRVGRP_GMG] = "drive_gmg",
|
||||
[PMUX_DRVGRP_GMH] = "drive_gmh",
|
||||
[PMUX_DRVGRP_OWR] = "drive_owr",
|
||||
[PMUX_DRVGRP_UDA] = "drive_uda",
|
||||
[PMUX_DRVGRP_GPV] = "drive_gpv",
|
||||
[PMUX_DRVGRP_DEV3] = "drive_dev3",
|
||||
[PMUX_DRVGRP_CEC] = "drive_cec",
|
||||
};
|
||||
|
||||
static const char * const tegra_pinctrl_to_func[] = {
|
||||
[PMUX_FUNC_DEFAULT] = "default",
|
||||
[PMUX_FUNC_BLINK] = "blink",
|
||||
[PMUX_FUNC_CEC] = "cec",
|
||||
[PMUX_FUNC_CLK_12M_OUT] = "clk_12m_out",
|
||||
[PMUX_FUNC_CLK_32K_IN] = "clk_32k_in",
|
||||
[PMUX_FUNC_CORE_PWR_REQ] = "core_pwr_req",
|
||||
[PMUX_FUNC_CPU_PWR_REQ] = "cpu_pwr_req",
|
||||
[PMUX_FUNC_CRT] = "crt",
|
||||
[PMUX_FUNC_DAP] = "dap",
|
||||
[PMUX_FUNC_DDR] = "ddr",
|
||||
[PMUX_FUNC_DEV3] = "dev3",
|
||||
[PMUX_FUNC_DISPLAYA] = "displaya",
|
||||
[PMUX_FUNC_DISPLAYB] = "displayb",
|
||||
[PMUX_FUNC_DTV] = "dtv",
|
||||
[PMUX_FUNC_EXTPERIPH1] = "extperiph1",
|
||||
[PMUX_FUNC_EXTPERIPH2] = "extperiph2",
|
||||
[PMUX_FUNC_EXTPERIPH3] = "extperiph3",
|
||||
[PMUX_FUNC_GMI] = "gmi",
|
||||
[PMUX_FUNC_GMI_ALT] = "gmi_alt",
|
||||
[PMUX_FUNC_HDA] = "hda",
|
||||
[PMUX_FUNC_HDCP] = "hdcp",
|
||||
[PMUX_FUNC_HDMI] = "hdmi",
|
||||
[PMUX_FUNC_HSI] = "hsi",
|
||||
[PMUX_FUNC_I2C1] = "i2c1",
|
||||
[PMUX_FUNC_I2C2] = "i2c2",
|
||||
[PMUX_FUNC_I2C3] = "i2c3",
|
||||
[PMUX_FUNC_I2C4] = "i2c4",
|
||||
[PMUX_FUNC_I2CPWR] = "i2cpwr",
|
||||
[PMUX_FUNC_I2S0] = "i2s0",
|
||||
[PMUX_FUNC_I2S1] = "i2s1",
|
||||
[PMUX_FUNC_I2S2] = "i2s2",
|
||||
[PMUX_FUNC_I2S3] = "i2s3",
|
||||
[PMUX_FUNC_I2S4] = "i2s4",
|
||||
[PMUX_FUNC_INVALID] = "invalid",
|
||||
[PMUX_FUNC_KBC] = "kbc",
|
||||
[PMUX_FUNC_MIO] = "mio",
|
||||
[PMUX_FUNC_NAND] = "nand",
|
||||
[PMUX_FUNC_NAND_ALT] = "nand_alt",
|
||||
[PMUX_FUNC_OWR] = "owr",
|
||||
[PMUX_FUNC_PCIE] = "pcie",
|
||||
[PMUX_FUNC_PWM0] = "pwm0",
|
||||
[PMUX_FUNC_PWM1] = "pwm1",
|
||||
[PMUX_FUNC_PWM2] = "pwm2",
|
||||
[PMUX_FUNC_PWM3] = "pwm3",
|
||||
[PMUX_FUNC_PWR_INT_N] = "pwr_int_n",
|
||||
[PMUX_FUNC_RTCK] = "rtck",
|
||||
[PMUX_FUNC_SATA] = "sata",
|
||||
[PMUX_FUNC_SDMMC1] = "sdmmc1",
|
||||
[PMUX_FUNC_SDMMC2] = "sdmmc2",
|
||||
[PMUX_FUNC_SDMMC3] = "sdmmc3",
|
||||
[PMUX_FUNC_SDMMC4] = "sdmmc4",
|
||||
[PMUX_FUNC_SPDIF] = "spdif",
|
||||
[PMUX_FUNC_SPI1] = "spi1",
|
||||
[PMUX_FUNC_SPI2] = "spi2",
|
||||
[PMUX_FUNC_SPI2_ALT] = "spi2_alt",
|
||||
[PMUX_FUNC_SPI3] = "spi3",
|
||||
[PMUX_FUNC_SPI4] = "spi4",
|
||||
[PMUX_FUNC_SPI5] = "spi5",
|
||||
[PMUX_FUNC_SPI6] = "spi6",
|
||||
[PMUX_FUNC_SYSCLK] = "sysclk",
|
||||
[PMUX_FUNC_TEST] = "test",
|
||||
[PMUX_FUNC_TRACE] = "trace",
|
||||
[PMUX_FUNC_UARTA] = "uarta",
|
||||
[PMUX_FUNC_UARTB] = "uartb",
|
||||
[PMUX_FUNC_UARTC] = "uartc",
|
||||
[PMUX_FUNC_UARTD] = "uartd",
|
||||
[PMUX_FUNC_UARTE] = "uarte",
|
||||
[PMUX_FUNC_ULPI] = "ulpi",
|
||||
[PMUX_FUNC_VGP1] = "vgp1",
|
||||
[PMUX_FUNC_VGP2] = "vgp2",
|
||||
[PMUX_FUNC_VGP3] = "vgp3",
|
||||
[PMUX_FUNC_VGP4] = "vgp4",
|
||||
[PMUX_FUNC_VGP5] = "vgp5",
|
||||
[PMUX_FUNC_VGP6] = "vgp6",
|
||||
[PMUX_FUNC_VI] = "vi",
|
||||
[PMUX_FUNC_VI_ALT1] = "vi_alt1",
|
||||
[PMUX_FUNC_VI_ALT2] = "vi_alt2",
|
||||
[PMUX_FUNC_VI_ALT3] = "vi_alt3",
|
||||
[PMUX_FUNC_RSVD1] = "rsvd1",
|
||||
[PMUX_FUNC_RSVD2] = "rsvd2",
|
||||
[PMUX_FUNC_RSVD3] = "rsvd3",
|
||||
[PMUX_FUNC_RSVD4] = "rsvd4",
|
||||
};
|
||||
|
||||
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
|
||||
#define TEGRA_PMX_SOC_HAS_DRVGRPS
|
||||
#define TEGRA_PMX_GRPS_HAVE_LPMD
|
||||
|
||||
@ -33,9 +33,6 @@ config TEGRA_IVC
|
||||
config TEGRA_MC
|
||||
bool
|
||||
|
||||
config TEGRA_PINCTRL
|
||||
bool
|
||||
|
||||
config TEGRA_PMC
|
||||
bool
|
||||
|
||||
@ -61,7 +58,6 @@ config TEGRA_COMMON
|
||||
select OF_CONTROL
|
||||
select SPI
|
||||
select SYSRESET
|
||||
select SPL_SYSRESET if SPL
|
||||
select SYSRESET_TEGRA
|
||||
imply CMD_DM
|
||||
imply CRC32_VERIFY
|
||||
@ -76,9 +72,15 @@ config TEGRA_ARMV7_COMMON
|
||||
bool "Tegra 32-bit common options"
|
||||
select BINMAN
|
||||
select CPU_V7A
|
||||
select PINCTRL
|
||||
select PINCTRL_TEGRA
|
||||
select SPL
|
||||
select SPL_BOARD_INIT if SPL
|
||||
select SPL_DM if SPL
|
||||
select SPL_PINCTRL if SPL
|
||||
select SPL_PINCTRL_TEGRA if SPL
|
||||
select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL
|
||||
select SPL_SYSRESET if SPL
|
||||
select SUPPORT_SPL
|
||||
select TIMER
|
||||
select TEGRA_CLKRST
|
||||
@ -87,7 +89,6 @@ config TEGRA_ARMV7_COMMON
|
||||
select TEGRA_GP_PADCTRL
|
||||
select TEGRA_MC
|
||||
select TEGRA_NO_BPMP
|
||||
select TEGRA_PINCTRL
|
||||
select TEGRA_PMC
|
||||
select TEGRA_TIMER
|
||||
|
||||
@ -134,6 +135,8 @@ config TEGRA124
|
||||
config TEGRA210
|
||||
bool "Tegra210 family"
|
||||
select GICV2
|
||||
select PINCTRL
|
||||
select PINCTRL_TEGRA
|
||||
select TIMER
|
||||
select TEGRA_ARMV8_COMMON
|
||||
select TEGRA_CLKRST
|
||||
@ -141,7 +144,6 @@ config TEGRA210
|
||||
select TEGRA_GP_PADCTRL
|
||||
select TEGRA_MC
|
||||
select TEGRA_NO_BPMP
|
||||
select TEGRA_PINCTRL
|
||||
select TEGRA_PMC
|
||||
select TEGRA_PMC_SECURE
|
||||
select TEGRA_TIMER
|
||||
@ -194,7 +196,7 @@ config TEGRA_SPI
|
||||
|
||||
choice
|
||||
prompt "UART to use for console"
|
||||
depends on TEGRA_PINCTRL
|
||||
depends on PINCTRL_TEGRA
|
||||
default TEGRA_ENABLE_UARTA
|
||||
|
||||
config TEGRA_ENABLE_UARTA
|
||||
|
||||
@ -17,7 +17,6 @@ obj-y += board.o board2.o
|
||||
obj-y += cache.o
|
||||
obj-$(CONFIG_TEGRA_CLKRST) += clock.o
|
||||
obj-$(CONFIG_$(SPL_)TEGRA_CRYPTO) += crypto.o
|
||||
obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o
|
||||
obj-$(CONFIG_TEGRA_PMC) += powergate.o
|
||||
obj-y += xusb-padctl-dummy.o
|
||||
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
|
||||
#include <asm/arch/clock.h>
|
||||
#endif
|
||||
#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
|
||||
#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
|
||||
#include <asm/arch/funcmux.h>
|
||||
#endif
|
||||
#if IS_ENABLED(CONFIG_TEGRA_MC)
|
||||
@ -163,7 +163,7 @@ int dram_init(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
|
||||
#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
|
||||
static int uart_configs[] = {
|
||||
#if defined(CONFIG_TEGRA20)
|
||||
#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
|
||||
@ -235,7 +235,7 @@ static void setup_uarts(int uart_ids)
|
||||
|
||||
void board_init_uart_f(void)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
|
||||
#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
|
||||
int uart_ids = 0; /* bit mask of which UART ids to enable */
|
||||
|
||||
#ifdef CONFIG_TEGRA_ENABLE_UARTA
|
||||
|
||||
@ -34,7 +34,7 @@
|
||||
#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
|
||||
#include <asm/arch/clock.h>
|
||||
#endif
|
||||
#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
|
||||
#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
|
||||
#include <asm/arch/funcmux.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#endif
|
||||
|
||||
@ -128,14 +128,14 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
|
||||
struct clk_pll_simple *simple_pll = NULL;
|
||||
u32 misc_data, data;
|
||||
|
||||
if (clkid < (enum clock_id)TEGRA_CLK_PLLS) {
|
||||
if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
|
||||
pll = get_pll(clkid);
|
||||
} else {
|
||||
else
|
||||
simple_pll = clock_get_simple_pll(clkid);
|
||||
if (!simple_pll) {
|
||||
debug("%s: Uknown simple PLL %d\n", __func__, clkid);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!simple_pll && !pll) {
|
||||
log_err("Unknown PLL id %d\n", clkid);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -542,7 +542,8 @@ unsigned int __weak clk_m_get_rate(unsigned int parent_rate)
|
||||
|
||||
unsigned clock_get_rate(enum clock_id clkid)
|
||||
{
|
||||
struct clk_pll *pll;
|
||||
struct clk_pll *pll = NULL;
|
||||
struct clk_pll_simple *simple_pll = NULL;
|
||||
u32 base, divm;
|
||||
u64 parent_rate, rate;
|
||||
struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
|
||||
@ -554,10 +555,20 @@ unsigned clock_get_rate(enum clock_id clkid)
|
||||
if (clkid == CLOCK_ID_CLK_M)
|
||||
return clk_m_get_rate(parent_rate);
|
||||
|
||||
pll = get_pll(clkid);
|
||||
if (!pll)
|
||||
if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
|
||||
pll = get_pll(clkid);
|
||||
else
|
||||
simple_pll = clock_get_simple_pll(clkid);
|
||||
|
||||
if (!simple_pll && !pll) {
|
||||
log_err("Unknown PLL id %d\n", clkid);
|
||||
return 0;
|
||||
base = readl(&pll->pll_base);
|
||||
}
|
||||
|
||||
if (pll)
|
||||
base = readl(&pll->pll_base);
|
||||
else
|
||||
base = readl(&simple_pll->pll_base);
|
||||
|
||||
rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
|
||||
divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
|
||||
@ -599,12 +610,24 @@ unsigned clock_get_rate(enum clock_id clkid)
|
||||
int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
|
||||
{
|
||||
u32 base_reg, misc_reg;
|
||||
struct clk_pll *pll;
|
||||
struct clk_pll *pll = NULL;
|
||||
struct clk_pll_simple *simple_pll = NULL;
|
||||
struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
|
||||
|
||||
pll = get_pll(clkid);
|
||||
if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
|
||||
pll = get_pll(clkid);
|
||||
else
|
||||
simple_pll = clock_get_simple_pll(clkid);
|
||||
|
||||
base_reg = readl(&pll->pll_base);
|
||||
if (!simple_pll && !pll) {
|
||||
log_err("Unknown PLL id %d\n", clkid);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (pll)
|
||||
base_reg = readl(&pll->pll_base);
|
||||
else
|
||||
base_reg = readl(&simple_pll->pll_base);
|
||||
|
||||
/* Set BYPASS, m, n and p to PLL_BASE */
|
||||
base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
|
||||
@ -631,21 +654,37 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
|
||||
}
|
||||
|
||||
base_reg |= PLL_BYPASS_MASK;
|
||||
writel(base_reg, &pll->pll_base);
|
||||
if (pll)
|
||||
writel(base_reg, &pll->pll_base);
|
||||
else
|
||||
writel(base_reg, &simple_pll->pll_base);
|
||||
|
||||
/* Set cpcon (KCP) to PLL_MISC */
|
||||
misc_reg = readl(&pll->pll_misc);
|
||||
if (pll)
|
||||
misc_reg = readl(&pll->pll_misc);
|
||||
else
|
||||
misc_reg = readl(&simple_pll->pll_misc);
|
||||
|
||||
misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
|
||||
misc_reg |= cpcon << pllinfo->kcp_shift;
|
||||
writel(misc_reg, &pll->pll_misc);
|
||||
if (pll)
|
||||
writel(misc_reg, &pll->pll_misc);
|
||||
else
|
||||
writel(misc_reg, &simple_pll->pll_misc);
|
||||
|
||||
/* Enable PLL */
|
||||
base_reg |= PLL_ENABLE_MASK;
|
||||
writel(base_reg, &pll->pll_base);
|
||||
if (pll)
|
||||
writel(base_reg, &pll->pll_base);
|
||||
else
|
||||
writel(base_reg, &simple_pll->pll_base);
|
||||
|
||||
/* Disable BYPASS */
|
||||
base_reg &= ~PLL_BYPASS_MASK;
|
||||
writel(base_reg, &pll->pll_base);
|
||||
if (pll)
|
||||
writel(base_reg, &pll->pll_base);
|
||||
else
|
||||
writel(base_reg, &simple_pll->pll_base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -729,6 +768,9 @@ void clock_init(void)
|
||||
pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
|
||||
pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
|
||||
pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
|
||||
#ifndef CONFIG_TEGRA20
|
||||
pll_rate[CLOCK_ID_DISPLAY2] = clock_get_rate(CLOCK_ID_DISPLAY2);
|
||||
#endif
|
||||
|
||||
debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
|
||||
debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);
|
||||
|
||||
@ -4,4 +4,4 @@
|
||||
|
||||
obj-$(CONFIG_SPL_BUILD) += cpu.o
|
||||
|
||||
obj-y += clock.o funcmux.o pinmux.o
|
||||
obj-y += clock.o
|
||||
|
||||
@ -457,6 +457,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
|
||||
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
|
||||
{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
|
||||
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
|
||||
{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
|
||||
.lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */
|
||||
};
|
||||
|
||||
/*
|
||||
@ -671,6 +673,9 @@ enum clock_id clk_id_to_pll_id(int clk_id)
|
||||
case TEGRA114_CLK_PLL_D:
|
||||
case TEGRA114_CLK_PLL_D_OUT0:
|
||||
return CLOCK_ID_DISPLAY;
|
||||
case TEGRA114_CLK_PLL_D2:
|
||||
case TEGRA114_CLK_PLL_D2_OUT0:
|
||||
return CLOCK_ID_DISPLAY2;
|
||||
case TEGRA114_CLK_PLL_X:
|
||||
return CLOCK_ID_XCPU;
|
||||
case TEGRA114_CLK_PLL_E_OUT0:
|
||||
@ -768,6 +773,23 @@ void arch_timer_init(void)
|
||||
debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
|
||||
}
|
||||
|
||||
struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
|
||||
switch (clkid) {
|
||||
case CLOCK_ID_XCPU:
|
||||
case CLOCK_ID_EPCI:
|
||||
case CLOCK_ID_SFROM32KHZ:
|
||||
return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
|
||||
case CLOCK_ID_DISPLAY2:
|
||||
return &clkrst->plld2;
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
struct periph_clk_init periph_clk_init_table[] = {
|
||||
{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
|
||||
|
||||
@ -8,8 +8,6 @@
|
||||
obj-$(CONFIG_SPL_BUILD) += cpu.o
|
||||
|
||||
obj-y += clock.o
|
||||
obj-y += funcmux.o
|
||||
obj-y += pinmux.o
|
||||
obj-y += pmc.o
|
||||
obj-y += xusb-padctl.o
|
||||
obj-y += ../xusb-padctl-common.o
|
||||
|
||||
@ -1189,10 +1189,16 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
|
||||
if (clkid == CLOCK_ID_DP)
|
||||
switch (clkid) {
|
||||
case CLOCK_ID_XCPU:
|
||||
case CLOCK_ID_EPCI:
|
||||
case CLOCK_ID_SFROM32KHZ:
|
||||
return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
|
||||
case CLOCK_ID_DP:
|
||||
return &clkrst->plldp;
|
||||
|
||||
return NULL;
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
struct periph_clk_init periph_clk_init_table[] = {
|
||||
|
||||
@ -11,7 +11,7 @@ CFLAGS_warmboot_avp.o = -march=armv4t -U__LINUX_ARM_ARCH__ \
|
||||
-D__LINUX_ARM_ARCH__=4
|
||||
CFLAGS_REMOVE_warmboot_avp.o := $(LTO_CFLAGS)
|
||||
|
||||
obj-y += clock.o funcmux.o pinmux.o
|
||||
obj-y += clock.o
|
||||
obj-$(CONFIG_TEGRA_LP0) += warmboot.o warmboot_avp.o
|
||||
obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
|
||||
obj-$(CONFIG_TEGRA_PMU) += pmu.o
|
||||
|
||||
@ -792,6 +792,21 @@ int tegra_plle_enable(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
|
||||
switch (clkid) {
|
||||
case CLOCK_ID_XCPU:
|
||||
case CLOCK_ID_EPCI:
|
||||
case CLOCK_ID_SFROM32KHZ:
|
||||
return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
struct periph_clk_init periph_clk_init_table[] = {
|
||||
{ PERIPH_ID_SPI1, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
|
||||
|
||||
@ -6,6 +6,5 @@
|
||||
#
|
||||
|
||||
obj-y += clock.o
|
||||
obj-y += funcmux.o
|
||||
obj-y += xusb-padctl.o
|
||||
obj-y += ../xusb-padctl-common.o
|
||||
|
||||
@ -1266,6 +1266,21 @@ int tegra_plle_enable(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
|
||||
switch (clkid) {
|
||||
case CLOCK_ID_XCPU:
|
||||
case CLOCK_ID_EPCI:
|
||||
case CLOCK_ID_SFROM32KHZ:
|
||||
return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
struct periph_clk_init periph_clk_init_table[] = {
|
||||
{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
|
||||
|
||||
@ -5,4 +5,4 @@
|
||||
obj-$(CONFIG_SPL_BUILD) += cpu.o
|
||||
obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o
|
||||
|
||||
obj-y += clock.o funcmux.o pinmux.o
|
||||
obj-y += clock.o
|
||||
|
||||
@ -438,6 +438,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
|
||||
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
|
||||
{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
|
||||
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
|
||||
{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
|
||||
.lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */
|
||||
};
|
||||
|
||||
/*
|
||||
@ -654,6 +656,9 @@ enum clock_id clk_id_to_pll_id(int clk_id)
|
||||
case TEGRA30_CLK_PLL_D:
|
||||
case TEGRA30_CLK_PLL_D_OUT0:
|
||||
return CLOCK_ID_DISPLAY;
|
||||
case TEGRA30_CLK_PLL_D2:
|
||||
case TEGRA30_CLK_PLL_D2_OUT0:
|
||||
return CLOCK_ID_DISPLAY2;
|
||||
case TEGRA30_CLK_PLL_X:
|
||||
return CLOCK_ID_XCPU;
|
||||
case TEGRA30_CLK_PLL_E:
|
||||
@ -871,6 +876,23 @@ int tegra_plle_enable(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
|
||||
switch (clkid) {
|
||||
case CLOCK_ID_XCPU:
|
||||
case CLOCK_ID_EPCI:
|
||||
case CLOCK_ID_SFROM32KHZ:
|
||||
return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
|
||||
case CLOCK_ID_DISPLAY2:
|
||||
return &clkrst->plld2;
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
struct periph_clk_init periph_clk_init_table[] = {
|
||||
{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
|
||||
|
||||
@ -7,25 +7,7 @@
|
||||
* Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch/gp_padctrl.h>
|
||||
|
||||
#include "pinmux-config-grouper.h"
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_config_pingrp_table(grouper_pinmux_common,
|
||||
ARRAY_SIZE(grouper_pinmux_common));
|
||||
|
||||
pinmux_config_drvgrp_table(grouper_padctrl,
|
||||
ARRAY_SIZE(grouper_padctrl));
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||
|
||||
@ -1,362 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_GROUPER_H_
|
||||
#define _PINMUX_CONFIG_GROUPER_H_
|
||||
|
||||
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
|
||||
}
|
||||
|
||||
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static struct pmux_pingrp_config grouper_pinmux_common[] = {
|
||||
/* SDMMC1 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC3 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC4 pinmux */
|
||||
LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* I2C pinmux */
|
||||
I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* HDMI-CEC pinmux */
|
||||
DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* ULPI pinmux */
|
||||
DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, UP, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_CLK_PY0, ULPI, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_DIR_PY1, ULPI, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_NXT_PY2, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_STP_PY3, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
|
||||
/* DAP3 pinmux */
|
||||
DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, DOWN, TRISTATE, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(PV0, RSVD1, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PV2, OWR, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(PV3, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* CLK2 pinmux */
|
||||
DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* LCD pinmux */
|
||||
DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* VI-group pinmux */
|
||||
LV_PINMUX(VI_D0_PT4, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D1_PD5, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D2_PL0, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D3_PL1, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D4_PL2, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D5_PL3, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D6_PL4, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D7_PL5, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D8_PL6, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D9_PL7, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D10_PT2, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D11_PT3, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_PCLK_PT0, SDMMC2, UP, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_MCLK_PT1, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_HSYNC_PD7, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_VSYNC_PD6, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* UART-B pinmux */
|
||||
DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* UART-C pinmux */
|
||||
DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* U-gpio group pinmux */
|
||||
DEFAULT_PINMUX(PU0, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU3, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU6, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* DAP4 pinmux */
|
||||
DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* CLK3 pinmux */
|
||||
DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, DOWN, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(PCC1, RSVD2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, UP, NORMAL, INPUT),
|
||||
|
||||
/* KBC keys */
|
||||
DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW1_PR1, KBC, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW2_PR2, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW3_PR3, KBC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW4_PR4, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW10_PS2, KBC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW11_PS3, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW15_PS7, KBC, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_COL2_PQ2, RSVD4, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL3_PQ3, RSVD4, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL4_PQ4, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* CLK */
|
||||
DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* DAP1 pinmux */
|
||||
DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* CLK1 pinmux */
|
||||
DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* SPDIF pinmux */
|
||||
DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* DAP2 pinmux */
|
||||
DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* SPI pinmux */
|
||||
DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI2_MISO_PX1, SPI2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI2_SCK_PX2, SPI2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* PEX pinmux */
|
||||
DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* GMI pinmux */
|
||||
DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_ADV_N_PK0, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS0_N_PJ0, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS6_N_PI3, GMI, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD0_PG0, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD1_PG1, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD2_PG2, RSVD1, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD3_PG3, RSVD1, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD6_PG6, RSVD1, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD7_PG7, RSVD1, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD9_PH1, RSVD4, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD10_PH2, PWM2, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD11_PH3, PWM3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD13_PH5, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD14_PH6, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD15_PH7, RSVD1, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_WR_N_PI0, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_DQS_PI2, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_RST_N_PI4, NAND, UP, NORMAL, OUTPUT),
|
||||
};
|
||||
|
||||
static struct pmux_drvgrp_config grouper_padctrl[] = {
|
||||
/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
|
||||
DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
|
||||
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
|
||||
};
|
||||
#endif /* _PINMUX_CONFIG_GROUPER_H_ */
|
||||
@ -1,365 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Copyright (c) 2021, Svyatoslav Ryhel.
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_TRANSFORMER_H_
|
||||
#define _PINMUX_CONFIG_TRANSFORMER_H_
|
||||
|
||||
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
|
||||
}
|
||||
|
||||
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static struct pmux_pingrp_config transformer_pinmux_common[] = {
|
||||
/* SDMMC1 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC3 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC4 pinmux */
|
||||
LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* I2C pinmux */
|
||||
I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* HDMI-CEC pinmux */
|
||||
DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* ULPI pinmux */
|
||||
DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, DOWN, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA3_PO4, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, TRISTATE, OUTPUT),
|
||||
|
||||
/* DAP3 pinmux */
|
||||
DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(PV0, RSVD1, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PV2, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PV3, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
|
||||
/* CLK2 pinmux */
|
||||
DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* LCD pinmux */
|
||||
DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, TRISTATE, OUTPUT),
|
||||
|
||||
/* VI-group pinmux */
|
||||
LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* UART-B pinmux */
|
||||
DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* UART-C pinmux */
|
||||
DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* U-gpio group pinmux */
|
||||
DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU4, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU6, RSVD1, DOWN, NORMAL, INPUT),
|
||||
|
||||
/* DAP4 pinmux */
|
||||
DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* CLK3 pinmux */
|
||||
DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* KBC keys */
|
||||
DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW2_PR2, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW4_PR4, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL2_PQ2, RSVD4, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL3_PQ3, RSVD4, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL4_PQ4, RSVD4, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* CLK */
|
||||
DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* DAP1 pinmux */
|
||||
DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* CLK1 pinmux */
|
||||
DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* SPDIF pinmux */
|
||||
DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, TRISTATE, OUTPUT),
|
||||
|
||||
/* DAP2 pinmux */
|
||||
DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* SPI pinmux */
|
||||
DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
|
||||
|
||||
/* PEX pinmux */
|
||||
DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* GMI pinmux */
|
||||
DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD13_PH5, NAND, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD15_PH7, NAND, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
};
|
||||
|
||||
static struct pmux_pingrp_config tf700t_mipi_pinmux[] = {
|
||||
DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS4_N_PK2, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, TRISTATE, INPUT),
|
||||
};
|
||||
|
||||
static struct pmux_drvgrp_config transformer_padctrl[] = {
|
||||
/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
|
||||
DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
|
||||
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
|
||||
};
|
||||
#endif /* _PINMUX_CONFIG_TRANSFORMER_H_ */
|
||||
@ -9,30 +9,7 @@
|
||||
|
||||
/* T30 Transformers derive from Cardhu board */
|
||||
|
||||
#include <dm.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch/gp_padctrl.h>
|
||||
|
||||
#include "pinmux-config-transformer.h"
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_config_pingrp_table(transformer_pinmux_common,
|
||||
ARRAY_SIZE(transformer_pinmux_common));
|
||||
|
||||
pinmux_config_drvgrp_table(transformer_padctrl,
|
||||
ARRAY_SIZE(transformer_padctrl));
|
||||
|
||||
if (of_machine_is_compatible("asus,tf700t")) {
|
||||
pinmux_config_pingrp_table(tf700t_mipi_pinmux,
|
||||
ARRAY_SIZE(tf700t_mipi_pinmux));
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||
|
||||
@ -1,8 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
|
||||
obj-y := paz00.o
|
||||
@ -1,53 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <log.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/tegra.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/gpio.h>
|
||||
|
||||
#ifdef CONFIG_MMC_SDHCI_TEGRA
|
||||
/*
|
||||
* Routine: pin_mux_mmc
|
||||
* Description: setup the pin muxes/tristate values for the SDMMC(s)
|
||||
*/
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
/* SDMMC4: config 3, x8 on 2nd set of pins */
|
||||
pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
|
||||
pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
|
||||
pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
|
||||
|
||||
pinmux_tristate_disable(PMUX_PINGRP_ATB);
|
||||
pinmux_tristate_disable(PMUX_PINGRP_GMA);
|
||||
pinmux_tristate_disable(PMUX_PINGRP_GME);
|
||||
|
||||
/* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
|
||||
pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
|
||||
|
||||
pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
|
||||
|
||||
/* For power GPIO PV1 */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_UAC);
|
||||
/* For CD GPIO PV5 */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_GPV);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
/* this is a weak define that we are overriding */
|
||||
void pin_mux_display(void)
|
||||
{
|
||||
debug("init display pinmux\n");
|
||||
|
||||
/* EN_VDD_PANEL GPIO A4 */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_DAP2);
|
||||
}
|
||||
#endif
|
||||
@ -7,21 +7,7 @@
|
||||
* Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
|
||||
#include "pinmux-config-endeavoru.h"
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_config_pingrp_table(endeavoru_pinmux_common,
|
||||
ARRAY_SIZE(endeavoru_pinmux_common));
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||
|
||||
@ -1,362 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Copyright (c) 2022, Svyatoslav Ryhel.
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_ENDEAVORU_H_
|
||||
#define _PINMUX_CONFIG_ENDEAVORU_H_
|
||||
|
||||
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
|
||||
}
|
||||
|
||||
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static struct pmux_pingrp_config endeavoru_pinmux_common[] = {
|
||||
/* SDMMC1 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT3_PY4, UARTE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT2_PY5, UARTE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT1_PY6, RSVD2, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC3 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT6_PD3, INVALID, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT7_PD4, INVALID, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC4 pinmux */
|
||||
LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* I2C pinmux */
|
||||
I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* HDMI pinmux */
|
||||
DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* ULPI pinmux */
|
||||
DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA2_PO3, SPI3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA3_PO4, HSI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA4_PO5, SPI2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA7_PO0, SPI2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_CLK_PY0, RSVD2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_DIR_PY1, RSVD2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_NXT_PY2, ULPI, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_STP_PY3, ULPI, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* DAP3 pinmux */
|
||||
DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* PV-gpio group pinmux */
|
||||
DEFAULT_PINMUX(PV0, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PV2, RSVD2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PV3, RSVD2, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* CLK2 pinmux */
|
||||
DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD4, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* LCD pinmux */
|
||||
DEFAULT_PINMUX(LCD_PWR1_PC1, RSVD4, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS0_N_PN4, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, UP, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D2_PE2, RSVD3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D6_PE6, RSVD3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D8_PF0, RSVD4, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D14_PF6, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D15_PF7, RSVD4, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D18_PM2, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D19_PM3, RSVD4, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D21_PM5, RSVD4, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_D22_PM6, RSVD4, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_D23_PM7, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS1_N_PW0, RSVD4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_DC1_PD2, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CRT_VSYNC_PV7, RSVD4, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* VI-group pinmux */
|
||||
LV_PINMUX(VI_D0_PT4, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D4_PL2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D6_PL4, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D10_PT2, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D11_PT3, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_PCLK_PT0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_MCLK_PT1, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_VSYNC_PD6, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_HSYNC_PD7, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* UART-2 pinmux */
|
||||
DEFAULT_PINMUX(UART2_RXD_PC3, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART2_TXD_PC2, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART2_RTS_N_PJ6, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART2_CTS_N_PJ5, SPI4, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* UART-3 pinmux */
|
||||
DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* PU-gpio group pinmux */
|
||||
DEFAULT_PINMUX(PU0, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU1, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU2, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU3, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU4, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU5, RSVD4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU6, PWM3, UP, TRISTATE, INPUT),
|
||||
|
||||
/* DAP4 pinmux */
|
||||
DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DOUT_PP6, RSVD4, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP4_SCLK_PP7, RSVD4, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* CLK3 pinmux */
|
||||
DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD4, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* GMI pinmux */
|
||||
DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_ADV_N_PK0, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CLK_PK1, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS6_N_PI3, NAND, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD0_PG0, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD1_PG1, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD2_PG2, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD3_PG3, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD4_PG4, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD5_PG5, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD6_PG6, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD7_PG7, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD9_PH1, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD11_PH3, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD12_PH4, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD13_PH5, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD14_PH6, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD15_PH7, NAND, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_WR_N_PI0, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_DQS_PI2, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_RST_N_PI4, RSVD4, UP, TRISTATE, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(PCC1, RSVD3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB0, RSVD3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB7, RSVD3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PCC2, RSVD3, UP, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, UP, NORMAL, INPUT),
|
||||
|
||||
/* KBC keys */
|
||||
DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW1_PR1, KBC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW2_PR2, RSVD4, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW3_PR3, RSVD3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW4_PR4, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW10_PS2, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW11_PS3, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW15_PS7, KBC, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL6_PQ6, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* CLK */
|
||||
DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(OWR, OWR, UP, NORMAL, INPUT),
|
||||
|
||||
/* DAP1 pinmux */
|
||||
DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, TRISTATE, OUTPUT),
|
||||
|
||||
/* CLK1 pinmux */
|
||||
DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK1_OUT_PW4, RSVD4, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* SPDIF pinmux */
|
||||
DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, TRISTATE, OUTPUT),
|
||||
|
||||
/* DAP2 pinmux */
|
||||
DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, DOWN, NORMAL, INPUT),
|
||||
|
||||
/* SPI pinmux */
|
||||
DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SPI2_MISO_PX1, SPI2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI2_CS0_N_PX3, SPI2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SPI2_SCK_PX2, SPI2, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, UP, TRISTATE, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_SCK_PX5, SPI2, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* PEX pinmux */
|
||||
DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
|
||||
};
|
||||
|
||||
#endif /* _PINMUX_CONFIG_TRANSFORMER_H_ */
|
||||
@ -9,16 +9,4 @@ config SYS_VENDOR
|
||||
config SYS_CONFIG_NAME
|
||||
default "x3-t30"
|
||||
|
||||
config DEVICE_P880
|
||||
bool "Enable support for LG Optimus 4X HD"
|
||||
help
|
||||
LG Optimus 4X HD derives from x3 board but has slight
|
||||
differences.
|
||||
|
||||
config DEVICE_P895
|
||||
bool "Enable support for LG Optimus Vu"
|
||||
help
|
||||
LG Optimus Vu derives from x3 board but has slight
|
||||
differences.
|
||||
|
||||
endif
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p880"
|
||||
CONFIG_DEVICE_P880=y
|
||||
CONFIG_SYS_PROMPT="Tegra30 (P880) # "
|
||||
CONFIG_VIDEO_LCD_RENESAS_R69328=y
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p895"
|
||||
CONFIG_DEVICE_P895=y
|
||||
CONFIG_SYS_PROMPT="Tegra30 (P895) # "
|
||||
CONFIG_VIDEO_LCD_RENESAS_R61307=y
|
||||
|
||||
@ -1,449 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Copyright (c) 2021, Svyatoslav Ryhel.
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_X3_H_
|
||||
#define _PINMUX_CONFIG_X3_H_
|
||||
|
||||
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
|
||||
}
|
||||
|
||||
static struct pmux_pingrp_config tegra3_x3_pinmux_common[] = {
|
||||
/* SDMMC1 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC3 pinmux */
|
||||
// DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
|
||||
// DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
|
||||
// DEFAULT_PINMUX(SDMMC3_DAT0_PB7, RSVD1, NORMAL, TRISTATE, INPUT), // device specific
|
||||
// DEFAULT_PINMUX(SDMMC3_DAT1_PB6, RSVD1, NORMAL, NORMAL, INPUT), // device specific
|
||||
// DEFAULT_PINMUX(SDMMC3_DAT2_PB5, RSVD1, NORMAL, TRISTATE, INPUT), // device specific
|
||||
// DEFAULT_PINMUX(SDMMC3_DAT3_PB4, RSVD1, NORMAL, TRISTATE, INPUT), // device specific
|
||||
// DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
|
||||
// DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
|
||||
// DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
|
||||
// DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD2, NORMAL, TRISTATE, INPUT), // device specific
|
||||
|
||||
/* SDMMC4 pinmux */
|
||||
LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
// LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), // device specific
|
||||
LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* I2C1 pinmux */
|
||||
I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* I2C2 pinmux */
|
||||
I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, UP, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, UP, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* I2C3 pinmux */
|
||||
I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* I2C4 pinmux */
|
||||
I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* Power I2C pinmux */
|
||||
I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* HDMI-CEC pinmux */
|
||||
DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* ULPI pinmux */
|
||||
DEFAULT_PINMUX(ULPI_DATA0_PO1, SPI3, UP, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA1_PO2, SPI3, UP, NORMAL, OUTPUT), // LCD_BRIDGE_RESET_N
|
||||
DEFAULT_PINMUX(ULPI_DATA2_PO3, SPI3, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA3_PO4, SPI3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT),
|
||||
// DEFAULT_PINMUX(ULPI_DATA5_PO6, SPI2, UP, TRISTATE, INPUT), // unconfigured
|
||||
// DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, UP, NORMAL, INPUT), // device specific
|
||||
// DEFAULT_PINMUX(ULPI_DATA7_PO0, SPI2, UP, NORMAL, INPUT), // unconfigured
|
||||
DEFAULT_PINMUX(ULPI_CLK_PY0, RSVD2, DOWN, NORMAL, OUTPUT), // LCD_EN
|
||||
DEFAULT_PINMUX(ULPI_DIR_PY1, RSVD2, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_NXT_PY2, RSVD2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* DAP3 pinmux */
|
||||
DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PV3, RSVD2, DOWN, NORMAL, INPUT),
|
||||
|
||||
/* CLK2 pinmux */
|
||||
DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD2, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* LCD pinmux */
|
||||
DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
|
||||
// DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, DOWN, TRISTATE, OUTPUT), // unconfigured
|
||||
DEFAULT_PINMUX(LCD_SDIN_PZ2, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SDI
|
||||
DEFAULT_PINMUX(LCD_SDOUT_PN5, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SDO
|
||||
DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS0_N_PN4, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_CS
|
||||
DEFAULT_PINMUX(LCD_DC0_PN6, RSVD3, NORMAL, NORMAL, OUTPUT), // LCD_CP_EN / BL
|
||||
DEFAULT_PINMUX(LCD_SCK_PZ4, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SCL
|
||||
DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_PCLK
|
||||
DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_HSYNC
|
||||
DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_VSYNC
|
||||
DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS1_N_PW0, RSVD4, UP, NORMAL, OUTPUT), // LCD_RESET_N
|
||||
DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, TRISTATE, OUTPUT), // LCD_MAKER_ID
|
||||
DEFAULT_PINMUX(LCD_DC1_PD2, RSVD3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CRT_HSYNC_PV6, RSVD2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CRT_VSYNC_PV7, RSVD2, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* VI-group pinmux */
|
||||
LV_PINMUX(VI_D0_PT4, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D10_PT2, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D11_PT3, RSVD2, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_HSYNC_PD7, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_VSYNC_PD6, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* UART-B pinmux */
|
||||
// DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), // device specific
|
||||
// DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), // device specific
|
||||
DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* UART-C pinmux */
|
||||
DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* PU-gpio group pinmux */
|
||||
// DEFAULT_PINMUX(PU0, UARTA, NORMAL, NORMAL, OUTPUT), // device specific
|
||||
// DEFAULT_PINMUX(PU1, UARTA, NORMAL, NORMAL, INPUT), // device specific
|
||||
// DEFAULT_PINMUX(PU2, RSVD1, NORMAL, TRISTATE, INPUT), // device specific
|
||||
// DEFAULT_PINMUX(PU3, PWM0, NORMAL, TRISTATE, INPUT), // device specific
|
||||
// DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT), // device specific
|
||||
DEFAULT_PINMUX(PU5, RSVD4, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU6, PWM3, DOWN, NORMAL, INPUT),
|
||||
|
||||
/* DAP4 pinmux */
|
||||
DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* CLK3 pinmux */
|
||||
DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), // MIPI_BRIDGE_CLK
|
||||
DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(PCC1, RSVD3, NORMAL, NORMAL, OUTPUT),
|
||||
// DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, OUTPUT), // device specific
|
||||
DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB7, I2S4, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PCC2, RSVD3, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* KBC keys */
|
||||
DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW2_PR2, RSVD4, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW3_PR3, RSVD3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW4_PR4, RSVD4, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW5_PR5, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW6_PR6, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW7_PR7, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW9_PS1, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW10_PS2, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW11_PS3, KBC, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW12_PS4, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW15_PS7, KBC, DOWN, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL3_PQ3, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
|
||||
|
||||
/* CLK */
|
||||
DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT),
|
||||
// DEFAULT_PINMUX(CORE_PWR_REQ, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured
|
||||
// DEFAULT_PINMUX(CPU_PWR_REQ, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured
|
||||
// DEFAULT_PINMUX(PWR_INT_N, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured
|
||||
// DEFAULT_PINMUX(CLK_32K_IN, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured
|
||||
DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* DAP1 pinmux */
|
||||
DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* CLK1 pinmux */
|
||||
DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, DOWN, NORMAL, INPUT),
|
||||
|
||||
/* SPDIF pinmux */
|
||||
DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, OUTPUT),
|
||||
// DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, DOWN, NORMAL, OUTPUT), // device specific
|
||||
|
||||
/* DAP2 pinmux */
|
||||
DEFAULT_PINMUX(DAP2_FS_PA2, HDA, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DIN_PA4, HDA, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DOUT_PA5, HDA, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_SCLK_PA3, HDA, DOWN, NORMAL, INPUT),
|
||||
|
||||
/* SPI pinmux */
|
||||
DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI2, NORMAL, NORMAL, OUTPUT),
|
||||
// DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, OUTPUT), // device specific
|
||||
// DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT), // device specific
|
||||
DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SPI2_MISO_PX1, GMI, NORMAL, NORMAL, OUTPUT),
|
||||
// DEFAULT_PINMUX(SPI2_CS0_N_PX3, SPI6, UP, NORMAL, INPUT), // unconfigured
|
||||
// DEFAULT_PINMUX(SPI2_SCK_PX2, SPI6, UP, NORMAL, INPUT), // unconfigured
|
||||
DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT),
|
||||
// DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, UP, TRISTATE, INPUT), // unconfigured
|
||||
|
||||
/* PEX pinmux */
|
||||
DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* GMI pinmux */
|
||||
DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WAIT_PI7, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_ADV_N_PK0, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CLK_PK1, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, UP, TRISTATE, INPUT), // LCD_RGB_DE
|
||||
DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
// DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT), // device specific
|
||||
DEFAULT_PINMUX(GMI_CS6_N_PI3, GMI, UP, NORMAL, INPUT),
|
||||
// DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT), // device specific
|
||||
DEFAULT_PINMUX(GMI_AD0_PG0, GMI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD1_PG1, GMI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD2_PG2, GMI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD3_PG3, GMI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD4_PG4, GMI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD5_PG5, GMI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD6_PG6, GMI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD7_PG7, GMI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD8_PH0, GMI, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD9_PH1, GMI, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD10_PH2, GMI, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD11_PH3, PWM3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD12_PH4, RSVD4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD13_PH5, RSVD4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD14_PH6, GMI, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD15_PH7, GMI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A18_PB1, UARTD, DOWN, NORMAL, OUTPUT), // RGB_IC_EN
|
||||
DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_WR_N_PI0, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_DQS_PI2, GMI, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_RST_N_PI4, GMI, UP, NORMAL, INPUT),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_DEVICE_P880
|
||||
static struct pmux_pingrp_config tegra3_p880_pinmux[] = {
|
||||
/* SDMMC3 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, TRISTATE, INPUT),
|
||||
|
||||
/* SDMMC4 pinmux */
|
||||
LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* ULPI pinmux */
|
||||
DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* UART-B pinmux */
|
||||
DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, UP, NORMAL, OUTPUT),
|
||||
|
||||
/* GPIO group pinmux */
|
||||
DEFAULT_PINMUX(PU0, UARTA, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU1, UARTA, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU2, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU3, UARTA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB0, I2S4, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* SPDIF pinmux */
|
||||
DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, UP, TRISTATE, OUTPUT),
|
||||
|
||||
/* SPI pinmux */
|
||||
DEFAULT_PINMUX(SPI1_SCK_PX5, SPI2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* GMI pinmux */
|
||||
DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, DOWN, NORMAL, OUTPUT),
|
||||
};
|
||||
#endif /* CONFIG_DEVICE_P880 */
|
||||
|
||||
#ifdef CONFIG_DEVICE_P895
|
||||
static struct pmux_pingrp_config tegra3_p895_pinmux[] = {
|
||||
/* SDMMC3 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT0_PB7, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT1_PB6, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT2_PB5, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT3_PB4, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD2, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* SDMMC4 pinmux */
|
||||
LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* ULPI pinmux */
|
||||
DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, UP, NORMAL, INPUT),
|
||||
|
||||
/* UART-B pinmux */
|
||||
DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* Gpio group pinmux */
|
||||
DEFAULT_PINMUX(PU0, UARTA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU1, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU2, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PU3, PWM0, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, OUTPUT), // LCD_EN_3V0
|
||||
|
||||
/* SPDIF pinmux */
|
||||
DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, DOWN, NORMAL, OUTPUT),
|
||||
|
||||
/* SPI pinmux */
|
||||
DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* GMI pinmux */
|
||||
DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT),
|
||||
};
|
||||
#endif /* CONFIG_DEVICE_P895 */
|
||||
#endif /* _PINMUX_CONFIG_X3_H_ */
|
||||
@ -9,32 +9,9 @@
|
||||
|
||||
#include <dm.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch-tegra/fuse.h>
|
||||
|
||||
#include "pinmux-config-x3.h"
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_config_pingrp_table(tegra3_x3_pinmux_common,
|
||||
ARRAY_SIZE(tegra3_x3_pinmux_common));
|
||||
|
||||
#ifdef CONFIG_DEVICE_P880
|
||||
pinmux_config_pingrp_table(tegra3_p880_pinmux,
|
||||
ARRAY_SIZE(tegra3_p880_pinmux));
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DEVICE_P895
|
||||
pinmux_config_pingrp_table(tegra3_p895_pinmux,
|
||||
ARRAY_SIZE(tegra3_p895_pinmux));
|
||||
#endif
|
||||
}
|
||||
|
||||
int nvidia_board_init(void)
|
||||
{
|
||||
/* Set up panel bridge clocks */
|
||||
|
||||
@ -46,6 +46,9 @@ CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_TEGRA=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_KEYBOARD=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_VIDEO=y
|
||||
|
||||
@ -238,6 +238,15 @@ config MAX7320_GPIO
|
||||
original maxim device has 8 push/pull outputs,
|
||||
some clones offers 16bit.
|
||||
|
||||
config MAX77663_GPIO
|
||||
bool "MAX77663 GPIO cell of PMIC driver"
|
||||
depends on DM_GPIO && DM_PMIC_MAX77663
|
||||
help
|
||||
GPIO driver for MAX77663 PMIC from Maxim Semiconductor.
|
||||
MAX77663 PMIC has 8 pins that can be configured as GPIOs
|
||||
and 3 GPIO-like pins dedicated for power/reset buttons
|
||||
and LID sensor.
|
||||
|
||||
config MCP230XX_GPIO
|
||||
bool "MCP230XX GPIO driver"
|
||||
depends on DM
|
||||
@ -426,6 +435,13 @@ config VYBRID_GPIO
|
||||
help
|
||||
Say yes here to support Vybrid vf610 GPIOs.
|
||||
|
||||
config PALMAS_GPIO
|
||||
bool "TI PALMAS series PMICs GPIO"
|
||||
depends on DM_GPIO && PMIC_PALMAS
|
||||
help
|
||||
Select this option to enable GPIO driver for the TI PALMAS
|
||||
series chip family.
|
||||
|
||||
config PIC32_GPIO
|
||||
bool "Microchip PIC32 GPIO driver"
|
||||
depends on DM_GPIO && MACH_PIC32
|
||||
|
||||
@ -55,6 +55,7 @@ obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
|
||||
obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
|
||||
obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o
|
||||
obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o
|
||||
obj-$(CONFIG_$(SPL_)PALMAS_GPIO) += palmas_gpio.o
|
||||
obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o
|
||||
obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o
|
||||
obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
|
||||
@ -68,6 +69,7 @@ obj-$(CONFIG_NX_GPIO) += nx_gpio.o
|
||||
obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o
|
||||
obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o
|
||||
obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o
|
||||
obj-$(CONFIG_$(SPL_)MAX77663_GPIO) += max77663_gpio.o
|
||||
obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o
|
||||
obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o
|
||||
obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o
|
||||
|
||||
@ -1143,9 +1143,29 @@ static int gpio_request_tail(int ret, const char *nodename,
|
||||
ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node,
|
||||
&desc->dev);
|
||||
if (ret) {
|
||||
#if CONFIG_IS_ENABLED(MAX77663_GPIO) || CONFIG_IS_ENABLED(PALMAS_GPIO)
|
||||
struct udevice *pmic;
|
||||
ret = uclass_get_device_by_ofnode(UCLASS_PMIC, args->node,
|
||||
&pmic);
|
||||
if (ret) {
|
||||
log_debug("%s: PMIC device get failed, err %d\n",
|
||||
__func__, ret);
|
||||
goto err;
|
||||
}
|
||||
|
||||
device_foreach_child(desc->dev, pmic) {
|
||||
if (device_get_uclass_id(desc->dev) == UCLASS_GPIO)
|
||||
break;
|
||||
}
|
||||
|
||||
/* if loop exits without GPIO device return error */
|
||||
if (device_get_uclass_id(desc->dev) != UCLASS_GPIO)
|
||||
goto err;
|
||||
#else
|
||||
debug("%s: uclass_get_device_by_ofnode failed\n",
|
||||
__func__);
|
||||
goto err;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
ret = gpio_find_and_xlate(desc, args);
|
||||
|
||||
178
drivers/gpio/max77663_gpio.c
Normal file
178
drivers/gpio/max77663_gpio.c
Normal file
@ -0,0 +1,178 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <power/max77663.h>
|
||||
#include <power/pmic.h>
|
||||
|
||||
#define NUM_ENTRIES 11 /* 8 GPIOs + 3 KEYs */
|
||||
#define NUM_GPIOS 8
|
||||
|
||||
#define MAX77663_CNFG1_GPIO 0x36
|
||||
#define GPIO_REG_ADDR(offset) (MAX77663_CNFG1_GPIO + (offset))
|
||||
|
||||
#define MAX77663_CNFG_GPIO_DIR_MASK BIT(1)
|
||||
#define MAX77663_CNFG_GPIO_DIR_INPUT BIT(1)
|
||||
#define MAX77663_CNFG_GPIO_DIR_OUTPUT 0
|
||||
#define MAX77663_CNFG_GPIO_INPUT_VAL_MASK BIT(2)
|
||||
#define MAX77663_CNFG_GPIO_OUTPUT_VAL_MASK BIT(3)
|
||||
#define MAX77663_CNFG_GPIO_OUTPUT_VAL_HIGH BIT(3)
|
||||
#define MAX77663_CNFG_GPIO_OUTPUT_VAL_LOW 0
|
||||
#define MAX77663_CNFG_IRQ GENMASK(5, 4)
|
||||
|
||||
#define MAX77663_ONOFFSTAT_REG 0x15
|
||||
#define EN0 BIT(2) /* KEY 2 */
|
||||
#define ACOK BIT(1) /* KEY 1 */
|
||||
#define LID BIT(0) /* KEY 0 */
|
||||
|
||||
static int max77663_gpio_direction_input(struct udevice *dev, unsigned int offset)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (offset >= NUM_GPIOS)
|
||||
return 0;
|
||||
|
||||
ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset),
|
||||
MAX77663_CNFG_GPIO_DIR_MASK,
|
||||
MAX77663_CNFG_GPIO_DIR_INPUT);
|
||||
if (ret < 0)
|
||||
log_debug("%s: CNFG_GPIOx dir update failed: %d\n", __func__, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int max77663_gpio_direction_output(struct udevice *dev, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
u8 val;
|
||||
int ret;
|
||||
|
||||
if (offset >= NUM_GPIOS)
|
||||
return -EINVAL;
|
||||
|
||||
val = (value) ? MAX77663_CNFG_GPIO_OUTPUT_VAL_HIGH :
|
||||
MAX77663_CNFG_GPIO_OUTPUT_VAL_LOW;
|
||||
|
||||
ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset),
|
||||
MAX77663_CNFG_GPIO_OUTPUT_VAL_MASK, val);
|
||||
if (ret < 0) {
|
||||
log_debug("%s: CNFG_GPIOx val update failed: %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset),
|
||||
MAX77663_CNFG_GPIO_DIR_MASK,
|
||||
MAX77663_CNFG_GPIO_DIR_OUTPUT);
|
||||
if (ret < 0)
|
||||
log_debug("%s: CNFG_GPIOx dir update failed: %d\n", __func__, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int max77663_gpio_get_value(struct udevice *dev, unsigned int offset)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (offset >= NUM_GPIOS) {
|
||||
ret = pmic_reg_read(dev->parent, MAX77663_ONOFFSTAT_REG);
|
||||
if (ret < 0) {
|
||||
log_debug("%s: ONOFFSTAT_REG read failed: %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return !!(ret & BIT(offset - NUM_GPIOS));
|
||||
}
|
||||
|
||||
ret = pmic_reg_read(dev->parent, GPIO_REG_ADDR(offset));
|
||||
if (ret < 0) {
|
||||
log_debug("%s: CNFG_GPIOx read failed: %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (ret & MAX77663_CNFG_GPIO_DIR_MASK)
|
||||
return !!(ret & MAX77663_CNFG_GPIO_INPUT_VAL_MASK);
|
||||
else
|
||||
return !!(ret & MAX77663_CNFG_GPIO_OUTPUT_VAL_MASK);
|
||||
}
|
||||
|
||||
static int max77663_gpio_set_value(struct udevice *dev, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
u8 val;
|
||||
int ret;
|
||||
|
||||
if (offset >= NUM_GPIOS)
|
||||
return -EINVAL;
|
||||
|
||||
val = (value) ? MAX77663_CNFG_GPIO_OUTPUT_VAL_HIGH :
|
||||
MAX77663_CNFG_GPIO_OUTPUT_VAL_LOW;
|
||||
|
||||
ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset),
|
||||
MAX77663_CNFG_GPIO_OUTPUT_VAL_MASK, val);
|
||||
if (ret < 0)
|
||||
log_debug("%s: CNFG_GPIO_OUT update failed: %d\n", __func__, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int max77663_gpio_get_function(struct udevice *dev, unsigned int offset)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (offset >= NUM_GPIOS)
|
||||
return GPIOF_INPUT;
|
||||
|
||||
ret = pmic_reg_read(dev->parent, GPIO_REG_ADDR(offset));
|
||||
if (ret < 0) {
|
||||
log_debug("%s: CNFG_GPIOx read failed: %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (ret & MAX77663_CNFG_GPIO_DIR_MASK)
|
||||
return GPIOF_INPUT;
|
||||
else
|
||||
return GPIOF_OUTPUT;
|
||||
}
|
||||
|
||||
static const struct dm_gpio_ops max77663_gpio_ops = {
|
||||
.direction_input = max77663_gpio_direction_input,
|
||||
.direction_output = max77663_gpio_direction_output,
|
||||
.get_value = max77663_gpio_get_value,
|
||||
.set_value = max77663_gpio_set_value,
|
||||
.get_function = max77663_gpio_get_function,
|
||||
};
|
||||
|
||||
static int max77663_gpio_probe(struct udevice *dev)
|
||||
{
|
||||
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
|
||||
int i, ret;
|
||||
|
||||
uc_priv->gpio_count = NUM_ENTRIES;
|
||||
uc_priv->bank_name = "GPIO";
|
||||
|
||||
/*
|
||||
* GPIO interrupts may be left ON after bootloader, hence let's
|
||||
* pre-initialize hardware to the expected state by disabling all
|
||||
* the interrupts.
|
||||
*/
|
||||
for (i = 0; i < NUM_GPIOS; i++) {
|
||||
ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(i),
|
||||
MAX77663_CNFG_IRQ, 0);
|
||||
if (ret < 0) {
|
||||
log_debug("%s: failed to disable interrupt: %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_DRIVER(max77663_gpio) = {
|
||||
.name = MAX77663_GPIO_DRIVER,
|
||||
.id = UCLASS_GPIO,
|
||||
.probe = max77663_gpio_probe,
|
||||
.ops = &max77663_gpio_ops,
|
||||
};
|
||||
132
drivers/gpio/palmas_gpio.c
Normal file
132
drivers/gpio/palmas_gpio.c
Normal file
@ -0,0 +1,132 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Based on mainline Linux palmas GPIO driver
|
||||
* Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <power/palmas.h>
|
||||
|
||||
#define NUM_GPIOS 8
|
||||
|
||||
static int palmas_gpio_set_value(struct udevice *dev, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct palmas_priv *priv = dev_get_priv(dev->parent);
|
||||
u32 reg;
|
||||
int ret;
|
||||
|
||||
reg = (value) ? PALMAS_GPIO_SET_DATA_OUT : PALMAS_GPIO_CLEAR_DATA_OUT;
|
||||
|
||||
ret = dm_i2c_reg_write(priv->chip2, reg, BIT(offset));
|
||||
if (ret < 0)
|
||||
log_debug("%s: Reg 0x%02x write failed, %d\n", __func__, reg, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int palmas_gpio_get_value(struct udevice *dev, unsigned int offset)
|
||||
{
|
||||
struct palmas_priv *priv = dev_get_priv(dev->parent);
|
||||
u32 reg;
|
||||
int ret;
|
||||
|
||||
ret = dm_i2c_reg_read(priv->chip2, PALMAS_GPIO_DATA_DIR);
|
||||
if (ret < 0) {
|
||||
log_debug("%s: GPIO_DATA_DIR read failed, %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (ret & BIT(offset))
|
||||
reg = PALMAS_GPIO_DATA_OUT;
|
||||
else
|
||||
reg = PALMAS_GPIO_DATA_IN;
|
||||
|
||||
ret = dm_i2c_reg_read(priv->chip2, reg);
|
||||
if (ret < 0) {
|
||||
log_debug("%s: Reg 0x%02x read failed, %d\n", __func__, reg, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return !!(ret & BIT(offset));
|
||||
}
|
||||
|
||||
static int palmas_gpio_direction_input(struct udevice *dev, unsigned int offset)
|
||||
{
|
||||
struct palmas_priv *priv = dev_get_priv(dev->parent);
|
||||
int ret;
|
||||
|
||||
ret = dm_i2c_reg_clrset(priv->chip2, PALMAS_GPIO_DATA_DIR,
|
||||
BIT(offset), 0);
|
||||
if (ret < 0)
|
||||
log_debug("%s: GPIO_DATA_DIR val update failed: %d\n", __func__, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int palmas_gpio_direction_output(struct udevice *dev, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct palmas_priv *priv = dev_get_priv(dev->parent);
|
||||
int ret;
|
||||
|
||||
/* Set the initial value */
|
||||
palmas_gpio_set_value(dev, offset, value);
|
||||
|
||||
ret = dm_i2c_reg_clrset(priv->chip2, PALMAS_GPIO_DATA_DIR,
|
||||
BIT(offset), BIT(offset));
|
||||
if (ret < 0)
|
||||
log_debug("%s: GPIO_DATA_DIR val update failed: %d\n", __func__, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int palmas_gpio_get_function(struct udevice *dev, unsigned int offset)
|
||||
{
|
||||
struct palmas_priv *priv = dev_get_priv(dev->parent);
|
||||
int ret;
|
||||
|
||||
ret = dm_i2c_reg_read(priv->chip2, PALMAS_GPIO_DATA_DIR);
|
||||
if (ret < 0) {
|
||||
log_debug("%s: GPIO_DATA_DIR read failed, %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (ret & BIT(offset))
|
||||
return GPIOF_OUTPUT;
|
||||
else
|
||||
return GPIOF_INPUT;
|
||||
}
|
||||
|
||||
static const struct dm_gpio_ops palmas_gpio_ops = {
|
||||
.direction_input = palmas_gpio_direction_input,
|
||||
.direction_output = palmas_gpio_direction_output,
|
||||
.get_value = palmas_gpio_get_value,
|
||||
.set_value = palmas_gpio_set_value,
|
||||
.get_function = palmas_gpio_get_function,
|
||||
};
|
||||
|
||||
static int palmas_gpio_probe(struct udevice *dev)
|
||||
{
|
||||
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
|
||||
|
||||
uc_priv->gpio_count = NUM_GPIOS;
|
||||
uc_priv->bank_name = "GPIO";
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id palmas_ids[] = {
|
||||
{ .compatible = "ti,palmas-gpio" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(palmas_gpio) = {
|
||||
.name = PALMAS_GPIO_DRIVER,
|
||||
.id = UCLASS_GPIO,
|
||||
.of_match = palmas_ids,
|
||||
.probe = palmas_gpio_probe,
|
||||
.ops = &palmas_gpio_ops,
|
||||
};
|
||||
@ -698,7 +698,7 @@ static int tegra_mmc_probe(struct udevice *dev)
|
||||
* (actually 52MHz)
|
||||
*/
|
||||
cfg->f_min = 375000;
|
||||
cfg->f_max = 48000000;
|
||||
cfg->f_max = dev_read_u32_default(dev, "max-frequency", 48000000);
|
||||
|
||||
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
||||
|
||||
|
||||
@ -358,6 +358,7 @@ source "drivers/pinctrl/nxp/Kconfig"
|
||||
source "drivers/pinctrl/renesas/Kconfig"
|
||||
source "drivers/pinctrl/rockchip/Kconfig"
|
||||
source "drivers/pinctrl/sunxi/Kconfig"
|
||||
source "drivers/pinctrl/tegra/Kconfig"
|
||||
source "drivers/pinctrl/uniphier/Kconfig"
|
||||
source "drivers/pinctrl/starfive/Kconfig"
|
||||
|
||||
|
||||
@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_RMOBILE) += renesas/
|
||||
obj-$(CONFIG_ARCH_RZN1) += renesas/
|
||||
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
|
||||
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
|
||||
obj-$(CONFIG_$(SPL_)PINCTRL_TEGRA) += tegra/
|
||||
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
|
||||
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o
|
||||
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
|
||||
|
||||
18
drivers/pinctrl/tegra/Kconfig
Normal file
18
drivers/pinctrl/tegra/Kconfig
Normal file
@ -0,0 +1,18 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
config PINCTRL_TEGRA
|
||||
bool "Nvidia Tegra pinctrl driver"
|
||||
depends on DM
|
||||
help
|
||||
Support pin multiplexing control on Nvidia Tegra SoCs.
|
||||
The driver is an overlay to existing driver and allows
|
||||
the usage of dedicated device tree node which contains
|
||||
full description of each pin.
|
||||
|
||||
config SPL_PINCTRL_TEGRA
|
||||
bool "Nvidia Tegra SPL pinctrl driver"
|
||||
depends on SPL_PINCTRL
|
||||
help
|
||||
Enables support of pre-DM version of pin multiplexing
|
||||
control driver used on SPL stage for board setup and
|
||||
available for backwards compatibility purpose.
|
||||
16
drivers/pinctrl/tegra/Makefile
Normal file
16
drivers/pinctrl/tegra/Makefile
Normal file
@ -0,0 +1,16 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
ifdef CONFIG_TEGRA20
|
||||
obj-y += pinctrl-tegra20.o
|
||||
else
|
||||
obj-y += pinctrl-tegra.o
|
||||
endif
|
||||
endif
|
||||
|
||||
obj-y += pinmux-common.o
|
||||
|
||||
obj-$(CONFIG_TEGRA20) += pinmux-tegra20.o funcmux-tegra20.o
|
||||
obj-$(CONFIG_TEGRA30) += pinmux-tegra30.o funcmux-tegra30.o
|
||||
obj-$(CONFIG_TEGRA114) += pinmux-tegra114.o funcmux-tegra114.o
|
||||
obj-$(CONFIG_TEGRA124) += pinmux-tegra124.o funcmux-tegra124.o
|
||||
obj-$(CONFIG_TEGRA210) += pinmux-tegra210.o funcmux-tegra210.o
|
||||
248
drivers/pinctrl/tegra/pinctrl-tegra.c
Normal file
248
drivers/pinctrl/tegra/pinctrl-tegra.c
Normal file
@ -0,0 +1,248 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2023
|
||||
* Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <dm/pinctrl.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <asm/arch/pinmux.h>
|
||||
|
||||
static void tegra_pinctrl_set_drive(struct udevice *config, int drvcnt)
|
||||
{
|
||||
struct pmux_drvgrp_config *drive_group;
|
||||
int i, ret, pad_id;
|
||||
const char **pads;
|
||||
|
||||
drive_group = kmalloc_array(drvcnt, sizeof(*drive_group), GFP_KERNEL);
|
||||
if (!drive_group) {
|
||||
log_debug("%s: cannot allocate drive group array\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", 0);
|
||||
drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", 0);
|
||||
drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", 0);
|
||||
drive_group[0].drvdn = dev_read_u32_default(config, "nvidia,pull-down-strength", 0);
|
||||
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
|
||||
drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", 0);
|
||||
#endif
|
||||
#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
|
||||
drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0);
|
||||
#endif
|
||||
#ifdef TEGRA_PMX_GRPS_HAVE_HSM
|
||||
drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0);
|
||||
#endif
|
||||
|
||||
for (i = 1; i < drvcnt; i++)
|
||||
memcpy(&drive_group[i], &drive_group[0], sizeof(drive_group[0]));
|
||||
|
||||
ret = dev_read_string_list(config, "nvidia,pins", &pads);
|
||||
if (ret < 0) {
|
||||
log_debug("%s: could not parse property nvidia,pins\n", __func__);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
for (i = 0; i < drvcnt; i++) {
|
||||
for (pad_id = 0; pad_id < PMUX_DRVGRP_COUNT; pad_id++)
|
||||
if (tegra_pinctrl_to_drvgrp[pad_id])
|
||||
if (!strcmp(pads[i], tegra_pinctrl_to_drvgrp[pad_id])) {
|
||||
drive_group[i].drvgrp = pad_id;
|
||||
break;
|
||||
}
|
||||
|
||||
debug("%s drvmap: %d, %d, %d, %d, %d\n", pads[i],
|
||||
drive_group[i].drvgrp, drive_group[i].slwf,
|
||||
drive_group[i].slwr, drive_group[i].drvup,
|
||||
drive_group[i].drvdn);
|
||||
}
|
||||
|
||||
pinmux_config_drvgrp_table(drive_group, drvcnt);
|
||||
|
||||
free(pads);
|
||||
exit:
|
||||
kfree(drive_group);
|
||||
}
|
||||
|
||||
static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt)
|
||||
{
|
||||
struct pmux_pingrp_config *pinmux_group;
|
||||
int i, ret, pin_id;
|
||||
const char *function;
|
||||
const char **pins;
|
||||
|
||||
pinmux_group = kmalloc_array(pincnt, sizeof(*pinmux_group), GFP_KERNEL);
|
||||
if (!pinmux_group) {
|
||||
log_debug("%s: cannot allocate pinmux group array\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/* decode function id and fill the first copy of pmux_pingrp_config */
|
||||
function = dev_read_string(config, "nvidia,function");
|
||||
if (function)
|
||||
for (i = 0; i < PMUX_FUNC_COUNT; i++)
|
||||
if (tegra_pinctrl_to_func[i])
|
||||
if (!strcmp(function, tegra_pinctrl_to_func[i]))
|
||||
break;
|
||||
|
||||
pinmux_group[0].func = i;
|
||||
|
||||
pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", 0);
|
||||
pinmux_group[0].tristate = dev_read_u32_default(config, "nvidia,tristate", 0);
|
||||
#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
|
||||
pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", 0);
|
||||
#endif
|
||||
#ifdef TEGRA_PMX_PINS_HAVE_LOCK
|
||||
pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", 0);
|
||||
#endif
|
||||
#ifdef TEGRA_PMX_PINS_HAVE_OD
|
||||
pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", 0);
|
||||
#endif
|
||||
#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
|
||||
pinmux_group[0].ioreset = dev_read_u32_default(config, "nvidia,io-reset", 0);
|
||||
#endif
|
||||
#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
|
||||
pinmux_group[0].rcv_sel = dev_read_u32_default(config, "nvidia,rcv-sel", 0);
|
||||
#endif
|
||||
#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
|
||||
pinmux_group[0].e_io_hv = dev_read_u32_default(config, "nvidia,io-hv", 0);
|
||||
#endif
|
||||
#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
|
||||
pinmux_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0);
|
||||
#endif
|
||||
#ifdef TEGRA_PMX_PINS_HAVE_HSM
|
||||
pinmux_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0);
|
||||
#endif
|
||||
|
||||
for (i = 1; i < pincnt; i++)
|
||||
memcpy(&pinmux_group[i], &pinmux_group[0], sizeof(pinmux_group[0]));
|
||||
|
||||
ret = dev_read_string_list(config, "nvidia,pins", &pins);
|
||||
if (ret < 0) {
|
||||
log_debug("%s: could not parse property nvidia,pins\n", __func__);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
for (i = 0; i < pincnt; i++) {
|
||||
for (pin_id = 0; pin_id < PMUX_PINGRP_COUNT; pin_id++)
|
||||
if (tegra_pinctrl_to_pingrp[pin_id])
|
||||
if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id])) {
|
||||
pinmux_group[i].pingrp = pin_id;
|
||||
break;
|
||||
}
|
||||
|
||||
debug("%s pinmap: %d, %d, %d, %d\n", pins[i],
|
||||
pinmux_group[i].pingrp, pinmux_group[i].func,
|
||||
pinmux_group[i].pull, pinmux_group[i].tristate);
|
||||
}
|
||||
|
||||
pinmux_config_pingrp_table(pinmux_group, pincnt);
|
||||
|
||||
free(pins);
|
||||
exit:
|
||||
kfree(pinmux_group);
|
||||
}
|
||||
|
||||
static int tegra_pinctrl_set_state(struct udevice *dev, struct udevice *config)
|
||||
{
|
||||
struct udevice *child;
|
||||
int ret;
|
||||
const char *name;
|
||||
|
||||
device_foreach_child(child, config) {
|
||||
/* Pinmux node can contain pins and drives */
|
||||
ret = dev_read_string_index(child, "nvidia,pins", 0,
|
||||
&name);
|
||||
if (ret < 0) {
|
||||
log_debug("%s: could not parse property nvidia,pins\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = dev_read_string_count(child, "nvidia,pins");
|
||||
if (ret < 0) {
|
||||
log_debug("%s: could not count nvidia,pins\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (!strncmp(name, "drive_", 6))
|
||||
/* Drive node is detected */
|
||||
tegra_pinctrl_set_drive(child, ret);
|
||||
else
|
||||
/* Pin node is detected */
|
||||
tegra_pinctrl_set_pin(child, ret);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_pinctrl_get_pins_count(struct udevice *dev)
|
||||
{
|
||||
return PMUX_PINGRP_COUNT;
|
||||
}
|
||||
|
||||
static const char *tegra_pinctrl_get_pin_name(struct udevice *dev,
|
||||
unsigned int selector)
|
||||
{
|
||||
return tegra_pinctrl_to_pingrp[selector];
|
||||
}
|
||||
|
||||
static int tegra_pinctrl_get_groups_count(struct udevice *dev)
|
||||
{
|
||||
return PMUX_DRVGRP_COUNT;
|
||||
}
|
||||
|
||||
static const char *tegra_pinctrl_get_group_name(struct udevice *dev,
|
||||
unsigned int selector)
|
||||
{
|
||||
return tegra_pinctrl_to_drvgrp[selector];
|
||||
}
|
||||
|
||||
static int tegra_pinctrl_get_functions_count(struct udevice *dev)
|
||||
{
|
||||
return PMUX_FUNC_COUNT;
|
||||
}
|
||||
|
||||
static const char *tegra_pinctrl_get_function_name(struct udevice *dev,
|
||||
unsigned int selector)
|
||||
{
|
||||
return tegra_pinctrl_to_func[selector];
|
||||
}
|
||||
|
||||
const struct pinctrl_ops tegra_pinctrl_ops = {
|
||||
.get_pins_count = tegra_pinctrl_get_pins_count,
|
||||
.get_pin_name = tegra_pinctrl_get_pin_name,
|
||||
.get_groups_count = tegra_pinctrl_get_groups_count,
|
||||
.get_group_name = tegra_pinctrl_get_group_name,
|
||||
.get_functions_count = tegra_pinctrl_get_functions_count,
|
||||
.get_function_name = tegra_pinctrl_get_function_name,
|
||||
.set_state = tegra_pinctrl_set_state,
|
||||
};
|
||||
|
||||
static int tegra_pinctrl_bind(struct udevice *dev)
|
||||
{
|
||||
/*
|
||||
* Make sure that the pinctrl driver gets probed after binding
|
||||
* to provide initial configuration and assure that further
|
||||
* probed devices are working correctly.
|
||||
*/
|
||||
dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id tegra_pinctrl_ids[] = {
|
||||
{ .compatible = "nvidia,tegra30-pinmux" },
|
||||
{ .compatible = "nvidia,tegra114-pinmux" },
|
||||
{ },
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(tegra_pinctrl) = {
|
||||
.name = "tegra_pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = tegra_pinctrl_ids,
|
||||
.bind = tegra_pinctrl_bind,
|
||||
.ops = &tegra_pinctrl_ops,
|
||||
};
|
||||
177
drivers/pinctrl/tegra/pinctrl-tegra20.c
Normal file
177
drivers/pinctrl/tegra/pinctrl-tegra20.c
Normal file
@ -0,0 +1,177 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2023
|
||||
* Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <dm/pinctrl.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <asm/arch/pinmux.h>
|
||||
|
||||
static void tegra_pinctrl_set_pin(struct udevice *config)
|
||||
{
|
||||
int i, count, pin_id, ret;
|
||||
int pull, tristate;
|
||||
const char **pins;
|
||||
|
||||
ret = dev_read_u32(config, "nvidia,pull", &pull);
|
||||
if (ret)
|
||||
pull = ret;
|
||||
|
||||
ret = dev_read_u32(config, "nvidia,tristate", &tristate);
|
||||
if (ret)
|
||||
tristate = ret;
|
||||
|
||||
count = dev_read_string_list(config, "nvidia,pins", &pins);
|
||||
if (count < 0) {
|
||||
log_debug("%s: could not parse property nvidia,pins\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
for (pin_id = 0; pin_id < PMUX_PINGRP_COUNT; pin_id++)
|
||||
if (tegra_pinctrl_to_pingrp[pin_id])
|
||||
if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id]))
|
||||
break;
|
||||
|
||||
if (pull >= 0)
|
||||
pinmux_set_pullupdown(pin_id, pull);
|
||||
|
||||
if (tristate >= 0) {
|
||||
if (!tristate)
|
||||
pinmux_tristate_disable(pin_id);
|
||||
else
|
||||
pinmux_tristate_enable(pin_id);
|
||||
}
|
||||
}
|
||||
|
||||
free(pins);
|
||||
}
|
||||
|
||||
static void tegra_pinctrl_set_func(struct udevice *config)
|
||||
{
|
||||
int i, count, func_id, pin_id;
|
||||
const char *function;
|
||||
const char **pins;
|
||||
|
||||
function = dev_read_string(config, "nvidia,function");
|
||||
if (function)
|
||||
for (i = 0; i < PMUX_FUNC_COUNT; i++)
|
||||
if (tegra_pinctrl_to_func[i])
|
||||
if (!strcmp(function, tegra_pinctrl_to_func[i]))
|
||||
break;
|
||||
|
||||
func_id = i;
|
||||
|
||||
count = dev_read_string_list(config, "nvidia,pins", &pins);
|
||||
if (count < 0) {
|
||||
log_debug("%s: could not parse property nvidia,pins\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
for (pin_id = 0; pin_id < PMUX_PINGRP_COUNT; pin_id++)
|
||||
if (tegra_pinctrl_to_pingrp[pin_id])
|
||||
if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id]))
|
||||
break;
|
||||
|
||||
debug("%s(%d) muxed to %s(%d)\n", pins[i], pin_id, function, func_id);
|
||||
|
||||
pinmux_set_func(pin_id, func_id);
|
||||
}
|
||||
|
||||
free(pins);
|
||||
}
|
||||
|
||||
static int tegra_pinctrl_set_state(struct udevice *dev, struct udevice *config)
|
||||
{
|
||||
struct udevice *child;
|
||||
|
||||
device_foreach_child(child, config) {
|
||||
/*
|
||||
* Tegra20 pinmux is set differently then any other
|
||||
* Tegra SOC. Nodes are arranged by function muxing,
|
||||
* then actual pins setup (with node name prefix
|
||||
* conf_*) and then drive setup.
|
||||
*/
|
||||
if (!strncmp(child->name, "conf_", 5))
|
||||
tegra_pinctrl_set_pin(child);
|
||||
else if (!strncmp(child->name, "drive_", 6))
|
||||
debug("%s: drive configuration is not supported\n", __func__);
|
||||
else
|
||||
tegra_pinctrl_set_func(child);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_pinctrl_get_pins_count(struct udevice *dev)
|
||||
{
|
||||
return PMUX_PINGRP_COUNT;
|
||||
}
|
||||
|
||||
static const char *tegra_pinctrl_get_pin_name(struct udevice *dev,
|
||||
unsigned int selector)
|
||||
{
|
||||
return tegra_pinctrl_to_pingrp[selector];
|
||||
}
|
||||
|
||||
static int tegra_pinctrl_get_groups_count(struct udevice *dev)
|
||||
{
|
||||
return PMUX_DRVGRP_COUNT;
|
||||
}
|
||||
|
||||
static const char *tegra_pinctrl_get_group_name(struct udevice *dev,
|
||||
unsigned int selector)
|
||||
{
|
||||
return tegra_pinctrl_to_drvgrp[selector];
|
||||
}
|
||||
|
||||
static int tegra_pinctrl_get_functions_count(struct udevice *dev)
|
||||
{
|
||||
return PMUX_FUNC_COUNT;
|
||||
}
|
||||
|
||||
static const char *tegra_pinctrl_get_function_name(struct udevice *dev,
|
||||
unsigned int selector)
|
||||
{
|
||||
return tegra_pinctrl_to_func[selector];
|
||||
}
|
||||
|
||||
const struct pinctrl_ops tegra_pinctrl_ops = {
|
||||
.get_pins_count = tegra_pinctrl_get_pins_count,
|
||||
.get_pin_name = tegra_pinctrl_get_pin_name,
|
||||
.get_groups_count = tegra_pinctrl_get_groups_count,
|
||||
.get_group_name = tegra_pinctrl_get_group_name,
|
||||
.get_functions_count = tegra_pinctrl_get_functions_count,
|
||||
.get_function_name = tegra_pinctrl_get_function_name,
|
||||
.set_state = tegra_pinctrl_set_state,
|
||||
};
|
||||
|
||||
static int tegra_pinctrl_bind(struct udevice *dev)
|
||||
{
|
||||
/*
|
||||
* Make sure that the pinctrl driver gets probed after binding
|
||||
* to provide initial configuration and assure that further
|
||||
* probed devices are working correctly.
|
||||
*/
|
||||
dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id tegra_pinctrl_ids[] = {
|
||||
{ .compatible = "nvidia,tegra20-pinmux" },
|
||||
{ },
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(tegra_pinctrl) = {
|
||||
.name = "tegra_pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = tegra_pinctrl_ids,
|
||||
.bind = tegra_pinctrl_bind,
|
||||
.ops = &tegra_pinctrl_ops,
|
||||
};
|
||||
190
drivers/pinctrl/tegra/pinmux-tegra210.c
Normal file
190
drivers/pinctrl/tegra/pinmux-tegra210.c
Normal file
@ -0,0 +1,190 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
|
||||
#define PIN(pin, f0, f1, f2, f3) \
|
||||
{ \
|
||||
.funcs = { \
|
||||
PMUX_FUNC_##f0, \
|
||||
PMUX_FUNC_##f1, \
|
||||
PMUX_FUNC_##f2, \
|
||||
PMUX_FUNC_##f3, \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define PIN_RESERVED {}
|
||||
|
||||
static const struct pmux_pingrp_desc tegra210_pingroups[] = {
|
||||
/* pin, f0, f1, f2, f3 */
|
||||
/* Offset 0x3000 */
|
||||
PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3),
|
||||
PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3),
|
||||
PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3),
|
||||
PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3),
|
||||
PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3),
|
||||
PIN_RESERVED,
|
||||
PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3),
|
||||
PIN_RESERVED,
|
||||
PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3),
|
||||
PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3),
|
||||
PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3),
|
||||
PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3),
|
||||
PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3),
|
||||
PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3),
|
||||
PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3),
|
||||
PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3),
|
||||
PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3),
|
||||
PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3),
|
||||
PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3),
|
||||
PIN_RESERVED,
|
||||
PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3),
|
||||
PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3),
|
||||
PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3),
|
||||
PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3),
|
||||
PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3),
|
||||
PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3),
|
||||
PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3),
|
||||
PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3),
|
||||
PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3),
|
||||
PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3),
|
||||
PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3),
|
||||
PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3),
|
||||
PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3),
|
||||
PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART),
|
||||
PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART),
|
||||
PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART),
|
||||
PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART),
|
||||
PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3),
|
||||
PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3),
|
||||
PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3),
|
||||
PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3),
|
||||
PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3),
|
||||
PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3),
|
||||
PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3),
|
||||
PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3),
|
||||
PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3),
|
||||
PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3),
|
||||
PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3),
|
||||
PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3),
|
||||
PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3),
|
||||
PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3),
|
||||
PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3),
|
||||
PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3),
|
||||
PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3),
|
||||
PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3),
|
||||
PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3),
|
||||
PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3),
|
||||
PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3),
|
||||
PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3),
|
||||
PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3),
|
||||
PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3),
|
||||
PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3),
|
||||
PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3),
|
||||
PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1),
|
||||
PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3),
|
||||
PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PA6, SATA, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3),
|
||||
PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3),
|
||||
PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3),
|
||||
PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3),
|
||||
PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3),
|
||||
PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3),
|
||||
PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PL1, SOC, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3),
|
||||
PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3),
|
||||
PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3),
|
||||
};
|
||||
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups;
|
||||
@ -55,6 +55,15 @@ static int max77663_bind(struct udevice *dev)
|
||||
}
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_MAX77663_GPIO)) {
|
||||
ret = device_bind_driver(dev, MAX77663_GPIO_DRIVER,
|
||||
"gpio", NULL);
|
||||
if (ret) {
|
||||
log_err("cannot bind GPIOs (ret = %d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
regulators_node = dev_read_subnode(dev, "regulators");
|
||||
if (!ofnode_valid(regulators_node)) {
|
||||
log_err("%s regulators subnode not found!\n", dev->name);
|
||||
|
||||
@ -46,7 +46,7 @@ static int palmas_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
|
||||
static int palmas_bind(struct udevice *dev)
|
||||
{
|
||||
ofnode pmic_node = ofnode_null(), regulators_node;
|
||||
ofnode subnode;
|
||||
ofnode subnode, gpio_node;
|
||||
int children, ret;
|
||||
|
||||
if (IS_ENABLED(CONFIG_SYSRESET_PALMAS)) {
|
||||
@ -58,6 +58,14 @@ static int palmas_bind(struct udevice *dev)
|
||||
}
|
||||
}
|
||||
|
||||
gpio_node = ofnode_find_subnode(dev_ofnode(dev), "gpio");
|
||||
if (ofnode_valid(gpio_node)) {
|
||||
ret = device_bind_driver_to_node(dev, PALMAS_GPIO_DRIVER,
|
||||
"gpio", gpio_node, NULL);
|
||||
if (ret)
|
||||
log_err("cannot bind GPIOs (ret = %d)\n", ret);
|
||||
}
|
||||
|
||||
dev_for_each_subnode(subnode, dev) {
|
||||
const char *name;
|
||||
char *temp;
|
||||
|
||||
@ -14,20 +14,9 @@
|
||||
|
||||
#include "tegra30-common.h"
|
||||
|
||||
/* High-level configuration options */
|
||||
#define CFG_TEGRA_BOARD_STRING "LG X3 Board"
|
||||
|
||||
#ifdef CONFIG_DEVICE_P880
|
||||
/* High-level configuration options */
|
||||
#undef CFG_TEGRA_BOARD_STRING
|
||||
#define CFG_TEGRA_BOARD_STRING "LG Optimus 4X HD"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DEVICE_P895
|
||||
/* High-level configuration options */
|
||||
#undef CFG_TEGRA_BOARD_STRING
|
||||
#define CFG_TEGRA_BOARD_STRING "LG Optimus Vu"
|
||||
#endif
|
||||
|
||||
#define X3_FLASH_UBOOT \
|
||||
"flash_uboot=echo Preparing RAM;" \
|
||||
"mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
|
||||
|
||||
18
include/dt-bindings/pmic/max77663.h
Normal file
18
include/dt-bindings/pmic/max77663.h
Normal file
@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_MAX77663_H_
|
||||
#define _DT_BINDINGS_MAX77663_H_
|
||||
|
||||
/*
|
||||
* MAX77663 has 8 GPIO (0 to 7) and 3 KEYS
|
||||
* KEYS are appended after GPIOs
|
||||
*/
|
||||
|
||||
#define EN0 10
|
||||
#define ACOK 9
|
||||
#define LID 8
|
||||
|
||||
#endif
|
||||
@ -13,6 +13,7 @@
|
||||
#define MAX77663_LDO_DRIVER "max77663_ldo"
|
||||
#define MAX77663_SD_DRIVER "max77663_sd"
|
||||
#define MAX77663_RST_DRIVER "max77663_rst"
|
||||
#define MAX77663_GPIO_DRIVER "max77663_gpio"
|
||||
|
||||
/* Step-Down (SD) Regulator calculations */
|
||||
#define SD_STATUS_MASK 0x30
|
||||
|
||||
@ -15,6 +15,7 @@ struct palmas_priv {
|
||||
#define PALMAS_LDO_DRIVER "palmas_ldo"
|
||||
#define PALMAS_SMPS_DRIVER "palmas_smps"
|
||||
#define PALMAS_RST_DRIVER "palmas_rst"
|
||||
#define PALMAS_GPIO_DRIVER "palmas_gpio"
|
||||
|
||||
#define PALMAS_SMPS_VOLT_MASK 0x7F
|
||||
#define PALMAS_SMPS_RANGE_MASK 0x80
|
||||
@ -35,3 +36,14 @@ struct palmas_priv {
|
||||
#define DEV_OFF 0x00
|
||||
#define PALMAS_INT3_MASK 0x1B
|
||||
#define MASK_VBUS BIT(7)
|
||||
|
||||
/* second chip */
|
||||
#define PALMAS_GPIO_DATA_IN 0x80
|
||||
#define PALMAS_GPIO_DATA_DIR 0x81
|
||||
#define PALMAS_GPIO_DATA_OUT 0x82
|
||||
#define PALMAS_GPIO_DEBOUNCE_EN 0x83
|
||||
#define PALMAS_GPIO_CLEAR_DATA_OUT 0x84
|
||||
#define PALMAS_GPIO_SET_DATA_OUT 0x85
|
||||
#define PALMAS_PU_PD_GPIO_CTRL1 0x86
|
||||
#define PALMAS_PU_PD_GPIO_CTRL2 0x87
|
||||
#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x88
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user