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Merge tag 'u-boot-imx-next-20240603' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/20956

- Support different RAM sizes on imx8m phycoce boards.
- Support new toradex variants.
- Support Samsung 4GB DDR and Realtek RTL8211E PHY on imx8mm-cl-iot-gate.
- Convert imx8mm-phycore and imx8mp-phycore boards to use OF_UPSTREAM.
This commit is contained in:
Tom Rini 2024-06-03 11:42:51 -06:00
commit 15d0dcc0ec
26 changed files with 454 additions and 2164 deletions
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3
arch/arm/dts/Makefile
View File

@ -926,8 +926,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-kontron-bl-osm-s.dtb \
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
imx8mm-phyboard-polis-rdk.dtb \
imx8mm-phygate-tauri-l.dtb \
imx8mn-bsh-smm-s2.dtb \
imx8mn-bsh-smm-s2pro.dtb \
imx8mq-cm.dtb \
@ -945,7 +943,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-msc-sm2s.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb \
imx8mq-librem5-r4.dtb

460
arch/arm/dts/imx8mm-phyboard-polis-rdk.dts
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@ -1,460 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm-phycore-som.dtsi"
/ {
model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
compatible = "phytec,imx8mm-phyboard-polis-rdk",
"phytec,imx8mm-phycore-som", "fsl,imx8mm";
chosen {
stdout-path = &uart3;
};
bt_osc_32k: bt-lp-clock {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "bt_osc_32k";
#clock-cells = <0>;
};
can_osc_40m: can-clock {
compatible = "fixed-clock";
clock-frequency = <40000000>;
clock-output-names = "can_osc_40m";
#clock-cells = <0>;
};
fan {
compatible = "gpio-fan";
gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = <0 0
13000 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fan>;
#cooling-cells = <2>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-0 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_DISK;
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc2";
};
led-1 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_DISK;
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
};
led-2 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_CPU;
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
usdhc1_pwrseq: pwr-seq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <60>;
reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
};
reg_can_en: regulator-can-en {
compatible = "regulator-fixed";
gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_en>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "CAN_EN";
startup-delay-us = <20>;
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
compatible = "regulator-fixed";
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1pwrgrp>;
regulator-name = "usb_otg1_vbus";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <20000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VSD_3V3";
};
reg_vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VCC_3V3";
};
};
/* SPI - CAN MCP251XFD */
&ecspi1 {
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
can0: can@0 {
compatible = "microchip,mcp251xfd";
clocks = <&can_osc_40m>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_int>;
reg = <0>;
spi-max-frequency = <20000000>;
xceiver-supply = <&reg_can_en>;
};
};
&gpio1 {
gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT",
"", "", "", "RESET_ETHPHY",
"CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
"USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";
};
&gpio2 {
gpio-line-names = "", "", "", "",
"", "", "BT_REG_ON", "WL_REG_ON",
"BT_DEV_WAKE", "BT_HOST_WAKE", "", "",
"X_SD2_CD_B", "", "", "",
"", "", "", "SD2_RESET_B";
};
&gpio4 {
gpio-line-names = "", "", "", "",
"", "", "", "",
"FAN", "miniPCIe_nPERST", "", "",
"COEX1", "COEX2";
};
&gpio5 {
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "ECSPI1_SS0";
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
};
/* PCIe */
&pcie0 {
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
assigned-clock-rates = <10000000>, <250000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie_phy {
clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
fsl,tx-deemph-gen2 = <0xf>;
status = "okay";
};
&rv3028 {
trickle-resistor-ohms = <3000>;
};
&snvs_pwrkey {
status = "okay";
};
/* UART - RS232/RS485 */
&uart1 {
assigned-clocks = <&clk IMX8MM_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "okay";
};
/* UART - Sterling-LWB Bluetooth */
&uart2 {
assigned-clocks = <&clk IMX8MM_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
fsl,dte-mode;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_bt>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&bt_osc_32k>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wakeup";
interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_EDGE_BOTH>;
max-speed = <2000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt>;
shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
vddio-supply = <&reg_vcc_3v3>;
};
};
/* UART - console */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
/* USB */
&usbotg1 {
adp-disable;
dr_mode = "otg";
over-current-active-low;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
srp-disable;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
};
/* SDIO - Sterling-LWB Wifi */
&usdhc1 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
assigned-clock-rates = <200000000>;
bus-width = <4>;
mmc-pwrseq = <&usdhc1_pwrseq>;
non-removable;
no-1-8-v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
/* SD-Card */
&usdhc2 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_usdhc2_vmmc>;
vqmmc-supply = <&reg_nvcc_sd2>;
status = "okay";
};
&iomuxc {
pinctrl_bt: btgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00
>;
};
pinctrl_can_en: can-engrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
>;
};
pinctrl_can_int: can-intgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
>;
};
pinctrl_fan: fan0grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
>;
};
pinctrl_leds: leds1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00
>;
};
pinctrl_uart2_bt: uart2btgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00
MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00
MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00
MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
>;
};
pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
pinctrl_wlan: wlangrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00
>;
};
};

440
arch/arm/dts/imx8mm-phycore-som.dtsi
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@ -1,440 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
#include "imx8mm.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "PHYTEC phyCORE-i.MX8MM";
compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
aliases {
rtc0 = &rv3028;
rtc1 = &snvs_rtc;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
reg_vdd_3v3_s: regulator-vdd-3v3-s {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VDD_3V3_S";
};
};
&A53_0 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_1 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_2 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_3 {
cpu-supply = <&reg_vdd_arm>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
};
/* Ethernet */
&fec1 {
fsl,magic-packet;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
enet-phy-lane-no-swap;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
reg = <0>;
reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
};
};
};
/* SPI Flash */
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
som_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&gpio1 {
gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT",
"", "", "", "RESET_ETHPHY",
"", "", "nENABLE_FLATLINK";
};
/* I2C1 */
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default","gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@8 {
compatible = "nxp,pf8121a";
reg = <0x08>;
regulators {
reg_nvcc_sd1: ldo1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "NVCC_SD1 (LDO1)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_nvcc_sd2: ldo2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "NVCC_SD2 (LDO2)";
vselect-en;
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vcc_enet: ldo3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2500000>;
regulator-min-microvolt = <1500000>;
regulator-name = "VCC_ENET_2V5 (LDO3)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vdda_1v8: ldo4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1500000>;
regulator-name = "VDDA_1V8 (LDO4)";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-min-microvolt = <1500000>;
regulator-suspend-max-microvolt = <1500000>;
};
};
reg_soc_vdda_phy: buck1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <900000>;
regulator-min-microvolt = <400000>;
regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-min-microvolt = <400000>;
regulator-suspend-max-microvolt = <400000>;
};
};
reg_vdd_gpu_dram: buck2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <1000000>;
regulator-name = "VDD_GPU_DRAM (BUCK2)";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <1000000>;
regulator-suspend-min-microvolt = <1000000>;
};
};
reg_vdd_gpu: buck3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <400000>;
regulator-name = "VDD_VPU (BUCK3)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vdd_mipi: buck4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1050000>;
regulator-min-microvolt = <900000>;
regulator-name = "VDD_MIPI_0P9 (BUCK4)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vdd_arm: buck5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1050000>;
regulator-min-microvolt = <400000>;
regulator-name = "VDD_ARM (BUCK5)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vdd_1v8: buck6 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "VDD_1V8 (BUCK6)";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <1800000>;
regulator-suspend-min-microvolt = <1800000>;
};
};
reg_nvcc_dram: buck7 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1100000>;
regulator-min-microvolt = <1100000>;
regulator-name = "NVCC_DRAM_1P1V (BUCK7)";
};
reg_vsnvs: vsnvs {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "NVCC_SNVS_1P8 (VSNVS)";
};
};
};
sn65dsi83: bridge@2d {
compatible = "ti,sn65dsi83";
enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sn65dsi83>;
reg = <0x2d>;
status = "disabled";
};
eeprom@51 {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x51>;
vcc-supply = <&reg_vdd_3v3_s>;
};
rv3028: rtc@52 {
compatible = "microcrystal,rv3028";
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
reg = <0x52>;
};
};
/* EMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
keep-power-in-suspend;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
non-removable;
status = "okay";
};
/* Watchdog */
&wdog1 {
fsl,ext-reset-output;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
>;
};
pinctrl_sn65dsi83: sn65dsi83grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26
>;
};
};

489
arch/arm/dts/imx8mm-phygate-tauri-l.dts
View File

@ -1,489 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include "imx8mm-phycore-som.dtsi"
/ {
model = "PHYTEC phyGATE-Tauri-L-iMX8MM";
compatible = "phytec,imx8mm-phygate-tauri-l",
"phytec,imx8mm-phycore-som", "fsl,imx8mm";
chosen {
stdout-path = &uart3;
};
can_osc_40m: clock-can {
compatible = "fixed-clock";
clock-frequency = <40000000>;
clock-output-names = "can_osc_40m";
#clock-cells = <0>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys>;
key {
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
label = "KEY-A";
linux,code = <KEY_A>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-1 {
color = <LED_COLOR_ID_RED>;
gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
led-2 {
color = <LED_COLOR_ID_YELLOW>;
gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
};
usdhc1_pwrseq: pwr-seq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <60>;
reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
};
reg_usb_hub_vbus: regulator-hub-otg1 {
compatible = "regulator-fixed";
gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbhubpwr>;
regulator-name = "usb_hub_vbus";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
compatible = "regulator-fixed";
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1pwr>;
regulator-name = "usb_otg1_vbus";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <20000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VSD_3V3";
};
};
&ecspi1 {
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
<&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio5 2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
/* CAN MCP251XFD */
can0: can@0 {
compatible = "microchip,mcp251xfd";
reg = <0>;
clocks = <&can_osc_40m>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_int>;
spi-max-frequency = <10000000>;
};
tpm: tpm@1 {
compatible = "tcg,tpm_tis-spi";
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm>;
reg = <1>;
spi-max-frequency = <38000000>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
temp_sense0: temperature-sensor@49 {
compatible = "ti,tmp102";
reg = <0x49>;
interrupt-parent = <&gpio4>;
interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tempsense>;
#thermal-sensor-cells = <1>;
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* PCIe */
&pcie0 {
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_100M>,
<&clk IMX8MM_SYS_PLL2_250M>;
assigned-clock-rates = <10000000>, <100000000>, <250000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
/* RTC */
&rv3028 {
trickle-resistor-ohms = <3000>;
};
&uart1 {
assigned-clocks = <&clk IMX8MM_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* UART2 - RS232 */
&uart2 {
assigned-clocks = <&clk IMX8MM_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* UART - console */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
/* USB */
&usbotg1 {
adp-disable;
dr_mode = "otg";
over-current-active-low;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
srp-disable;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
vbus-supply = <&reg_usb_hub_vbus>;
status = "okay";
};
/* SD-Card */
&usdhc2 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_usdhc2_vmmc>;
vqmmc-supply = <&reg_nvcc_sd2>;
status = "okay";
};
&iomuxc {
pinctrl_can_int: can-intgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
>;
};
pinctrl_ecspi1_cs: ecspi1csgrp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00
>;
};
pinctrl_gpiokeys: keygrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0
>;
};
pinctrl_leds: leds1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
/* COEX2 */
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00
/* COEX1 */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
>;
};
pinctrl_tempsense: tempsensegrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00
>;
};
pinctrl_tpm: tpmgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_usbhubpwr: usbhubpwrgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00
>;
};
pinctrl_usbotg1pwr: usbotg1pwrgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
>;
};
pinctrl_usdhc2_100mhz: usdhc2100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
};

361
arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
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@ -1,361 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
/dts-v1/;
#include <dt-bindings/leds/leds-pca9532.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx8mp-phycore-som.dtsi"
/ {
model = "PHYTEC phyBOARD-Pollux i.MX8MP";
compatible = "phytec,imx8mp-phyboard-pollux-rdk",
"phytec,imx8mp-phycore-som", "fsl,imx8mp";
chosen {
stdout-path = &uart1;
};
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1_reg>;
gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can1-stby";
};
reg_can2_stby: regulator-can2-stby {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2_reg>;
gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can2-stby";
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus>;
gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb1_host_vbus";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
enet-phy-lane-no-swap;
};
};
};
/* CAN FD */
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can1_stby>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can2_stby>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
leds@62 {
compatible = "nxp,pca9533";
reg = <0x62>;
led-1 {
type = <PCA9532_TYPE_LED>;
};
led-2 {
type = <PCA9532_TYPE_LED>;
};
led-3 {
type = <PCA9532_TYPE_LED>;
};
};
};
&snvs_pwrkey {
status = "okay";
};
/* debug console */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* USB1 Host mode Type-A */
&usb3_phy0 {
vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
status = "okay";
};
/* USB2 4-port USB3.0 HUB */
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
fsl,permanently-attached;
fsl,disable-port-power-control;
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
/* RS232/RS485 */
&uart2 {
assigned-clocks = <&clk IMX8MP_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
};
/* SD-Card */
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&gpio1 {
gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
"PMIC_SD_VSEL", "", "", "", "", "",
"", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
};
&gpio2 {
gpio-line-names = "", "", "", "",
"", "", "", "", "", "",
"", "", "X_SD2_CD_B", "", "", "",
"", "", "", "SD2_RESET_B";
};
&gpio3 {
gpio-line-names = "", "", "", "",
"", "", "", "", "", "",
"", "", "", "", "", "",
"", "", "", "", "nCAN1_EN", "nCAN2_EN";
};
&gpio4 {
gpio-line-names = "", "", "", "",
"", "", "", "", "", "",
"", "", "", "", "", "",
"", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
>;
};
pinctrl_flexcan1_reg: flexcan1reggrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154
>;
};
pinctrl_flexcan2_reg: flexcan2reggrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
>;
};
pinctrl_usb1_vbus: usb1vbusgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140
MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140
>;
};
pinctrl_usdhc2_pins: usdhc2-gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
};

323
arch/arm/dts/imx8mp-phycore-som.dtsi
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@ -1,323 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
#include <dt-bindings/net/ti-dp83867.h>
#include "imx8mp.dtsi"
/ {
model = "PHYTEC phyCORE-i.MX8MP";
compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
aliases {
rtc0 = &rv3028;
rtc1 = &snvs_rtc;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
/* ethernet 1 */
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,min-output-impedance;
enet-phy-lane-no-swap;
};
};
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
som_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic: pmic@25 {
reg = <0x25>;
compatible = "nxp,pca9450c";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio4>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
regulators {
buck1: BUCK1 {
regulator-compatible = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-compatible = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4 {
regulator-compatible = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-compatible = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-compatible = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-compatible = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-compatible = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-compatible = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-compatible = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
ldo5: LDO5 {
regulator-compatible = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
eeprom@51 {
compatible = "atmel,24c32";
reg = <0x51>;
pagesize = <32>;
};
rv3028: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
trickle-resistor-ohms = <3000>;
};
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14
MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6
>;
};
};

2
arch/arm/mach-imx/imx8m/Kconfig
View File

@ -296,12 +296,14 @@ config TARGET_PHYCORE_IMX8MM
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
imply OF_UPSTREAM
config TARGET_PHYCORE_IMX8MP
bool "PHYTEC PHYCORE i.MX8MP"
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
imply OF_UPSTREAM
config TARGET_IMX8MM_CL_IOT_GATE
bool "CompuLab iot-gate-imx8"

4
board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
View File

@ -46,7 +46,9 @@ struct lpddr4_desc {
static const struct lpddr4_desc lpddr4_array[] = {
{ .name = "Nanya", .id = 0x05000010, .subind = 0xff,
.size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
{ .name = "Samsung", .id = 0x01061010, .subind = 0xff,
{ .name = "Samsung", .id = 0x01061010, .subind = 0x04,
.size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
{ .name = "Samsung", .id = 0x01061010, .subind = 0x02,
.size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
{ .name = "Kingston", .id = 0xff000010, .subind = 0x04,
.size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},

106
board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
View File

@ -8,6 +8,7 @@
#include <efi_loader.h>
#include <env.h>
#include <extension_board.h>
#include <fdt_support.h>
#include <hang.h>
#include <i2c.h>
#include <init.h>
@ -30,6 +31,8 @@
DECLARE_GLOBAL_DATA_PTR;
static int fec_phyaddr = -1;
#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
struct efi_fw_image fw_images[] = {
#if defined(CONFIG_TARGET_IMX8MM_CL_IOT_GATE)
@ -109,10 +112,72 @@ static int setup_fec(void)
return 0;
}
#define FDT_PHYADDR "/soc@0/bus@30800000/ethernet@30be0000/mdio/ethernet-phy@0"
#define FLIP_32B(val) (((val >> 24) & 0xff) | ((val << 8) & 0xff0000) | ((val >> 8) & 0xff00) | ((val << 24) & 0xff000000))
static int fdt_set_fec_phy_addr(void *blob)
{
u32 val;
if (fec_phyaddr < 0)
return -EINVAL;
val = FLIP_32B(fec_phyaddr);
return fdt_find_and_setprop(blob, FDT_PHYADDR, "reg", (const void *)&val,
sizeof(val), 0);
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
fdt_set_fec_phy_addr(blob);
return 0;
}
/*
* These are specific ID, purposed to distiguish between PHY vendors.
* These values are not equal to real vendors' OUI (half of MAC address)
*/
#define OUI_PHY_ATHEROS 0x1374
#define OUI_PHY_REALTEK 0x0732
int board_phy_config(struct phy_device *phydev)
{
if (IS_ENABLED(CONFIG_FEC_MXC)) {
unsigned int model, rev, oui;
int phyid1, phyid2;
unsigned int reg;
if (!IS_ENABLED(CONFIG_FEC_MXC))
return 0;
phyid1 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID1);
if (phyid1 < 0) {
printf("%s: PHYID1 registry read fail %i\n", __func__, phyid1);
return phyid1;
}
phyid2 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID2);
if (phyid2 < 0) {
printf("%s: PHYID2 registry read fail %i\n", __func__, phyid2);
return phyid2;
}
reg = phyid2 | phyid1 << 16;
if (reg == 0xffff) {
printf("%s: There is no device @%i\n", __func__, phydev->addr);
return -ENODEV;
}
rev = reg & 0xf;
reg >>= 4;
model = reg & 0x3f;
reg >>= 6;
oui = reg;
debug("%s: PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n",
__func__, phydev->addr, oui, model, rev);
switch (oui) {
case OUI_PHY_ATHEROS:
/* enable rgmii rxc skew and phy mode select to RGMII copper */
printf("phy: AR803x@%x\t", phydev->addr);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
@ -120,10 +185,45 @@ int board_phy_config(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
break;
case OUI_PHY_REALTEK:
printf("phy: RTL8211E@%x\t", phydev->addr);
/* RTL8211E-VB-CG - add TX and RX delay */
unsigned short val;
if (phydev->drv->config)
phydev->drv->config(phydev);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x07);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0xa4);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1c);
val |= (0x1 << 13) | (0x1 << 12) | (0x1 << 11);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, val);
/* LEDs: set to extension page */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0007);
/* extension Page44 */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x002c);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, 0x0430);//LCR
phy_write(phydev, MDIO_DEVAD_NONE, 0x1a, 0x0010);//LACR
/*
* To disable EEE LED mode (blinking .4s/2s)
* Extension Page5
*/
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0005);
phy_write(phydev, MDIO_DEVAD_NONE, 0x05, 0x8b82);//magic const
phy_write(phydev, MDIO_DEVAD_NONE, 0x06, 0x052b);//magic const
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x00);// Back to Page0
break;
default:
printf("%s: ERROR: unknown PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n",
__func__, phydev->addr, oui, model, rev);
return -ENOSYS;
}
fec_phyaddr = phydev->addr;
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}

3
board/phytec/phycore_imx8mm/MAINTAINERS
View File

@ -2,10 +2,7 @@ phyCORE-i.MX8M Mini
M: Teresa Remmet <t.remmet@phytec.de>
W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/
S: Maintained
F: arch/arm/dts/imx8mm-phyboard-polis-rdk.dts
F: arch/arm/dts/imx8mm-phycore-som.dtsi
F: arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
F: arch/arm/dts/imx8mm-phygate-tauri-l.dts
F: arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi
F: board/phytec/phycore_imx8mm/
F: configs/imx8mm-phygate-tauri-l_defconfig

67
board/phytec/phycore_imx8mp/Kconfig
View File

@ -12,5 +12,72 @@ config SYS_CONFIG_NAME
config IMX_CONFIG
default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg"
config PHYCORE_IMX8MP_RAM_SIZE_FIX
bool "Set phyCORE-i.MX8MP RAM size fix instead of detecting"
default false
help
RAM size is automatic being detected with the help of
the EEPROM introspection data. Set RAM size to a fix value
instead.
choice
prompt "phyCORE-i.MX8MP RAM size"
depends on PHYCORE_IMX8MP_RAM_SIZE_FIX
default PHYCORE_IMX8MP_RAM_SIZE_2GB
config PHYCORE_IMX8MP_RAM_SIZE_1GB
bool "1GB RAM"
help
Set RAM size fix to 1GB for phyCORE-i.MX8MP.
RAM frequency is configured independent.
config PHYCORE_IMX8MP_RAM_SIZE_2GB
bool "2GB RAM"
help
Set RAM size fix to 2GB for phyCORE-i.MX8MP.
RAM frequency is configured independent.
config PHYCORE_IMX8MP_RAM_SIZE_4GB
bool "4GB RAM"
help
Set RAM size fix to 4GB for phyCORE-i.MX8MP.
RAM frequency is configured independent.
config PHYCORE_IMX8MP_RAM_SIZE_8GB
bool "8GB RAM"
select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
help
Set RAM size fix to 8GB for phyCORE-i.MX8MP.
Only 2GHz RAMs are supported.
endchoice
config PHYCORE_IMX8MP_RAM_FREQ_FIX
bool "Set phyCORE-i.MX8MP RAM frequency fix instead of detecting"
default false
help
RAM frequency is automatic being detected with the help of
the EEPROM introspection data. Set RAM frequency to a fix value
instead.
choice
prompt "phyCORE-i.MX8MP RAM frequency"
depends on PHYCORE_IMX8MP_RAM_FREQ_FIX
default PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS
config PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
bool "Use 2GHz RAM timings"
help
Use fix 2GHz RAM timings for phyCORE-i.MX8MP instead of
1.5GHz timings.
config PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS
depends on !PHYCORE_IMX8MP_RAM_SIZE_8GB
bool "Use 1.5GHz RAM timings"
help
Use fix 1.5GHz RAM timings for phyCORE-i.MX8MP instead of
2GHz timings.
endchoice
source "board/phytec/common/Kconfig"
endif

1
board/phytec/phycore_imx8mp/MAINTAINERS
View File

@ -2,7 +2,6 @@ phyCORE-i.MX8M Plus
M: Teresa Remmet <t.remmet@phytec.de>
W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-plus/
S: Maintained
F: arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
F: arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
F: board/phytec/phycore_imx8mp/
F: configs/phycore-imx8mp_defconfig

153
board/phytec/phycore_imx8mp/lpddr4_timing.c
View File

@ -1839,3 +1839,156 @@ struct dram_timing_info dram_timing = {
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3000, 400, 100, },
};
void set_dram_timings_2ghz_2gb(void)
{
dram_timing.ddrc_cfg[3].val = 0x1323;
dram_timing.ddrc_cfg[4].val = 0x1e84800;
dram_timing.ddrc_cfg[5].val = 0x7a0118;
dram_timing.ddrc_cfg[8].val = 0xc00307a3;
dram_timing.ddrc_cfg[9].val = 0xc50000;
dram_timing.ddrc_cfg[10].val = 0xf4003f;
dram_timing.ddrc_cfg[11].val = 0xf30000;
dram_timing.ddrc_cfg[14].val = 0x2028222a;
dram_timing.ddrc_cfg[15].val = 0x8083f;
dram_timing.ddrc_cfg[16].val = 0xe0e000;
dram_timing.ddrc_cfg[17].val = 0x12040a12;
dram_timing.ddrc_cfg[18].val = 0x2050f0f;
dram_timing.ddrc_cfg[19].val = 0x1010009;
dram_timing.ddrc_cfg[20].val = 0x502;
dram_timing.ddrc_cfg[21].val = 0x20800;
dram_timing.ddrc_cfg[22].val = 0xe100002;
dram_timing.ddrc_cfg[23].val = 0x120;
dram_timing.ddrc_cfg[24].val = 0xc80064;
dram_timing.ddrc_cfg[25].val = 0x3e8001e;
dram_timing.ddrc_cfg[26].val = 0x3207a12;
dram_timing.ddrc_cfg[28].val = 0x4a3820e;
dram_timing.ddrc_cfg[30].val = 0x230e;
dram_timing.ddrc_cfg[37].val = 0x799;
dram_timing.ddrc_cfg[38].val = 0x9141d1c;
dram_timing.ddrc_cfg[74].val = 0x302;
dram_timing.ddrc_cfg[83].val = 0x599;
dram_timing.ddrc_cfg[99].val = 0x302;
dram_timing.ddrc_cfg[108].val = 0x599;
dram_timing.ddrphy_cfg[66].val = 0x18;
dram_timing.ddrphy_cfg[75].val = 0x1e3;
dram_timing.ddrphy_cfg[77].val = 0x1e3;
dram_timing.ddrphy_cfg[79].val = 0x1e3;
dram_timing.ddrphy_cfg[145].val = 0x3e8;
dram_timing.fsp_msg[0].drate = 4000;
dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
dram_timing.fsp_msg[3].drate = 4000;
dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0;
dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
dram_timing.ddrphy_pie[480].val = 0x465;
dram_timing.ddrphy_pie[481].val = 0xfa;
dram_timing.ddrphy_pie[482].val = 0x9c4;
dram_timing.fsp_table[0] = 4000;
}
void set_dram_timings_1_5ghz_1gb(void)
{
dram_timing.ddrc_cfg[3].val = 0x1233;
dram_timing.ddrc_cfg[5].val = 0x5b0087;
dram_timing.ddrc_cfg[6].val = 0x61027f10;
dram_timing.ddrc_cfg[7].val = 0x7b0;
dram_timing.ddrc_cfg[11].val = 0xf30000;
dram_timing.ddrc_cfg[23].val = 0x8d;
dram_timing.ddrc_cfg[45].val = 0xf070707;
dram_timing.ddrc_cfg[59].val = 0x1031;
dram_timing.ddrc_cfg[62].val = 0xc0012;
dram_timing.ddrc_cfg[77].val = 0x13;
dram_timing.ddrc_cfg[84].val = 0x1031;
dram_timing.ddrc_cfg[87].val = 0x30005;
dram_timing.ddrc_cfg[102].val = 0x5;
dram_timing.ddrphy_cfg[75].val = 0x1e3;
dram_timing.ddrphy_cfg[77].val = 0x1e3;
dram_timing.ddrphy_cfg[79].val = 0x1e3;
dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf32d;
dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf32d;
dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf32d;
dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf32d;
}
void set_dram_timings_2ghz_1gb(void)
{
set_dram_timings_2ghz_2gb();
dram_timing.ddrc_cfg[5].val = 0x7a00b4;
dram_timing.ddrc_cfg[23].val = 0xbc;
dram_timing.ddrc_cfg[45].val = 0xf070707;
dram_timing.ddrc_cfg[62].val = 0xc0012;
dram_timing.ddrc_cfg[77].val = 0x13;
dram_timing.ddrc_cfg[87].val = 0x30005;
dram_timing.ddrc_cfg[102].val = 0x5;
}
void set_dram_timings_1_5ghz_4gb(void)
{
dram_timing.ddrc_cfg[2].val = 0xa3080020;
dram_timing.ddrc_cfg[39].val = 0x17;
dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
}
void set_dram_timings_2ghz_4gb(void)
{
set_dram_timings_2ghz_2gb();
dram_timing.ddrc_cfg[2].val = 0xa3080020;
dram_timing.ddrc_cfg[39].val = 0x17;
dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
}
void set_dram_timings_2ghz_8gb(void)
{
set_dram_timings_2ghz_2gb();
dram_timing.ddrc_cfg[2].val = 0xa3080020;
dram_timing.ddrc_cfg[5].val = 0x7a017c;
dram_timing.ddrc_cfg[23].val = 0x184;
dram_timing.ddrc_cfg[39].val = 0x18;
dram_timing.ddrc_cfg[46].val = 0xf07;
dram_timing.ddrc_cfg[62].val = 0xc0026;
dram_timing.ddrc_cfg[77].val = 0x27;
dram_timing.ddrc_cfg[87].val = 0x3000a;
dram_timing.ddrc_cfg[102].val = 0xa;
dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
}

16
board/phytec/phycore_imx8mp/lpddr4_timing.h Normal file
View File

@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2024 PHYTEC Messtechnik GmbH
*/
#ifndef __LPDDR4_TIMING_H__
#define __LPDDR4_TIMING_H__
void set_dram_timings_2ghz_2gb(void);
void set_dram_timings_2ghz_1gb(void);
void set_dram_timings_2ghz_4gb(void);
void set_dram_timings_1_5ghz_1gb(void);
void set_dram_timings_1_5ghz_4gb(void);
void set_dram_timings_2ghz_8gb(void);
#endif /* __LPDDR4_TIMING_H__ */

11
board/phytec/phycore_imx8mp/phycore-imx8mp.c
View File

@ -9,6 +9,7 @@
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <env.h>
#include <init.h>
#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
@ -55,3 +56,13 @@ int board_late_init(void)
return 0;
}
int board_phys_sdram_size(phys_size_t *size)
{
if (!size)
return -EINVAL;
*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
return 0;
}

136
board/phytec/phycore_imx8mp/spl.c
View File

@ -20,95 +20,103 @@
#include <power/pca9450.h>
#include <spl.h>
#include "lpddr4_timing.h"
#include "../common/imx8m_som_detection.h"
DECLARE_GLOBAL_DATA_PTR;
#define EEPROM_ADDR 0x51
#define EEPROM_ADDR_FALLBACK 0x59
#define EEPROM_ADDR 0x51
#define EEPROM_ADDR_FALLBACK 0x59
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
}
enum phytec_imx8mp_ddr_eeprom_code {
PHYTEC_IMX8MP_DDR_1GB = 2,
PHYTEC_IMX8MP_DDR_2GB = 3,
PHYTEC_IMX8MP_DDR_4GB = 5,
PHYTEC_IMX8MP_DDR_8GB = 7,
PHYTEC_IMX8MP_DDR_4GB_2GHZ = 8,
};
void spl_dram_init(void)
{
int ret;
bool use_2ghz_timings = false;
enum phytec_imx8mp_ddr_eeprom_code size = PHYTEC_EEPROM_INVAL;
ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
EEPROM_ADDR_FALLBACK);
if (ret)
if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX))
goto out;
ret = phytec_imx8m_detect(NULL);
if (!ret)
phytec_print_som_info(NULL);
u8 rev = phytec_get_rev(NULL);
u8 somtype = phytec_get_som_type(NULL);
if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) {
dram_timing.ddrc_cfg[3].val = 0x1323;
dram_timing.ddrc_cfg[4].val = 0x1e84800;
dram_timing.ddrc_cfg[5].val = 0x7a0118;
dram_timing.ddrc_cfg[8].val = 0xc00307a3;
dram_timing.ddrc_cfg[9].val = 0xc50000;
dram_timing.ddrc_cfg[10].val = 0xf4003f;
dram_timing.ddrc_cfg[11].val = 0xf30000;
dram_timing.ddrc_cfg[14].val = 0x2028222a;
dram_timing.ddrc_cfg[15].val = 0x8083f;
dram_timing.ddrc_cfg[16].val = 0xe0e000;
dram_timing.ddrc_cfg[17].val = 0x12040a12;
dram_timing.ddrc_cfg[18].val = 0x2050f0f;
dram_timing.ddrc_cfg[19].val = 0x1010009;
dram_timing.ddrc_cfg[20].val = 0x502;
dram_timing.ddrc_cfg[21].val = 0x20800;
dram_timing.ddrc_cfg[22].val = 0xe100002;
dram_timing.ddrc_cfg[23].val = 0x120;
dram_timing.ddrc_cfg[24].val = 0xc80064;
dram_timing.ddrc_cfg[25].val = 0x3e8001e;
dram_timing.ddrc_cfg[26].val = 0x3207a12;
dram_timing.ddrc_cfg[28].val = 0x4a3820e;
dram_timing.ddrc_cfg[30].val = 0x230e;
dram_timing.ddrc_cfg[37].val = 0x799;
dram_timing.ddrc_cfg[38].val = 0x9141d1c;
dram_timing.ddrc_cfg[74].val = 0x302;
dram_timing.ddrc_cfg[83].val = 0x599;
dram_timing.ddrc_cfg[99].val = 0x302;
dram_timing.ddrc_cfg[108].val = 0x599;
dram_timing.ddrphy_cfg[66].val = 0x18;
dram_timing.ddrphy_cfg[75].val = 0x1e3;
dram_timing.ddrphy_cfg[77].val = 0x1e3;
dram_timing.ddrphy_cfg[79].val = 0x1e3;
dram_timing.ddrphy_cfg[145].val = 0x3e8;
dram_timing.fsp_msg[0].drate = 4000;
dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
dram_timing.fsp_msg[3].drate = 4000;
dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0;
dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
dram_timing.ddrphy_pie[480].val = 0x465;
dram_timing.ddrphy_pie[481].val = 0xfa;
dram_timing.ddrphy_pie[482].val = 0x9c4;
dram_timing.fsp_table[0] = 4000;
if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) {
if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_1GB))
size = PHYTEC_IMX8MP_DDR_1GB;
else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_2GB))
size = PHYTEC_IMX8MP_DDR_2GB;
else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_4GB))
size = PHYTEC_IMX8MP_DDR_4GB;
else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB))
size = PHYTEC_IMX8MP_DDR_8GB;
} else {
size = phytec_get_imx8m_ddr_size(NULL);
}
if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_FREQ_FIX)) {
if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) {
if (size == PHYTEC_IMX8MP_DDR_4GB)
size = PHYTEC_IMX8MP_DDR_4GB_2GHZ;
else
use_2ghz_timings = true;
} else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS)) {
if (size == PHYTEC_IMX8MP_DDR_4GB_2GHZ)
size = PHYTEC_IMX8MP_DDR_4GB;
else
use_2ghz_timings = false;
}
} else {
u8 rev = phytec_get_rev(NULL);
u8 somtype = phytec_get_som_type(NULL);
if (rev != PHYTEC_EEPROM_INVAL &&
(rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1)))
use_2ghz_timings = true;
}
switch (size) {
case PHYTEC_IMX8MP_DDR_1GB:
if (use_2ghz_timings)
set_dram_timings_2ghz_1gb();
else
set_dram_timings_1_5ghz_1gb();
break;
case PHYTEC_IMX8MP_DDR_2GB:
if (use_2ghz_timings)
set_dram_timings_2ghz_2gb();
break;
case PHYTEC_IMX8MP_DDR_4GB:
set_dram_timings_1_5ghz_4gb();
break;
case PHYTEC_IMX8MP_DDR_4GB_2GHZ:
set_dram_timings_2ghz_4gb();
break;
case PHYTEC_IMX8MP_DDR_8GB:
set_dram_timings_2ghz_8gb();
break;
default:
goto out;
}
ddr_init(&dram_timing);
return;
out:
printf("Could not detect correct RAM size. Fallback to default.\n");
ddr_init(&dram_timing);
}

3
board/toradex/common/tdx-cfg-block.c
View File

@ -158,6 +158,9 @@ const struct toradex_som toradex_modules[] = {
[85] = { "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) },
[86] = { "Verdin iMX8M Mini DualLite 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
[87] = { "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
[88] = { "Aquila AM69 Octa 32GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) },
[89] = { "Verdin iMX95 Hexa 16GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) },
[90] = { "Verdin iMX8M Mini Quad 4GB WB ET", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
};
struct pid4list {

3
board/toradex/common/tdx-cfg-block.h
View File

@ -113,6 +113,9 @@ enum {
APALIS_IMX6Q_IT_NOWINCE, /* 85 */
VERDIN_IMX8MMDL_2G_IT,
VERDIN_IMX8MMQ_2G_IT_NO_CAN,
AQUILA_AM69O_32G_WIFI_BT_IT,
VERDIN_IMX95H_16G_WIFI_BT_IT,
VERDIN_IMX8MMQ_4G_WIFI_BT_ET, /* 90 */
};
enum {

14
board/toradex/verdin-imx8mm/lpddr4_timing.c
View File

@ -18,7 +18,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400000, 0xa1080020},
{0x3d400020, 0x202},
{0x3d400024, 0x3a980},
{0x3d400064, 0x2d00d2},
{0x3d400064, 0x2d011d},
{0x3d4000d0, 0xc00305ba},
{0x3d4000d4, 0x940000},
{0x3d4000dc, 0xd4002d},
@ -34,7 +34,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d40011c, 0x402},
{0x3d400130, 0x20600},
{0x3d400134, 0xc100002},
{0x3d400138, 0xd8},
{0x3d400138, 0x123},
{0x3d400144, 0x96004b},
{0x3d400180, 0x2ee0017},
{0x3d400184, 0x2605b8e},
@ -56,7 +56,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400204, 0x80808},
{0x3d400214, 0x7070707},
{0x3d400218, 0x7070707},
{0x3d40021c, 0xf0f},
{0x3d40021c, 0xf07},
{0x3d400250, 0x29001701},
{0x3d400254, 0x2c},
{0x3d40025c, 0x4000030},
@ -71,7 +71,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d402020, 0x0},
{0x3d402024, 0x7d00},
{0x3d402050, 0x20d040},
{0x3d402064, 0x6001c},
{0x3d402064, 0x60026},
{0x3d4020dc, 0x840000},
{0x3d4020e0, 0x310000},
{0x3d4020e8, 0x66004d},
@ -86,7 +86,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d40211c, 0x302},
{0x3d402130, 0x20300},
{0x3d402134, 0xa100002},
{0x3d402138, 0x1d},
{0x3d402138, 0x27},
{0x3d402144, 0x14000a},
{0x3d402180, 0x640004},
{0x3d402190, 0x3818200},
@ -96,7 +96,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d403020, 0x0},
{0x3d403024, 0x1f40},
{0x3d403050, 0x20d040},
{0x3d403064, 0x30007},
{0x3d403064, 0x3000A},
{0x3d4030dc, 0x840000},
{0x3d4030e0, 0x310000},
{0x3d4030e8, 0x66004d},
@ -111,7 +111,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d40311c, 0x302},
{0x3d403130, 0x20300},
{0x3d403134, 0xa100002},
{0x3d403138, 0x8},
{0x3d403138, 0xA},
{0x3d403144, 0x50003},
{0x3d403180, 0x190004},
{0x3d403190, 0x3818200},

5
board/toradex/verdin-imx8mm/verdin-imx8mm.c
View File

@ -84,7 +84,8 @@ static void select_dt_from_module_version(void)
*/
is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) ||
(tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT) ||
(tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN);
(tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN) ||
(tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET);
}
switch (get_pcb_revision()) {
@ -117,7 +118,7 @@ int board_phys_sdram_size(phys_size_t *size)
if (!size)
return -EINVAL;
*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
return 0;
}

2
configs/imx8mm-phygate-tauri-l_defconfig
View File

@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phygate-tauri-l"
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phygate-tauri-l"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PHYCORE_IMX8MM=y
CONFIG_SYS_MONITOR_LEN=524288

2
configs/phycore-imx8mm_defconfig
View File

@ -9,7 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=80000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phyboard-polis-rdk"
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phyboard-polis-rdk"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PHYCORE_IMX8MM=y
CONFIG_SYS_MONITOR_LEN=524288

2
configs/phycore-imx8mp_defconfig
View File

@ -9,7 +9,7 @@ CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk"
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_PHYCORE_IMX8MP=y
CONFIG_PHYTEC_SOM_DETECTION=y

2
include/configs/imx8mm-cl-iot-gate.h
View File

@ -136,7 +136,7 @@
#define CFG_SYS_FSL_USDHC_NUM 2
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CFG_FEC_MXC_PHYADDR 0
#define CFG_FEC_MXC_PHYADDR -1 /* Auto search of PHY on MII */
/* USB Configs */
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)

4
include/configs/phycore_imx8mp.h
View File

@ -22,6 +22,8 @@
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000
#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* 5GB */
#endif /* __PHYCORE_IMX8MP_H */

6
include/configs/verdin-imx8mm.h
View File

@ -58,8 +58,10 @@
#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE (long)(SZ_2G + SZ_1G)
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE (long)(SZ_1G)
/* USB Configs */
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)