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tegra20: enable SPL for tegra20 boards
Add SPL options to tegra20 config files and enable SPL build for tegra20 boards. Also remove redundant code from u-boot that is not contained in SPL. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Allen Martin
Albert ARIBAUD
parent
a49716aa7c
commit
12b7b70cb0
9
Makefile
9
Makefile
@ -381,6 +381,15 @@ ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
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ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
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ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
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ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
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ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
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# enable combined SPL/u-boot/dtb rules for tegra
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ifeq ($(SOC),tegra20)
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ifeq ($(CONFIG_OF_SEPARATE),y)
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ALL-y += $(obj)u-boot-dtb-tegra.bin
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else
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ALL-y += $(obj)u-boot-nodtb-tegra.bin
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endif
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endif
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all: $(ALL-y) $(SUBDIR_EXAMPLES)
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all: $(ALL-y) $(SUBDIR_EXAMPLES)
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$(obj)u-boot.dtb: $(obj)u-boot
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$(obj)u-boot.dtb: $(obj)u-boot
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@ -32,7 +32,7 @@ COBJS += cache_v7.o
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COBJS += cpu.o
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COBJS += cpu.o
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COBJS += syslib.o
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COBJS += syslib.o
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ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
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ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
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SOBJS += lowlevel_init.o
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SOBJS += lowlevel_init.o
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endif
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endif
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@ -133,7 +133,6 @@ reset:
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orr r0, r0, #0xd3
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orr r0, r0, #0xd3
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msr cpsr,r0
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msr cpsr,r0
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#if !defined(CONFIG_TEGRA20)
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/*
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/*
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* Setup vector:
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* Setup vector:
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* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
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* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
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@ -149,7 +148,6 @@ reset:
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ldr r0, =_start
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ldr r0, =_start
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mcr p15, 0, r0, c12, c0, 0 @Set VBAR
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mcr p15, 0, r0, c12, c0, 0 @Set VBAR
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#endif
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#endif
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#endif /* !Tegra20 */
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/* the mask ROM code should have PLL and others stable */
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/* the mask ROM code should have PLL and others stable */
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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@ -20,16 +20,11 @@
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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* MA 02111-1307 USA
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*/
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*/
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/arch/tegra20.h>
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#include <asm/arch/ap20.h>
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#include <asm/arch/ap20.h>
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#include <asm/arch/clk_rst.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fuse.h>
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#include <asm/arch/fuse.h>
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#include <asm/arch/gp_padctrl.h>
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#include <asm/arch/gp_padctrl.h>
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#include <asm/arch/pmc.h>
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#include <asm/arch/pmc.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/scu.h>
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#include <asm/arch/scu.h>
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#include <asm/arch/warmboot.h>
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#include <asm/arch/warmboot.h>
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#include <common.h>
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#include <common.h>
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@ -68,235 +63,7 @@ int tegra_get_chip_type(void)
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return TEGRA_SOC_UNKNOWN;
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return TEGRA_SOC_UNKNOWN;
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}
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}
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/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
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static void enable_scu(void)
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static int ap20_cpu_is_cortexa9(void)
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{
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u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
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return id == (PG_UP_TAG_0_PID_CPU & 0xff);
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}
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void init_pllx(void)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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struct clk_pll_simple *pll =
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&clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE];
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u32 reg;
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/* If PLLX is already enabled, just return */
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if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
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return;
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/* Set PLLX_MISC */
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writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
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/* Use 12MHz clock here */
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reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
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reg |= 1000 << PLL_DIVN_SHIFT;
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writel(reg, &pll->pll_base);
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reg |= PLL_ENABLE_MASK;
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writel(reg, &pll->pll_base);
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reg &= ~PLL_BYPASS_MASK;
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writel(reg, &pll->pll_base);
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}
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static void enable_cpu_clock(int enable)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 clk;
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/*
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* NOTE:
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* Regardless of whether the request is to enable or disable the CPU
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* clock, every processor in the CPU complex except the master (CPU 0)
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* will have it's clock stopped because the AVP only talks to the
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* master. The AVP does not know (nor does it need to know) that there
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* are multiple processors in the CPU complex.
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*/
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if (enable) {
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/* Initialize PLLX */
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init_pllx();
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/* Wait until all clocks are stable */
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udelay(PLL_STABILIZATION_DELAY);
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writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
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writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
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}
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/*
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* Read the register containing the individual CPU clock enables and
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* always stop the clock to CPU 1.
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*/
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clk = readl(&clkrst->crc_clk_cpu_cmplx);
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clk |= 1 << CPU1_CLK_STP_SHIFT;
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/* Stop/Unstop the CPU clock */
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clk &= ~CPU0_CLK_STP_MASK;
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clk |= !enable << CPU0_CLK_STP_SHIFT;
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writel(clk, &clkrst->crc_clk_cpu_cmplx);
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clock_enable(PERIPH_ID_CPU);
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}
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static int is_cpu_powered(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
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return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
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}
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static void remove_cpu_io_clamps(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
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u32 reg;
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/* Remove the clamps on the CPU I/O signals */
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reg = readl(&pmc->pmc_remove_clamping);
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reg |= CPU_CLMP;
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writel(reg, &pmc->pmc_remove_clamping);
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/* Give I/O signals time to stabilize */
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udelay(IO_STABILIZATION_DELAY);
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}
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static void powerup_cpu(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
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u32 reg;
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int timeout = IO_STABILIZATION_DELAY;
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if (!is_cpu_powered()) {
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/* Toggle the CPU power state (OFF -> ON) */
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reg = readl(&pmc->pmc_pwrgate_toggle);
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reg &= PARTID_CP;
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reg |= START_CP;
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writel(reg, &pmc->pmc_pwrgate_toggle);
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/* Wait for the power to come up */
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while (!is_cpu_powered()) {
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if (timeout-- == 0)
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printf("CPU failed to power up!\n");
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else
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udelay(10);
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}
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/*
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* Remove the I/O clamps from CPU power partition.
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* Recommended only on a Warm boot, if the CPU partition gets
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* power gated. Shouldn't cause any harm when called after a
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* cold boot according to HW, probably just redundant.
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*/
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remove_cpu_io_clamps();
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}
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}
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static void enable_cpu_power_rail(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
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u32 reg;
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reg = readl(&pmc->pmc_cntrl);
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reg |= CPUPWRREQ_OE;
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writel(reg, &pmc->pmc_cntrl);
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/*
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* The TI PMU65861C needs a 3.75ms delay between enabling
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* the power rail and enabling the CPU clock. This delay
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* between SM1EN and SM1 is for switching time + the ramp
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* up of the voltage to the CPU (VDD_CPU from PMU).
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*/
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udelay(3750);
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}
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static void reset_A9_cpu(int reset)
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{
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/*
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* NOTE: Regardless of whether the request is to hold the CPU in reset
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* or take it out of reset, every processor in the CPU complex
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* except the master (CPU 0) will be held in reset because the
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* AVP only talks to the master. The AVP does not know that there
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* are multiple processors in the CPU complex.
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*/
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/* Hold CPU 1 in reset, and CPU 0 if asked */
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reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
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reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
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reset);
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/* Enable/Disable master CPU reset */
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reset_set_enable(PERIPH_ID_CPU, reset);
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}
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static void clock_enable_coresight(int enable)
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{
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u32 rst, src;
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clock_set_enable(PERIPH_ID_CORESIGHT, enable);
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reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
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if (enable) {
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/*
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* Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
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* 1.5, giving an effective frequency of 144MHz.
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* Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
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* (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
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*/
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src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
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clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
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/* Unlock the CPU CoreSight interfaces */
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rst = 0xC5ACCE55;
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writel(rst, CSITE_CPU_DBG0_LAR);
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writel(rst, CSITE_CPU_DBG1_LAR);
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}
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}
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void start_cpu(u32 reset_vector)
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{
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/* Enable VDD_CPU */
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enable_cpu_power_rail();
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/* Hold the CPUs in reset */
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reset_A9_cpu(1);
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/* Disable the CPU clock */
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enable_cpu_clock(0);
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/* Enable CoreSight */
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clock_enable_coresight(1);
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/*
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* Set the entry point for CPU execution from reset,
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* if it's a non-zero value.
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*/
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if (reset_vector)
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writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
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/* Enable the CPU clock */
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enable_cpu_clock(1);
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/* If the CPU doesn't already have power, power it up */
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powerup_cpu();
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/* Take the CPU out of reset */
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reset_A9_cpu(0);
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}
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void halt_avp(void)
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{
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for (;;) {
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writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
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| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
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FLOW_CTLR_HALT_COP_EVENTS);
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}
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}
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void enable_scu(void)
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{
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{
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struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
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struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
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u32 reg;
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u32 reg;
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@ -332,7 +99,7 @@ static u32 get_odmdata(void)
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return odmdata;
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return odmdata;
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}
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}
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void init_pmc_scratch(void)
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static void init_pmc_scratch(void)
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{
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{
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struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
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struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
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u32 odmdata;
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u32 odmdata;
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@ -347,27 +114,8 @@ void init_pmc_scratch(void)
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writel(odmdata, &pmc->pmc_scratch20);
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writel(odmdata, &pmc->pmc_scratch20);
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}
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}
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void tegra20_start(void)
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void s_init(void)
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{
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{
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struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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/* If we are the AVP, start up the first Cortex-A9 */
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if (!ap20_cpu_is_cortexa9()) {
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/* enable JTAG */
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writel(0xC0, &pmt->pmt_cfg_ctl);
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/*
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* If we are ARM7 - give it a different stack. We are about to
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* start up the A9 which will want to use this one.
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*/
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asm volatile("mov sp, %0\n"
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: : "r"(AVP_EARLY_BOOT_STACK_LIMIT));
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start_cpu((u32)_start);
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halt_avp();
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/* not reached */
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}
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/* Init PMC scratch memory */
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/* Init PMC scratch memory */
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init_pmc_scratch();
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init_pmc_scratch();
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@ -23,12 +23,12 @@
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#include <common.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/arch/ap20.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/pmc.h>
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#include <asm/arch/pmc.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/sys_proto.h>
|
||||||
#include <asm/arch/tegra20.h>
|
#include <asm/arch/tegra20.h>
|
||||||
|
#include <asm/arch/warmboot.h>
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
@ -80,27 +80,6 @@ int checkboard(void)
|
|||||||
}
|
}
|
||||||
#endif /* CONFIG_DISPLAY_BOARDINFO */
|
#endif /* CONFIG_DISPLAY_BOARDINFO */
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_CPU_INIT
|
|
||||||
/*
|
|
||||||
* Note this function is executed by the ARM7TDMI AVP. It does not return
|
|
||||||
* in this case. It is also called once the A9 starts up, but does nothing in
|
|
||||||
* that case.
|
|
||||||
*/
|
|
||||||
int arch_cpu_init(void)
|
|
||||||
{
|
|
||||||
/* Fire up the Cortex A9 */
|
|
||||||
tegra20_start();
|
|
||||||
|
|
||||||
/* We didn't do this init in start.S, so do it now */
|
|
||||||
cpu_init_cp15();
|
|
||||||
|
|
||||||
/* Initialize essential common plls */
|
|
||||||
clock_early_init();
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static int uart_configs[] = {
|
static int uart_configs[] = {
|
||||||
#if defined(CONFIG_TEGRA20_UARTA_UAA_UAB)
|
#if defined(CONFIG_TEGRA20_UARTA_UAA_UAB)
|
||||||
FUNCMUX_UART1_UAA_UAB,
|
FUNCMUX_UART1_UAA_UAB,
|
||||||
|
|||||||
18
boards.cfg
18
boards.cfg
@ -265,10 +265,10 @@ s5pc210_universal arm armv7 universal_c210 samsung
|
|||||||
smdk5250 arm armv7 smdk5250 samsung exynos
|
smdk5250 arm armv7 smdk5250 samsung exynos
|
||||||
smdkv310 arm armv7 smdkv310 samsung exynos
|
smdkv310 arm armv7 smdkv310 samsung exynos
|
||||||
trats arm armv7 trats samsung exynos
|
trats arm armv7 trats samsung exynos
|
||||||
harmony arm armv7 harmony nvidia tegra20
|
harmony arm armv7:arm720t harmony nvidia tegra20
|
||||||
seaboard arm armv7 seaboard nvidia tegra20
|
seaboard arm armv7:arm720t seaboard nvidia tegra20
|
||||||
ventana arm armv7 ventana nvidia tegra20
|
ventana arm armv7:arm720t ventana nvidia tegra20
|
||||||
whistler arm armv7 whistler nvidia tegra20
|
whistler arm armv7:arm720t whistler nvidia tegra20
|
||||||
u8500_href arm armv7 u8500 st-ericsson u8500
|
u8500_href arm armv7 u8500 st-ericsson u8500
|
||||||
snowball arm armv7 snowball st-ericsson u8500
|
snowball arm armv7 snowball st-ericsson u8500
|
||||||
actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
|
actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
|
||||||
@ -295,11 +295,11 @@ xaeniax arm pxa
|
|||||||
zipitz2 arm pxa
|
zipitz2 arm pxa
|
||||||
colibri_pxa270 arm pxa - toradex
|
colibri_pxa270 arm pxa - toradex
|
||||||
jornada arm sa1100
|
jornada arm sa1100
|
||||||
plutux arm armv7 plutux avionic-design tegra20
|
plutux arm armv7:arm720t plutux avionic-design tegra20
|
||||||
medcom arm armv7 medcom avionic-design tegra20
|
medcom arm armv7:arm720t medcom avionic-design tegra20
|
||||||
tec arm armv7 tec avionic-design tegra20
|
tec arm armv7:arm720t tec avionic-design tegra20
|
||||||
paz00 arm armv7 paz00 compal tegra20
|
paz00 arm armv7:arm720t paz00 compal tegra20
|
||||||
trimslice arm armv7 trimslice compulab tegra20
|
trimslice arm armv7:arm720t trimslice compulab tegra20
|
||||||
atngw100 avr32 at32ap - atmel at32ap700x
|
atngw100 avr32 at32ap - atmel at32ap700x
|
||||||
atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
|
atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
|
||||||
atstk1003 avr32 at32ap atstk1000 atmel at32ap700x
|
atstk1003 avr32 at32ap atstk1000 atmel at32ap700x
|
||||||
|
|||||||
@ -146,4 +146,69 @@
|
|||||||
"fdt_high=01100000\0" \
|
"fdt_high=01100000\0" \
|
||||||
BOOTCMDS_COMMON
|
BOOTCMDS_COMMON
|
||||||
|
|
||||||
|
/* overrides for SPL build here */
|
||||||
|
#ifdef CONFIG_SPL_BUILD
|
||||||
|
|
||||||
|
/* remove devicetree support */
|
||||||
|
#ifdef CONFIG_OF_CONTROL
|
||||||
|
#undef CONFIG_OF_CONTROL
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* remove SERIAL_MULTI */
|
||||||
|
#ifdef CONFIG_SERIAL_MULTI
|
||||||
|
#undef CONFIG_SERIAL_MULTI
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* remove I2C support */
|
||||||
|
#ifdef CONFIG_TEGRA_I2C
|
||||||
|
#undef CONFIG_TEGRA_I2C
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_CMD_I2C
|
||||||
|
#undef CONFIG_CMD_I2C
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* remove MMC support */
|
||||||
|
#ifdef CONFIG_MMC
|
||||||
|
#undef CONFIG_MMC
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_GENERIC_MMC
|
||||||
|
#undef CONFIG_GENERIC_MMC
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_TEGRA20_MMC
|
||||||
|
#undef CONFIG_TEGRA20_MMC
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_CMD_MMC
|
||||||
|
#undef CONFIG_CMD_MMC
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* remove partitions/filesystems */
|
||||||
|
#ifdef CONFIG_DOS_PARTITION
|
||||||
|
#undef CONFIG_DOS_PARTITION
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_EFI_PARTITION
|
||||||
|
#undef CONFIG_EFI_PARTITION
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_CMD_EXT2
|
||||||
|
#undef CONFIG_CMD_EXT2
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_CMD_FAT
|
||||||
|
#undef CONFIG_CMD_FAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* remove USB */
|
||||||
|
#ifdef CONFIG_USB_EHCI
|
||||||
|
#undef CONFIG_USB_EHCI
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_USB_EHCI_TEGRA
|
||||||
|
#undef CONFIG_USB_EHCI_TEGRA
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_USB_STORAGE
|
||||||
|
#undef CONFIG_USB_STORAGE
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_CMD_USB
|
||||||
|
#undef CONFIG_CMD_USB
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* CONFIG_SPL_BUILD */
|
||||||
|
|
||||||
#endif /* __TEGRA20_COMMON_POST_H */
|
#endif /* __TEGRA20_COMMON_POST_H */
|
||||||
|
|||||||
@ -43,8 +43,6 @@
|
|||||||
|
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||||
|
|
||||||
#define CONFIG_ARCH_CPU_INIT /* Fire up the A9 core */
|
|
||||||
|
|
||||||
#include <asm/arch/tegra20.h> /* get chip and board defs */
|
#include <asm/arch/tegra20.h> /* get chip and board defs */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -53,8 +51,6 @@
|
|||||||
#define CONFIG_DISPLAY_CPUINFO
|
#define CONFIG_DISPLAY_CPUINFO
|
||||||
#define CONFIG_DISPLAY_BOARDINFO
|
#define CONFIG_DISPLAY_BOARDINFO
|
||||||
|
|
||||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
|
||||||
|
|
||||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||||
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
|
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
|
||||||
|
|
||||||
@ -182,7 +178,7 @@
|
|||||||
#define PHYS_SDRAM_1 TEGRA20_SDRC_CS0
|
#define PHYS_SDRAM_1 TEGRA20_SDRC_CS0
|
||||||
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
|
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
|
||||||
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x00108000
|
#define CONFIG_SYS_TEXT_BASE 0x0010c000
|
||||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
|
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
|
||||||
@ -195,4 +191,20 @@
|
|||||||
#define CONFIG_CMD_GPIO
|
#define CONFIG_CMD_GPIO
|
||||||
#define CONFIG_CMD_ENTERRCM
|
#define CONFIG_CMD_ENTERRCM
|
||||||
#define CONFIG_CMD_BOOTZ
|
#define CONFIG_CMD_BOOTZ
|
||||||
|
|
||||||
|
/* Defines for SPL */
|
||||||
|
#define CONFIG_SPL
|
||||||
|
#define CONFIG_SPL_NAND_SIMPLE
|
||||||
|
#define CONFIG_SPL_TEXT_BASE 0x00108000
|
||||||
|
#define CONFIG_SPL_MAX_SIZE 0x00004000
|
||||||
|
#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
|
||||||
|
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
|
||||||
|
#define CONFIG_SPL_STACK 0x000ffffc
|
||||||
|
|
||||||
|
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||||
|
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||||
|
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||||
|
#define CONFIG_SPL_GPIO_SUPPORT
|
||||||
|
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
|
||||||
|
|
||||||
#endif /* __TEGRA20_COMMON_H */
|
#endif /* __TEGRA20_COMMON_H */
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user