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mvebu: dts: a80x0: Sync the DB DTS with standard config A
Sync the default configuration of Armada-8040-DB with Marvell u-boot-2015 standard configuration "A" for the same board. The standard configuration "A" enables 2 PCIe slots on CP0 and 3 PCIe slots on CP1. This is the main configuration used for u-boot and Linux tests. This patch also re-arranges the DTS file entries by grouping all nodes related to CP0 and CP1. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Konstantin Porotchkin
Stefan Roese
parent
3f75e0ce7b
commit
0f712f2c8d
@ -83,28 +83,68 @@
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&cpm_pinctl {
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&cpm_pinctl {
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/* MPP Bus:
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/* MPP Bus:
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* [0-31] = 0xff: Keep default CP0_shared_pins:
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* [0-31] = 0xff: Keep default CP0_shared_pins
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* [11] CLKOUT_MPP_11 (out)
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* [11] CLKOUT_MPP_11 (out)
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* [23] LINK_RD_IN_CP2CP (in)
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* [23] LINK_RD_IN_CP2CP (in)
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* [25] CLKOUT_MPP_25 (out)
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* [25] CLKOUT_MPP_25 (out)
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* [29] AVS_FB_IN_CP2CP (in)
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* [29] AVS_FB_IN_CP2CP (in)
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* [32,34] SMI
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* [32,34] GE_MDIO/MDC
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* [31] GPIO: push button/Wake
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* [33] GPIO: GE_INT#/push button/Wake
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* [35-36] GPIO
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* [35] MSS_GPIO[3]: MSS_PWDN
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* [37-38] I2C
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* [36] MSS_GPIO[5]: MSS_VTT_EN
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* [40-41] SATA[0/1]_PRESENT_ACTIVEn
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* [37-38] I2C0
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* [42-43] XSMI
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* [39] PTP_CLK
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* [44-55] RGMII1
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* [40-41] SATA[0/1]_PRESENT_ACTIVEn
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* [56-62] SD
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* [42-43] XG_MDC/XG_MDIO (XSMI)
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* [44-55] RGMII1
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* [56-62] SD
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*/
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0 7 0 7 0 0 2 2 0
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0xff 0xff 0x7 0x0 0x7 0xa 0xa 0x2 0x2 0x5
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0 0 8 8 1 1 1 1 1 1
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0x9 0x9 0x8 0x8 0x1 0x1 0x1 0x1 0x1 0x1
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1 1 1 1 1 1 0xe 0xe 0xe 0xe
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0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
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0xe 0xe 0xe >;
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0xe 0xe 0xe>;
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};
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&cpm_comphy {
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/* Serdes Configuration:
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* Lane 0: PCIe0 (x1)
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* Lane 1: SATA0
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* Lane 2: KR (10G)
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* Lane 3: SATA1
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* Lane 4: USB3_HOST1
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* Lane 5: PCIe2 (x1)
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*/
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phy0 {
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phy-type = <PHY_TYPE_PEX0>;
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};
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phy1 {
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phy-type = <PHY_TYPE_SATA0>;
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};
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phy2 {
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phy-type = <PHY_TYPE_KR>;
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};
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phy3 {
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phy-type = <PHY_TYPE_SATA1>;
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};
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phy4 {
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phy-type = <PHY_TYPE_USB3_HOST1>;
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};
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phy5 {
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phy-type = <PHY_TYPE_PEX2>;
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};
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};
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/* CON6 on CP0 expansion */
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&cpm_pcie0 {
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status = "okay";
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};
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&cpm_pcie1 {
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status = "disabled";
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};
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};
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/* CON5 on CP0 expansion */
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/* CON5 on CP0 expansion */
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@ -134,21 +174,69 @@
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status = "okay";
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status = "okay";
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};
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};
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&cpm_utmi0 {
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status = "okay";
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};
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&cpm_utmi1 {
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status = "okay";
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};
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&cps_pinctl {
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&cps_pinctl {
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/* MPP Bus:
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/* MPP Bus:
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* [0-11] RGMII0
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* [0-11] RGMII0
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* [13-16] SPI1
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* [13-16] SPI1
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* [27,31] GE_MDIO/MDC
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* [27,31] GE_MDIO/MDC
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* [32-62] = 0xff: Keep default CP1_shared_pins:
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* [28] SATA1_PRESENT_ACTIVEn
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* [29-30] UART0
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* [32-62] = 0xff: Keep default CP1_shared_pins
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*/
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
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pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
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0x3 0x3 0xff 0x3 0x3 0x3 0x3 0xff 0xff 0xff
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0x3 0x3 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0x9 0xa
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0xff 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xA 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff >;
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0xff 0xff 0xff>;
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};
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&cps_comphy {
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/* Serdes Configuration:
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* Lane 0: PCIe0 (x1)
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* Lane 1: SATA0
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* Lane 2: KR (10G)
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* Lane 3: SATA1
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* Lane 4: PCIe1 (x1)
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* Lane 5: PCIe2 (x1)
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*/
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phy0 {
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phy-type = <PHY_TYPE_PEX0>;
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};
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phy1 {
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phy-type = <PHY_TYPE_SATA0>;
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};
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phy2 {
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phy-type = <PHY_TYPE_KR>;
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};
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phy3 {
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phy-type = <PHY_TYPE_SATA1>;
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};
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phy4 {
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phy-type = <PHY_TYPE_PEX1>;
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};
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phy5 {
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phy-type = <PHY_TYPE_PEX2>;
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};
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};
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/* CON6 on CP1 expansion */
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&cps_pcie0 {
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status = "okay";
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};
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&cps_pcie1 {
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status = "okay";
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};
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};
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/* CON5 on CP1 expansion */
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/* CON5 on CP1 expansion */
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@ -200,86 +288,6 @@
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status = "okay";
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status = "okay";
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};
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};
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&cpm_comphy {
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/*
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* Serdes Configuration:
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* Lane 0: SGMII2
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* Lane 1: USB3_HOST0
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* Lane 2: KR (10G)
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* Lane 3: SATA1
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* Lane 4: USB3_HOST1
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* Lane 5: PEX2x1
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*/
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phy0 {
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phy-type = <PHY_TYPE_SGMII2>;
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phy-speed = <PHY_SPEED_3_125G>;
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};
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phy1 {
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phy-type = <PHY_TYPE_USB3_HOST0>;
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};
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phy2 {
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phy-type = <PHY_TYPE_KR>;
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};
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phy3 {
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phy-type = <PHY_TYPE_SATA1>;
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};
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phy4 {
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phy-type = <PHY_TYPE_USB3_HOST1>;
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};
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phy5 {
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phy-type = <PHY_TYPE_PEX2>;
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};
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};
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&cps_comphy {
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/*
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* Serdes Configuration:
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* Lane 0: SGMII2
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* Lane 1: USB3_HOST0
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* Lane 2: KR (10G)
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* Lane 3: SATA1
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* Lane 4: Unconnected
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* Lane 5: PEX2x1
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*/
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phy0 {
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phy-type = <PHY_TYPE_SGMII2>;
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phy-speed = <PHY_SPEED_3_125G>;
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};
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phy1 {
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phy-type = <PHY_TYPE_USB3_HOST0>;
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};
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phy2 {
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phy-type = <PHY_TYPE_KR>;
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};
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phy3 {
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phy-type = <PHY_TYPE_SATA1>;
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};
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phy4 {
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phy-type = <PHY_TYPE_UNCONNECTED>;
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};
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phy5 {
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phy-type = <PHY_TYPE_PEX2>;
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};
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};
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&cpm_utmi0 {
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status = "okay";
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};
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&cpm_utmi1 {
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status = "okay";
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};
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&cps_utmi0 {
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&cps_utmi0 {
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status = "okay";
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status = "okay";
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};
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};
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