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clk: mediatek: mt8188: refactor driver to improve readability
Refactor some part of the driver to improve readability and future additions: - use CLK_TOP_NR_CLK for added clocks - rename the id map to make it more clear that the map applies to top clocks only - refactor the id map to improve readability - xtal2_rate is only used for PLL clocks, so only the apmixedsys clock tree needs it. Remove it elsewhere. Signed-off-by: Julien Stephan <jstephan@baylibre.com>
This commit is contained in:
Julien Stephan
Tom Rini
parent
2797fa3efd
commit
0cdd01dbde
@ -20,12 +20,13 @@
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#define MT8188_PLL_FMIN (1500UL * MHZ)
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/* Missing topckgen clocks definition in dt-bindings */
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#define CLK_TOP_ADSPPLL 206
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#define CLK_TOP_CLK13M 207
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#define CLK_TOP_CLK26M 208
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#define CLK_TOP_CLK32K 209
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#define CLK_TOP_IMGPLL 210
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#define CLK_TOP_MSDCPLL 211
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#define CLK_TOP_ADSPPLL CLK_TOP_NR_CLK
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#define CLK_TOP_CLK13M CLK_TOP_NR_CLK + 1
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#define CLK_TOP_CLK26M CLK_TOP_NR_CLK + 2
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#define CLK_TOP_CLK32K CLK_TOP_NR_CLK + 3
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#define CLK_TOP_IMGPLL CLK_TOP_NR_CLK + 4
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#define CLK_TOP_MSDCPLL CLK_TOP_NR_CLK + 5
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#define CLK_TOP_FULL_NR_CLK CLK_TOP_NR_CLK + 6
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/* apmixedsys */
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#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
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@ -1141,219 +1142,211 @@ static const struct mtk_composite top_muxes[] = {
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MUX_GATE(CLK_TOP_SRCK, srck_parents, 0x0128, 16, 4, 23),
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};
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static const int mt8188_id_offs_map[] = {
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88, /* CLK_TOP_AXI */
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89, /* CLK_TOP_SPM */
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90, /* CLK_TOP_SCP */
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91, /* CLK_TOP_BUS_AXIMEM */
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92, /* CLK_TOP_VPP */
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93, /* CLK_TOP_ETHDR */
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94, /* CLK_TOP_IPE */
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95, /* CLK_TOP_CAM */
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96, /* CLK_TOP_CCU */
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97, /* CLK_TOP_CCU_AHB */
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98, /* CLK_TOP_IMG */
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99, /* CLK_TOP_CAMTM */
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100, /* CLK_TOP_DSP */
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101, /* CLK_TOP_DSP1 */
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102, /* CLK_TOP_DSP2 */
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103, /* CLK_TOP_DSP3 */
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104, /* CLK_TOP_DSP4 */
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105, /* CLK_TOP_DSP5 */
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106, /* CLK_TOP_DSP6 */
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107, /* CLK_TOP_DSP7 */
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108, /* CLK_TOP_MFG_CORE_TMP */
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109, /* CLK_TOP_CAMTG */
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110, /* CLK_TOP_CAMTG2 */
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111, /* CLK_TOP_CAMTG3 */
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112, /* CLK_TOP_UART */
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113, /* CLK_TOP_SPI */
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114, /* CLK_TOP_MSDC50_0_HCLK */
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115, /* CLK_TOP_MSDC50_0 */
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116, /* CLK_TOP_MSDC30_1 */
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117, /* CLK_TOP_MSDC30_2 */
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118, /* CLK_TOP_INTDIR */
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119, /* CLK_TOP_AUD_INTBUS */
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120, /* CLK_TOP_AUDIO_H */
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121, /* CLK_TOP_PWRAP_ULPOSC */
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122, /* CLK_TOP_ATB */
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123, /* CLK_TOP_SSPM */
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124, /* CLK_TOP_DP */
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125, /* CLK_TOP_EDP */
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126, /* CLK_TOP_DPI */
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127, /* CLK_TOP_DISP_PWM0 */
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128, /* CLK_TOP_DISP_PWM1 */
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129, /* CLK_TOP_USB_TOP */
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130, /* CLK_TOP_SSUSB_XHCI */
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131, /* CLK_TOP_USB_TOP_2P */
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132, /* CLK_TOP_SSUSB_XHCI_2P */
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133, /* CLK_TOP_USB_TOP_3P */
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134, /* CLK_TOP_SSUSB_XHCI_3P */
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135, /* CLK_TOP_I2C */
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136, /* CLK_TOP_SENINF */
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137, /* CLK_TOP_SENINF1 */
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138, /* CLK_TOP_GCPU */
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139, /* CLK_TOP_VENC */
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140, /* CLK_TOP_VDEC */
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141, /* CLK_TOP_PWM */
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142, /* CLK_TOP_MCUPM */
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143, /* CLK_TOP_SPMI_P_MST */
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144, /* CLK_TOP_SPMI_M_MST */
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145, /* CLK_TOP_DVFSRC */
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146, /* CLK_TOP_TL */
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147, /* CLK_TOP_AES_MSDCFDE */
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148, /* CLK_TOP_DSI_OCC */
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149, /* CLK_TOP_WPE_VPP */
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150, /* CLK_TOP_HDCP */
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151, /* CLK_TOP_HDCP_24M */
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152, /* CLK_TOP_HDMI_APB */
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153, /* CLK_TOP_SNPS_ETH_250M */
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154, /* CLK_TOP_SNPS_ETH_62P4M_PTP */
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155, /* CLK_TOP_SNPS_ETH_50M_RMII */
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156, /* CLK_TOP_ADSP */
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157, /* CLK_TOP_AUDIO_LOCAL_BUS */
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158, /* CLK_TOP_ASM_H */
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159, /* CLK_TOP_ASM_L */
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160, /* CLK_TOP_APLL1 */
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161, /* CLK_TOP_APLL2 */
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162, /* CLK_TOP_APLL3 */
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163, /* CLK_TOP_APLL4 */
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164, /* CLK_TOP_APLL5 */
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165, /* CLK_TOP_I2SO1 */
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166, /* CLK_TOP_I2SO2 */
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167, /* CLK_TOP_I2SI1 */
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168, /* CLK_TOP_I2SI2 */
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169, /* CLK_TOP_DPTX */
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170, /* CLK_TOP_AUD_IEC */
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171, /* CLK_TOP_A1SYS_HP */
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172, /* CLK_TOP_A2SYS */
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173, /* CLK_TOP_A3SYS */
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174, /* CLK_TOP_A4SYS */
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175, /* CLK_TOP_ECC */
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176, /* CLK_TOP_SPINOR */
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177, /* CLK_TOP_ULPOSC */
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178, /* CLK_TOP_SRCK */
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-1, /* CLK_TOP_MFG_CK_FAST_REF */
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9, /* CLK_TOP_MAINPLL_D3 */
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10, /* CLK_TOP_MAINPLL_D4 */
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11, /* CLK_TOP_MAINPLL_D4_D2 */
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12, /* CLK_TOP_MAINPLL_D4_D4 */
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13, /* CLK_TOP_MAINPLL_D4_D8 */
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14, /* CLK_TOP_MAINPLL_D5 */
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15, /* CLK_TOP_MAINPLL_D5_D2 */
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16, /* CLK_TOP_MAINPLL_D5_D4 */
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17, /* CLK_TOP_MAINPLL_D5_D8 */
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18, /* CLK_TOP_MAINPLL_D6 */
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19, /* CLK_TOP_MAINPLL_D6_D2 */
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20, /* CLK_TOP_MAINPLL_D6_D4 */
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21, /* CLK_TOP_MAINPLL_D6_D8 */
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22, /* CLK_TOP_MAINPLL_D7 */
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23, /* CLK_TOP_MAINPLL_D7_D2 */
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24, /* CLK_TOP_MAINPLL_D7_D4 */
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25, /* CLK_TOP_MAINPLL_D7_D8 */
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26, /* CLK_TOP_MAINPLL_D9 */
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27, /* CLK_TOP_UNIVPLL_D2 */
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28, /* CLK_TOP_UNIVPLL_D3 */
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29, /* CLK_TOP_UNIVPLL_D4 */
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30, /* CLK_TOP_UNIVPLL_D4_D2 */
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31, /* CLK_TOP_UNIVPLL_D4_D4 */
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32, /* CLK_TOP_UNIVPLL_D4_D8 */
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33, /* CLK_TOP_UNIVPLL_D5 */
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34, /* CLK_TOP_UNIVPLL_D5_D2 */
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35, /* CLK_TOP_UNIVPLL_D5_D4 */
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36, /* CLK_TOP_UNIVPLL_D5_D8 */
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37, /* CLK_TOP_UNIVPLL_D6 */
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38, /* CLK_TOP_UNIVPLL_D6_D2 */
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39, /* CLK_TOP_UNIVPLL_D6_D4 */
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40, /* CLK_TOP_UNIVPLL_D6_D8 */
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41, /* CLK_TOP_UNIVPLL_D7 */
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42, /* CLK_TOP_UNIVPLL_192M */
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43, /* CLK_TOP_UNIVPLL_192M_D4 */
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44, /* CLK_TOP_UNIVPLL_192M_D8 */
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45, /* CLK_TOP_UNIVPLL_192M_D10 */
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46, /* CLK_TOP_UNIVPLL_192M_D16 */
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47, /* CLK_TOP_UNIVPLL_192M_D32 */
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48, /* CLK_TOP_APLL1_D3 */
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49, /* CLK_TOP_APLL1_D4 */
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50, /* CLK_TOP_APLL2_D3 */
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51, /* CLK_TOP_APLL2_D4 */
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52, /* CLK_TOP_APLL3_D4 */
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53, /* CLK_TOP_APLL4_D4 */
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54, /* CLK_TOP_APLL5_D4 */
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55, /* CLK_TOP_MMPLL_D4 */
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56, /* CLK_TOP_MMPLL_D4_D2 */
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57, /* CLK_TOP_MMPLL_D5 */
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58, /* CLK_TOP_MMPLL_D5_D2 */
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59, /* CLK_TOP_MMPLL_D5_D4 */
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60, /* CLK_TOP_MMPLL_D6 */
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61, /* CLK_TOP_MMPLL_D6_D2 */
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62, /* CLK_TOP_MMPLL_D7 */
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62, /* CLK_TOP_MMPLL_D9 */
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-1, /* CLK_TOP_TVDPLL1 */
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64, /* CLK_TOP_TVDPLL1_D2 */
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65, /* CLK_TOP_TVDPLL1_D4 */
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66, /* CLK_TOP_TVDPLL1_D8 */
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67, /* CLK_TOP_TVDPLL1_D16 */
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-1, /* CLK_TOP_TVDPLL2 */
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68, /* CLK_TOP_TVDPLL2_D2 */
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69, /* CLK_TOP_TVDPLL2_D4 */
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70, /* CLK_TOP_TVDPLL2_D8 */
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71, /* CLK_TOP_TVDPLL2_D16 */
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73, /* CLK_TOP_MSDCPLL_D2 */
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74, /* CLK_TOP_MSDCPLL_D16 */
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-1, /* CLK_TOP_ETHPLL */
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75, /* CLK_TOP_ETHPLL_D2 */
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76, /* CLK_TOP_ETHPLL_D4 */
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77, /* CLK_TOP_ETHPLL_D8 */
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78, /* CLK_TOP_ETHPLL_D10 */
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79, /* CLK_TOP_ADSPPLL_D2 */
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80, /* CLK_TOP_ADSPPLL_D4 */
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81, /* CLK_TOP_ADSPPLL_D8 */
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0, /* CLK_TOP_ULPOSC1 */
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82, /* CLK_TOP_ULPOSC1_D2 */
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83, /* CLK_TOP_ULPOSC1_D4 */
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84, /* CLK_TOP_ULPOSC1_D8 */
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85, /* CLK_TOP_ULPOSC1_D7 */
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86, /* CLK_TOP_ULPOSC1_D10 */
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87, /* CLK_TOP_ULPOSC1_D16 */
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1, /* CLK_TOP_MPHONE_SLAVE_BCK */
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2, /* CLK_TOP_PAD_FPC */
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3, /* CLK_TOP_466M_FMEM */
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4, /* CLK_TOP_PEXTP_PIPE */
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5, /* CLK_TOP_DSI_PHY */
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-1, /* CLK_TOP_APLL12_CK_DIV0 */
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-1, /* CLK_TOP_APLL12_CK_DIV1 */
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-1, /* CLK_TOP_APLL12_CK_DIV2 */
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-1, /* CLK_TOP_APLL12_CK_DIV3 */
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-1, /* CLK_TOP_APLL12_CK_DIV4 */
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-1, /* CLK_TOP_APLL12_CK_DIV9 */
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188, /* CLK_TOP_CFGREG_CLOCK_EN_VPP0 */
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189, /* CLK_TOP_CFGREG_CLOCK_EN_VPP1 */
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190, /* CLK_TOP_CFGREG_CLOCK_EN_VDO0 */
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191, /* CLK_TOP_CFGREG_CLOCK_EN_VDO1 */
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192, /* CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS */
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193, /* CLK_TOP_CFGREG_F26M_VPP0 */
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194, /* CLK_TOP_CFGREG_F26M_VPP1 */
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195, /* CLK_TOP_CFGREG_F26M_VDO0 */
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196, /* CLK_TOP_CFGREG_F26M_VDO1 */
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197, /* CLK_TOP_CFGREG_AUD_F26M_AUD */
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198, /* CLK_TOP_CFGREG_UNIPLL_SES */
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199, /* CLK_TOP_CFGREG_F_PCIE_PHY_REF */
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200, /* CLK_TOP_SSUSB_TOP_REF */
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201, /* CLK_TOP_SSUSB_PHY_REF */
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202, /* CLK_TOP_SSUSB_TOP_P1_REF */
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203, /* CLK_TOP_SSUSB_PHY_P1_REF */
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204, /* CLK_TOP_SSUSB_TOP_P2_REF */
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205, /* CLK_TOP_SSUSB_PHY_P2_REF */
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206, /* CLK_TOP_SSUSB_TOP_P3_REF */
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207, /* CLK_TOP_SSUSB_PHY_P3_REF */
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-1, /* CLK_TOP_NR_CLK */
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-1, /* CLK_TOP_ADSPPLL */
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6, /* CLK_TOP_CLK13M */
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7, /* CLK_TOP_CLK26M */
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8, /* CLK_TOP_CLK32K */
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-1, /* CLK_TOP_IMGPLL */
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72, /* CLK_TOP_MSDCPLL */
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static const int mt8188_id_top_offs_map[] = {
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[0 ... CLK_TOP_FULL_NR_CLK - 1] = -1,
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/* FIXED */
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[CLK_TOP_ULPOSC1] = 0,
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[CLK_TOP_MPHONE_SLAVE_BCK] = 1,
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[CLK_TOP_PAD_FPC] = 2,
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[CLK_TOP_466M_FMEM] = 3,
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[CLK_TOP_PEXTP_PIPE] = 4,
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[CLK_TOP_DSI_PHY] = 5,
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[CLK_TOP_CLK13M] = 6,
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[CLK_TOP_CLK26M] = 7,
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[CLK_TOP_CLK32K] = 8,
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/* FACTOR */
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[CLK_TOP_MAINPLL_D3] = 9,
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[CLK_TOP_MAINPLL_D4] = 10,
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[CLK_TOP_MAINPLL_D4_D2] = 11,
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[CLK_TOP_MAINPLL_D4_D4] = 12,
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[CLK_TOP_MAINPLL_D4_D8] = 13,
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[CLK_TOP_MAINPLL_D5] = 14,
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[CLK_TOP_MAINPLL_D5_D2] = 15,
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[CLK_TOP_MAINPLL_D5_D4] = 16,
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[CLK_TOP_MAINPLL_D5_D8] = 17,
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[CLK_TOP_MAINPLL_D6] = 18,
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[CLK_TOP_MAINPLL_D6_D2] = 19,
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[CLK_TOP_MAINPLL_D6_D4] = 20,
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[CLK_TOP_MAINPLL_D6_D8] = 21,
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[CLK_TOP_MAINPLL_D7] = 22,
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[CLK_TOP_MAINPLL_D7_D2] = 23,
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[CLK_TOP_MAINPLL_D7_D4] = 24,
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[CLK_TOP_MAINPLL_D7_D8] = 25,
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[CLK_TOP_MAINPLL_D9] = 26,
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[CLK_TOP_UNIVPLL_D2] = 27,
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[CLK_TOP_UNIVPLL_D3] = 28,
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[CLK_TOP_UNIVPLL_D4] = 29,
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[CLK_TOP_UNIVPLL_D4_D2] = 30,
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[CLK_TOP_UNIVPLL_D4_D4] = 31,
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[CLK_TOP_UNIVPLL_D4_D8] = 32,
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[CLK_TOP_UNIVPLL_D5] = 33,
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[CLK_TOP_UNIVPLL_D5_D2] = 34,
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[CLK_TOP_UNIVPLL_D5_D4] = 35,
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[CLK_TOP_UNIVPLL_D5_D8] = 36,
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[CLK_TOP_UNIVPLL_D6] = 37,
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[CLK_TOP_UNIVPLL_D6_D2] = 38,
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[CLK_TOP_UNIVPLL_D6_D4] = 39,
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[CLK_TOP_UNIVPLL_D6_D8] = 40,
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[CLK_TOP_UNIVPLL_D7] = 41,
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[CLK_TOP_UNIVPLL_192M] = 42,
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[CLK_TOP_UNIVPLL_192M_D4] = 43,
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[CLK_TOP_UNIVPLL_192M_D8] = 44,
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[CLK_TOP_UNIVPLL_192M_D10] = 45,
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[CLK_TOP_UNIVPLL_192M_D16] = 46,
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[CLK_TOP_UNIVPLL_192M_D32] = 47,
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[CLK_TOP_APLL1_D3] = 48,
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[CLK_TOP_APLL1_D4] = 49,
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[CLK_TOP_APLL2_D3] = 50,
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[CLK_TOP_APLL2_D4] = 51,
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[CLK_TOP_APLL3_D4] = 52,
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[CLK_TOP_APLL4_D4] = 53,
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[CLK_TOP_APLL5_D4] = 54,
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[CLK_TOP_MMPLL_D4] = 55,
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[CLK_TOP_MMPLL_D4_D2] = 56,
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[CLK_TOP_MMPLL_D5] = 57,
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[CLK_TOP_MMPLL_D5_D2] = 58,
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[CLK_TOP_MMPLL_D5_D4] = 59,
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[CLK_TOP_MMPLL_D6] = 60,
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[CLK_TOP_MMPLL_D6_D2] = 61,
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[CLK_TOP_MMPLL_D7] = 62,
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[CLK_TOP_MMPLL_D9] = 62,
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[CLK_TOP_TVDPLL1_D2] = 64,
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[CLK_TOP_TVDPLL1_D4] = 65,
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[CLK_TOP_TVDPLL1_D8] = 66,
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[CLK_TOP_TVDPLL1_D16] = 67,
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[CLK_TOP_TVDPLL2_D2] = 68,
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[CLK_TOP_TVDPLL2_D4] = 69,
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[CLK_TOP_TVDPLL2_D8] = 70,
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[CLK_TOP_TVDPLL2_D16] = 71,
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[CLK_TOP_MSDCPLL] = 72,
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[CLK_TOP_MSDCPLL_D2] = 73,
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[CLK_TOP_MSDCPLL_D16] = 74,
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[CLK_TOP_ETHPLL_D2] = 75,
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[CLK_TOP_ETHPLL_D4] = 76,
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[CLK_TOP_ETHPLL_D8] = 77,
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[CLK_TOP_ETHPLL_D10] = 78,
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[CLK_TOP_ADSPPLL_D2] = 79,
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[CLK_TOP_ADSPPLL_D4] = 80,
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[CLK_TOP_ADSPPLL_D8] = 81,
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[CLK_TOP_ULPOSC1_D2] = 82,
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[CLK_TOP_ULPOSC1_D4] = 83,
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[CLK_TOP_ULPOSC1_D8] = 84,
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[CLK_TOP_ULPOSC1_D7] = 85,
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[CLK_TOP_ULPOSC1_D10] = 86,
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[CLK_TOP_ULPOSC1_D16] = 87,
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/* MUX */
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[CLK_TOP_AXI] = 88,
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[CLK_TOP_SPM] = 89,
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[CLK_TOP_SCP] = 90,
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[CLK_TOP_BUS_AXIMEM] = 91,
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[CLK_TOP_VPP] = 92,
|
||||
[CLK_TOP_ETHDR] = 93,
|
||||
[CLK_TOP_IPE] = 94,
|
||||
[CLK_TOP_CAM] = 95,
|
||||
[CLK_TOP_CCU] = 96,
|
||||
[CLK_TOP_CCU_AHB] = 97,
|
||||
[CLK_TOP_IMG] = 98,
|
||||
[CLK_TOP_CAMTM] = 99,
|
||||
[CLK_TOP_DSP] = 100,
|
||||
[CLK_TOP_DSP1] = 101,
|
||||
[CLK_TOP_DSP2] = 102,
|
||||
[CLK_TOP_DSP3] = 103,
|
||||
[CLK_TOP_DSP4] = 104,
|
||||
[CLK_TOP_DSP5] = 105,
|
||||
[CLK_TOP_DSP6] = 106,
|
||||
[CLK_TOP_DSP7] = 107,
|
||||
[CLK_TOP_MFG_CORE_TMP] = 108,
|
||||
[CLK_TOP_CAMTG] = 109,
|
||||
[CLK_TOP_CAMTG2] = 110,
|
||||
[CLK_TOP_CAMTG3] = 111,
|
||||
[CLK_TOP_UART] = 112,
|
||||
[CLK_TOP_SPI] = 113,
|
||||
[CLK_TOP_MSDC50_0_HCLK] = 114,
|
||||
[CLK_TOP_MSDC50_0] = 115,
|
||||
[CLK_TOP_MSDC30_1] = 116,
|
||||
[CLK_TOP_MSDC30_2] = 117,
|
||||
[CLK_TOP_INTDIR] = 118,
|
||||
[CLK_TOP_AUD_INTBUS] = 119,
|
||||
[CLK_TOP_AUDIO_H] = 120,
|
||||
[CLK_TOP_PWRAP_ULPOSC] = 121,
|
||||
[CLK_TOP_ATB] = 122,
|
||||
[CLK_TOP_SSPM] = 123,
|
||||
[CLK_TOP_DP] = 124,
|
||||
[CLK_TOP_EDP] = 125,
|
||||
[CLK_TOP_DPI] = 126,
|
||||
[CLK_TOP_DISP_PWM0] = 127,
|
||||
[CLK_TOP_DISP_PWM1] = 128,
|
||||
[CLK_TOP_USB_TOP] = 129,
|
||||
[CLK_TOP_SSUSB_XHCI] = 130,
|
||||
[CLK_TOP_USB_TOP_2P] = 131,
|
||||
[CLK_TOP_SSUSB_XHCI_2P] = 132,
|
||||
[CLK_TOP_USB_TOP_3P] = 133,
|
||||
[CLK_TOP_SSUSB_XHCI_3P] = 134,
|
||||
[CLK_TOP_I2C] = 135,
|
||||
[CLK_TOP_SENINF] = 136,
|
||||
[CLK_TOP_SENINF1] = 137,
|
||||
[CLK_TOP_GCPU] = 138,
|
||||
[CLK_TOP_VENC] = 139,
|
||||
[CLK_TOP_VDEC] = 140,
|
||||
[CLK_TOP_PWM] = 141,
|
||||
[CLK_TOP_MCUPM] = 142,
|
||||
[CLK_TOP_SPMI_P_MST] = 143,
|
||||
[CLK_TOP_SPMI_M_MST] = 144,
|
||||
[CLK_TOP_DVFSRC] = 145,
|
||||
[CLK_TOP_TL] = 146,
|
||||
[CLK_TOP_AES_MSDCFDE] = 147,
|
||||
[CLK_TOP_DSI_OCC] = 148,
|
||||
[CLK_TOP_WPE_VPP] = 149,
|
||||
[CLK_TOP_HDCP] = 150,
|
||||
[CLK_TOP_HDCP_24M] = 151,
|
||||
[CLK_TOP_HDMI_APB] = 152,
|
||||
[CLK_TOP_SNPS_ETH_250M] = 153,
|
||||
[CLK_TOP_SNPS_ETH_62P4M_PTP] = 154,
|
||||
[CLK_TOP_SNPS_ETH_50M_RMII] = 155,
|
||||
[CLK_TOP_ADSP] = 156,
|
||||
[CLK_TOP_AUDIO_LOCAL_BUS] = 157,
|
||||
[CLK_TOP_ASM_H] = 158,
|
||||
[CLK_TOP_ASM_L] = 159,
|
||||
[CLK_TOP_APLL1] = 160,
|
||||
[CLK_TOP_APLL2] = 161,
|
||||
[CLK_TOP_APLL3] = 162,
|
||||
[CLK_TOP_APLL4] = 163,
|
||||
[CLK_TOP_APLL5] = 164,
|
||||
[CLK_TOP_I2SO1] = 165,
|
||||
[CLK_TOP_I2SO2] = 166,
|
||||
[CLK_TOP_I2SI1] = 167,
|
||||
[CLK_TOP_I2SI2] = 168,
|
||||
[CLK_TOP_DPTX] = 169,
|
||||
[CLK_TOP_AUD_IEC] = 170,
|
||||
[CLK_TOP_A1SYS_HP] = 171,
|
||||
[CLK_TOP_A2SYS] = 172,
|
||||
[CLK_TOP_A3SYS] = 173,
|
||||
[CLK_TOP_A4SYS] = 174,
|
||||
[CLK_TOP_ECC] = 175,
|
||||
[CLK_TOP_SPINOR] = 176,
|
||||
[CLK_TOP_ULPOSC] = 177,
|
||||
[CLK_TOP_SRCK] = 178,
|
||||
/* GATE */
|
||||
[CLK_TOP_CFGREG_CLOCK_EN_VPP0] = 179,
|
||||
[CLK_TOP_CFGREG_CLOCK_EN_VPP1] = 180,
|
||||
[CLK_TOP_CFGREG_CLOCK_EN_VDO0] = 181,
|
||||
[CLK_TOP_CFGREG_CLOCK_EN_VDO1] = 182,
|
||||
[CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS] = 183,
|
||||
[CLK_TOP_CFGREG_F26M_VPP0] = 184,
|
||||
[CLK_TOP_CFGREG_F26M_VPP1] = 185,
|
||||
[CLK_TOP_CFGREG_F26M_VDO0] = 186,
|
||||
[CLK_TOP_CFGREG_F26M_VDO1] = 187,
|
||||
[CLK_TOP_CFGREG_AUD_F26M_AUD] = 188,
|
||||
[CLK_TOP_CFGREG_UNIPLL_SES] = 189,
|
||||
[CLK_TOP_CFGREG_F_PCIE_PHY_REF] = 190,
|
||||
[CLK_TOP_SSUSB_TOP_REF] = 191,
|
||||
[CLK_TOP_SSUSB_PHY_REF] = 192,
|
||||
[CLK_TOP_SSUSB_TOP_P1_REF] = 193,
|
||||
[CLK_TOP_SSUSB_PHY_P1_REF] = 194,
|
||||
[CLK_TOP_SSUSB_TOP_P2_REF] = 195,
|
||||
[CLK_TOP_SSUSB_PHY_P2_REF] = 196,
|
||||
[CLK_TOP_SSUSB_TOP_P3_REF] = 197,
|
||||
[CLK_TOP_SSUSB_PHY_P3_REF] = 198,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs top0_cg_regs = {
|
||||
@ -1411,12 +1404,11 @@ static const struct mtk_gate topckgen_cg_clks[] = {
|
||||
|
||||
static const struct mtk_clk_tree mt8188_topckgen_clk_tree = {
|
||||
.xtal_rate = 26 * MHZ,
|
||||
.xtal2_rate = 26 * MHZ,
|
||||
.id_offs_map = mt8188_id_offs_map,
|
||||
.id_offs_map_size = ARRAY_SIZE(mt8188_id_offs_map),
|
||||
.fdivs_offs = 9, /* CLK_TOP_MAINPLL_D3 */
|
||||
.muxes_offs = 88, /* CLK_TOP_AXI */
|
||||
.gates_offs = 188, /* CLK_TOP_CFGREG_CLOCK_EN_VPP0 */
|
||||
.id_offs_map = mt8188_id_top_offs_map,
|
||||
.id_offs_map_size = ARRAY_SIZE(mt8188_id_top_offs_map),
|
||||
.fdivs_offs = mt8188_id_top_offs_map[CLK_TOP_MAINPLL_D3],
|
||||
.muxes_offs = mt8188_id_top_offs_map[CLK_TOP_AXI],
|
||||
.gates_offs = mt8188_id_top_offs_map[CLK_TOP_CFGREG_CLOCK_EN_VPP0],
|
||||
.fclks = top_fixed_clks,
|
||||
.fdivs = top_fixed_divs,
|
||||
.muxes = top_muxes,
|
||||
@ -1590,7 +1582,6 @@ static const struct mtk_gate infracfg_ao_clks[] = {
|
||||
|
||||
static const struct mtk_clk_tree mt8188_infracfg_ao_clk_tree = {
|
||||
.xtal_rate = 26 * MHZ,
|
||||
.xtal2_rate = 26 * MHZ,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs peri_ao_cg_regs = {
|
||||
@ -1624,7 +1615,6 @@ static const struct mtk_gate pericfg_ao_clks[] = {
|
||||
|
||||
static const struct mtk_clk_tree mt8188_pericfg_ao_clk_tree = {
|
||||
.xtal_rate = 26 * MHZ,
|
||||
.xtal2_rate = 26 * MHZ,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
|
||||
@ -1659,17 +1649,14 @@ static const struct mtk_gate imp_iic_wrap_en_clks[] = {
|
||||
|
||||
const struct mtk_clk_tree mt8188_imp_iic_wrap_c_clk_tree = {
|
||||
.xtal_rate = 26 * MHZ,
|
||||
.xtal2_rate = 26 * MHZ,
|
||||
};
|
||||
|
||||
const struct mtk_clk_tree mt8188_imp_iic_wrap_w_clk_tree = {
|
||||
.xtal_rate = 26 * MHZ,
|
||||
.xtal2_rate = 26 * MHZ,
|
||||
};
|
||||
|
||||
const struct mtk_clk_tree mt8188_imp_iic_wrap_en_clk_tree = {
|
||||
.xtal_rate = 26 * MHZ,
|
||||
.xtal2_rate = 26 * MHZ,
|
||||
};
|
||||
|
||||
static int mt8188_apmixedsys_probe(struct udevice *dev)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user