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phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver
Add Starfive JH7110 PCIe 2.0 PHY driver, which is generic PHY driver and can be used as USB 3.0 driver. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Tested-by: E Shattow <lucent@gmail.com>
This commit is contained in:
Minda Chen
Marek Vasut
parent
20281cc309
commit
0cbecd6954
@ -4,6 +4,13 @@
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menu "Starfive PHY driver"
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config PHY_STARFIVE_JH7110_PCIE
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bool "Starfive JH7110 PCIe 2.0 PHY driver"
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depends on PHY
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help
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Enable this to support the Starfive JH7110 PCIE 2.0/USB 3.0 PHY.
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Generic PHY driver JH7110 USB 3.0/ PCIe 2.0.
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config PHY_STARFIVE_JH7110_USB2
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bool "Starfive JH7110 USB 2.0 PHY driver"
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depends on PHY
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@ -3,4 +3,5 @@
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# Copyright (C) 2023 Starfive
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#
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obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
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obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o
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239
drivers/phy/starfive/phy-jh7110-pcie.c
Normal file
239
drivers/phy/starfive/phy-jh7110-pcie.c
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@ -0,0 +1,239 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* StarFive JH7110 PCIe 2.0 PHY driver
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*
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* Copyright (C) 2024 StarFive Technology Co., Ltd.
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* Author: Minda Chen <minda.chen@starfivetech.com>
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*/
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#include <asm/io.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <errno.h>
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#include <generic-phy.h>
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#include <regmap.h>
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#include <soc.h>
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#include <syscon.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include "phy-jh7110-usb-syscon.h"
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#define PCIE_KVCO_LEVEL_OFF 0x28
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#define PCIE_USB3_PHY_PLL_CTL_OFF 0x7c
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#define PCIE_USB3_PHY_SS_MODE BIT(4)
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#define PCIE_KVCO_TUNE_SIGNAL_OFF 0x80
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#define PHY_KVCO_FINE_TUNE_LEVEL 0x91
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#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc
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#define PCIE_USB3_PHY_MODE 0x1
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#define PCIE_BUS_WIDTH 0x2
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#define PCIE_USB3_PHY_ENABLE 0x1
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#define PCIE_USB3_PHY_SPLIT 0x1
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struct jh7110_pcie_phy {
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struct phy *phy;
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struct regmap *stg_syscon;
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struct regmap *sys_syscon;
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void __iomem *regs;
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struct regmap_field *phy_mode;
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struct regmap_field *bus_width;
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struct regmap_field *usb3_phy_en;
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struct regmap_field *usb_split;
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enum phy_mode mode;
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};
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static int phy_pcie_mode_set(struct jh7110_pcie_phy *data, bool usb_mode)
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{
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unsigned int phy_mode, width, usb3_phy, ss_mode, split;
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/* default is PCIe mode */
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if (!data->stg_syscon || !data->sys_syscon) {
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if (usb_mode) {
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dev_err(data->phy->dev, "doesn't support USB3 mode\n");
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return -EINVAL;
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}
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return 0;
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}
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if (usb_mode) {
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phy_mode = PCIE_USB3_PHY_MODE;
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width = 0;
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usb3_phy = PCIE_USB3_PHY_ENABLE;
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ss_mode = PCIE_USB3_PHY_SS_MODE;
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split = 0;
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} else {
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phy_mode = 0;
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width = PCIE_BUS_WIDTH;
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usb3_phy = 0;
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ss_mode = 0;
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split = PCIE_USB3_PHY_SPLIT;
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}
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regmap_field_write(data->phy_mode, phy_mode);
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regmap_field_write(data->bus_width, width);
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regmap_field_write(data->usb3_phy_en, usb3_phy);
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clrsetbits_le32(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF,
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PCIE_USB3_PHY_SS_MODE, ss_mode);
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regmap_field_write(data->usb_split, split);
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return 0;
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}
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static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy)
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{
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/* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
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writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
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writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF);
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}
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static int jh7110_pcie_phy_set_mode(struct phy *phy,
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enum phy_mode mode, int submode)
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{
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struct udevice *dev = phy->dev;
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struct jh7110_pcie_phy *pcie_phy = dev_get_priv(dev);
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int ret;
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if (mode == pcie_phy->mode)
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return 0;
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switch (mode) {
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case PHY_MODE_USB_HOST:
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case PHY_MODE_USB_DEVICE:
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case PHY_MODE_USB_OTG:
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ret = phy_pcie_mode_set(pcie_phy, 1);
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if (ret)
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return ret;
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break;
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case PHY_MODE_PCIE:
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phy_pcie_mode_set(pcie_phy, 0);
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break;
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default:
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return -EINVAL;
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}
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dev_dbg(phy->dev, "Changing PHY mode to %d\n", mode);
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pcie_phy->mode = mode;
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return 0;
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}
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static const struct phy_ops jh7110_pcie_phy_ops = {
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.set_mode = jh7110_pcie_phy_set_mode,
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};
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static int phy_stg_regfield_init(struct udevice *dev, int mode, int usb3)
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{
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struct jh7110_pcie_phy *phy = dev_get_priv(dev);
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struct reg_field phy_mode = REG_FIELD(mode, 20, 21);
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struct reg_field bus_width = REG_FIELD(usb3, 2, 3);
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struct reg_field usb3_phy_en = REG_FIELD(usb3, 4, 4);
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phy->phy_mode = devm_regmap_field_alloc(dev, phy->stg_syscon, phy_mode);
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if (IS_ERR(phy->phy_mode)) {
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dev_err(dev, "PHY mode reg field init failed\n");
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return PTR_ERR(phy->phy_mode);
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}
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phy->bus_width = devm_regmap_field_alloc(dev, phy->stg_syscon, bus_width);
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if (IS_ERR(phy->bus_width)) {
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dev_err(dev, "PHY bus width reg field init failed\n");
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return PTR_ERR(phy->bus_width);
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}
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phy->usb3_phy_en = devm_regmap_field_alloc(dev, phy->stg_syscon, usb3_phy_en);
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if (IS_ERR(phy->usb3_phy_en)) {
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dev_err(dev, "USB3 PHY enable field init failed\n");
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return PTR_ERR(phy->bus_width);
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}
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return 0;
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}
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static int phy_sys_regfield_init(struct udevice *dev, int split)
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{
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struct jh7110_pcie_phy *phy = dev_get_priv(dev);
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struct reg_field usb_split = REG_FIELD(split, USB_PDRSTN_SPLIT_BIT, USB_PDRSTN_SPLIT_BIT);
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phy->usb_split = devm_regmap_field_alloc(dev, phy->sys_syscon, usb_split);
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if (IS_ERR(phy->usb_split)) {
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dev_err(dev, "USB split field init failed\n");
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return PTR_ERR(phy->usb_split);
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}
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return 0;
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}
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static int starfive_pcie_phy_get_syscon(struct udevice *dev)
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{
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struct jh7110_pcie_phy *phy = dev_get_priv(dev);
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struct ofnode_phandle_args sys_phandle, stg_phandle;
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int ret;
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/* get corresponding syscon phandle */
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ret = dev_read_phandle_with_args(dev, "starfive,sys-syscon", NULL, 0, 0,
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&sys_phandle);
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if (ret < 0) {
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dev_err(dev, "Can't get sys cfg phandle: %d\n", ret);
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return ret;
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}
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ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 2, 0,
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&stg_phandle);
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if (ret < 0) {
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dev_err(dev, "Can't get stg cfg phandle: %d\n", ret);
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return ret;
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}
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phy->sys_syscon = syscon_node_to_regmap(sys_phandle.node);
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/* get syscon register offset */
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if (!IS_ERR(phy->sys_syscon)) {
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ret = phy_sys_regfield_init(dev, SYSCON_USB_PDRSTN_REG_OFFSET);
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if (ret)
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return ret;
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} else {
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phy->sys_syscon = NULL;
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}
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phy->stg_syscon = syscon_node_to_regmap(stg_phandle.node);
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if (!IS_ERR(phy->stg_syscon))
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return phy_stg_regfield_init(dev, stg_phandle.args[0],
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stg_phandle.args[1]);
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else
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phy->stg_syscon = NULL;
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return 0;
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}
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int jh7110_pcie_phy_probe(struct udevice *dev)
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{
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struct jh7110_pcie_phy *phy = dev_get_priv(dev);
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int rc;
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phy->regs = dev_read_addr_ptr(dev);
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if (!phy->regs)
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return -EINVAL;
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rc = starfive_pcie_phy_get_syscon(dev);
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if (rc)
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return rc;
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phy_kvco_gain_set(phy);
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return 0;
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}
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static const struct udevice_id jh7110_pcie_phy[] = {
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{ .compatible = "starfive,jh7110-pcie-phy"},
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{},
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};
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U_BOOT_DRIVER(jh7110_pcie_phy) = {
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.name = "jh7110_pcie_phy",
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.id = UCLASS_PHY,
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.of_match = jh7110_pcie_phy,
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.probe = jh7110_pcie_phy_probe,
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.ops = &jh7110_pcie_phy_ops,
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.priv_auto = sizeof(struct jh7110_pcie_phy),
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};
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