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sunxi: mmc: A20: Fix MMC optimisation

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Some SoCs (as seen on A20) seem to misreport the MMC FIFO level if the
FIFO is completely full: the level size reads as zero, but the FIFO_FULL
bit is set. We won't do a single iteration of the read loop in this
case, so will be stuck forever.

Check for this situation and use a safe minimal FIFO size instead when
we hit this case.

This fixes MMC boot on A20 devices after the MMC FIFO optimisation
(9faae5457f52).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This commit is contained in:
Andre Przywara 2021-09-03 16:49:16 +01:00
parent 7958292f5f
commit 0b508ca821
1 changed files with 7 additions and 3 deletions
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10
drivers/mmc/sunxi_mmc.c
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@ -349,10 +349,14 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
* register without checking the status register after every * register without checking the status register after every
* read. That saves half of the costly MMIO reads, effectively * read. That saves half of the costly MMIO reads, effectively
* doubling the read performance. * doubling the read performance.
* Some SoCs (A20) report a level of 0 if the FIFO is
* completely full (value masked out?). Use a safe minimal
* FIFO size in this case.
*/ */
for (in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status); in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status);
in_fifo > 0; if (in_fifo == 0 && (status & SUNXI_MMC_STATUS_FIFO_FULL))
in_fifo--) in_fifo = 32;
for (; in_fifo > 0; in_fifo--)
buff[i++] = readl_relaxed(&priv->reg->fifo); buff[i++] = readl_relaxed(&priv->reg->fifo);
dmb(); dmb();
} }