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synced 2026-05-04 20:26:13 +02:00
ram: k3-ddrss: Support multiple ECC regions for a single controller
K3 Inline ECC mechanism can support up to 3 regions of inline ECC, add this support for single controller. Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
This commit is contained in:
Neha Malcom Francis
Tom Rini
parent
d1efbc8d65
commit
0824703fb2
@ -176,7 +176,7 @@ struct k3_ddrss_desc {
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lpddr4_obj *driverdt;
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lpddr4_config config;
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lpddr4_privatedata pd;
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struct k3_ddrss_ecc_region ecc_range;
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struct k3_ddrss_ecc_region ecc_ranges[K3_DDRSS_MAX_ECC_REG];
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struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REG];
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u64 ecc_reserved_space;
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u64 ddr_bank_base[CONFIG_NR_DRAM_BANKS];
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@ -576,10 +576,26 @@ void k3_lpddr4_start(struct k3_ddrss_desc *ddrss)
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}
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}
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static void k3_ddrss_set_ecc_range_r0(u32 base, u64 start_address, u64 size)
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static void k3_ddrss_set_ecc_range_rx(u32 x, u32 base, u64 start_address, u64 size)
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{
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writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG);
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writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG);
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u32 start_reg, end_reg;
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switch (x) {
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case 1:
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start_reg = DDRSS_ECC_R1_STR_ADDR_REG;
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end_reg = DDRSS_ECC_R1_END_ADDR_REG;
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break;
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case 2:
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start_reg = DDRSS_ECC_R2_STR_ADDR_REG;
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end_reg = DDRSS_ECC_R2_END_ADDR_REG;
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break;
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default:
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start_reg = DDRSS_ECC_R0_STR_ADDR_REG;
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end_reg = DDRSS_ECC_R0_END_ADDR_REG;
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break;
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}
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writel((start_address) >> 16, base + start_reg);
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writel((start_address + size - 1) >> 16, base + end_reg);
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}
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#define BIST_MODE_MEM_INIT 4
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@ -755,27 +771,40 @@ static void k3_ddrss_ddr_reg_init(struct k3_ddrss_desc *ddrss)
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writel(DDRSS_ECC_CTRL_REG_DEFAULT, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
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}
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ofnode get_next_ecc_node(ofnode ecc)
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{
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do {
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ecc = ofnode_by_prop_value(ecc, "device_type", "ecc", 4);
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} while (!ofnode_is_enabled(ecc));
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return ecc;
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}
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static void k3_ddrss_ddr_inline_ecc_base_size_calc(struct k3_ddrss_ecc_region *range)
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{
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fdt_addr_t base;
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fdt_size_t size;
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ofnode node1;
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ofnode ecc_node = ofnode_null();
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node1 = ofnode_null();
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do {
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node1 = ofnode_by_prop_value(node1, "device_type", "ecc", 4);
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} while (!ofnode_is_enabled(node1));
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base = ofnode_get_addr_size(node1, "reg", &size);
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if (base == FDT_ADDR_T_NONE) {
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debug("%s: Failed to get ECC node reg and size\n", __func__);
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ecc_node = get_next_ecc_node(ecc_node);
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if (!ofnode_valid(ecc_node)) {
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debug("%s: No ECC node, enabling for entire region\n", __func__);
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range->start = 0;
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range->range = 0;
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} else {
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return;
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}
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for (int i = 0; i < K3_DDRSS_MAX_ECC_REG; i++) {
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base = ofnode_get_addr_size(ecc_node, "reg", &size);
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if (base == FDT_ADDR_T_NONE) {
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range->start = 0;
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range->range = 0;
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break;
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}
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range->start = base;
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range->range = size;
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range++;
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ecc_node = get_next_ecc_node(ecc_node);
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}
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}
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@ -798,13 +827,21 @@ static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss)
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static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss)
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{
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u64 ecc_region_start = ddrss->ecc_regions[0].start;
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u64 ecc_range = ddrss->ecc_regions[0].range;
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u64 ecc_region0_start = ddrss->ecc_regions[0].start;
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u64 ecc_range0 = ddrss->ecc_regions[0].range;
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u64 ecc_region1_start = ddrss->ecc_regions[1].start;
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u64 ecc_range1 = ddrss->ecc_regions[1].range;
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u64 ecc_region2_start = ddrss->ecc_regions[2].start;
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u64 ecc_range2 = ddrss->ecc_regions[2].range;
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u32 base = (u32)ddrss->ddrss_ss_cfg;
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u32 val;
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/* Only Program region 0 which covers full ddr space */
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k3_ddrss_set_ecc_range_r0(base, ecc_region_start, ecc_range);
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k3_ddrss_set_ecc_range_rx(0, base, ecc_region0_start, ecc_range0);
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if (ecc_range1)
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k3_ddrss_set_ecc_range_rx(1, base, ecc_region1_start, ecc_range1);
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if (ecc_range2)
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k3_ddrss_set_ecc_range_rx(2, base, ecc_region2_start, ecc_range2);
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/* Enable ECC, RMW, WR_ALLOC */
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writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN |
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@ -829,12 +866,12 @@ static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss)
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static int k3_ddrss_probe(struct udevice *dev)
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{
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u64 end, bank0, bank1;
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u64 end, bank0, bank1, bank0_size;
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int ret;
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struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
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__maybe_unused u64 ddr_ram_size, ecc_res;
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__maybe_unused u32 inst, st;
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__maybe_unused struct k3_ddrss_ecc_region *range = &ddrss->ecc_range;
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__maybe_unused u32 inst;
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__maybe_unused struct k3_ddrss_ecc_region *range = ddrss->ecc_ranges;
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__maybe_unused struct k3_msmc *msmc_parent = NULL;
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debug("%s(dev=%p)\n", __func__, dev);
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@ -875,39 +912,43 @@ static int k3_ddrss_probe(struct udevice *dev)
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k3_ddrss_ddr_inline_ecc_base_size_calc(range);
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end = ddrss->ecc_range.start + ddrss->ecc_range.range;
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inst = ddrss->instance;
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ddr_ram_size = ddrss->ddr_ram_size;
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ecc_res = ddrss->ecc_reserved_space;
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bank0 = ddrss->ddr_bank_base[0];
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bank1 = ddrss->ddr_bank_base[1];
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bank0_size = ddrss->ddr_bank_size[0];
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if (!range->range) {
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/* Configure entire DDR space by default */
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debug("%s: Defaulting to protecting entire DDR space using inline ECC\n",
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__func__);
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ddrss->ecc_range.start = bank0;
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ddrss->ecc_range.range = ddr_ram_size - ecc_res;
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ddrss->ecc_ranges[0].start = bank0;
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ddrss->ecc_ranges[0].range = ddr_ram_size - ecc_res;
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} else {
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ddrss->ecc_range.start = range->start;
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ddrss->ecc_range.range = range->range;
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ddrss->ecc_ranges[0].start = range->start;
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ddrss->ecc_ranges[0].range = range->range;
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}
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st = ddrss->ecc_range.start;
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if (!CONFIG_IS_ENABLED(K3_MULTI_DDR)) {
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if (end > (ddr_ram_size - ecc_res))
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ddrss->ecc_regions[0].range = ddr_ram_size - ecc_res;
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else
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ddrss->ecc_regions[0].range = ddrss->ecc_range.range;
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struct k3_ddrss_ecc_region *r = range;
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/* Check in which bank we are */
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if (st > bank1)
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ddrss->ecc_regions[0].start = st - bank1 + ddrss->ddr_bank_size[0];
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else
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ddrss->ecc_regions[0].start = st - bank0;
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for (int i = 0; (i < K3_DDRSS_MAX_ECC_REG) && (r->range != 0); i++, r++) {
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end = r->start + r->range;
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ddr_ram_size = ddrss->ddr_ram_size;
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ecc_res = ddrss->ecc_reserved_space;
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if (end > (ddr_ram_size - ecc_res))
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ddrss->ecc_regions[i].range = ddr_ram_size - ecc_res;
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else
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ddrss->ecc_regions[i].range = r->range;
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/* Check in which bank we are */
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if (r->start > bank1)
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ddrss->ecc_regions[i].start = r->start - bank1 + bank0_size;
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else
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ddrss->ecc_regions[i].start = r->start - bank0;
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}
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} else {
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/* For multi-DDR, we rely on MSMC's calculation of regions for each DDR */
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inst = ddrss->instance;
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msmc_parent = kzalloc(sizeof(msmc_parent), GFP_KERNEL);
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if (!msmc_parent)
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return -ENOMEM;
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@ -922,7 +963,7 @@ static int k3_ddrss_probe(struct udevice *dev)
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if (msmc_parent->R0[0].start < 0) {
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/* Configure entire DDR space by default */
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ddrss->ecc_regions[0].start = ddrss->ddr_bank_base[0];
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ddrss->ecc_regions[0].start = bank0;
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ddrss->ecc_regions[0].range = ddr_ram_size - ecc_res;
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} else {
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end = msmc_parent->R0[inst].start + msmc_parent->R0[inst].range;
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