diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c index a422919fab1..8f4ddf59753 100644 --- a/arch/arm/mach-k3/am62x/am625_init.c +++ b/arch/arm/mach-k3/am62x/am625_init.c @@ -294,15 +294,6 @@ void board_init_f(ulong dummy) } spl_enable_cache(); - if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) && - spl_boot_device() == BOOT_DEVICE_ETHERNET) { - struct udevice *cpswdev; - - if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), - &cpswdev)) - printf("Failed to probe am65_cpsw_nuss driver\n"); - } - fixup_a53_cpu_freq_by_speed_grade(); } diff --git a/arch/arm/mach-k3/am64x/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c index 41812b7dbf7..219798315db 100644 --- a/arch/arm/mach-k3/am64x/am642_init.c +++ b/arch/arm/mach-k3/am64x/am642_init.c @@ -263,13 +263,6 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif - if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) && - spl_boot_device() == BOOT_DEVICE_ETHERNET) { - struct udevice *cpswdev; - - if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), &cpswdev)) - printf("Failed to probe am65_cpsw_nuss driver\n"); - } } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index f8c53b286eb..5483ac9906c 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -322,17 +322,6 @@ void spl_board_prepare_for_linux(void) int misc_init_r(void) { - if (IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS)) { - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(am65_cpsw_nuss), - &dev); - if (ret) - printf("Failed to probe am65_cpsw_nuss driver\n"); - } - if (IS_ENABLED(CONFIG_TI_ICSSG_PRUETH)) { struct udevice *dev; int ret; diff --git a/arch/arm/mach-k3/include/mach/j721s2_spl.h b/arch/arm/mach-k3/include/mach/j721s2_spl.h index d8fae2c8b45..47a61281d94 100644 --- a/arch/arm/mach-k3/include/mach/j721s2_spl.h +++ b/arch/arm/mach-k3/include/mach/j721s2_spl.h @@ -12,6 +12,7 @@ #define BOOT_DEVICE_OSPI 0x01 #define BOOT_DEVICE_QSPI 0x02 #define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_CPGMAC 0x04 #define BOOT_DEVICE_ETHERNET 0x04 #define BOOT_DEVICE_I2C 0x06 #define BOOT_DEVICE_UART 0x07 diff --git a/arch/arm/mach-k3/include/mach/j784s4_spl.h b/arch/arm/mach-k3/include/mach/j784s4_spl.h index d481a46c675..3814dc95d01 100644 --- a/arch/arm/mach-k3/include/mach/j784s4_spl.h +++ b/arch/arm/mach-k3/include/mach/j784s4_spl.h @@ -44,4 +44,6 @@ #define K3_PRIMARY_BOOTMODE 0x0 #define K3_BACKUP_BOOTMODE 0x1 +#define BOOT_DEVICE_CPGMAC 0x04 + #endif diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c b/arch/arm/mach-k3/r5/am62px/clk-data.c index bc62d1d0d08..b552a2be74d 100644 --- a/arch/arm/mach-k3/r5/am62px/clk-data.c +++ b/arch/arm/mach-k3/r5/am62px/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof . * - * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -62,6 +62,17 @@ static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk10", }; +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { "postdiv4_16ff_main_0_hsdivout5_clk", "hsdiv4_16fft_main_2_hsdivout2_clk", @@ -99,8 +110,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = { "board_0_cp_gemac_cpts0_rft_clk_out", "hsdiv4_16fft_main_1_hsdivout3_clk", "postdiv4_16ff_main_2_hsdivout6_clk", - NULL, - NULL, + "cpsw_3guss_am67_main_0_cpts_genf0", + "cpsw_3guss_am67_main_0_cpts_genf1", NULL, NULL, NULL, @@ -148,7 +159,12 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0), CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0), CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -201,6 +217,7 @@ static const struct clk_data clk_list[] = { CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0), CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), @@ -216,6 +233,24 @@ static const struct clk_data clk_list[] = { }; static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"), + DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(13, 9, "board_0_ext_refclk1_out"), + DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"), + DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"), DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), @@ -240,6 +275,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), + DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"), + DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"), DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), @@ -286,6 +323,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 54, "mshsi2c_main_0_porscl"), DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 96, "cpsw_3guss_am67_main_0_mdio_mdclk_o"), DEV_CLK(157, 101, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 103, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 143, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), diff --git a/arch/arm/mach-k3/r5/am62px/dev-data.c b/arch/arm/mach-k3/r5/am62px/dev-data.c index 3cc211ea202..63e6beb4d57 100644 --- a/arch/arm/mach-k3/r5/am62px/dev-data.c +++ b/arch/arm/mach-k3/r5/am62px/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof . * - * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -31,11 +31,12 @@ static struct ti_lpsc soc_lpsc_list[] = { [6] = PSC_LPSC(24, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), [7] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), [8] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), - [9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]), - [10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]), - [11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), - [12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]), - [13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]), + [9] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [10] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]), + [11] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[10]), + [12] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), + [13] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]), + [14] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[13]), }; static struct ti_dev soc_dev_list[] = { @@ -52,11 +53,12 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(36, &soc_lpsc_list[8]), PSC_DEV(102, &soc_lpsc_list[8]), PSC_DEV(146, &soc_lpsc_list[8]), - PSC_DEV(166, &soc_lpsc_list[9]), - PSC_DEV(135, &soc_lpsc_list[10]), - PSC_DEV(170, &soc_lpsc_list[11]), - PSC_DEV(177, &soc_lpsc_list[12]), - PSC_DEV(55, &soc_lpsc_list[13]), + PSC_DEV(13, &soc_lpsc_list[9]), + PSC_DEV(166, &soc_lpsc_list[10]), + PSC_DEV(135, &soc_lpsc_list[11]), + PSC_DEV(170, &soc_lpsc_list[12]), + PSC_DEV(177, &soc_lpsc_list[13]), + PSC_DEV(55, &soc_lpsc_list[14]), }; const struct ti_k3_pd_platdata am62px_pd_platdata = { diff --git a/arch/arm/mach-k3/r5/j721s2/clk-data.c b/arch/arm/mach-k3/r5/j721s2/clk-data.c index 0c5c321c1eb..0130c9c4b86 100644 --- a/arch/arm/mach-k3/r5/j721s2/clk-data.c +++ b/arch/arm/mach-k3/r5/j721s2/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Dave Gerlach . * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -55,6 +55,32 @@ static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = { "hsdiv4_16fft_mcu_2_hsdivout4_clk", }; +static const char * const wkup_gpio0_clksel_out0_parents[] = { + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", + "j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", + "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", +}; + static const char * const mcu_usart_clksel_out0_parents[] = { "hsdiv4_16fft_mcu_1_hsdivout3_clk", "postdiv3_16fft_main_1_hsdivout5_clk", @@ -174,7 +200,11 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -199,6 +229,8 @@ static const struct clk_data clk_list[] = { CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), + CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), + CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0), CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0), CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0), CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), @@ -275,6 +307,24 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(29, 3, "cpsw2g_cpts_rclk_sel_out0"), + DEV_CLK(29, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(29, 5, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(29, 6, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(29, 7, "board_0_cpts0_rft_clk_out"), + DEV_CLK(29, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(29, 9, "board_0_ext_refclk1_out"), + DEV_CLK(29, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(29, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(29, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 22, "board_0_mcu_rgmii1_rxc_out"), + DEV_CLK(29, 26, "board_0_mcu_rmii1_ref_clk_out"), + DEV_CLK(29, 28, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(29, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 30, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 32, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 33, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"), DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"), DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"), @@ -367,6 +417,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"), DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"), + DEV_CLK(157, 207, "cpsw_2guss_mcu_0_mdio_mdclk_o"), DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"), DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), DEV_CLK(157, 221, "mcu_clkout_mux_out0"), @@ -374,6 +425,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"), DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), + DEV_CLK(157, 244, "cpsw_2guss_mcu_0_rgmii1_txc_o"), DEV_CLK(157, 352, "dpi0_ext_clksel_out0"), DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"), DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), @@ -400,7 +452,7 @@ static const struct dev_clk soc_dev_clk_data[] = { const struct ti_k3_clk_platdata j721s2_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 105, + .clk_list_cnt = ARRAY_SIZE(clk_list), .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 124, + .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data), }; diff --git a/arch/arm/mach-k3/r5/j721s2/dev-data.c b/arch/arm/mach-k3/r5/j721s2/dev-data.c index df70c5e5d7c..b78550707c5 100644 --- a/arch/arm/mach-k3/r5/j721s2/dev-data.c +++ b/arch/arm/mach-k3/r5/j721s2/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Dave Gerlach . * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = { }; static struct ti_dev soc_dev_list[] = { + PSC_DEV(29, &soc_lpsc_list[0]), PSC_DEV(35, &soc_lpsc_list[0]), PSC_DEV(108, &soc_lpsc_list[0]), PSC_DEV(109, &soc_lpsc_list[0]), diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c b/arch/arm/mach-k3/r5/j722s/clk-data.c index b4f27af333d..238d57d0aa0 100644 --- a/arch/arm/mach-k3/r5/j722s/clk-data.c +++ b/arch/arm/mach-k3/r5/j722s/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof . * - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -57,9 +57,15 @@ static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk", }; -static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { - "postdiv4_16ff_main_0_hsdivout5_clk", - "hsdiv4_16fft_main_2_hsdivout2_clk", +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", }; static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { @@ -94,8 +100,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = { "board_0_cp_gemac_cpts0_rft_clk_out", "hsdiv4_16fft_main_1_hsdivout3_clk", "postdiv4_16ff_main_2_hsdivout6_clk", - NULL, - NULL, + "cpsw_3guss_am67_main_0_cpts_genf0", + "cpsw_3guss_am67_main_0_cpts_genf1", NULL, NULL, NULL, @@ -143,7 +149,12 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0), CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0), CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -194,7 +205,7 @@ static const struct clk_data clk_list[] = { CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), - CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), + CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0), CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), @@ -209,6 +220,24 @@ static const struct clk_data clk_list[] = { }; static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"), + DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(13, 9, "board_0_ext_refclk1_out"), + DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"), + DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"), DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), @@ -233,10 +262,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), - DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), - DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), - DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"), + DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"), DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), DEV_CLK(58, 2, "board_0_mmc1_clk_out"), @@ -279,6 +306,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 74, "mshsi2c_main_0_porscl"), DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 140, "cpsw_3guss_am67_main_0_mdio_mdclk_o"), DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c b/arch/arm/mach-k3/r5/j722s/dev-data.c index 59176c98999..d6832266884 100644 --- a/arch/arm/mach-k3/r5/j722s/dev-data.c +++ b/arch/arm/mach-k3/r5/j722s/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof . * - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -23,16 +23,16 @@ static struct ti_pd soc_pd_list[] = { static struct ti_lpsc soc_lpsc_list[] = { [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), - [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), - [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), - [3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]), + [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]), + [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]), + [3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[6]), [9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]), - [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]), + [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]), [11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]), [12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]), }; @@ -43,13 +43,13 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(61, &soc_lpsc_list[0]), PSC_DEV(178, &soc_lpsc_list[1]), PSC_DEV(179, &soc_lpsc_list[2]), - PSC_DEV(57, &soc_lpsc_list[3]), - PSC_DEV(58, &soc_lpsc_list[4]), - PSC_DEV(161, &soc_lpsc_list[5]), - PSC_DEV(75, &soc_lpsc_list[6]), - PSC_DEV(36, &soc_lpsc_list[7]), - PSC_DEV(102, &soc_lpsc_list[7]), - PSC_DEV(146, &soc_lpsc_list[7]), + PSC_DEV(58, &soc_lpsc_list[3]), + PSC_DEV(161, &soc_lpsc_list[4]), + PSC_DEV(75, &soc_lpsc_list[5]), + PSC_DEV(36, &soc_lpsc_list[6]), + PSC_DEV(102, &soc_lpsc_list[6]), + PSC_DEV(146, &soc_lpsc_list[6]), + PSC_DEV(13, &soc_lpsc_list[7]), PSC_DEV(166, &soc_lpsc_list[8]), PSC_DEV(135, &soc_lpsc_list[9]), PSC_DEV(170, &soc_lpsc_list[10]), diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c index 97d969271ec..24780eb6562 100644 --- a/arch/arm/mach-k3/r5/j784s4/clk-data.c +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c @@ -57,6 +57,25 @@ static const char * const wkup_gpio0_clksel_out0_parents[] = { "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", }; +static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", +}; + static const char * const mcu_usart_clksel_out0_parents[] = { "hsdiv4_16fft_mcu_1_hsdivout3_clk", "postdiv3_16fft_main_1_hsdivout5_clk", @@ -132,6 +151,11 @@ static const char * const main_pll_hfosc_sel_out8_parents[] = { "board_0_hfosc1_clk_out", }; +static const char * const mcu_clkout_mux_out0_parents[] = { + "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", +}; + static const char * const usb0_refclk_sel_out0_parents[] = { "gluelogic_hfosc0_clkout", "board_0_hfosc1_clk_out", @@ -142,11 +166,6 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = { "board_0_mmc1_clk_out", }; -static const char * const mcu_clkout_mux_out0_parents[] = { - "hsdiv4_16fft_mcu_2_hsdivout0_clk", - "hsdiv4_16fft_mcu_2_hsdivout1_clk", -}; - static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { "main_pll_hfosc_sel_out0", "hsdiv4_16fft_main_0_hsdivout0_clk", @@ -201,7 +220,11 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -224,6 +247,7 @@ static const struct clk_data clk_list[] = { CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), + CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0), CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0), CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0), CLK_MUX("wkup_usart_clksel_out0", wkup_usart_clksel_out0_parents, 2, 0x43008064, 0, 1, 0), @@ -317,6 +341,24 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(63, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(63, 3, "cpsw2g_cpts_rclk_sel_out0"), + DEV_CLK(63, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(63, 5, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(63, 6, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(63, 7, "board_0_cpts0_rft_clk_out"), + DEV_CLK(63, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(63, 9, "board_0_ext_refclk1_out"), + DEV_CLK(63, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(63, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(63, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 22, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 24, "board_0_mcu_rgmii1_rxc_out"), + DEV_CLK(63, 27, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 28, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 30, "board_0_mcu_rmii1_ref_clk_out"), DEV_CLK(78, 0, "postdiv3_16fft_main_0_hsdivout8_clk"), DEV_CLK(78, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), DEV_CLK(78, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), @@ -353,10 +395,12 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), + DEV_CLK(157, 190, "cpsw_2guss_mcu_0_mdio_mdclk_o"), DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"), DEV_CLK(157, 226, "fss_mcu_0_ospi_0_ospi_oclk_clk"), DEV_CLK(157, 228, "fss_mcu_0_ospi_1_ospi_oclk_clk"), DEV_CLK(157, 230, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(157, 233, "cpsw_2guss_mcu_0_rgmii1_txc_o"), DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c index b32b4ba9588..19901821225 100644 --- a/arch/arm/mach-k3/r5/j784s4/dev-data.c +++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c @@ -54,6 +54,7 @@ static struct ti_lpsc soc_lpsc_list[] = { }; static struct ti_dev soc_dev_list[] = { + PSC_DEV(63, &soc_lpsc_list[0]), PSC_DEV(35, &soc_lpsc_list[0]), PSC_DEV(160, &soc_lpsc_list[0]), PSC_DEV(161, &soc_lpsc_list[0]), diff --git a/board/ti/am62px/MAINTAINERS b/board/ti/am62px/MAINTAINERS index 57c86ddbc4a..c6c6deca61e 100644 --- a/board/ti/am62px/MAINTAINERS +++ b/board/ti/am62px/MAINTAINERS @@ -7,3 +7,5 @@ F: board/ti/am62px/ F: include/configs/am62p5_evm.h F: configs/am62px_evm_r5_defconfig F: configs/am62px_evm_a53_defconfig +F: configs/am62px_evm_r5_ethboot_defconfig +F: configs/am62px_evm_a53_ethboot_defconfig diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 2e85363cf5f..c06e3878d67 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -41,6 +42,13 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; +#if IS_ENABLED(CONFIG_SPL_BUILD) +void spl_board_init(void) +{ + enable_caches(); +} +#endif + #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { diff --git a/board/ti/j721s2/MAINTAINERS b/board/ti/j721s2/MAINTAINERS index e31f2acea7b..96d225a3ac5 100644 --- a/board/ti/j721s2/MAINTAINERS +++ b/board/ti/j721s2/MAINTAINERS @@ -9,6 +9,8 @@ F: configs/j721s2_evm_r5_defconfig F: configs/j721s2_evm_a72_defconfig F: configs/am68_sk_r5_defconfig F: configs/am68_sk_a72_defconfig +F: configs/am68_sk_r5_ethboot_defconfig +F: configs/am68_sk_a72_ethboot_defconfig F: arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi F: arch/arm/dts/k3-j721s2-r5.dtsi F: arch/arm/dts/k3-j721s2-r5-common-proc-board.dts diff --git a/board/ti/j722s/MAINTAINERS b/board/ti/j722s/MAINTAINERS index 7908c30def2..c97b3661e0a 100644 --- a/board/ti/j722s/MAINTAINERS +++ b/board/ti/j722s/MAINTAINERS @@ -7,3 +7,5 @@ F: board/ti/j722s/ F: include/configs/j722s_evm.h F: configs/j722s_evm_r5_defconfig F: configs/j722s_evm_a53_defconfig +F: configs/j722s_evm_r5_ethboot_defconfig +F: configs/j722s_evm_a53_ethboot_defconfig diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c index d2b94913c12..32d767cb7d2 100644 --- a/board/ti/j722s/evm.c +++ b/board/ti/j722s/evm.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -15,6 +16,13 @@ #include #include "../common/fdt_ops.h" +#if IS_ENABLED(CONFIG_SPL_BUILD) +void spl_board_init(void) +{ + enable_caches(); +} +#endif + #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS index b289c639f3f..f9fe9a9f661 100644 --- a/board/ti/j784s4/MAINTAINERS +++ b/board/ti/j784s4/MAINTAINERS @@ -20,6 +20,8 @@ F: arch/arm/dts/k3-am69-sk-u-boot.dtsi F: arch/arm/dts/k3-am69-r5-sk.dts F: configs/am69_sk_r5_defconfig F: configs/am69_sk_a72_defconfig +F: configs/am69_sk_r5_ethboot_defconfig +F: configs/am69_sk_a72_ethboot_defconfig J742S2 EVM BOARD M: Manorit Chawdhry diff --git a/configs/am62px_evm_a53_ethboot_defconfig b/configs/am62px_evm_a53_ethboot_defconfig new file mode 100644 index 00000000000..57da40d4b2e --- /dev/null +++ b/configs/am62px_evm_a53_ethboot_defconfig @@ -0,0 +1,13 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_AM62P5=y +CONFIG_TARGET_AM62P5_A53_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62p5-sk" +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ETH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM62PX U-Boot A53 SPL" diff --git a/configs/am62px_evm_r5_ethboot_defconfig b/configs/am62px_evm_r5_ethboot_defconfig new file mode 100644 index 00000000000..dfd944ad7c0 --- /dev/null +++ b/configs/am62px_evm_r5_ethboot_defconfig @@ -0,0 +1,29 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_AM62P5=y +CONFIG_TARGET_AM62P5_R5_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-r5-sk" +CONFIG_NET=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_ETH=y +CONFIG_SPL_I2C=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM62PX U-Boot R5 SPL" +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_SPL_SPI=n +CONFIG_SPL_MMC=n +CONFIG_SPL_MTD_LOAD=n +CONFIG_SPL_NAND_SPI_SUPPORT=n +CONFIG_SPL_DM_DEVICE_REMOVE=n +CONFIG_DM_MTD=n +CONFIG_MTD_SPI_NAND=n +CONFIG_DM_SPI_FLASH=n +CONFIG_SPI=n +CONFIG_DM_SPI=n +CONFIG_CADENCE_QSPI=n diff --git a/configs/am68_sk_a72_ethboot_defconfig b/configs/am68_sk_a72_ethboot_defconfig new file mode 100644 index 00000000000..d9d6ca6088e --- /dev/null +++ b/configs/am68_sk_a72_ethboot_defconfig @@ -0,0 +1,14 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J721S2=y +CONFIG_TARGET_J721S2_A72_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am68-sk-base-board" +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ETH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM68 U-Boot A72 SPL" diff --git a/configs/am68_sk_r5_ethboot_defconfig b/configs/am68_sk_r5_ethboot_defconfig new file mode 100644 index 00000000000..f0815b781d5 --- /dev/null +++ b/configs/am68_sk_r5_ethboot_defconfig @@ -0,0 +1,23 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J721S2=y +CONFIG_TARGET_J721S2_R5_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am68-sk-r5-base-board" +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ETH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM68 U-Boot R5 SPL" +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_SPI=n +CONFIG_SPL_SPI=n +CONFIG_DM_SPI=n +CONFIG_MTD=n +CONFIG_SPL_MTD=n +CONFIG_SPL_NAND_SPI_SUPPORT=n +CONFIG_NOR_SUPPORT=n +CONFIG_SPL_NOR_SUPPORT=n +CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n diff --git a/configs/am69_sk_a72_ethboot_defconfig b/configs/am69_sk_a72_ethboot_defconfig new file mode 100644 index 00000000000..676db01b2e2 --- /dev/null +++ b/configs/am69_sk_a72_ethboot_defconfig @@ -0,0 +1,11 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J784S4=y +CONFIG_TARGET_J784S4_A72_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am69-sk" +CONFIG_SPL_ETH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM69 U-Boot A72 SPL" +CONFIG_SYS_K3_SPL_ATF=y diff --git a/configs/am69_sk_r5_ethboot_defconfig b/configs/am69_sk_r5_ethboot_defconfig new file mode 100644 index 00000000000..c85aa72cf04 --- /dev/null +++ b/configs/am69_sk_r5_ethboot_defconfig @@ -0,0 +1,15 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J784S4=y +CONFIG_TARGET_J784S4_R5_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am69-r5-sk" +CONFIG_SPL_ETH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM69 U-Boot R5 SPL" +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_TI_I2C_BOARD_DETECT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 diff --git a/configs/j722s_evm_a53_ethboot_defconfig b/configs/j722s_evm_a53_ethboot_defconfig new file mode 100644 index 00000000000..a5a2a15849c --- /dev/null +++ b/configs/j722s_evm_a53_ethboot_defconfig @@ -0,0 +1,13 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J722S=y +CONFIG_TARGET_J722S_A53_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j722s-evm" +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ETH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="J722S U-Boot A53 SPL" diff --git a/configs/j722s_evm_r5_ethboot_defconfig b/configs/j722s_evm_r5_ethboot_defconfig new file mode 100644 index 00000000000..fd58485bff2 --- /dev/null +++ b/configs/j722s_evm_r5_ethboot_defconfig @@ -0,0 +1,30 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J722S=y +CONFIG_TARGET_J722S_R5_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="k3-j722s-r5-evm" +CONFIG_NET=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_ETH=y +CONFIG_SPL_I2C=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="J722S U-Boot R5 SPL" +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_SPL_MMC=n +CONFIG_SPL_SPI=n +CONFIG_SPL_MTD_LOAD=n +CONFIG_SPL_NAND_SPI_SUPPORT=n +CONFIG_SPL_DM_DEVICE_REMOVE=n +CONFIG_DM_MTD=n +CONFIG_MTD_SPI_NAND=n +CONFIG_DM_SPI_FLASH=n +CONFIG_SPI=n +CONFIG_DM_SPI=n +CONFIG_CADENCE_QSPI=n diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index 52267339de0..93c3a0c35f2 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -49,6 +49,7 @@ config TI_AM65_CPSW_NUSS imply MISC imply SYSCON imply MDIO_TI_CPSW + imply SPL_SYSCON select PHYLIB help This driver supports TI K3 MCU CPSW Nuss Ethernet controller diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 723dde284fb..2aa7e5e3a30 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -705,7 +705,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) struct am65_cpsw_common *cpsw_common = dev_get_priv(dev); ofnode ports_np, node; int ret, i; - struct udevice *port_dev; cpsw_common->dev = dev; cpsw_common->ss_base = dev_read_addr(dev); @@ -732,6 +731,7 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) ports_np = dev_read_subnode(dev, "ethernet-ports"); if (!ofnode_valid(ports_np)) { ret = -ENOENT; + dev_err(dev, "Invalid device tree node %d\n", ret); goto out; } @@ -763,12 +763,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) continue; cpsw_common->ports[port_id].disabled = disabled; - if (disabled) - continue; - - ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", ofnode_get_name(node), node, &port_dev); - if (ret) - dev_err(dev, "Failed to bind to %s node\n", ofnode_get_name(node)); } for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) { @@ -798,6 +792,37 @@ out: return ret; } +static int am65_cpsw_nuss_bind(struct udevice *dev) +{ + struct uclass_driver *drv; + struct udevice *port_dev; + ofnode ports_np, node; + int ret; + + drv = lists_uclass_lookup(UCLASS_ETH); + if (!drv) { + puts("Cannot find eth driver"); + return -ENOENT; + } + + ports_np = dev_read_subnode(dev, "ethernet-ports"); + if (!ofnode_valid(ports_np)) + return -ENOENT; + + ofnode_for_each_subnode(node, ports_np) { + const char *node_name; + + node_name = ofnode_get_name(node); + + ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", node_name, node, + &port_dev); + if (ret) + dev_err(dev, "Failed to bind to %s node\n", node_name); + } + + return ret; +} + static const struct udevice_id am65_cpsw_nuss_ids[] = { { .compatible = "ti,am654-cpsw-nuss" }, { .compatible = "ti,j721e-cpsw-nuss" }, @@ -809,6 +834,7 @@ U_BOOT_DRIVER(am65_cpsw_nuss) = { .name = "am65_cpsw_nuss", .id = UCLASS_MISC, .of_match = am65_cpsw_nuss_ids, + .bind = am65_cpsw_nuss_bind, .probe = am65_cpsw_probe_nuss, .priv_auto = sizeof(struct am65_cpsw_common), };