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Merge patch series "Add support for TI AM6254atl SiP"

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Anshul Dalal <anshuld@ti.com> says:

This patch series adds support for AM6254atl SiP (or AM62x SiP for
short) to U-Boot.

The OPN (Orderable Part Number) 'AM6254atl' expands as follows[1]:

AM6254atl
     ||||
     |||+-- Feature Lookup (L indicates 512MiB of integrated LPDDR4)
     ||+--- Device Speed Grade (T indicates 1.25GHz on A53 cores)
     |+---- Silicon PG Revision (A indicates SR 1.0)
     +----- Core configuration (4 indicates A53's in Quad core config)

AM62x SiP provides the existing AM62x SoC with 512MiB of DDR
integrated in a single packages. The first 4 patches in the series
are cherry-picked from the devicetree-rebasing repository at
'v6.18-rc2-dts'.

Link: https://lore.kernel.org/r/20251025-62sip_support-v3-0-b4c8314d0055@ti.com
This commit is contained in:
Tom Rini 2025-11-07 16:10:49 -06:00
commit 04ccb271ff
27 changed files with 3046 additions and 318 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

102
arch/arm/dts/k3-am6254atl-r5-sk.dts Normal file
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@ -0,0 +1,102 @@
// SPDX-License-Identifier: GPL-2.0
/*
* AM6254atl SiP SK dts for R5 SPL
* Webpage: https://www.ti.com/tool/SK-AM62-SIP
*
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am6254atl-sk.dts"
#include "k3-am6254atl-sip-ddr-lp4-50-800.dtsi"
#include "k3-am62-ddr.dtsi"
#include "k3-am6254atl-sk-u-boot.dtsi"
/ {
aliases {
tick-timer = &main_timer0;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial3 = &main_uart1;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&secure_proxy_sa3 {
/* We require this for boot handshake */
status = "okay";
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
status = "okay";
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
status = "okay";
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x08000000>;
};
&main_pktdma {
ti,sci = <&dm_tifs>;
bootph-all;
};

2191
arch/arm/dts/k3-am6254atl-sip-ddr-lp4-50-800.dtsi Normal file
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File diff suppressed because it is too large Load Diff

21
arch/arm/dts/k3-am6254atl-sk-u-boot.dtsi Normal file
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@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Common AM6254atl SK dts file for SPLs
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am625-sk-u-boot.dtsi"
#ifdef CONFIG_TARGET_AM625_A53_EVM
#define SPL_AM6254ATL_SK_DTB "spl/dts/ti/k3-am6254atl-sk.dtb"
&spl_am625_sk_dtb {
filename = SPL_AM6254ATL_SK_DTB;
};
&spl_am625_sk_dtb_unsigned {
filename = SPL_AM6254ATL_SK_DTB;
};
#endif

2
board/ti/am62x/MAINTAINERS
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@ -10,3 +10,5 @@ F: configs/am62x_evm_r5_ethboot_defconfig
F: configs/am62x_evm_a53_ethboot_defconfig
F: configs/am62x_lpsk_r5_defconfig
F: configs/am62x_lpsk_a53_defconfig
F: configs/am6254atl_evm_r5_defconfig
F: configs/am6254atl_evm_a53_defconfig

37
board/ti/am62x/am6254atl.env Normal file
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#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
#include <env/ti/k3_dfu.env>
#if CONFIG_CMD_REMOTEPROC
#include <env/ti/k3_rproc.env>
#endif
rproc_fw_binaries= 0 /lib/firmware/am62-mcu-m4f0_0-fw
name_kern=Image
console=ttyS2,115200n8
args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
${mtdparts}
run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
boot_targets=mmc1 mmc0 usb pxe dhcp
boot=mmc
mmcdev=1
bootpart=1:2
bootdir=/boot
rd_spec=-
splashfile=ti_logo_414x97_32bpp.bmp.gz
splashimage=0x82180000
splashpos=m,m
splashsource=sf
dfu_alt_info_ram=
tispl.bin ram 0x82000000 0x200000;
u-boot.img ram 0x82f80000 0x400000
#if CONFIG_BOOTMETH_ANDROID
#include <env/ti/android.env>
adtb_idx=0
#endif

15
configs/am6254atl_evm_a53_defconfig Normal file
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@ -0,0 +1,15 @@
#include <configs/am62x_evm_a53_defconfig>
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SOC_K3_AM625=y
CONFIG_TARGET_AM625_A53_EVM=y
CONFIG_TEXT_BASE=0x82f80000
CONFIG_SPL_TEXT_BASE=0x82000000
CONFIG_SPL_STACK_R_ADDR=0x83f80000
CONFIG_K3_OPTEE_LOAD_ADDR=0x80080000
CONFIG_SPL_BSS_START_ADDR=0x82c00000
CONFIG_SPL_LOAD_FIT_ADDRESS=0x82f80000
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82b00000
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am6254atl-sk"
CONFIG_ENV_SOURCE_FILE="am6254atl"

10
configs/am6254atl_evm_r5_defconfig Normal file
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@ -0,0 +1,10 @@
#include <configs/am62x_evm_r5_defconfig>
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SOC_K3_AM625=y
CONFIG_TARGET_AM625_R5_EVM=y
CONFIG_ENV_SOURCE_FILE="am6254atl"
CONFIG_K3_OPTEE_LOAD_ADDR=0x80080000
CONFIG_SPL_LOAD_FIT_ADDRESS=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="k3-am6254atl-r5-sk"

308
doc/board/ti/am6254atl_sk.rst Normal file
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@ -0,0 +1,308 @@
.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
.. sectionauthor:: Anshul Dalal <anshuld@ti.com>
AM6254ATL SIP Platforms
=======================
Introduction:
-------------
The AM6254atl SiP (System In Package) provides existing :doc:`am62x_sk` with
512MiB of DDR integrated in a single packages.
More details can be found in the Technical Reference Manual:
https://www.ti.com/lit/pdf/spruiv7
Platform information:
* https://www.ti.com/tool/SK-AM62-SIP
Boot Flow:
----------
Below is the pictorial representation of boot flow:
.. image:: img/boot_diagram_am62.svg
:alt: Boot flow diagram
- Here TIFS acts as master and provides all the critical services. R5/A53
requests TIFS to get these services done as shown in the above diagram.
Sources:
--------
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_boot_sources
:end-before: .. k3_rst_include_end_boot_sources
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_boot_firmwares
:end-before: .. k3_rst_include_end_tifsstub
Build procedure:
----------------
0. Setup the environment variables:
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_desc
:end-before: .. k3_rst_include_end_common_env_vars_desc
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_board_env_vars_desc
:end-before: .. k3_rst_include_end_board_env_vars_desc
Set the variables corresponding to this platform:
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
.. prompt:: bash $
export UBOOT_CFG_CORTEXR=am6254atl_evm_r5_defconfig
export UBOOT_CFG_CORTEXA=am6254atl_evm_a53_defconfig
export TFA_BOARD=lite
export TFA_EXTRA_ARGS="PRELOADED_BL33_BASE=0x81880000 BL32_BASE=0x80080000"
export OPTEE_PLATFORM=k3-am62x
export OPTEE_EXTRA_ARGS="CFG_TZDRAM_START=0x80080000"
1. Trusted Firmware-A:
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_tfa
:end-before: .. k3_rst_include_end_build_steps_tfa
2. OP-TEE:
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_optee
:end-before: .. k3_rst_include_end_build_steps_optee
3. U-Boot:
* 3.1 R5:
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_spl_r5
:end-before: .. k3_rst_include_end_build_steps_spl_r5
* 3.1.1 Alternative build of R5 for DFU boot:
As the SPL size can get too big when building with support for booting both
from local storage *and* DFU an extra config fragment should be used to enable
DFU support (and disable storage support)
.. prompt:: bash $
export UBOOT_CFG_CORTEXR="${UBOOT_CFG_CORTEXR} am62x_r5_usbdfu.config"
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_spl_r5
:end-before: .. k3_rst_include_end_build_steps_spl_r5
* 3.2 A53:
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_uboot
:end-before: .. k3_rst_include_end_build_steps_uboot
Target Images
-------------
In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
variant (HS-FS or HS-SE) requires a different source for these files.
- HS-FS
* tiboot3-am62x-hs-fs-evm.bin from step 3.1
* tispl.bin, u-boot.img from step 3.2
- HS-SE
* tiboot3-am62x-hs-evm.bin from step 3.1
* tispl.bin, u-boot.img from step 3.2
Image formats:
--------------
- tiboot3.bin
.. image:: img/multi_cert_tiboot3.bin.svg
:alt: tiboot3.bin image format
- tispl.bin
.. image:: img/tifsstub_dm_tispl.bin.svg
:alt: tispl.bin image format
OSPI:
-----
ROM supports booting from OSPI from offset 0x0.
Flashing images to OSPI:
Below commands can be used to download tiboot3.bin, tispl.bin, and u-boot.img,
over tftp and then flash those to OSPI at their respective addresses.
.. prompt:: bash =>
sf probe
tftp ${loadaddr} tiboot3.bin
sf update $loadaddr 0x0 $filesize
tftp ${loadaddr} tispl.bin
sf update $loadaddr 0x80000 $filesize
tftp ${loadaddr} u-boot.img
sf update $loadaddr 0x280000 $filesize
Flash layout for OSPI:
.. image:: img/ospi_sysfw2.svg
:alt: OSPI flash partition layout
A53 SPL DDR Memory Layout
-------------------------
This provides an overview memory usage in A53 SPL stage.
.. list-table::
:widths: 16 16 16
:header-rows: 1
* - Region
- Start Address
- End Address
* - ATF
- 0x80000000
- 0x80080000
* - OPTEE
- 0x80080000
- 0x81880000
* - TEXT BASE
- 0x81880000
- 0x818d8000
* - EMPTY
- 0x818d8000
- 0x81a00000
* - BMP IMAGE
- 0x81a00000
- 0x82377660
* - STACK
- 0x82377660
- 0x82377e60
* - GD
- 0x82377e60
- 0x80b78000
* - MALLOC
- 0x82378000
- 0x82380000
* - EMPTY
- 0x82380000
- 0x82480000
* - BSS
- 0x82480000
- 0x82500000
* - BLOBS
- 0x82500000
- 0x82500400
* - EMPTY
- 0x82500400
- 0x82800000
Switch Setting for Boot Mode
----------------------------
Boot Mode pins provide means to select the boot mode and options before the
device is powered up. After every POR, they are the main source to populate
the Boot Parameter Tables.
The following table shows some common boot modes used on AM62 platform. More
details can be found in the Technical Reference Manual:
https://www.ti.com/lit/pdf/spruiv7 under the `Boot Mode Pins` section.
.. list-table:: Boot Modes
:widths: 16 16 16
:header-rows: 1
* - Switch Label
- SW2: 12345678
- SW3: 12345678
* - SD
- 01000000
- 11000010
* - OSPI
- 00000000
- 11001110
* - EMMC
- 00000000
- 11010010
* - UART
- 00000000
- 11011100
* - USB DFU
- 00000000
- 11001010
* - Ethernet
- 00110000
- 11000100
For SW2 and SW1, the switch state in the "ON" position = 1.
DFU based boot
--------------
To boot the board over DFU, set the switches to DFU mode and connect to the
USB type C DRD port on the board. After power-on the build artifacts needs to be
uploaded one by one with a tool like dfu-util.
The initial ROM will have a DFU alt named `bootloader` for the initial R5 spl
upload. The next stages as exposed by U-Boot have target alts matching the name
of the artifacts, for these a USB reset has to be done after each upload.
When using dfu-util the following commands can be used to boot to a U-Boot shell:
.. prompt:: bash $
dfu-util -a bootloader -D tiboot3.bin
dfu-util -R -a tispl -D tispl.bin
dfu-util -R -a u-boot.img -D u-boot.img
Debugging U-Boot
----------------
See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
detailed setup information.
.. warning::
**OpenOCD support since**: v0.12.0
If the default package version of OpenOCD in your development
environment's distribution needs to be updated, it might be necessary to
build OpenOCD from the source.
.. include:: k3.rst
:start-after: .. k3_rst_include_start_openocd_connect_XDS110
:end-before: .. k3_rst_include_end_openocd_connect_XDS110
To start OpenOCD and connect to the board
.. prompt:: bash $
openocd -f board/ti_am625evm.cfg

1
doc/board/ti/k3.rst
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@ -33,6 +33,7 @@ K3 Based SoCs
am62ax_sk
am62x_sk
am62px_sk
am6254atl_sk
am64x_evm
am65x_evm
j7200_evm

8
dts/upstream/src/arm64/ti/k3-am62-lp-sk.dts
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@ -7,12 +7,20 @@
/dts-v1/;
#include "k3-am625.dtsi"
#include "k3-am62x-sk-common.dtsi"
/ {
compatible = "ti,am62-lp-sk", "ti,am625";
model = "Texas Instruments AM62x LP SK";
memory@80000000 {
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
device_type = "memory";
bootph-pre-ram;
};
vmain_pd: regulator-0 {
/* TPS65988 PD CONTROLLER OUTPUT */
compatible = "regulator-fixed";

2
dts/upstream/src/arm64/ti/k3-am62-verdin.dtsi
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@ -189,7 +189,7 @@
regulator-name = "USB_1_EN";
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

296
dts/upstream/src/arm64/ti/k3-am625-sk-common.dtsi Normal file
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@ -0,0 +1,296 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Common dtsi for AM625 SK and derivatives
*
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am62x-sk-common.dtsi"
/ {
opp-table {
/* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-supported-hw = <0x01 0x0004>;
clock-latency-ns = <6000000>;
};
};
vmain_pd: regulator-0 {
/* TPS65988 PD CONTROLLER OUTPUT */
compatible = "regulator-fixed";
regulator-name = "vmain_pd";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
bootph-all;
};
vcc_5v0: regulator-1 {
/* Output of LM34936 */
compatible = "regulator-fixed";
regulator-name = "vcc_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vmain_pd>;
regulator-always-on;
regulator-boot-on;
bootph-all;
};
vcc_3v3_sys: regulator-2 {
/* output of LM61460-Q1 */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vmain_pd>;
regulator-always-on;
regulator-boot-on;
bootph-all;
};
vdd_mmc1: regulator-3 {
/* TPS22918DBVR */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vcc_3v3_sys>;
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
bootph-all;
};
vdd_sd_dv: regulator-4 {
/* Output of TLV71033 */
compatible = "regulator-gpio";
regulator-name = "tlv71033";
pinctrl-names = "default";
pinctrl-0 = <&vdd_sd_dv_pins_default>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&vcc_5v0>;
gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
states = <1800000 0x0>,
<3300000 0x1>;
bootph-all;
};
vcc_1v8: regulator-5 {
/* output of TPS6282518DMQ */
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3_sys>;
regulator-always-on;
regulator-boot-on;
};
};
&main_pmx0 {
main_mmc0_pins_default: main-mmc0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
>;
};
main_rgmii2_pins_default: main-rgmii2-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
>;
};
ospi0_pins_default: ospi0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
>;
};
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
>;
bootph-all;
};
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
>;
bootph-all;
};
};
&main_gpio0 {
bootph-all;
};
&main_gpio1 {
bootph-all;
};
&main_i2c1 {
exp1: gpio@22 {
compatible = "ti,tca6424";
reg = <0x22>;
pinctrl-names = "default";
pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
interrupt-parent = <&main_gpio1>;
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
"PRU_DETECT", "MMC1_SD_EN",
"VPP_LDO_EN", "EXP_PS_3V3_En",
"EXP_PS_5V0_En", "EXP_HAT_DETECT",
"GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
"UART1_FET_BUF_EN", "WL_LT_EN",
"GPIO_HDMI_RSTn", "CSI_GPIO1",
"CSI_GPIO2", "PRU_3V3_EN",
"HDMI_INTn", "PD_I2C_IRQ",
"MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
"MCASP1_FET_SEL", "UART1_FET_SEL",
"TSINT#", "IO_EXP_TEST_LED";
bootph-all;
};
};
&sdhci0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
disable-wp;
};
&sdhci1 {
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv>;
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
};
&cpsw_port2 {
/* PCB provides an internal delay of 2ns */
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
};
&cpsw3g_mdio {
cpsw3g_phy1: ethernet-phy@1 {
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
};
&fss {
bootph-all;
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootph-all;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "ospi.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "ospi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "ospi.env";
reg = <0x680000 0x40000>;
};
partition@6c0000 {
label = "ospi.env.backup";
reg = <0x6c0000 0x40000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
bootph-pre-ram;
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};

301
dts/upstream/src/arm64/ti/k3-am625-sk.dts
View File

@ -7,310 +7,17 @@
/dts-v1/;
#include "k3-am62x-sk-common.dtsi"
#include "k3-am625.dtsi"
#include "k3-am625-sk-common.dtsi"
/ {
compatible = "ti,am625-sk", "ti,am625";
model = "Texas Instruments AM625 SK";
opp-table {
/* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-supported-hw = <0x01 0x0004>;
clock-latency-ns = <6000000>;
};
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
vmain_pd: regulator-0 {
/* TPS65988 PD CONTROLLER OUTPUT */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vmain_pd";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vcc_5v0: regulator-1 {
/* Output of LM34936 */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vcc_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vmain_pd>;
regulator-always-on;
regulator-boot-on;
};
vcc_3v3_sys: regulator-2 {
/* output of LM61460-Q1 */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vmain_pd>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: regulator-3 {
/* TPS22918DBVR */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vcc_3v3_sys>;
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
vdd_sd_dv: regulator-4 {
/* Output of TLV71033 */
bootph-all;
compatible = "regulator-gpio";
regulator-name = "tlv71033";
pinctrl-names = "default";
pinctrl-0 = <&vdd_sd_dv_pins_default>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&vcc_5v0>;
gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
states = <1800000 0x0>,
<3300000 0x1>;
};
vcc_1v8: regulator-5 {
/* output of TPS6282518DMQ */
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3_sys>;
regulator-always-on;
regulator-boot-on;
device_type = "memory";
bootph-pre-ram;
};
};
&main_pmx0 {
main_mmc0_pins_default: main-mmc0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
>;
};
main_rgmii2_pins_default: main-rgmii2-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
>;
};
ospi0_pins_default: ospi0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
>;
};
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
>;
};
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
>;
};
};
&main_gpio0 {
bootph-all;
};
&main_gpio1 {
bootph-all;
};
&main_i2c1 {
bootph-all;
exp1: gpio@22 {
bootph-all;
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
"PRU_DETECT", "MMC1_SD_EN",
"VPP_LDO_EN", "EXP_PS_3V3_En",
"EXP_PS_5V0_En", "EXP_HAT_DETECT",
"GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
"UART1_FET_BUF_EN", "WL_LT_EN",
"GPIO_HDMI_RSTn", "CSI_GPIO1",
"CSI_GPIO2", "PRU_3V3_EN",
"HDMI_INTn", "PD_I2C_IRQ",
"MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
"MCASP1_FET_SEL", "UART1_FET_SEL",
"TSINT#", "IO_EXP_TEST_LED";
interrupt-parent = <&main_gpio1>;
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
};
};
&sdhci0 {
bootph-all;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
status = "okay";
};
&sdhci1 {
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv>;
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
};
&cpsw3g_mdio {
cpsw3g_phy1: ethernet-phy@1 {
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
};
&fss {
bootph-all;
};
&ospi0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0 {
bootph-all;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
partitions {
bootph-all;
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "ospi.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "ospi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "ospi.env";
reg = <0x680000 0x40000>;
};
partition@6c0000 {
label = "ospi.env.backup";
reg = <0x6c0000 0x40000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
bootph-pre-ram;
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};
&tlv320aic3106 {
DVDD-supply = <&vcc_1v8>;
};

15
dts/upstream/src/arm64/ti/k3-am6254atl-sk.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* AM6254atl SiP SK: https://www.ti.com/lit/df/sprr482b/sprr482b.zip
* Webpage: https://www.ti.com/tool/SK-AM62-SIP
*
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am6254atl.dtsi"
#include "k3-am625-sk-common.dtsi"
/ {
model = "Texas Instruments AM6254atl SK";
compatible = "ti,am6254atl-sk", "ti,am6254atl", "ti,am625";
};

23
dts/upstream/src/arm64/ti/k3-am6254atl.dtsi Normal file
View File

@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* DTS for AM625 SiP SoC family in Quad core configuration and 512MiB RAM.
*
* Webpage: https://www.ti.com/product/AM625SIP
*
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am625.dtsi"
/ {
model = "Texas Instruments AM6254atl SiP";
compatible = "ti,am6254atl", "ti,am625";
memory@80000000 {
/* 512MiB of integrated RAM */
reg = <0x00000000 0x80000000 0x00000000 0x20000000>;
device_type = "memory";
bootph-all;
};
};

2
dts/upstream/src/arm64/ti/k3-am62a-phycore-som.dtsi
View File

@ -45,7 +45,7 @@
bootph-all;
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

2
dts/upstream/src/arm64/ti/k3-am62a7-sk.dts
View File

@ -39,7 +39,7 @@
bootph-all;
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

2
dts/upstream/src/arm64/ti/k3-am62d2-evm.dts
View File

@ -39,7 +39,7 @@
bootph-all;
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

2
dts/upstream/src/arm64/ti/k3-am62p-verdin.dtsi
View File

@ -147,7 +147,7 @@
regulator-name = "+V_SODIMM";
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

2
dts/upstream/src/arm64/ti/k3-am62p5-sk.dts
View File

@ -44,7 +44,7 @@
bootph-pre-ram;
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

10
dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi
View File

@ -8,7 +8,6 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am625.dtsi"
/ {
aliases {
@ -29,14 +28,7 @@
stdout-path = "serial2:115200n8";
};
memory@80000000 {
bootph-pre-ram;
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

2
dts/upstream/src/arm64/ti/k3-am642-evm.dts
View File

@ -42,7 +42,7 @@
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

2
dts/upstream/src/arm64/ti/k3-am642-sk.dts
View File

@ -40,7 +40,7 @@
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

2
dts/upstream/src/arm64/ti/k3-am642-sr-som.dtsi
View File

@ -105,7 +105,7 @@
device_type = "memory";
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

2
dts/upstream/src/arm64/ti/k3-am642-tqma64xxl.dtsi
View File

@ -20,7 +20,7 @@
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

2
dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi
View File

@ -36,7 +36,7 @@
stdout-path = "serial3:115200n8";
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

2
dts/upstream/src/arm64/ti/k3-am654-base-board.dts
View File

@ -39,7 +39,7 @@
<0x00000008 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;