net: zynq_gem: set 128-bit AXI bus width for 10GBE

Set 128-bit AXI bus width in network config for 10GBE. The default 64-bit
setting causes DMA data corruption.

Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260410093018.1461732-3-pranav.vinaytilak@amd.com
This commit is contained in:
Pranav Tilak 2026-04-10 15:00:17 +05:30 committed by Michal Simek
parent 8342f57579
commit 0443deb428

View File

@ -69,10 +69,13 @@
#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
#define ZYNQ_GEM_DBUS_WIDTH_MASK (3 << 21) /* bits 22:21 */
#ifdef CONFIG_ARM64
# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
# define ZYNQ_GEM_DBUS_WIDTH_128 (2 << 21) /* 128 bit bus */
#else
# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
# define ZYNQ_GEM_DBUS_WIDTH_128 (0 << 21) /* 32 bit bus */
#endif
#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
@ -533,6 +536,8 @@ static int zynq_gem_init(struct udevice *dev)
nwconfig = ZYNQ_GEM_NWCFG_INIT;
if (device_is_compatible(dev, "amd,versal2-10gbe")) {
nwconfig &= ~ZYNQ_GEM_DBUS_WIDTH_MASK;
nwconfig |= ZYNQ_GEM_DBUS_WIDTH_128;
if (priv->interface == PHY_INTERFACE_MODE_10GBASER) {
ctrl = readl(&regs->nwcfg);
ctrl |= PCSSEL;