From 1054163c4dc79eef2732d1129990d47827ae1c06 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:30 +0100 Subject: [PATCH 01/33] clk: Add clk_resolve_parent_clk() Add clk_resolve_parent_clk() to resolve parent clock udevice name based on clock-names DT property. This is used in SoC clock drivers to look up the clock name in clock tables, which matches a clock name in DT clock-names property, and convert it into udevice name which is used by U-Boot clock framework to look up parent clock in e.g. clk_register() using uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent); Signed-off-by: Marek Vasut --- drivers/clk/clk-uclass.c | 18 ++++++++++++++++++ include/clk.h | 9 +++++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 353ae476068..90b70529a47 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -420,6 +420,24 @@ int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) return clk_get_by_index_nodev(node, index, clk); } +const char * +clk_resolve_parent_clk(struct udevice *dev, const char *name) +{ + struct udevice *parent; + struct clk clk; + int ret; + + ret = uclass_get_device_by_name(UCLASS_CLK, name, &parent); + if (!ret) + return name; + + ret = clk_get_by_name(dev, name, &clk); + if (!clk.dev) + return name; + + return clk.dev->name; +} + int clk_release_all(struct clk *clk, unsigned int count) { unsigned int i; diff --git a/include/clk.h b/include/clk.h index 045e923a529..a6ef4e02692 100644 --- a/include/clk.h +++ b/include/clk.h @@ -350,6 +350,15 @@ static inline int clk_get_by_name_nodev_optional(ofnode node, const char *name, return ret; } +/** + * clk_resolve_parent_clk - Determine name of clock udevice based on clock-names + * @dev: The client udevice. + * @name: The name of the clock to look up. + * + * Return name of the clock udevice which represents clock with clock-names name. + */ +const char *clk_resolve_parent_clk(struct udevice *dev, const char *name); + /** * enum clk_defaults_stage - What stage clk_set_defaults() is called at * @CLK_DEFAULTS_PRE: Called before probe. Setting of defaults for clocks owned From 7cc520fe297dba17f681377ad201f258f927c662 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:31 +0100 Subject: [PATCH 02/33] clk: clk-mux: Fold clk_register_mux() Neither clk_register_mux_table() nor clk_hw_register_mux_table() are called outside of clk-mux.c , fold both into clk_register_mux(). No functional change. Signed-off-by: Marek Vasut --- drivers/clk/clk-mux.c | 39 +++++---------------------------------- 1 file changed, 5 insertions(+), 34 deletions(-) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 62477e15d27..9507a779525 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -159,15 +159,15 @@ const struct clk_ops clk_mux_ops = { .set_parent = clk_mux_set_parent, }; -struct clk *clk_hw_register_mux_table(struct device *dev, const char *name, +struct clk *clk_register_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, - void __iomem *reg, u8 shift, u32 mask, - u8 clk_mux_flags, u32 *table) + void __iomem *reg, u8 shift, u8 width, + u8 clk_mux_flags) { + u32 mask = BIT(width) - 1; struct clk_mux *mux; struct clk *clk; - u8 width = 0; int ret; if (clk_mux_flags & CLK_MUX_HIWORD_MASK) { @@ -192,7 +192,7 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name, mux->shift = shift; mux->mask = mask; mux->flags = clk_mux_flags; - mux->table = table; + mux->table = NULL; #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) mux->io_mux_val = *(u32 *)reg; #endif @@ -216,35 +216,6 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name, return clk; } -struct clk *clk_register_mux_table(struct device *dev, const char *name, - const char * const *parent_names, u8 num_parents, - unsigned long flags, - void __iomem *reg, u8 shift, u32 mask, - u8 clk_mux_flags, u32 *table) -{ - struct clk *clk; - - clk = clk_hw_register_mux_table(dev, name, parent_names, num_parents, - flags, reg, shift, mask, clk_mux_flags, - table); - if (IS_ERR(clk)) - return ERR_CAST(clk); - return clk; -} - -struct clk *clk_register_mux(struct device *dev, const char *name, - const char * const *parent_names, u8 num_parents, - unsigned long flags, - void __iomem *reg, u8 shift, u8 width, - u8 clk_mux_flags) -{ - u32 mask = BIT(width) - 1; - - return clk_register_mux_table(dev, name, parent_names, num_parents, - flags, reg, shift, mask, clk_mux_flags, - NULL); -} - U_BOOT_DRIVER(ccf_clk_mux) = { .name = UBOOT_DM_CLK_CCF_MUX, .id = UCLASS_CLK, From 54a4c83b12ae81289df93c048c4dd6f62481d242 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:32 +0100 Subject: [PATCH 03/33] clk: clk-mux: Use struct udevice instead of struct device Use U-Boot specific struct udevice instead of Linux compatibility struct device in clk-mux registration. Signed-off-by: Marek Vasut --- drivers/clk/clk-mux.c | 2 +- include/linux/clk-provider.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 9507a779525..e2331a07840 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -159,7 +159,7 @@ const struct clk_ops clk_mux_ops = { .set_parent = clk_mux_set_parent, }; -struct clk *clk_register_mux(struct device *dev, const char *name, +struct clk *clk_register_mux(struct udevice *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u8 width, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 59f9c241b84..f27878ae6fa 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -242,7 +242,7 @@ struct clk *clk_register_divider(struct device *dev, const char *name, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags); -struct clk *clk_register_mux(struct device *dev, const char *name, +struct clk *clk_register_mux(struct udevice *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u8 width, From 3070d30df12f7b17551a51942324cd86332b0cbe Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:33 +0100 Subject: [PATCH 04/33] clk: clk-mux: Resolve parent clock by name Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut --- drivers/clk/clk-mux.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index e2331a07840..d7411f8f282 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -113,6 +113,11 @@ int clk_mux_fetch_parent_index(struct clk *clk, struct clk *parent) for (i = 0; i < mux->num_parents; i++) { if (!strcmp(parent->dev->name, mux->parent_names[i])) return i; + if (!strcmp(parent->dev->name, + clk_resolve_parent_clk(clk->dev, + mux->parent_names[i]))) + return i; + } return -EINVAL; @@ -207,7 +212,8 @@ struct clk *clk_register_mux(struct udevice *dev, const char *name, * for the corresponding clock (to do that define .set_parent() method). */ ret = clk_register(clk, UBOOT_DM_CLK_CCF_MUX, name, - parent_names[clk_mux_get_parent(clk)]); + clk_resolve_parent_clk(dev, + parent_names[clk_mux_get_parent(clk)])); if (ret) { kfree(mux); return ERR_PTR(ret); From eca4e5e01394c374b2f44d48efe3dc99d185554a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:34 +0100 Subject: [PATCH 05/33] clk: imx: Pass struct udevice into imx_clk_mux*() Pass struct udevice * into imx_clk_mux*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut --- drivers/clk/imx/clk-imx6q.c | 16 +++++++------- drivers/clk/imx/clk-imx8mm.c | 24 ++++++++++----------- drivers/clk/imx/clk-imx8mn.c | 24 ++++++++++----------- drivers/clk/imx/clk-imx8mp.c | 26 +++++++++++----------- drivers/clk/imx/clk-imx8mq.c | 38 ++++++++++++++++----------------- drivers/clk/imx/clk-imx93.c | 2 +- drivers/clk/imx/clk-imxrt1020.c | 18 ++++++++-------- drivers/clk/imx/clk-imxrt1050.c | 32 +++++++++++++-------------- drivers/clk/imx/clk-imxrt1170.c | 8 +++---- drivers/clk/imx/clk.h | 12 +++++------ 10 files changed, 100 insertions(+), 100 deletions(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 61ca2982add..92b79a3a02c 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -68,24 +68,24 @@ static int imx6q_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMX6QDL_CLK_USDHC1_SEL, - imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, + imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC2_SEL, - imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, + imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC3_SEL, - imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, + imx_clk_mux(dev, "usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC4_SEL, - imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, + imx_clk_mux(dev, "usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); if (of_machine_is_compatible("fsl,imx6qp")) { clk_dm(IMX6QDL_CLK_UART_SEL, - imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, + imx_clk_mux(dev, "uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels))); clk_dm(IMX6QDL_CLK_ECSPI_SEL, - imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, + imx_clk_mux(dev, "ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels))); } @@ -136,10 +136,10 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8)); clk_dm(IMX6QDL_CLK_PERIPH_PRE, - imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, + imx_clk_mux(dev, "periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels))); clk_dm(IMX6QDL_CLK_PERIPH, - imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, + imx_clk_busy_mux(dev, "periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels))); clk_dm(IMX6QDL_CLK_AHB, imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 378c07caba3..54eaff273d0 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -172,19 +172,19 @@ static int imx8mm_clk_probe(struct udevice *dev) base = (void *)ANATOP_BASE_ADDR; clk_dm(IMX8MM_DRAM_PLL_REF_SEL, - imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, + imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MM_ARM_PLL_REF_SEL, - imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, + imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MM_SYS_PLL1_REF_SEL, - imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, + imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MM_SYS_PLL2_REF_SEL, - imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, + imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MM_SYS_PLL3_REF_SEL, - imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, + imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MM_DRAM_PLL, @@ -205,27 +205,27 @@ static int imx8mm_clk_probe(struct udevice *dev) /* PLL bypass out */ clk_dm(IMX8MM_DRAM_PLL_BYPASS, - imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, + imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MM_ARM_PLL_BYPASS, - imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, + imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MM_SYS_PLL1_BYPASS, - imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, + imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MM_SYS_PLL2_BYPASS, - imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, + imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MM_SYS_PLL3_BYPASS, - imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, + imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT)); @@ -291,7 +291,7 @@ static int imx8mm_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMX8MM_CLK_A53_SRC, - imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, + imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels))); clk_dm(IMX8MM_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); @@ -454,7 +454,7 @@ static int imx8mm_clk_probe(struct udevice *dev) #endif clk_dm(IMX8MM_CLK_ARM, - imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1, + imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1, imx8mm_arm_core_sels, ARRAY_SIZE(imx8mm_arm_core_sels), CLK_IS_CRITICAL)); diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 54ae887817a..dbc94ff9450 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -164,19 +164,19 @@ static int imx8mn_clk_probe(struct udevice *dev) base = (void *)ANATOP_BASE_ADDR; clk_dm(IMX8MN_DRAM_PLL_REF_SEL, - imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, + imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MN_ARM_PLL_REF_SEL, - imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, + imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MN_SYS_PLL1_REF_SEL, - imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, + imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MN_SYS_PLL2_REF_SEL, - imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, + imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MN_SYS_PLL3_REF_SEL, - imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, + imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MN_DRAM_PLL, @@ -197,27 +197,27 @@ static int imx8mn_clk_probe(struct udevice *dev) /* PLL bypass out */ clk_dm(IMX8MN_DRAM_PLL_BYPASS, - imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, + imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MN_ARM_PLL_BYPASS, - imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, + imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MN_SYS_PLL1_BYPASS, - imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, + imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MN_SYS_PLL2_BYPASS, - imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, + imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MN_SYS_PLL3_BYPASS, - imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, + imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT)); @@ -288,7 +288,7 @@ static int imx8mn_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMX8MN_CLK_A53_SRC, - imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, + imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels))); clk_dm(IMX8MN_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); @@ -438,7 +438,7 @@ static int imx8mn_clk_probe(struct udevice *dev) #endif clk_dm(IMX8MN_CLK_ARM, - imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1, + imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1, imx8mn_arm_core_sels, ARRAY_SIZE(imx8mn_arm_core_sels), CLK_IS_CRITICAL)); diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 1d04090ca00..4b916bef7a1 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -199,11 +199,11 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0)); - clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); - clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); - clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); - clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); - clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll)); @@ -216,11 +216,11 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll)); - clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT)); - clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT)); - clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT)); - clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT)); - clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT)); + clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT)); + clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT)); + clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT)); + clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT)); + clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13)); clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11)); @@ -262,7 +262,7 @@ static int imx8mp_clk_probe(struct udevice *dev) if (!base) return -EINVAL; - clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels))); + clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels))); clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); @@ -314,7 +314,7 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80)); clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4)); - clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL)); + clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags(dev, "dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL)); clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL)); clk_dm(IMX8MP_CLK_ECSPI1_ROOT, imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); @@ -359,7 +359,7 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); clk_dm(IMX8MP_CLK_ARM, - imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1, + imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1, imx8mp_arm_core_sels, ARRAY_SIZE(imx8mp_arm_core_sels), CLK_IS_CRITICAL)); diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index ed4acd79ef7..dc9b7d56815 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -152,31 +152,31 @@ static int imx8mq_clk_probe(struct udevice *dev) clk_dm(IMX8MQ_CLK_27M, clk_register_fixed_rate(NULL, "clock-osc-27m", 27000000)); clk_dm(IMX8MQ_DRAM_PLL1_REF_SEL, - imx_clk_mux("dram_pll_ref_sel", base + 0x60, 0, 2, + imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_ARM_PLL_REF_SEL, - imx_clk_mux("arm_pll_ref_sel", base + 0x28, 0, 2, + imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_GPU_PLL_REF_SEL, - imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 0, 2, + imx_clk_mux(dev, "gpu_pll_ref_sel", base + 0x18, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_VPU_PLL_REF_SEL, - imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 0, 2, + imx_clk_mux(dev, "vpu_pll_ref_sel", base + 0x20, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_SYS3_PLL1_REF_SEL, - imx_clk_mux("sys3_pll_ref_sel", base + 0x48, 0, 2, + imx_clk_mux(dev, "sys3_pll_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_AUDIO_PLL1_REF_SEL, - imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, + imx_clk_mux(dev, "audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_AUDIO_PLL2_REF_SEL, - imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 0, 2, + imx_clk_mux(dev, "audio_pll2_ref_sel", base + 0x8, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_VIDEO_PLL1_REF_SEL, - imx_clk_mux("video_pll1_ref_sel", base + 0x10, 0, 2, + imx_clk_mux(dev, "video_pll1_ref_sel", base + 0x10, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_VIDEO2_PLL1_REF_SEL, - imx_clk_mux("video_pll2_ref_sel", base + 0x54, 0, 2, + imx_clk_mux(dev, "video_pll2_ref_sel", base + 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_ARM_PLL, @@ -207,32 +207,32 @@ static int imx8mq_clk_probe(struct udevice *dev) /* PLL bypass out */ clk_dm(IMX8MQ_ARM_PLL_BYPASS, - imx_clk_mux_flags("arm_pll_bypass", base + 0x28, 4, 1, + imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x28, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MQ_GPU_PLL_BYPASS, - imx_clk_mux_flags("gpu_pll_bypass", base + 0x18, 4, 1, + imx_clk_mux_flags(dev, "gpu_pll_bypass", base + 0x18, 4, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MQ_VPU_PLL_BYPASS, - imx_clk_mux_flags("vpu_pll_bypass", base + 0x20, 4, 1, + imx_clk_mux_flags(dev, "vpu_pll_bypass", base + 0x20, 4, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MQ_AUDIO_PLL1_BYPASS, - imx_clk_mux_flags("audio_pll1_bypass", base + 0x0, 4, 1, + imx_clk_mux_flags(dev, "audio_pll1_bypass", base + 0x0, 4, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MQ_AUDIO_PLL2_BYPASS, - imx_clk_mux_flags("audio_pll2_bypass", base + 0x8, 4, 1, + imx_clk_mux_flags(dev, "audio_pll2_bypass", base + 0x8, 4, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MQ_VIDEO_PLL1_BYPASS, - imx_clk_mux_flags("video_pll1_bypass", base + 0x10, 4, 1, + imx_clk_mux_flags(dev, "video_pll1_bypass", base + 0x10, 4, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT)); @@ -335,7 +335,7 @@ static int imx8mq_clk_probe(struct udevice *dev) clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL2_DIV, imx_clk_divider("video_pll2_out_monitor", "video_pll2_out", base + 0x7c, 16, 3)); clk_dm(IMX8MQ_CLK_MON_SEL, - imx_clk_mux_flags("pllout_monitor_sel", base + 0x74, 0, 4, + imx_clk_mux_flags(dev, "pllout_monitor_sel", base + 0x74, 0, 4, pllout_monitor_sels, ARRAY_SIZE(pllout_monitor_sels), CLK_SET_RATE_PARENT)); @@ -349,7 +349,7 @@ static int imx8mq_clk_probe(struct udevice *dev) } clk_dm(IMX8MQ_CLK_A53_SRC, - imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, + imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels))); clk_dm(IMX8MQ_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); @@ -357,7 +357,7 @@ static int imx8mq_clk_probe(struct udevice *dev) imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); clk_dm(IMX8MQ_CLK_A53_CORE, - imx_clk_mux2("arm_a53_src", base + 0x9880, 24, 1, + imx_clk_mux2(dev, "arm_a53_src", base + 0x9880, 24, 1, imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels))); clk_dm(IMX8MQ_CLK_AHB, @@ -378,7 +378,7 @@ static int imx8mq_clk_probe(struct udevice *dev) /* DRAM */ clk_dm(IMX8MQ_CLK_DRAM_CORE, - imx_clk_mux2("dram_core_clk", base + 0x9800, 24, 1, + imx_clk_mux2(dev, "dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels))); clk_dm(IMX8MQ_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000)); diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index b31e57a4a01..0caec91fd9a 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -338,7 +338,7 @@ static int imx93_clk_probe(struct udevice *dev) } clk_dm(IMX93_CLK_A55_SEL, - imx_clk_mux2("a55_sel", base + 0x4820, 0, 1, + imx_clk_mux2(dev, "a55_sel", base + 0x4820, 0, 1, a55_core_sels, ARRAY_SIZE(a55_core_sels))); return 0; diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c index 752434cb0ad..16fc3bcdb3e 100644 --- a/drivers/clk/imx/clk-imxrt1020.c +++ b/drivers/clk/imx/clk-imxrt1020.c @@ -46,12 +46,12 @@ static int imxrt1020_clk_probe(struct udevice *dev) /* PLL bypass out */ clk_dm(IMXRT1020_CLK_PLL2_BYPASS, - imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, + imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMXRT1020_CLK_PLL3_BYPASS, - imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, + imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT)); @@ -78,25 +78,25 @@ static int imxrt1020_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMXRT1020_CLK_PRE_PERIPH_SEL, - imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, + imx_clk_mux(dev, "pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels))); clk_dm(IMXRT1020_CLK_PERIPH_SEL, - imx_clk_mux("periph_sel", base + 0x14, 25, 1, + imx_clk_mux(dev, "periph_sel", base + 0x14, 25, 1, periph_sels, ARRAY_SIZE(periph_sels))); clk_dm(IMXRT1020_CLK_USDHC1_SEL, - imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, + imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMXRT1020_CLK_USDHC2_SEL, - imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, + imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMXRT1020_CLK_LPUART_SEL, - imx_clk_mux("lpuart_sel", base + 0x24, 6, 1, + imx_clk_mux(dev, "lpuart_sel", base + 0x24, 6, 1, lpuart_sels, ARRAY_SIZE(lpuart_sels))); clk_dm(IMXRT1020_CLK_SEMC_ALT_SEL, - imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1, + imx_clk_mux(dev, "semc_alt_sel", base + 0x14, 7, 1, semc_alt_sels, ARRAY_SIZE(semc_alt_sels))); clk_dm(IMXRT1020_CLK_SEMC_SEL, - imx_clk_mux("semc_sel", base + 0x14, 6, 1, + imx_clk_mux(dev, "semc_sel", base + 0x14, 6, 1, semc_sels, ARRAY_SIZE(semc_sels))); clk_dm(IMXRT1020_CLK_AHB_PODF, diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 2c029ec5a6e..5f37915f593 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -36,16 +36,16 @@ static int imxrt1050_clk_probe(struct udevice *dev) base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop")); clk_dm(IMXRT1050_CLK_PLL1_REF_SEL, - imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2, + imx_clk_mux(dev, "pll1_arm_ref_sel", base + 0x0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMXRT1050_CLK_PLL2_REF_SEL, - imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14, 2, + imx_clk_mux(dev, "pll2_sys_ref_sel", base + 0x30, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMXRT1050_CLK_PLL3_REF_SEL, - imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10, 14, 2, + imx_clk_mux(dev, "pll3_usb_otg_ref_sel", base + 0x10, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMXRT1050_CLK_PLL5_REF_SEL, - imx_clk_mux("pll5_video_ref_sel", base + 0xa0, 14, 2, + imx_clk_mux(dev, "pll5_video_ref_sel", base + 0xa0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMXRT1050_CLK_PLL1_ARM, @@ -64,22 +64,22 @@ static int imxrt1050_clk_probe(struct udevice *dev) /* PLL bypass out */ clk_dm(IMXRT1050_CLK_PLL1_BYPASS, - imx_clk_mux_flags("pll1_bypass", base + 0x0, 16, 1, + imx_clk_mux_flags(dev, "pll1_bypass", base + 0x0, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMXRT1050_CLK_PLL2_BYPASS, - imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, + imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMXRT1050_CLK_PLL3_BYPASS, - imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, + imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMXRT1050_CLK_PLL5_BYPASS, - imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, + imx_clk_mux_flags(dev, "pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT)); @@ -117,28 +117,28 @@ static int imxrt1050_clk_probe(struct udevice *dev) base + 0x10, 0, 3)); clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL, - imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, + imx_clk_mux(dev, "pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels))); clk_dm(IMXRT1050_CLK_PERIPH_SEL, - imx_clk_mux("periph_sel", base + 0x14, 25, 1, + imx_clk_mux(dev, "periph_sel", base + 0x14, 25, 1, periph_sels, ARRAY_SIZE(periph_sels))); clk_dm(IMXRT1050_CLK_USDHC1_SEL, - imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, + imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMXRT1050_CLK_USDHC2_SEL, - imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, + imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMXRT1050_CLK_LPUART_SEL, - imx_clk_mux("lpuart_sel", base + 0x24, 6, 1, + imx_clk_mux(dev, "lpuart_sel", base + 0x24, 6, 1, lpuart_sels, ARRAY_SIZE(lpuart_sels))); clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL, - imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1, + imx_clk_mux(dev, "semc_alt_sel", base + 0x14, 7, 1, semc_alt_sels, ARRAY_SIZE(semc_alt_sels))); clk_dm(IMXRT1050_CLK_SEMC_SEL, - imx_clk_mux("semc_sel", base + 0x14, 6, 1, + imx_clk_mux(dev, "semc_sel", base + 0x14, 6, 1, semc_sels, ARRAY_SIZE(semc_sels))); clk_dm(IMXRT1050_CLK_LCDIF_SEL, - imx_clk_mux("lcdif_sel", base + 0x38, 15, 3, + imx_clk_mux(dev, "lcdif_sel", base + 0x38, 15, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels))); clk_dm(IMXRT1050_CLK_AHB_PODF, diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c index 88a294f4165..7e06504584f 100644 --- a/drivers/clk/imx/clk-imxrt1170.c +++ b/drivers/clk/imx/clk-imxrt1170.c @@ -157,28 +157,28 @@ static int imxrt1170_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMXRT1170_CLK_LPUART1_SEL, - imx_clk_mux("lpuart1_sel", base + (25 * 0x80), 8, 3, + imx_clk_mux(dev, "lpuart1_sel", base + (25 * 0x80), 8, 3, lpuart1_sels, ARRAY_SIZE(lpuart1_sels))); clk_dm(IMXRT1170_CLK_LPUART1, imx_clk_divider("lpuart1", "lpuart1_sel", base + (25 * 0x80), 0, 8)); clk_dm(IMXRT1170_CLK_USDHC1_SEL, - imx_clk_mux("usdhc1_sel", base + (58 * 0x80), 8, 3, + imx_clk_mux(dev, "usdhc1_sel", base + (58 * 0x80), 8, 3, usdhc1_sels, ARRAY_SIZE(usdhc1_sels))); clk_dm(IMXRT1170_CLK_USDHC1, imx_clk_divider("usdhc1", "usdhc1_sel", base + (58 * 0x80), 0, 8)); clk_dm(IMXRT1170_CLK_GPT1_SEL, - imx_clk_mux("gpt1_sel", base + (14 * 0x80), 8, 3, + imx_clk_mux(dev, "gpt1_sel", base + (14 * 0x80), 8, 3, gpt1_sels, ARRAY_SIZE(gpt1_sels))); clk_dm(IMXRT1170_CLK_GPT1, imx_clk_divider("gpt1", "gpt1_sel", base + (14 * 0x80), 0, 8)); clk_dm(IMXRT1170_CLK_SEMC_SEL, - imx_clk_mux("semc_sel", base + (4 * 0x80), 8, 3, + imx_clk_mux(dev, "semc_sel", base + (4 * 0x80), 8, 3, semc_sels, ARRAY_SIZE(semc_sels))); clk_dm(IMXRT1170_CLK_SEMC, imx_clk_divider("semc", "semc_sel", diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 27a53ae5583..f18249ee8a8 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -167,7 +167,7 @@ struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, void (*fixup)(u32 *val)); -static inline struct clk *imx_clk_mux_flags(const char *name, +static inline struct clk *imx_clk_mux_flags(struct udevice *dev, const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, unsigned long flags) @@ -177,7 +177,7 @@ static inline struct clk *imx_clk_mux_flags(const char *name, width, 0); } -static inline struct clk *imx_clk_mux2_flags(const char *name, +static inline struct clk *imx_clk_mux2_flags(struct udevice *dev, const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, unsigned long flags) @@ -187,8 +187,8 @@ static inline struct clk *imx_clk_mux2_flags(const char *name, reg, shift, width, 0); } -static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, - u8 shift, u8 width, const char * const *parents, +static inline struct clk *imx_clk_mux(struct udevice *dev, const char *name, + void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents) { return clk_register_mux(NULL, name, parents, num_parents, @@ -197,7 +197,7 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, } static inline struct clk * -imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width, +imx_clk_busy_mux(struct udevice *dev, const char *name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift, const char * const *parents, int num_parents) { @@ -206,7 +206,7 @@ imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width, width, 0); } -static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, +static inline struct clk *imx_clk_mux2(struct udevice *dev, const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents) { From 0a930930f88bed1f195fc8a4b5103df3263a41ce Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:35 +0100 Subject: [PATCH 06/33] clk: imx: Pass struct udevice to clk_register_mux() Pass U-Boot specific struct udevice pointer to clock parent device to clk_register_mux(), so clk_register_mux() can access the parent udevice. Signed-off-by: Marek Vasut --- drivers/clk/imx/clk.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index f18249ee8a8..6f0ae86f612 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -172,7 +172,7 @@ static inline struct clk *imx_clk_mux_flags(struct udevice *dev, const char *nam const char * const *parents, int num_parents, unsigned long flags) { - return clk_register_mux(NULL, name, parents, num_parents, + return clk_register_mux(dev, name, parents, num_parents, flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0); } @@ -182,7 +182,7 @@ static inline struct clk *imx_clk_mux2_flags(struct udevice *dev, const char *na const char * const *parents, int num_parents, unsigned long flags) { - return clk_register_mux(NULL, name, parents, num_parents, + return clk_register_mux(dev, name, parents, num_parents, flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, reg, shift, width, 0); } @@ -191,7 +191,7 @@ static inline struct clk *imx_clk_mux(struct udevice *dev, const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents) { - return clk_register_mux(NULL, name, parents, num_parents, + return clk_register_mux(dev, name, parents, num_parents, CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0); } @@ -201,7 +201,7 @@ imx_clk_busy_mux(struct udevice *dev, const char *name, void __iomem *reg, u8 sh void __iomem *busy_reg, u8 busy_shift, const char * const *parents, int num_parents) { - return clk_register_mux(NULL, name, parents, num_parents, + return clk_register_mux(dev, name, parents, num_parents, CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0); } @@ -210,7 +210,7 @@ static inline struct clk *imx_clk_mux2(struct udevice *dev, const char *name, vo u8 shift, u8 width, const char * const *parents, int num_parents) { - return clk_register_mux(NULL, name, parents, num_parents, + return clk_register_mux(dev, name, parents, num_parents, CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, reg, shift, width, 0); } From aee51ad0d945cf3ffbad143adb76aba40f66ecb7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:36 +0100 Subject: [PATCH 07/33] clk: clk-gate: Use struct udevice instead of struct device Use U-Boot specific struct udevice instead of Linux compatibility struct device in clk-gate registration. Signed-off-by: Marek Vasut --- drivers/clk/clk-gate.c | 2 +- include/linux/clk-provider.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index bf1c6a93b46..cef98720b69 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -117,7 +117,7 @@ const struct clk_ops clk_gate_ops = { .get_rate = clk_generic_get_rate, }; -struct clk *clk_register_gate(struct device *dev, const char *name, +struct clk *clk_register_gate(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index f27878ae6fa..e282be12897 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -105,7 +105,7 @@ struct clk_gate { #define CLK_GATE_HIWORD_MASK BIT(1) extern const struct clk_ops clk_gate_ops; -struct clk *clk_register_gate(struct device *dev, const char *name, +struct clk *clk_register_gate(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); From 742e0205d1938f272413455492b4deff016c1031 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:37 +0100 Subject: [PATCH 08/33] clk: clk-gate: Resolve parent clock by name Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut --- drivers/clk/clk-gate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index cef98720b69..256ff108991 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -149,7 +149,8 @@ struct clk *clk_register_gate(struct udevice *dev, const char *name, clk = &gate->clk; clk->flags = flags; - ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name); + ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, + clk_resolve_parent_clk(dev, parent_name)); if (ret) { kfree(gate); return ERR_PTR(ret); From 2eafd7a28edc8fe8be42aca475dcb1b8bc066f21 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:38 +0100 Subject: [PATCH 09/33] clk: imx: gate2: Use struct udevice instead of struct device Use U-Boot specific struct udevice instead of Linux compatibility struct device in gate2 clock registration. Signed-off-by: Marek Vasut --- drivers/clk/imx/clk-gate2.c | 2 +- drivers/clk/imx/clk.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index 65fa6b5b139..400121a8ae1 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -90,7 +90,7 @@ static const struct clk_ops clk_gate2_ops = { .get_rate = clk_generic_get_rate, }; -struct clk *clk_register_gate2(struct device *dev, const char *name, +struct clk *clk_register_gate2(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 clk_gate2_flags, unsigned int *share_count) diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 6f0ae86f612..6f964f2679f 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -78,7 +78,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, void __iomem *base, const struct imx_pll14xx_clk *pll_clk); -struct clk *clk_register_gate2(struct device *dev, const char *name, +struct clk *clk_register_gate2(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 clk_gate_flags, unsigned int *share_count); From 5d82183d4a7506768eb48437a81f545958eb72a3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:39 +0100 Subject: [PATCH 10/33] clk: imx: gate2: Resolve parent clock by name Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut --- drivers/clk/imx/clk-gate2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index 400121a8ae1..fa07b13249b 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -111,7 +111,8 @@ struct clk *clk_register_gate2(struct udevice *dev, const char *name, clk = &gate->clk; - ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name, parent_name); + ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name, + clk_resolve_parent_clk(dev, parent_name)); if (ret) { kfree(gate); return ERR_PTR(ret); From e7f32d75615f3b5aeff44619145b2c88ccc58a0c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:40 +0100 Subject: [PATCH 11/33] clk: imx: Pass struct udevice into imx_clk_gate*() Pass struct udevice * into imx_clk_gate*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut --- drivers/clk/imx/clk-imx6q.c | 32 ++++++------ drivers/clk/imx/clk-imx8mm.c | 56 ++++++++++---------- drivers/clk/imx/clk-imx8mn.c | 66 +++++++++++------------ drivers/clk/imx/clk-imx8mp.c | 92 ++++++++++++++++----------------- drivers/clk/imx/clk-imx8mq.c | 72 +++++++++++++------------- drivers/clk/imx/clk-imxrt1020.c | 8 +-- drivers/clk/imx/clk-imxrt1050.c | 14 ++--- drivers/clk/imx/clk.h | 28 +++++----- 8 files changed, 186 insertions(+), 182 deletions(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 92b79a3a02c..d9eb43d82be 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -60,7 +60,7 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3)); clk_dm(IMX6QDL_CLK_PLL6_ENET, - imx_clk_gate("pll6_enet", "pll6", base + 0xe0, 13)); + imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); /* CCM clocks */ base = dev_read_addr_ptr(dev); @@ -115,25 +115,25 @@ static int imx6q_clk_probe(struct udevice *dev) } clk_dm(IMX6QDL_CLK_ECSPI1, - imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0)); + imx_clk_gate2(dev, "ecspi1", "ecspi_root", base + 0x6c, 0)); clk_dm(IMX6QDL_CLK_ECSPI2, - imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2)); + imx_clk_gate2(dev, "ecspi2", "ecspi_root", base + 0x6c, 2)); clk_dm(IMX6QDL_CLK_ECSPI3, - imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4)); + imx_clk_gate2(dev, "ecspi3", "ecspi_root", base + 0x6c, 4)); clk_dm(IMX6QDL_CLK_ECSPI4, - imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6)); + imx_clk_gate2(dev, "ecspi4", "ecspi_root", base + 0x6c, 6)); clk_dm(IMX6QDL_CLK_UART_IPG, - imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24)); + imx_clk_gate2(dev, "uart_ipg", "ipg", base + 0x7c, 24)); clk_dm(IMX6QDL_CLK_UART_SERIAL, - imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26)); + imx_clk_gate2(dev, "uart_serial", "uart_serial_podf", base + 0x7c, 26)); clk_dm(IMX6QDL_CLK_USDHC1, - imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2)); + imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2)); clk_dm(IMX6QDL_CLK_USDHC2, - imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4)); + imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4)); clk_dm(IMX6QDL_CLK_USDHC3, - imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6)); + imx_clk_gate2(dev, "usdhc3", "usdhc3_podf", base + 0x80, 6)); clk_dm(IMX6QDL_CLK_USDHC4, - imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8)); + imx_clk_gate2(dev, "usdhc4", "usdhc4_podf", base + 0x80, 8)); clk_dm(IMX6QDL_CLK_PERIPH_PRE, imx_clk_mux(dev, "periph_pre", base + 0x18, 18, 2, periph_pre_sels, @@ -149,15 +149,15 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_IPG_PER, imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6)); clk_dm(IMX6QDL_CLK_I2C1, - imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6)); + imx_clk_gate2(dev, "i2c1", "ipg_per", base + 0x70, 6)); clk_dm(IMX6QDL_CLK_I2C2, - imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8)); + imx_clk_gate2(dev, "i2c2", "ipg_per", base + 0x70, 8)); clk_dm(IMX6QDL_CLK_I2C3, - imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10)); + imx_clk_gate2(dev, "i2c3", "ipg_per", base + 0x70, 10)); clk_dm(IMX6QDL_CLK_PWM1, - imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16)); + imx_clk_gate2(dev, "pwm1", "ipg_per", base + 0x78, 16)); - clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10)); + clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); clk_dm(IMX6QDL_CLK_ENET_REF, imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1)); diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 54eaff273d0..30762666754 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -232,19 +232,19 @@ static int imx8mm_clk_probe(struct udevice *dev) /* PLL out gate */ clk_dm(IMX8MM_DRAM_PLL_OUT, - imx_clk_gate("dram_pll_out", "dram_pll_bypass", + imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass", base + 0x50, 13)); clk_dm(IMX8MM_ARM_PLL_OUT, - imx_clk_gate("arm_pll_out", "arm_pll_bypass", + imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass", base + 0x84, 11)); clk_dm(IMX8MM_SYS_PLL1_OUT, - imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", + imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11)); clk_dm(IMX8MM_SYS_PLL2_OUT, - imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", + imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11)); clk_dm(IMX8MM_SYS_PLL3_OUT, - imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", + imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11)); /* SYS PLL fixed output */ @@ -294,7 +294,7 @@ static int imx8mm_clk_probe(struct udevice *dev) imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels))); clk_dm(IMX8MM_CLK_A53_CG, - imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); + imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); clk_dm(IMX8MM_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); @@ -366,29 +366,29 @@ static int imx8mm_clk_probe(struct udevice *dev) clk_dm(IMX8MM_CLK_USB_PHY_REF, imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180)); clk_dm(IMX8MM_CLK_I2C1_ROOT, - imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0)); + imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0)); clk_dm(IMX8MM_CLK_I2C2_ROOT, - imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0)); + imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0)); clk_dm(IMX8MM_CLK_I2C3_ROOT, - imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); + imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0)); clk_dm(IMX8MM_CLK_I2C4_ROOT, - imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); + imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0)); clk_dm(IMX8MM_CLK_OCOTP_ROOT, - imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0)); + imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0)); clk_dm(IMX8MM_CLK_USDHC1_ROOT, - imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); + imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MM_CLK_USDHC2_ROOT, - imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); + imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); clk_dm(IMX8MM_CLK_WDOG1_ROOT, - imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0)); + imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0)); clk_dm(IMX8MM_CLK_WDOG2_ROOT, - imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0)); + imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0)); clk_dm(IMX8MM_CLK_WDOG3_ROOT, - imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0)); + imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0)); clk_dm(IMX8MM_CLK_USDHC3_ROOT, - imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); + imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT, - imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); + imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); /* clks not needed in SPL stage */ #ifndef CONFIG_XPL_BUILD @@ -405,7 +405,7 @@ static int imx8mm_clk_probe(struct udevice *dev) imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels, base + 0xaa80)); clk_dm(IMX8MM_CLK_ENET1_ROOT, - imx_clk_gate4("enet1_root_clk", "enet_axi", + imx_clk_gate4(dev, "enet1_root_clk", "enet_axi", base + 0x40a0, 0)); clk_dm(IMX8MM_CLK_PWM1, imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380)); @@ -416,18 +416,18 @@ static int imx8mm_clk_probe(struct udevice *dev) clk_dm(IMX8MM_CLK_PWM4, imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500)); clk_dm(IMX8MM_CLK_PWM1_ROOT, - imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0)); + imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0)); clk_dm(IMX8MM_CLK_PWM2_ROOT, - imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0)); + imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0)); clk_dm(IMX8MM_CLK_PWM3_ROOT, - imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0)); + imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0)); clk_dm(IMX8MM_CLK_PWM4_ROOT, - imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0)); + imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0)); #endif #if CONFIG_IS_ENABLED(PCIE_DW_IMX) clk_dm(IMX8MM_CLK_PCIE1_ROOT, - imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0)); + imx_clk_gate4(dev, "pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0)); #endif #if CONFIG_IS_ENABLED(DM_SPI) @@ -439,18 +439,18 @@ static int imx8mm_clk_probe(struct udevice *dev) imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180)); clk_dm(IMX8MM_CLK_ECSPI1_ROOT, - imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); + imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); clk_dm(IMX8MM_CLK_ECSPI2_ROOT, - imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); + imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); clk_dm(IMX8MM_CLK_ECSPI3_ROOT, - imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); + imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); #endif #if CONFIG_IS_ENABLED(NXP_FSPI) clk_dm(IMX8MM_CLK_QSPI, imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80)); clk_dm(IMX8MM_CLK_QSPI_ROOT, - imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); + imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0)); #endif clk_dm(IMX8MM_CLK_ARM, diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index dbc94ff9450..a8ccc97f096 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -224,19 +224,19 @@ static int imx8mn_clk_probe(struct udevice *dev) /* PLL out gate */ clk_dm(IMX8MN_DRAM_PLL_OUT, - imx_clk_gate("dram_pll_out", "dram_pll_bypass", + imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass", base + 0x50, 13)); clk_dm(IMX8MN_ARM_PLL_OUT, - imx_clk_gate("arm_pll_out", "arm_pll_bypass", + imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass", base + 0x84, 11)); clk_dm(IMX8MN_SYS_PLL1_OUT, - imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", + imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11)); clk_dm(IMX8MN_SYS_PLL2_OUT, - imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", + imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11)); clk_dm(IMX8MN_SYS_PLL3_OUT, - imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", + imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11)); /* SYS PLL fixed output */ @@ -291,7 +291,7 @@ static int imx8mn_clk_probe(struct udevice *dev) imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels))); clk_dm(IMX8MN_CLK_A53_CG, - imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); + imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); clk_dm(IMX8MN_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); @@ -350,45 +350,45 @@ static int imx8mn_clk_probe(struct udevice *dev) imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180)); clk_dm(IMX8MN_CLK_I2C1_ROOT, - imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0)); + imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0)); clk_dm(IMX8MN_CLK_I2C2_ROOT, - imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0)); + imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0)); clk_dm(IMX8MN_CLK_I2C3_ROOT, - imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); + imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0)); clk_dm(IMX8MN_CLK_I2C4_ROOT, - imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); + imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0)); clk_dm(IMX8MN_CLK_OCOTP_ROOT, - imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0)); + imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0)); clk_dm(IMX8MN_CLK_USDHC1_ROOT, - imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); + imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MN_CLK_USDHC2_ROOT, - imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); + imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); clk_dm(IMX8MN_CLK_WDOG1_ROOT, - imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0)); + imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0)); clk_dm(IMX8MN_CLK_WDOG2_ROOT, - imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0)); + imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0)); clk_dm(IMX8MN_CLK_WDOG3_ROOT, - imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0)); + imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0)); clk_dm(IMX8MN_CLK_USDHC3_ROOT, - imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); + imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); clk_dm(IMX8MN_CLK_QSPI_ROOT, - imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); + imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0)); clk_dm(IMX8MN_CLK_NAND_ROOT, - imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand)); + imx_clk_gate2_shared2(dev, "nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand)); clk_dm(IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK, - imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", + imx_clk_gate2_shared2(dev, "nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand)); clk_dm(IMX8MN_CLK_UART1_ROOT, - imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0)); + imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0)); clk_dm(IMX8MN_CLK_UART2_ROOT, - imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); + imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MN_CLK_UART3_ROOT, - imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); + imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MN_CLK_UART4_ROOT, - imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); + imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0)); clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT, - imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); + imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); /* clks not needed in SPL stage */ #ifndef CONFIG_XPL_BUILD @@ -402,7 +402,7 @@ static int imx8mn_clk_probe(struct udevice *dev) imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80)); clk_dm(IMX8MN_CLK_ENET1_ROOT, - imx_clk_gate4("enet1_root_clk", "enet_axi", + imx_clk_gate4(dev, "enet1_root_clk", "enet_axi", base + 0x40a0, 0)); clk_dm(IMX8MN_CLK_PWM1, imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380)); @@ -413,13 +413,13 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_CLK_PWM4, imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500)); clk_dm(IMX8MN_CLK_PWM1_ROOT, - imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0)); + imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0)); clk_dm(IMX8MN_CLK_PWM2_ROOT, - imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0)); + imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0)); clk_dm(IMX8MN_CLK_PWM3_ROOT, - imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0)); + imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0)); clk_dm(IMX8MN_CLK_PWM4_ROOT, - imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0)); + imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0)); #endif #if CONFIG_IS_ENABLED(DM_SPI) @@ -430,11 +430,11 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_CLK_ECSPI3, imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180)); clk_dm(IMX8MN_CLK_ECSPI1_ROOT, - imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); + imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); clk_dm(IMX8MN_CLK_ECSPI2_ROOT, - imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); + imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); clk_dm(IMX8MN_CLK_ECSPI3_ROOT, - imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); + imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); #endif clk_dm(IMX8MN_CLK_ARM, diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 4b916bef7a1..718ba095bef 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -222,11 +222,11 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT)); - clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13)); - clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11)); - clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11)); - clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11)); - clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11)); + clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass", base + 0x50, 13)); + clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass", base + 0x84, 11)); + clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11)); + clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11)); + clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11)); clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20)); clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10)); @@ -263,7 +263,7 @@ static int imx8mp_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels))); - clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); + clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite("hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380)); @@ -316,47 +316,47 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4)); clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags(dev, "dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL)); - clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL)); - clk_dm(IMX8MP_CLK_ECSPI1_ROOT, imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); - clk_dm(IMX8MP_CLK_ECSPI2_ROOT, imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); - clk_dm(IMX8MP_CLK_ECSPI3_ROOT, imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); - clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0)); - clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0)); - clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0)); - clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0)); - clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0)); - clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0)); - clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0)); - clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0)); - clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); - clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); - clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4("pcie_root_clk", "pcie_aux", base + 0x4250, 0)); - clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0)); - clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0)); - clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0)); - clk_dm(IMX8MP_CLK_PWM4_ROOT, imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0)); - clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4("qos_root_clk", "ipg_root", base + 0x42c0, 0)); - clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4("qos_enet_root_clk", "ipg_root", base + 0x42e0, 0)); - clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); - clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0)); - clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0)); - clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0)); - clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4("enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0)); - clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0)); - clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); - clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); - clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); - clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0)); - clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); - clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); - clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); - clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); - clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0)); - clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0)); - clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0)); - clk_dm(IMX8MP_CLK_HSIO_ROOT, imx_clk_gate4("hsio_root_clk", "ipg_root", base + 0x45c0, 0)); + clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags(dev, "dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL)); + clk_dm(IMX8MP_CLK_ECSPI1_ROOT, imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); + clk_dm(IMX8MP_CLK_ECSPI2_ROOT, imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); + clk_dm(IMX8MP_CLK_ECSPI3_ROOT, imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); + clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4(dev, "enet1_root_clk", "enet_axi", base + 0x40a0, 0)); + clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4(dev, "gpio1_root_clk", "ipg_root", base + 0x40b0, 0)); + clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4(dev, "gpio2_root_clk", "ipg_root", base + 0x40c0, 0)); + clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4(dev, "gpio3_root_clk", "ipg_root", base + 0x40d0, 0)); + clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4(dev, "gpio4_root_clk", "ipg_root", base + 0x40e0, 0)); + clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4(dev, "gpio5_root_clk", "ipg_root", base + 0x40f0, 0)); + clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0)); + clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0)); + clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0)); + clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0)); + clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4(dev, "pcie_root_clk", "pcie_aux", base + 0x4250, 0)); + clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0)); + clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0)); + clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0)); + clk_dm(IMX8MP_CLK_PWM4_ROOT, imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0)); + clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4(dev, "qos_root_clk", "ipg_root", base + 0x42c0, 0)); + clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4(dev, "qos_enet_root_clk", "ipg_root", base + 0x42e0, 0)); + clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0)); + clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2(dev, "i2c5_root_clk", "i2c5", base + 0x4330, 0)); + clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2(dev, "i2c6_root_clk", "i2c6", base + 0x4340, 0)); + clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4(dev, "sim_enet_root_clk", "enet_axi", base + 0x4400, 0)); + clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4(dev, "enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0)); + clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0)); + clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0)); + clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0)); + clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0)); + clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2(dev, "usb_root_clk", "hsio_axi", base + 0x44d0, 0)); + clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2(dev, "usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); + clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4(dev, "usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); + clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); + clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); + clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0)); + clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0)); + clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0)); + clk_dm(IMX8MP_CLK_HSIO_ROOT, imx_clk_gate4(dev, "hsio_root_clk", "ipg_root", base + 0x45c0, 0)); - clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); + clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); clk_dm(IMX8MP_CLK_ARM, imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1, diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index dc9b7d56815..782dd39a300 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -239,38 +239,38 @@ static int imx8mq_clk_probe(struct udevice *dev) /* PLL out gate */ clk_dm(IMX8MQ_DRAM_PLL_OUT, - imx_clk_gate("dram_pll_out", "dram_pll_ref_sel", + imx_clk_gate(dev, "dram_pll_out", "dram_pll_ref_sel", base + 0x60, 13)); clk_dm(IMX8MQ_ARM_PLL_OUT, - imx_clk_gate("arm_pll_out", "arm_pll_bypass", + imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass", base + 0x28, 11)); clk_dm(IMX8MQ_GPU_PLL_OUT, - imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", + imx_clk_gate(dev, "gpu_pll_out", "gpu_pll_bypass", base + 0x18, 11)); clk_dm(IMX8MQ_VPU_PLL_OUT, - imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", + imx_clk_gate(dev, "vpu_pll_out", "vpu_pll_bypass", base + 0x20, 11)); clk_dm(IMX8MQ_AUDIO_PLL1_OUT, - imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", + imx_clk_gate(dev, "audio_pll1_out", "audio_pll1_bypass", base + 0x0, 11)); clk_dm(IMX8MQ_AUDIO_PLL2_OUT, - imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", + imx_clk_gate(dev, "audio_pll2_out", "audio_pll2_bypass", base + 0x8, 11)); clk_dm(IMX8MQ_VIDEO_PLL1_OUT, - imx_clk_gate("video_pll1_out", "video_pll1_bypass", + imx_clk_gate(dev, "video_pll1_out", "video_pll1_bypass", base + 0x10, 11)); clk_dm(IMX8MQ_SYS1_PLL_OUT, - imx_clk_gate("sys_pll1_out", "sys1_pll", + imx_clk_gate(dev, "sys_pll1_out", "sys1_pll", base + 0x30, 11)); clk_dm(IMX8MQ_SYS2_PLL_OUT, - imx_clk_gate("sys_pll2_out", "sys2_pll", + imx_clk_gate(dev, "sys_pll2_out", "sys2_pll", base + 0x3c, 11)); clk_dm(IMX8MQ_SYS3_PLL_OUT, - imx_clk_gate("sys_pll3_out", "sys3_pll", + imx_clk_gate(dev, "sys_pll3_out", "sys3_pll", base + 0x48, 11)); clk_dm(IMX8MQ_VIDEO2_PLL_OUT, - imx_clk_gate("video_pll2_out", "video_pll2_ref_sel", + imx_clk_gate(dev, "video_pll2_out", "video_pll2_ref_sel", base + 0x54, 11)); /* SYS PLL fixed output */ @@ -340,7 +340,7 @@ static int imx8mq_clk_probe(struct udevice *dev) ARRAY_SIZE(pllout_monitor_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MQ_CLK_MON_CLK2_OUT, - imx_clk_gate4("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4)); + imx_clk_gate4(dev, "pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4)); base = dev_read_addr_ptr(dev); if (!base) { @@ -352,7 +352,7 @@ static int imx8mq_clk_probe(struct udevice *dev) imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels))); clk_dm(IMX8MQ_CLK_A53_CG, - imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); + imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); clk_dm(IMX8MQ_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); @@ -424,49 +424,49 @@ static int imx8mq_clk_probe(struct udevice *dev) imx8m_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180)); clk_dm(IMX8MQ_CLK_ECSPI1_ROOT, - imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); + imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); clk_dm(IMX8MQ_CLK_ECSPI2_ROOT, - imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); + imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); clk_dm(IMX8MQ_CLK_ECSPI3_ROOT, - imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); + imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); clk_dm(IMX8MQ_CLK_I2C1_ROOT, - imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0)); + imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0)); clk_dm(IMX8MQ_CLK_I2C2_ROOT, - imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0)); + imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0)); clk_dm(IMX8MQ_CLK_I2C3_ROOT, - imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); + imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0)); clk_dm(IMX8MQ_CLK_I2C4_ROOT, - imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); + imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0)); clk_dm(IMX8MQ_CLK_UART1_ROOT, - imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0)); + imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0)); clk_dm(IMX8MQ_CLK_UART2_ROOT, - imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); + imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MQ_CLK_UART3_ROOT, - imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); + imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MQ_CLK_UART4_ROOT, - imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); + imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0)); clk_dm(IMX8MQ_CLK_OCOTP_ROOT, - imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0)); + imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0)); clk_dm(IMX8MQ_CLK_USDHC1_ROOT, - imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); + imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MQ_CLK_USDHC2_ROOT, - imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); + imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); clk_dm(IMX8MQ_CLK_WDOG1_ROOT, - imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0)); + imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0)); clk_dm(IMX8MQ_CLK_WDOG2_ROOT, - imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0)); + imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0)); clk_dm(IMX8MQ_CLK_WDOG3_ROOT, - imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0)); + imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0)); clk_dm(IMX8MQ_CLK_QSPI_ROOT, - imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); + imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0)); clk_dm(IMX8MQ_CLK_USB1_CTRL_ROOT, - imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); + imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); clk_dm(IMX8MQ_CLK_USB2_CTRL_ROOT, - imx_clk_gate4("usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0)); + imx_clk_gate4(dev, "usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0)); clk_dm(IMX8MQ_CLK_USB1_PHY_ROOT, - imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); + imx_clk_gate4(dev, "usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); clk_dm(IMX8MQ_CLK_USB2_PHY_ROOT, - imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0)); + imx_clk_gate4(dev, "usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0)); clk_dm(IMX8MQ_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mq_enet_ref_sels, @@ -478,7 +478,7 @@ static int imx8mq_clk_probe(struct udevice *dev) imx8m_clk_composite("enet_phy", imx8mq_enet_phy_sels, base + 0xaa80)); clk_dm(IMX8MQ_CLK_ENET1_ROOT, - imx_clk_gate4("enet1_root_clk", "enet_axi", + imx_clk_gate4(dev, "enet1_root_clk", "enet_axi", base + 0x40a0, 0)); clk_dm(IMX8MQ_CLK_DRAM_ALT_ROOT, diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c index 16fc3bcdb3e..40cba218c29 100644 --- a/drivers/clk/imx/clk-imxrt1020.c +++ b/drivers/clk/imx/clk-imxrt1020.c @@ -116,13 +116,13 @@ static int imxrt1020_clk_probe(struct udevice *dev) base + 0x14, 16, 3)); clk_dm(IMXRT1020_CLK_USDHC1, - imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2)); + imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2)); clk_dm(IMXRT1020_CLK_USDHC2, - imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4)); + imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4)); clk_dm(IMXRT1020_CLK_LPUART1, - imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24)); + imx_clk_gate2(dev, "lpuart1", "lpuart_podf", base + 0x7c, 24)); clk_dm(IMXRT1020_CLK_SEMC, - imx_clk_gate2("semc", "semc_podf", base + 0x74, 4)); + imx_clk_gate2(dev, "semc", "semc_podf", base + 0x74, 4)); #ifdef CONFIG_XPL_BUILD struct clk *clk, *clk1; diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 5f37915f593..71d5fa8a90e 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -167,19 +167,19 @@ static int imxrt1050_clk_probe(struct udevice *dev) base + 0x18, 23, 3)); clk_dm(IMXRT1050_CLK_USDHC1, - imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2)); + imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2)); clk_dm(IMXRT1050_CLK_USDHC2, - imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4)); + imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4)); clk_dm(IMXRT1050_CLK_LPUART1, - imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24)); + imx_clk_gate2(dev, "lpuart1", "lpuart_podf", base + 0x7c, 24)); clk_dm(IMXRT1050_CLK_SEMC, - imx_clk_gate2("semc", "semc_podf", base + 0x74, 4)); + imx_clk_gate2(dev, "semc", "semc_podf", base + 0x74, 4)); clk_dm(IMXRT1050_CLK_LCDIF_APB, - imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28)); + imx_clk_gate2(dev, "lcdif", "lcdif_podf", base + 0x70, 28)); clk_dm(IMXRT1050_CLK_LCDIF_PIX, - imx_clk_gate2("lcdif_pix", "lcdif", base + 0x74, 10)); + imx_clk_gate2(dev, "lcdif_pix", "lcdif", base + 0x74, 10)); clk_dm(IMXRT1050_CLK_USBOH3, - imx_clk_gate2("usboh3", "pll3_usb_otg", base + 0x80, 0)); + imx_clk_gate2(dev, "usboh3", "pll3_usb_otg", base + 0x80, 0)); struct clk *clk, *clk1; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 6f964f2679f..d2122977e47 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -87,14 +87,15 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask); -static inline struct clk *imx_clk_gate2(const char *name, const char *parent, - void __iomem *reg, u8 shift) +static inline struct clk *imx_clk_gate2(struct udevice *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift) { return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0x3, 0, NULL); } -static inline struct clk *imx_clk_gate2_shared(const char *name, +static inline struct clk *imx_clk_gate2_shared(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned int *share_count) @@ -103,7 +104,7 @@ static inline struct clk *imx_clk_gate2_shared(const char *name, shift, 0x3, 0, share_count); } -static inline struct clk *imx_clk_gate2_shared2(const char *name, +static inline struct clk *imx_clk_gate2_shared2(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned int *share_count) @@ -113,7 +114,7 @@ static inline struct clk *imx_clk_gate2_shared2(const char *name, share_count); } -static inline struct clk *imx_clk_gate4(const char *name, const char *parent, +static inline struct clk *imx_clk_gate4(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, u8 shift) { return clk_register_gate2(NULL, name, parent, @@ -121,7 +122,7 @@ static inline struct clk *imx_clk_gate4(const char *name, const char *parent, reg, shift, 0x3, 0, NULL); } -static inline struct clk *imx_clk_gate4_flags(const char *name, +static inline struct clk *imx_clk_gate4_flags(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned long flags) { @@ -215,22 +216,25 @@ static inline struct clk *imx_clk_mux2(struct udevice *dev, const char *name, vo reg, shift, width, 0); } -static inline struct clk *imx_clk_gate(const char *name, const char *parent, - void __iomem *reg, u8 shift) +static inline struct clk *imx_clk_gate(struct udevice *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift) { return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0, NULL); } -static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent, - void __iomem *reg, u8 shift, unsigned long flags) +static inline struct clk *imx_clk_gate_flags(struct udevice *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift, unsigned long flags) { return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, shift, 0, NULL); } -static inline struct clk *imx_clk_gate3(const char *name, const char *parent, - void __iomem *reg, u8 shift) +static inline struct clk *imx_clk_gate3(struct udevice *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift) { return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, From 86bde56bcc3f56031e197e02d9dca97a13815457 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:41 +0100 Subject: [PATCH 12/33] clk: imx: Pass struct udevice to clk_register_gate*() Pass U-Boot specific struct udevice pointer to clock parent device to clk_register_gate*(), so clk_register_gate*() can access the parent udevice. Signed-off-by: Marek Vasut --- drivers/clk/imx/clk.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index d2122977e47..22b5d823ff9 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -91,7 +91,7 @@ static inline struct clk *imx_clk_gate2(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, u8 shift) { - return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0x3, 0, NULL); } @@ -100,7 +100,7 @@ static inline struct clk *imx_clk_gate2_shared(struct udevice *dev, const char * void __iomem *reg, u8 shift, unsigned int *share_count) { - return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0x3, 0, share_count); } @@ -109,7 +109,7 @@ static inline struct clk *imx_clk_gate2_shared2(struct udevice *dev, const char void __iomem *reg, u8 shift, unsigned int *share_count) { - return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | + return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, share_count); } @@ -117,7 +117,7 @@ static inline struct clk *imx_clk_gate2_shared2(struct udevice *dev, const char static inline struct clk *imx_clk_gate4(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, u8 shift) { - return clk_register_gate2(NULL, name, parent, + return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, NULL); } @@ -126,7 +126,7 @@ static inline struct clk *imx_clk_gate4_flags(struct udevice *dev, const char *n const char *parent, void __iomem *reg, u8 shift, unsigned long flags) { - return clk_register_gate2(NULL, name, parent, + return clk_register_gate2(dev, name, parent, flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, NULL); } @@ -220,7 +220,7 @@ static inline struct clk *imx_clk_gate(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, u8 shift) { - return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + return clk_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0, NULL); } @@ -228,7 +228,7 @@ static inline struct clk *imx_clk_gate_flags(struct udevice *dev, const char *na const char *parent, void __iomem *reg, u8 shift, unsigned long flags) { - return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, + return clk_register_gate(dev, name, parent, flags | CLK_SET_RATE_PARENT, reg, shift, 0, NULL); } @@ -236,7 +236,7 @@ static inline struct clk *imx_clk_gate3(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, u8 shift) { - return clk_register_gate(NULL, name, parent, + return clk_register_gate(dev, name, parent, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, reg, shift, 0, NULL); } From 45c6b6a850895b58d39ca1906a741ebc8563f4bc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:42 +0100 Subject: [PATCH 13/33] clk: clk-composite: Use struct udevice instead of struct device Use U-Boot specific struct udevice instead of Linux compatibility struct device in clk-composite registration. Signed-off-by: Marek Vasut --- drivers/clk/clk-composite.c | 2 +- include/linux/clk-provider.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 199ca6eaa37..1191bdf87df 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -97,7 +97,7 @@ static int clk_composite_disable(struct clk *clk) return 0; } -struct clk *clk_register_composite(struct device *dev, const char *name, +struct clk *clk_register_composite(struct udevice *dev, const char *name, const char * const *parent_names, int num_parents, struct clk *mux, const struct clk_ops *mux_ops, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index e282be12897..d44ead53079 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -223,7 +223,7 @@ struct clk_composite { #define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk) -struct clk *clk_register_composite(struct device *dev, const char *name, +struct clk *clk_register_composite(struct udevice *dev, const char *name, const char * const *parent_names, int num_parents, struct clk *mux_clk, const struct clk_ops *mux_ops, struct clk *rate_clk, const struct clk_ops *rate_ops, From f98cd471f06b59dc9b6ff27ada5b18d138fc3095 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:43 +0100 Subject: [PATCH 14/33] clk: clk-composite: Resolve parent clock by name Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut --- drivers/clk/clk-composite.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 1191bdf87df..9e3b5191767 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -149,7 +149,7 @@ struct clk *clk_register_composite(struct udevice *dev, const char *name, clk = &composite->clk; clk->flags = flags; ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name, - parent_names[clk_composite_get_parent(clk)]); + clk_resolve_parent_clk(dev, parent_names[clk_composite_get_parent(clk)])); if (ret) { clk = ERR_PTR(ret); goto err; From bcb141d114284d5c90b76635337c85d5838db5c9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:44 +0100 Subject: [PATCH 15/33] clk: imx: Pass struct udevice into imx_clk_composite*() Pass struct udevice * into imx_clk_composite*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut --- drivers/clk/imx/clk-composite-8m.c | 4 +- drivers/clk/imx/clk-imx8mm.c | 74 ++++++++++++++------------- drivers/clk/imx/clk-imx8mn.c | 60 +++++++++++----------- drivers/clk/imx/clk-imx8mp.c | 80 +++++++++++++++--------------- drivers/clk/imx/clk-imx8mq.c | 52 +++++++++---------- drivers/clk/imx/clk.h | 14 +++--- 6 files changed, 141 insertions(+), 143 deletions(-) diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index 64bffa3b181..14c5b92939c 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -151,7 +151,7 @@ const struct clk_ops imx8m_clk_mux_ops = { .set_parent = imx8m_clk_mux_set_parent, }; -struct clk *imx8m_clk_composite_flags(const char *name, +struct clk *imx8m_clk_composite_flags(struct udevice *dev, const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, unsigned long flags) @@ -187,7 +187,7 @@ struct clk *imx8m_clk_composite_flags(const char *name, gate->reg = reg; gate->bit_idx = PCG_CGC_SHIFT; - clk = clk_register_composite(NULL, name, + clk = clk_register_composite(dev, name, parent_names, num_parents, &mux->clk, &imx8m_clk_mux_ops, &div->clk, &imx8m_clk_composite_divider_ops, diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 30762666754..c9d6954ac75 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -300,71 +300,69 @@ static int imx8mm_clk_probe(struct udevice *dev) base + 0x8000, 0, 3)); clk_dm(IMX8MM_CLK_AHB, - imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels, + imx8m_clk_composite_critical(dev, "ahb", imx8mm_ahb_sels, base + 0x9000)); clk_dm(IMX8MM_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1)); clk_dm(IMX8MM_CLK_NAND_USDHC_BUS, - imx8m_clk_composite_critical("nand_usdhc_bus", + imx8m_clk_composite_critical(dev, "nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900)); clk_dm(IMX8MM_CLK_USB_BUS, - imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80)); + imx8m_clk_composite(dev, "usb_bus", imx8mm_usb_bus_sels, base + 0x8b80)); /* IP */ #if CONFIG_IS_ENABLED(PCIE_DW_IMX) clk_dm(IMX8MM_CLK_PCIE1_CTRL, - imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels, + imx8m_clk_composite(dev, "pcie1_ctrl", imx8mm_pcie1_ctrl_sels, base + 0xa300)); clk_dm(IMX8MM_CLK_PCIE1_PHY, - imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels, + imx8m_clk_composite(dev, "pcie1_phy", imx8mm_pcie1_phy_sels, base + 0xa380)); clk_dm(IMX8MM_CLK_PCIE1_AUX, - imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels, + imx8m_clk_composite(dev, "pcie1_aux", imx8mm_pcie1_aux_sels, base + 0xa400)); #endif clk_dm(IMX8MM_CLK_USDHC1, - imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels, + imx8m_clk_composite(dev, "usdhc1", imx8mm_usdhc1_sels, base + 0xac00)); clk_dm(IMX8MM_CLK_USDHC2, - imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels, + imx8m_clk_composite(dev, "usdhc2", imx8mm_usdhc2_sels, base + 0xac80)); clk_dm(IMX8MM_CLK_I2C1, - imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00)); + imx8m_clk_composite(dev, "i2c1", imx8mm_i2c1_sels, base + 0xad00)); clk_dm(IMX8MM_CLK_I2C2, - imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80)); + imx8m_clk_composite(dev, "i2c2", imx8mm_i2c2_sels, base + 0xad80)); clk_dm(IMX8MM_CLK_I2C3, - imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00)); + imx8m_clk_composite(dev, "i2c3", imx8mm_i2c3_sels, base + 0xae00)); clk_dm(IMX8MM_CLK_I2C4, - imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80)); - + imx8m_clk_composite(dev, "i2c4", imx8mm_i2c4_sels, base + 0xae80)); clk_dm(IMX8MM_CLK_UART1, - imx8m_clk_composite("uart1", imx8mm_uart1_sels, base + 0xaf00)); + imx8m_clk_composite(dev, "uart1", imx8mm_uart1_sels, base + 0xaf00)); clk_dm(IMX8MM_CLK_UART2, - imx8m_clk_composite("uart2", imx8mm_uart2_sels, base + 0xaf80)); + imx8m_clk_composite(dev, "uart2", imx8mm_uart2_sels, base + 0xaf80)); clk_dm(IMX8MM_CLK_UART3, - imx8m_clk_composite("uart3", imx8mm_uart3_sels, base + 0xb000)); + imx8m_clk_composite(dev, "uart3", imx8mm_uart3_sels, base + 0xb000)); clk_dm(IMX8MM_CLK_UART4, - imx8m_clk_composite("uart4", imx8mm_uart4_sels, base + 0xb080)); + imx8m_clk_composite(dev, "uart4", imx8mm_uart4_sels, base + 0xb080)); clk_dm(IMX8MM_CLK_UART1_ROOT, - imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0)); + imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0)); clk_dm(IMX8MM_CLK_UART2_ROOT, - imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); + imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MM_CLK_UART3_ROOT, - imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); + imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MM_CLK_UART4_ROOT, - imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); - + imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0)); clk_dm(IMX8MM_CLK_WDOG, - imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900)); + imx8m_clk_composite(dev, "wdog", imx8mm_wdog_sels, base + 0xb900)); clk_dm(IMX8MM_CLK_USDHC3, - imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels, + imx8m_clk_composite(dev, "usdhc3", imx8mm_usdhc3_sels, base + 0xbc80)); clk_dm(IMX8MM_CLK_USB_CORE_REF, - imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100)); + imx8m_clk_composite(dev, "usb_core_ref", imx8mm_usb_core_sels, base + 0xb100)); clk_dm(IMX8MM_CLK_USB_PHY_REF, - imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180)); + imx8m_clk_composite(dev, "usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180)); clk_dm(IMX8MM_CLK_I2C1_ROOT, imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0)); clk_dm(IMX8MM_CLK_I2C2_ROOT, @@ -393,28 +391,28 @@ static int imx8mm_clk_probe(struct udevice *dev) /* clks not needed in SPL stage */ #ifndef CONFIG_XPL_BUILD clk_dm(IMX8MM_CLK_ENET_AXI, - imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels, + imx8m_clk_composite(dev, "enet_axi", imx8mm_enet_axi_sels, base + 0x8880)); clk_dm(IMX8MM_CLK_ENET_REF, - imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels, + imx8m_clk_composite(dev, "enet_ref", imx8mm_enet_ref_sels, base + 0xa980)); clk_dm(IMX8MM_CLK_ENET_TIMER, - imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels, + imx8m_clk_composite(dev, "enet_timer", imx8mm_enet_timer_sels, base + 0xaa00)); clk_dm(IMX8MM_CLK_ENET_PHY_REF, - imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels, + imx8m_clk_composite(dev, "enet_phy", imx8mm_enet_phy_sels, base + 0xaa80)); clk_dm(IMX8MM_CLK_ENET1_ROOT, imx_clk_gate4(dev, "enet1_root_clk", "enet_axi", base + 0x40a0, 0)); clk_dm(IMX8MM_CLK_PWM1, - imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380)); + imx8m_clk_composite(dev, "pwm1", imx8mm_pwm1_sels, base + 0xb380)); clk_dm(IMX8MM_CLK_PWM2, - imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400)); + imx8m_clk_composite(dev, "pwm2", imx8mm_pwm2_sels, base + 0xb400)); clk_dm(IMX8MM_CLK_PWM3, - imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480)); + imx8m_clk_composite(dev, "pwm3", imx8mm_pwm3_sels, base + 0xb480)); clk_dm(IMX8MM_CLK_PWM4, - imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500)); + imx8m_clk_composite(dev, "pwm4", imx8mm_pwm4_sels, base + 0xb500)); clk_dm(IMX8MM_CLK_PWM1_ROOT, imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0)); clk_dm(IMX8MM_CLK_PWM2_ROOT, @@ -432,11 +430,11 @@ static int imx8mm_clk_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(DM_SPI) clk_dm(IMX8MM_CLK_ECSPI1, - imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280)); + imx8m_clk_composite(dev, "ecspi1", imx8mm_ecspi1_sels, base + 0xb280)); clk_dm(IMX8MM_CLK_ECSPI2, - imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300)); + imx8m_clk_composite(dev, "ecspi2", imx8mm_ecspi2_sels, base + 0xb300)); clk_dm(IMX8MM_CLK_ECSPI3, - imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180)); + imx8m_clk_composite(dev, "ecspi3", imx8mm_ecspi3_sels, base + 0xc180)); clk_dm(IMX8MM_CLK_ECSPI1_ROOT, imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); @@ -448,7 +446,7 @@ static int imx8mm_clk_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(NXP_FSPI) clk_dm(IMX8MM_CLK_QSPI, - imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80)); + imx8m_clk_composite(dev, "qspi", imx8mm_qspi_sels, base + 0xab80)); clk_dm(IMX8MM_CLK_QSPI_ROOT, imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0)); #endif diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index a8ccc97f096..18621fc1226 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -297,57 +297,57 @@ static int imx8mn_clk_probe(struct udevice *dev) base + 0x8000, 0, 3)); clk_dm(IMX8MN_CLK_AHB, - imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels, + imx8m_clk_composite_critical(dev, "ahb", imx8mn_ahb_sels, base + 0x9000)); clk_dm(IMX8MN_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1)); clk_dm(IMX8MN_CLK_ENET_AXI, - imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels, + imx8m_clk_composite(dev, "enet_axi", imx8mn_enet_axi_sels, base + 0x8880)); clk_dm(IMX8MN_CLK_NAND_USDHC_BUS, - imx8m_clk_composite_critical("nand_usdhc_bus", + imx8m_clk_composite_critical(dev, "nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900)); clk_dm(IMX8MN_CLK_USB_BUS, - imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80)); + imx8m_clk_composite(dev, "usb_bus", imx8mn_usb_bus_sels, base + 0x8b80)); /* IP */ clk_dm(IMX8MN_CLK_USDHC1, - imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels, + imx8m_clk_composite(dev, "usdhc1", imx8mn_usdhc1_sels, base + 0xac00)); clk_dm(IMX8MN_CLK_USDHC2, - imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels, + imx8m_clk_composite(dev, "usdhc2", imx8mn_usdhc2_sels, base + 0xac80)); clk_dm(IMX8MN_CLK_I2C1, - imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00)); + imx8m_clk_composite(dev, "i2c1", imx8mn_i2c1_sels, base + 0xad00)); clk_dm(IMX8MN_CLK_I2C2, - imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80)); + imx8m_clk_composite(dev, "i2c2", imx8mn_i2c2_sels, base + 0xad80)); clk_dm(IMX8MN_CLK_I2C3, - imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00)); + imx8m_clk_composite(dev, "i2c3", imx8mn_i2c3_sels, base + 0xae00)); clk_dm(IMX8MN_CLK_I2C4, - imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80)); + imx8m_clk_composite(dev, "i2c4", imx8mn_i2c4_sels, base + 0xae80)); clk_dm(IMX8MN_CLK_UART1, - imx8m_clk_composite("uart1", imx8mn_uart1_sels, base + 0xaf00)); + imx8m_clk_composite(dev, "uart1", imx8mn_uart1_sels, base + 0xaf00)); clk_dm(IMX8MN_CLK_UART2, - imx8m_clk_composite("uart2", imx8mn_uart2_sels, base + 0xaf80)); + imx8m_clk_composite(dev, "uart2", imx8mn_uart2_sels, base + 0xaf80)); clk_dm(IMX8MN_CLK_UART3, - imx8m_clk_composite("uart3", imx8mn_uart3_sels, base + 0xb000)); + imx8m_clk_composite(dev, "uart3", imx8mn_uart3_sels, base + 0xb000)); clk_dm(IMX8MN_CLK_UART4, - imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080)); + imx8m_clk_composite(dev, "uart4", imx8mn_uart4_sels, base + 0xb080)); clk_dm(IMX8MN_CLK_WDOG, - imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900)); + imx8m_clk_composite(dev, "wdog", imx8mn_wdog_sels, base + 0xb900)); clk_dm(IMX8MN_CLK_USDHC3, - imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels, + imx8m_clk_composite(dev, "usdhc3", imx8mn_usdhc3_sels, base + 0xbc80)); clk_dm(IMX8MN_CLK_NAND, - imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00)); + imx8m_clk_composite(dev, "nand", imx8mn_nand_sels, base + 0xab00)); clk_dm(IMX8MN_CLK_QSPI, - imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80)); + imx8m_clk_composite(dev, "qspi", imx8mn_qspi_sels, base + 0xab80)); clk_dm(IMX8MN_CLK_USB_CORE_REF, - imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100)); + imx8m_clk_composite(dev, "usb_core_ref", imx8mn_usb_core_sels, base + 0xb100)); clk_dm(IMX8MN_CLK_USB_PHY_REF, - imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180)); + imx8m_clk_composite(dev, "usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180)); clk_dm(IMX8MN_CLK_I2C1_ROOT, imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0)); @@ -393,25 +393,25 @@ static int imx8mn_clk_probe(struct udevice *dev) /* clks not needed in SPL stage */ #ifndef CONFIG_XPL_BUILD clk_dm(IMX8MN_CLK_ENET_REF, - imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels, + imx8m_clk_composite(dev, "enet_ref", imx8mn_enet_ref_sels, base + 0xa980)); clk_dm(IMX8MN_CLK_ENET_TIMER, - imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels, + imx8m_clk_composite(dev, "enet_timer", imx8mn_enet_timer_sels, base + 0xaa00)); clk_dm(IMX8MN_CLK_ENET_PHY_REF, - imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, + imx8m_clk_composite(dev, "enet_phy", imx8mn_enet_phy_sels, base + 0xaa80)); clk_dm(IMX8MN_CLK_ENET1_ROOT, imx_clk_gate4(dev, "enet1_root_clk", "enet_axi", base + 0x40a0, 0)); clk_dm(IMX8MN_CLK_PWM1, - imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380)); + imx8m_clk_composite(dev, "pwm1", imx8mn_pwm1_sels, base + 0xb380)); clk_dm(IMX8MN_CLK_PWM2, - imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400)); + imx8m_clk_composite(dev, "pwm2", imx8mn_pwm2_sels, base + 0xb400)); clk_dm(IMX8MN_CLK_PWM3, - imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480)); + imx8m_clk_composite(dev, "pwm3", imx8mn_pwm3_sels, base + 0xb480)); clk_dm(IMX8MN_CLK_PWM4, - imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500)); + imx8m_clk_composite(dev, "pwm4", imx8mn_pwm4_sels, base + 0xb500)); clk_dm(IMX8MN_CLK_PWM1_ROOT, imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0)); clk_dm(IMX8MN_CLK_PWM2_ROOT, @@ -424,11 +424,11 @@ static int imx8mn_clk_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(DM_SPI) clk_dm(IMX8MN_CLK_ECSPI1, - imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280)); + imx8m_clk_composite(dev, "ecspi1", imx8mn_ecspi1_sels, base + 0xb280)); clk_dm(IMX8MN_CLK_ECSPI2, - imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300)); + imx8m_clk_composite(dev, "ecspi2", imx8mn_ecspi2_sels, base + 0xb300)); clk_dm(IMX8MN_CLK_ECSPI3, - imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180)); + imx8m_clk_composite(dev, "ecspi3", imx8mn_ecspi3_sels, base + 0xc180)); clk_dm(IMX8MN_CLK_ECSPI1_ROOT, imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); clk_dm(IMX8MN_CLK_ECSPI2_ROOT, diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 718ba095bef..5768504e7c9 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -266,52 +266,52 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); - clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite("hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380)); - clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800)); - clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", imx8mp_enet_axi_sels, base + 0x8880)); - clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900)); - clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical("noc", imx8mp_noc_sels, base + 0x8d00)); - clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical("noc_io", imx8mp_noc_io_sels, base + 0x8d80)); + clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite(dev, "hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380)); + clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical(dev, "main_axi", imx8mp_main_axi_sels, base + 0x8800)); + clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical(dev, "enet_axi", imx8mp_enet_axi_sels, base + 0x8880)); + clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical(dev, "nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900)); + clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical(dev, "noc", imx8mp_noc_sels, base + 0x8d00)); + clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical(dev, "noc_io", imx8mp_noc_io_sels, base + 0x8d80)); - clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical("ahb_root", imx8mp_ahb_sels, base + 0x9000)); + clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical(dev, "ahb_root", imx8mp_ahb_sels, base + 0x9000)); clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1)); - clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000)); - clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080)); - clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite("pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400)); - clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480)); - clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500)); - clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880)); - clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900)); - clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980)); - clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00)); - clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80)); - clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite("qspi", imx8mp_qspi_sels, base + 0xab80)); - clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite("usdhc1", imx8mp_usdhc1_sels, base + 0xac00)); - clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mp_usdhc2_sels, base + 0xac80)); - clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mp_i2c1_sels, base + 0xad00)); - clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite("i2c2", imx8mp_i2c2_sels, base + 0xad80)); - clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite("i2c3", imx8mp_i2c3_sels, base + 0xae00)); - clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mp_i2c4_sels, base + 0xae80)); + clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite(dev, "dram_alt", imx8mp_dram_alt_sels, base + 0xa000)); + clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical(dev, "dram_apb", imx8mp_dram_apb_sels, base + 0xa080)); + clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite(dev, "pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400)); + clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite(dev, "i2c5", imx8mp_i2c5_sels, base + 0xa480)); + clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite(dev, "i2c6", imx8mp_i2c6_sels, base + 0xa500)); + clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite(dev, "enet_qos", imx8mp_enet_qos_sels, base + 0xa880)); + clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite(dev, "enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900)); + clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite(dev, "enet_ref", imx8mp_enet_ref_sels, base + 0xa980)); + clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite(dev, "enet_timer", imx8mp_enet_timer_sels, base + 0xaa00)); + clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite(dev, "enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80)); + clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite(dev, "qspi", imx8mp_qspi_sels, base + 0xab80)); + clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite(dev, "usdhc1", imx8mp_usdhc1_sels, base + 0xac00)); + clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite(dev, "usdhc2", imx8mp_usdhc2_sels, base + 0xac80)); + clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite(dev, "i2c1", imx8mp_i2c1_sels, base + 0xad00)); + clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite(dev, "i2c2", imx8mp_i2c2_sels, base + 0xad80)); + clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite(dev, "i2c3", imx8mp_i2c3_sels, base + 0xae00)); + clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite(dev, "i2c4", imx8mp_i2c4_sels, base + 0xae80)); - clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite("uart1", imx8mp_uart1_sels, base + 0xaf00)); - clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80)); - clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000)); - clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080)); - clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite("usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100)); - clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180)); - clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200)); - clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base + 0xb280)); - clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base + 0xb300)); - clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical("pwm1", imx8mp_pwm1_sels, base + 0xb380)); - clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical("pwm2", imx8mp_pwm2_sels, base + 0xb400)); - clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical("pwm3", imx8mp_pwm3_sels, base + 0xb480)); - clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical("pwm4", imx8mp_pwm4_sels, base + 0xb500)); - clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base + 0xc180)); + clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite(dev, "uart1", imx8mp_uart1_sels, base + 0xaf00)); + clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite(dev, "uart2", imx8mp_uart2_sels, base + 0xaf80)); + clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite(dev, "uart3", imx8mp_uart3_sels, base + 0xb000)); + clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite(dev, "uart4", imx8mp_uart4_sels, base + 0xb080)); + clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite(dev, "usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100)); + clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite(dev, "usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180)); + clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical(dev, "gic", imx8mp_gic_sels, base + 0xb200)); + clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite(dev, "ecspi1", imx8mp_ecspi1_sels, base + 0xb280)); + clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite(dev, "ecspi2", imx8mp_ecspi2_sels, base + 0xb300)); + clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical(dev, "pwm1", imx8mp_pwm1_sels, base + 0xb380)); + clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical(dev, "pwm2", imx8mp_pwm2_sels, base + 0xb400)); + clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical(dev, "pwm3", imx8mp_pwm3_sels, base + 0xb480)); + clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical(dev, "pwm4", imx8mp_pwm4_sels, base + 0xb500)); + clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite(dev, "ecspi3", imx8mp_ecspi3_sels, base + 0xc180)); - clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900)); - clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80)); + clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite(dev, "wdog", imx8mp_wdog_sels, base + 0xb900)); + clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite(dev, "usdhc3", imx8mp_usdhc3_sels, base + 0xbc80)); clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4)); clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags(dev, "dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL)); diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 782dd39a300..5faa2d20224 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -361,67 +361,67 @@ static int imx8mq_clk_probe(struct udevice *dev) imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels))); clk_dm(IMX8MQ_CLK_AHB, - imx8m_clk_composite_critical("ahb", imx8mq_ahb_sels, + imx8m_clk_composite_critical(dev, "ahb", imx8mq_ahb_sels, base + 0x9000)); clk_dm(IMX8MQ_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1)); clk_dm(IMX8MQ_CLK_ENET_AXI, - imx8m_clk_composite("enet_axi", imx8mq_enet_axi_sels, + imx8m_clk_composite(dev, "enet_axi", imx8mq_enet_axi_sels, base + 0x8880)); clk_dm(IMX8MQ_CLK_NAND_USDHC_BUS, - imx8m_clk_composite_critical("nand_usdhc_bus", + imx8m_clk_composite_critical(dev, "nand_usdhc_bus", imx8mq_nand_usdhc_sels, base + 0x8900)); clk_dm(IMX8MQ_CLK_USB_BUS, - imx8m_clk_composite("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80)); + imx8m_clk_composite(dev, "usb_bus", imx8mq_usb_bus_sels, base + 0x8b80)); /* DRAM */ clk_dm(IMX8MQ_CLK_DRAM_CORE, imx_clk_mux2(dev, "dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels))); clk_dm(IMX8MQ_CLK_DRAM_ALT, - imx8m_clk_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000)); + imx8m_clk_composite(dev, "dram_alt", imx8mq_dram_alt_sels, base + 0xa000)); clk_dm(IMX8MQ_CLK_DRAM_APB, - imx8m_clk_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080)); + imx8m_clk_composite_critical(dev, "dram_apb", imx8mq_dram_apb_sels, base + 0xa080)); /* IP */ clk_dm(IMX8MQ_CLK_USDHC1, - imx8m_clk_composite("usdhc1", imx8mq_usdhc1_sels, + imx8m_clk_composite(dev, "usdhc1", imx8mq_usdhc1_sels, base + 0xac00)); clk_dm(IMX8MQ_CLK_USDHC2, - imx8m_clk_composite("usdhc2", imx8mq_usdhc2_sels, + imx8m_clk_composite(dev, "usdhc2", imx8mq_usdhc2_sels, base + 0xac80)); clk_dm(IMX8MQ_CLK_I2C1, - imx8m_clk_composite("i2c1", imx8mq_i2c1_sels, base + 0xad00)); + imx8m_clk_composite(dev, "i2c1", imx8mq_i2c1_sels, base + 0xad00)); clk_dm(IMX8MQ_CLK_I2C2, - imx8m_clk_composite("i2c2", imx8mq_i2c2_sels, base + 0xad80)); + imx8m_clk_composite(dev, "i2c2", imx8mq_i2c2_sels, base + 0xad80)); clk_dm(IMX8MQ_CLK_I2C3, - imx8m_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00)); + imx8m_clk_composite(dev, "i2c3", imx8mq_i2c3_sels, base + 0xae00)); clk_dm(IMX8MQ_CLK_I2C4, - imx8m_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80)); + imx8m_clk_composite(dev, "i2c4", imx8mq_i2c4_sels, base + 0xae80)); clk_dm(IMX8MQ_CLK_WDOG, - imx8m_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900)); + imx8m_clk_composite(dev, "wdog", imx8mq_wdog_sels, base + 0xb900)); clk_dm(IMX8MQ_CLK_UART1, - imx8m_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf00)); + imx8m_clk_composite(dev, "uart1", imx8mq_uart1_sels, base + 0xaf00)); clk_dm(IMX8MQ_CLK_UART2, - imx8m_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf80)); + imx8m_clk_composite(dev, "uart2", imx8mq_uart2_sels, base + 0xaf80)); clk_dm(IMX8MQ_CLK_UART3, - imx8m_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb000)); + imx8m_clk_composite(dev, "uart3", imx8mq_uart3_sels, base + 0xb000)); clk_dm(IMX8MQ_CLK_UART4, - imx8m_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080)); + imx8m_clk_composite(dev, "uart4", imx8mq_uart4_sels, base + 0xb080)); clk_dm(IMX8MQ_CLK_QSPI, - imx8m_clk_composite("qspi", imx8mq_qspi_sels, base + 0xab80)); + imx8m_clk_composite(dev, "qspi", imx8mq_qspi_sels, base + 0xab80)); clk_dm(IMX8MQ_CLK_USB_CORE_REF, - imx8m_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100)); + imx8m_clk_composite(dev, "usb_core_ref", imx8mq_usb_core_sels, base + 0xb100)); clk_dm(IMX8MQ_CLK_USB_PHY_REF, - imx8m_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180)); + imx8m_clk_composite(dev, "usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180)); clk_dm(IMX8MQ_CLK_ECSPI1, - imx8m_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280)); + imx8m_clk_composite(dev, "ecspi1", imx8mq_ecspi1_sels, base + 0xb280)); clk_dm(IMX8MQ_CLK_ECSPI2, - imx8m_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300)); + imx8m_clk_composite(dev, "ecspi2", imx8mq_ecspi2_sels, base + 0xb300)); clk_dm(IMX8MQ_CLK_ECSPI3, - imx8m_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180)); + imx8m_clk_composite(dev, "ecspi3", imx8mq_ecspi3_sels, base + 0xc180)); clk_dm(IMX8MQ_CLK_ECSPI1_ROOT, imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); @@ -469,13 +469,13 @@ static int imx8mq_clk_probe(struct udevice *dev) imx_clk_gate4(dev, "usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0)); clk_dm(IMX8MQ_CLK_ENET_REF, - imx8m_clk_composite("enet_ref", imx8mq_enet_ref_sels, + imx8m_clk_composite(dev, "enet_ref", imx8mq_enet_ref_sels, base + 0xa980)); clk_dm(IMX8MQ_CLK_ENET_TIMER, - imx8m_clk_composite("enet_timer", imx8mq_enet_timer_sels, + imx8m_clk_composite(dev, "enet_timer", imx8mq_enet_timer_sels, base + 0xaa00)); clk_dm(IMX8MQ_CLK_ENET_PHY_REF, - imx8m_clk_composite("enet_phy", imx8mq_enet_phy_sels, + imx8m_clk_composite(dev, "enet_phy", imx8mq_enet_phy_sels, base + 0xaa80)); clk_dm(IMX8MQ_CLK_ENET1_ROOT, imx_clk_gate4(dev, "enet1_root_clk", "enet_axi", diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 22b5d823ff9..1a814d9a386 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -241,20 +241,20 @@ static inline struct clk *imx_clk_gate3(struct udevice *dev, const char *name, reg, shift, 0, NULL); } -struct clk *imx8m_clk_composite_flags(const char *name, +struct clk *imx8m_clk_composite_flags(struct udevice *dev, const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, unsigned long flags); -#define __imx8m_clk_composite(name, parent_names, reg, flags) \ - imx8m_clk_composite_flags(name, parent_names, \ +#define __imx8m_clk_composite(dev, name, parent_names, reg, flags) \ + imx8m_clk_composite_flags(dev, name, parent_names, \ ARRAY_SIZE(parent_names), reg, \ flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) -#define imx8m_clk_composite(name, parent_names, reg) \ - __imx8m_clk_composite(name, parent_names, reg, 0) +#define imx8m_clk_composite(dev, name, parent_names, reg) \ + __imx8m_clk_composite(dev, name, parent_names, reg, 0) -#define imx8m_clk_composite_critical(name, parent_names, reg) \ - __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL) +#define imx8m_clk_composite_critical(dev, name, parent_names, reg) \ + __imx8m_clk_composite(dev, name, parent_names, reg, CLK_IS_CRITICAL) struct clk *imx93_clk_composite_flags(const char *name, const char * const *parent_names, From b4734c9c333b9dfdbafaf8c7d5b8500eb0c718c3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:45 +0100 Subject: [PATCH 16/33] clk: imx: Convert clock-osc-* back to osc_* Convert clock-osc-24m back to osc_24m and clock-osc-32k back to osc_32k. These are the clock which match clock tables in Linux. This is now possible because the clock drivers now resolve clock names based on clock-names DT property in the CCM DT node. Signed-off-by: Marek Vasut --- drivers/clk/imx/clk-imx8mm.c | 60 ++++++++++++------------- drivers/clk/imx/clk-imx8mn.c | 56 +++++++++++------------ drivers/clk/imx/clk-imx8mp.c | 86 ++++++++++++++++++------------------ 3 files changed, 101 insertions(+), 101 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index c9d6954ac75..07e0f6da33e 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -14,7 +14,7 @@ #include "clk.h" -static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; +static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; @@ -23,61 +23,61 @@ static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_se static const char * const imx8mm_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", }; -static const char * const imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", +static const char * const imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; -static const char * const imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", +static const char * const imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; #ifndef CONFIG_XPL_BUILD -static const char * const imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", +static const char * const imx8mm_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; -static const char * const imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", +static const char * const imx8mm_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", }; -static const char * const imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", +static const char * const imx8mm_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", "video_pll1_out", }; -static const char * const imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", +static const char * const imx8mm_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", }; #endif -static const char * const imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", +static const char * const imx8mm_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; -static const char * const imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", +static const char * const imx8mm_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; -static const char * const imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mm_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; -static const char * const imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mm_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; -static const char * const imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mm_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mm_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mm_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mm_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; @@ -98,69 +98,69 @@ static const char * const imx8mm_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m" "audio_pll2_out", }; #if CONFIG_IS_ENABLED(PCIE_DW_IMX) -static const char * const imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m", +static const char * const imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", }; -static const char * const imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m", +static const char * const imx8mm_pcie1_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", "sys_pll1_400m", }; -static const char * const imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", +static const char * const imx8mm_pcie1_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", }; #endif #ifndef CONFIG_XPL_BUILD -static const char * const imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mm_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; -static const char * const imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; -static const char * const imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; -static const char * const imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; #endif -static const char * const imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", +static const char * const imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; -static const char * const imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mm_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", }; #if CONFIG_IS_ENABLED(NXP_FSPI) -static const char * const imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", +static const char * const imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; #endif -static const char * const imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", +static const char * const imx8mm_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; -static const char * const imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", +static const char * const imx8mm_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; #if CONFIG_IS_ENABLED(DM_SPI) -static const char * const imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mm_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mm_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mm_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; #endif diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 18621fc1226..5f7530eafc8 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -16,7 +16,7 @@ static u32 share_count_nand; -static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; +static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; @@ -25,75 +25,75 @@ static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_se static const char * const imx8mn_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", }; -static const char * const imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", +static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; -static const char * const imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", +static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", }; -static const char * const imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", +static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", }; #ifndef CONFIG_XPL_BUILD -static const char * const imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", +static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", }; -static const char * const imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", +static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", "video_pll_out", }; -static const char * const imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", +static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; #endif -static const char * const imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", +static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; -static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", +static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; -static const char * const imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; -static const char * const imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; #if CONFIG_IS_ENABLED(DM_SPI) -static const char * const imx8mn_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mn_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mn_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; #endif -static const char * const imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; @@ -114,44 +114,44 @@ static const char * const imx8mn_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m" "clk_ext3", "audio_pll2_out", }; #ifndef CONFIG_XPL_BUILD -static const char * const imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; -static const char * const imx8mn_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; -static const char * const imx8mn_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; -static const char * const imx8mn_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; #endif -static const char * const imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", +static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "m7_alt_pll", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; -static const char * const imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", }; -static const char * const imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", +static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; -static const char * const imx8mn_nand_sels[] = {"clock-osc-24m", "sys_pll2_500m", "audio_pll1_out", +static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll_out", }; -static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", +static const char * const imx8mn_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; -static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", +static const char * const imx8mn_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 5768504e7c9..7c6b5322427 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -14,7 +14,7 @@ #include "clk.h" -static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; +static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; @@ -23,167 +23,167 @@ static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_se static const char * const imx8mp_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", }; -static const char * const imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", +static const char * const imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; -static const char * const imx8mp_hsio_axi_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", +static const char * const imx8mp_hsio_axi_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; -static const char * const imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m", +static const char * const imx8mp_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "sys_pll1_100m",}; -static const char * const imx8mp_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", +static const char * const imx8mp_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; -static const char * const imx8mp_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", +static const char * const imx8mp_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; -static const char * const imx8mp_noc_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out", +static const char * const imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; -static const char * const imx8mp_noc_io_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out", +static const char * const imx8mp_noc_io_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; -static const char * const imx8mp_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", +static const char * const imx8mp_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; -static const char * const imx8mp_dram_alt_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll1_100m", +static const char * const imx8mp_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll1_out", "sys_pll1_266m", }; -static const char * const imx8mp_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mp_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mp_pcie_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", +static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", }; -static const char * const imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mp_i2c5_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mp_i2c6_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mp_enet_qos_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", +static const char * const imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", }; -static const char * const imx8mp_enet_qos_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", +static const char * const imx8mp_enet_qos_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", "video_pll1_out", }; -static const char * const imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mp_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; -static const char * const imx8mp_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mp_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; -static const char * const imx8mp_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mp_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mp_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mp_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mp_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mp_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mp_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mp_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mp_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", +static const char * const imx8mp_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; -static const char * const imx8mp_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", +static const char * const imx8mp_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; -static const char * const imx8mp_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", +static const char * const imx8mp_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; -static const char * const imx8mp_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", +static const char * const imx8mp_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; -static const char * const imx8mp_usb_core_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", +static const char * const imx8mp_usb_core_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; -static const char * const imx8mp_usb_phy_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", +static const char * const imx8mp_usb_phy_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; -static const char * const imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mp_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_500m", "clk_ext4", "audio_pll2_out" }; -static const char * const imx8mp_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mp_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; -static const char * const imx8mp_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mp_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; -static const char * const imx8mp_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mp_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; -static const char * const imx8mp_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mp_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; -static const char * const imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mp_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mp_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mp_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mp_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", +static const char * const imx8mp_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m" }; -static const char * const imx8mp_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", +static const char * const imx8mp_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; -static const char * const imx8mp_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; -static const char * const imx8mp_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", +static const char * const imx8mp_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", }; -static const char * const imx8mp_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", +static const char * const imx8mp_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", "video_pll1_out", }; -static const char * const imx8mp_enet_phy_ref_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", +static const char * const imx8mp_enet_phy_ref_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; @@ -347,7 +347,7 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0)); clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2(dev, "usb_root_clk", "hsio_axi", base + 0x44d0, 0)); - clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2(dev, "usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); + clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2(dev, "usb_suspend_clk", "osc_24m", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4(dev, "usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); From 8c1024636fbbcf1b19836fac2776ec829f2a7519 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:46 +0100 Subject: [PATCH 17/33] clk: imx: Pass struct udevice into imx_clk_pllv3*() Pass struct udevice * into imx_clk_pllv3*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut --- drivers/clk/imx/clk-imx6q.c | 6 +++--- drivers/clk/imx/clk-imxrt1020.c | 4 ++-- drivers/clk/imx/clk-imxrt1050.c | 8 ++++---- drivers/clk/imx/clk-imxrt1170.c | 6 +++--- drivers/clk/imx/clk-pllv3.c | 6 +++--- drivers/clk/imx/clk.h | 6 +++--- 6 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index d9eb43d82be..8327aea8950 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -46,10 +46,10 @@ static int imx6q_clk_probe(struct udevice *dev) base = (void *)ANATOP_BASE_ADDR; clk_dm(IMX6QDL_CLK_PLL2, - imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", + imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1)); clk_dm(IMX6QDL_CLK_PLL3_USB_OTG, - imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", + imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3)); clk_dm(IMX6QDL_CLK_PLL3_60M, imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8)); @@ -58,7 +58,7 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M, imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2)); clk_dm(IMX6QDL_CLK_PLL6, - imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3)); + imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3)); clk_dm(IMX6QDL_CLK_PLL6_ENET, imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c index 40cba218c29..62c00ba3314 100644 --- a/drivers/clk/imx/clk-imxrt1020.c +++ b/drivers/clk/imx/clk-imxrt1020.c @@ -38,10 +38,10 @@ static int imxrt1020_clk_probe(struct udevice *dev) base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop")); clk_dm(IMXRT1020_CLK_PLL2_SYS, - imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc", + imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_sys", "osc", base + 0x30, 0x1)); clk_dm(IMXRT1020_CLK_PLL3_USB_OTG, - imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", + imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x1)); /* PLL bypass out */ diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 71d5fa8a90e..02f7b05da5f 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -49,17 +49,17 @@ static int imxrt1050_clk_probe(struct udevice *dev) pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMXRT1050_CLK_PLL1_ARM, - imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel", + imx_clk_pllv3(dev, IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel", base + 0x0, 0x7f)); clk_dm(IMXRT1050_CLK_PLL2_SYS, - imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel", + imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel", base + 0x30, 0x1)); clk_dm(IMXRT1050_CLK_PLL3_USB_OTG, - imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", + imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "pll3_usb_otg_ref_sel", base + 0x10, 0x1)); clk_dm(IMXRT1050_CLK_PLL5_VIDEO, - imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel", + imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel", base + 0xa0, 0x7f)); /* PLL bypass out */ diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c index 7e06504584f..caf34a55459 100644 --- a/drivers/clk/imx/clk-imxrt1170.c +++ b/drivers/clk/imx/clk-imxrt1170.c @@ -121,13 +121,13 @@ static int imxrt1170_clk_probe(struct udevice *dev) imx_clk_fixed_factor("rcosc48M_div2", "rcosc48M", 1, 2)); clk_dm(IMXRT1170_CLK_PLL_ARM, - imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm", "osc", + imx_clk_pllv3(dev, IMX_PLLV3_SYS, "pll_arm", "osc", base + 0x200, 0xff)); clk_dm(IMXRT1170_CLK_PLL3, - imx_clk_pllv3(IMX_PLLV3_GENERICV2, "pll3_sys", "osc", + imx_clk_pllv3(dev, IMX_PLLV3_GENERICV2, "pll3_sys", "osc", base + 0x210, 1)); clk_dm(IMXRT1170_CLK_PLL2, - imx_clk_pllv3(IMX_PLLV3_GENERICV2, "pll2_sys", "osc", + imx_clk_pllv3(dev, IMX_PLLV3_GENERICV2, "pll2_sys", "osc", base + 0x240, 1)); clk_dm(IMXRT1170_CLK_PLL3_PFD0, diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index c6692f2f9f5..bc9916385c8 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -281,9 +281,9 @@ static const struct clk_ops clk_pllv3_enet_ops = { .get_rate = clk_pllv3_enet_get_rate, }; -struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, - const char *parent_name, void __iomem *base, - u32 div_mask) +struct clk *imx_clk_pllv3(struct udevice *dev, enum imx_pllv3_type type, + const char *name, const char *parent_name, + void __iomem *base, u32 div_mask) { struct clk_pllv3 *pll; struct clk *clk; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 1a814d9a386..4caf3b053d4 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -83,9 +83,9 @@ struct clk *clk_register_gate2(struct udevice *dev, const char *name, void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 clk_gate_flags, unsigned int *share_count); -struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, - const char *parent_name, void __iomem *base, - u32 div_mask); +struct clk *imx_clk_pllv3(struct udevice *dev, enum imx_pllv3_type type, + const char *name, const char *parent_name, + void __iomem *base, u32 div_mask); static inline struct clk *imx_clk_gate2(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, From 63fa94855078e87a72877b314fb5a118fb93dfaf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:47 +0100 Subject: [PATCH 18/33] clk: imx: pllv3: Resolve parent clock by name Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut --- drivers/clk/imx/clk-pllv3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index bc9916385c8..85b6a9809e8 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -339,7 +339,8 @@ struct clk *imx_clk_pllv3(struct udevice *dev, enum imx_pllv3_type type, pll->div_mask = div_mask; clk = &pll->clk; - ret = clk_register(clk, drv_name, name, parent_name); + ret = clk_register(clk, drv_name, name, + clk_resolve_parent_clk(dev, parent_name)); if (ret) { kfree(pll); return ERR_PTR(ret); From e14dd5c35aa8098b024257d9ee0073d1ba6e0281 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:48 +0100 Subject: [PATCH 19/33] clk: clk-divider: Use struct udevice instead of struct device Use U-Boot specific struct udevice instead of Linux compatibility struct device in clk-divider clock registration. Signed-off-by: Marek Vasut --- drivers/clk/clk-divider.c | 4 ++-- include/linux/clk-provider.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index aa210e3d15f..3b4b3c4fa5f 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -183,7 +183,7 @@ const struct clk_ops clk_divider_ops = { .set_rate = clk_divider_set_rate, }; -static struct clk *_register_divider(struct device *dev, const char *name, +static struct clk *_register_divider(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table) @@ -227,7 +227,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, return clk; } -struct clk *clk_register_divider(struct device *dev, const char *name, +struct clk *clk_register_divider(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index d44ead53079..198f3ff0e42 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -237,7 +237,7 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); -struct clk *clk_register_divider(struct device *dev, const char *name, +struct clk *clk_register_divider(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags); From df9c287e42967e22cdf161f4cbca36f2772bdb4a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:49 +0100 Subject: [PATCH 20/33] clk: imx: Pass struct udevice into imx_clk_divider*() Pass struct udevice * into imx_clk_divider*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut --- drivers/clk/imx/clk-imx6q.c | 22 +++++++++++----------- drivers/clk/imx/clk-imx8mm.c | 4 ++-- drivers/clk/imx/clk-imx8mn.c | 4 ++-- drivers/clk/imx/clk-imx8mp.c | 4 ++-- drivers/clk/imx/clk-imx8mq.c | 26 +++++++++++++------------- drivers/clk/imx/clk-imxrt1020.c | 10 +++++----- drivers/clk/imx/clk-imxrt1050.c | 22 +++++++++++----------- drivers/clk/imx/clk-imxrt1170.c | 8 ++++---- drivers/clk/imx/clk.h | 21 ++++++++++++--------- 9 files changed, 62 insertions(+), 59 deletions(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 8327aea8950..5313db9e757 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -90,28 +90,28 @@ static int imx6q_clk_probe(struct udevice *dev) } clk_dm(IMX6QDL_CLK_USDHC1_PODF, - imx_clk_divider("usdhc1_podf", "usdhc1_sel", + imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3)); clk_dm(IMX6QDL_CLK_USDHC2_PODF, - imx_clk_divider("usdhc2_podf", "usdhc2_sel", + imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3)); clk_dm(IMX6QDL_CLK_USDHC3_PODF, - imx_clk_divider("usdhc3_podf", "usdhc3_sel", + imx_clk_divider(dev, "usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3)); clk_dm(IMX6QDL_CLK_USDHC4_PODF, - imx_clk_divider("usdhc4_podf", "usdhc4_sel", + imx_clk_divider(dev, "usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3)); if (of_machine_is_compatible("fsl,imx6qp")) { clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF, - imx_clk_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6)); + imx_clk_divider(dev, "uart_serial_podf", "uart_sel", base + 0x24, 0, 6)); clk_dm(IMX6QDL_CLK_ECSPI_ROOT, - imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6)); + imx_clk_divider(dev, "ecspi_root", "ecspi_sel", base + 0x38, 19, 6)); } else { clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF, - imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6)); + imx_clk_divider(dev, "uart_serial_podf", "pll3_80m", base + 0x24, 0, 6)); clk_dm(IMX6QDL_CLK_ECSPI_ROOT, - imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6)); + imx_clk_divider(dev, "ecspi_root", "pll3_60m", base + 0x38, 19, 6)); } clk_dm(IMX6QDL_CLK_ECSPI1, @@ -142,12 +142,12 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_busy_mux(dev, "periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels))); clk_dm(IMX6QDL_CLK_AHB, - imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, + imx_clk_busy_divider(dev, "ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1)); clk_dm(IMX6QDL_CLK_IPG, - imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2)); + imx_clk_divider(dev, "ipg", "ahb", base + 0x14, 8, 2)); clk_dm(IMX6QDL_CLK_IPG_PER, - imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6)); + imx_clk_divider(dev, "ipg_per", "ipg", base + 0x1c, 0, 6)); clk_dm(IMX6QDL_CLK_I2C1, imx_clk_gate2(dev, "i2c1", "ipg_per", base + 0x70, 6)); clk_dm(IMX6QDL_CLK_I2C2, diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 07e0f6da33e..05b864dd34b 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -296,14 +296,14 @@ static int imx8mm_clk_probe(struct udevice *dev) clk_dm(IMX8MM_CLK_A53_CG, imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); clk_dm(IMX8MM_CLK_A53_DIV, - imx_clk_divider2("arm_a53_div", "arm_a53_cg", + imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); clk_dm(IMX8MM_CLK_AHB, imx8m_clk_composite_critical(dev, "ahb", imx8mm_ahb_sels, base + 0x9000)); clk_dm(IMX8MM_CLK_IPG_ROOT, - imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1)); + imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1)); clk_dm(IMX8MM_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical(dev, "nand_usdhc_bus", diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 5f7530eafc8..540726f0c9c 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -293,14 +293,14 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_CLK_A53_CG, imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); clk_dm(IMX8MN_CLK_A53_DIV, - imx_clk_divider2("arm_a53_div", "arm_a53_cg", + imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); clk_dm(IMX8MN_CLK_AHB, imx8m_clk_composite_critical(dev, "ahb", imx8mn_ahb_sels, base + 0x9000)); clk_dm(IMX8MN_CLK_IPG_ROOT, - imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1)); + imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1)); clk_dm(IMX8MN_CLK_ENET_AXI, imx8m_clk_composite(dev, "enet_axi", imx8mn_enet_axi_sels, diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 7c6b5322427..ed11d751af0 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -264,7 +264,7 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels))); clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); - clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); + clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite(dev, "hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380)); clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical(dev, "main_axi", imx8mp_main_axi_sels, base + 0x8800)); @@ -275,7 +275,7 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical(dev, "ahb_root", imx8mp_ahb_sels, base + 0x9000)); - clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1)); + clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2(dev, "ipg_root", "ahb_root", base + 0x9080, 0, 1)); clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite(dev, "dram_alt", imx8mp_dram_alt_sels, base + 0xa000)); clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical(dev, "dram_apb", imx8mp_dram_apb_sels, base + 0xa080)); diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 5faa2d20224..7632ffe72e7 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -313,27 +313,27 @@ static int imx8mq_clk_probe(struct udevice *dev) imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL1_DIV, - imx_clk_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3)); + imx_clk_divider(dev, "audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3)); clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL2_DIV, - imx_clk_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3)); + imx_clk_divider(dev, "audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3)); clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL1_DIV, - imx_clk_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3)); + imx_clk_divider(dev, "video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3)); clk_dm(IMX8MQ_CLK_MON_GPU_PLL_DIV, - imx_clk_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3)); + imx_clk_divider(dev, "gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3)); clk_dm(IMX8MQ_CLK_MON_VPU_PLL_DIV, - imx_clk_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3)); + imx_clk_divider(dev, "vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3)); clk_dm(IMX8MQ_CLK_MON_ARM_PLL_DIV, - imx_clk_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3)); + imx_clk_divider(dev, "arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3)); clk_dm(IMX8MQ_CLK_MON_SYS_PLL1_DIV, - imx_clk_divider("sys_pll1_out_monitor", "sys_pll1_out", base + 0x7c, 0, 3)); + imx_clk_divider(dev, "sys_pll1_out_monitor", "sys_pll1_out", base + 0x7c, 0, 3)); clk_dm(IMX8MQ_CLK_MON_SYS_PLL2_DIV, - imx_clk_divider("sys_pll2_out_monitor", "sys_pll2_out", base + 0x7c, 4, 3)); + imx_clk_divider(dev, "sys_pll2_out_monitor", "sys_pll2_out", base + 0x7c, 4, 3)); clk_dm(IMX8MQ_CLK_MON_SYS_PLL3_DIV, - imx_clk_divider("sys_pll3_out_monitor", "sys_pll3_out", base + 0x7c, 8, 3)); + imx_clk_divider(dev, "sys_pll3_out_monitor", "sys_pll3_out", base + 0x7c, 8, 3)); clk_dm(IMX8MQ_CLK_MON_DRAM_PLL_DIV, - imx_clk_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3)); + imx_clk_divider(dev, "dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3)); clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL2_DIV, - imx_clk_divider("video_pll2_out_monitor", "video_pll2_out", base + 0x7c, 16, 3)); + imx_clk_divider(dev, "video_pll2_out_monitor", "video_pll2_out", base + 0x7c, 16, 3)); clk_dm(IMX8MQ_CLK_MON_SEL, imx_clk_mux_flags(dev, "pllout_monitor_sel", base + 0x74, 0, 4, pllout_monitor_sels, @@ -354,7 +354,7 @@ static int imx8mq_clk_probe(struct udevice *dev) clk_dm(IMX8MQ_CLK_A53_CG, imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); clk_dm(IMX8MQ_CLK_A53_DIV, - imx_clk_divider2("arm_a53_div", "arm_a53_cg", + imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); clk_dm(IMX8MQ_CLK_A53_CORE, imx_clk_mux2(dev, "arm_a53_src", base + 0x9880, 24, 1, @@ -364,7 +364,7 @@ static int imx8mq_clk_probe(struct udevice *dev) imx8m_clk_composite_critical(dev, "ahb", imx8mq_ahb_sels, base + 0x9000)); clk_dm(IMX8MQ_CLK_IPG_ROOT, - imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1)); + imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1)); clk_dm(IMX8MQ_CLK_ENET_AXI, imx8m_clk_composite(dev, "enet_axi", imx8mq_enet_axi_sels, diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c index 62c00ba3314..775cc73b4db 100644 --- a/drivers/clk/imx/clk-imxrt1020.c +++ b/drivers/clk/imx/clk-imxrt1020.c @@ -100,19 +100,19 @@ static int imxrt1020_clk_probe(struct udevice *dev) semc_sels, ARRAY_SIZE(semc_sels))); clk_dm(IMXRT1020_CLK_AHB_PODF, - imx_clk_divider("ahb_podf", "periph_sel", + imx_clk_divider(dev, "ahb_podf", "periph_sel", base + 0x14, 10, 3)); clk_dm(IMXRT1020_CLK_USDHC1_PODF, - imx_clk_divider("usdhc1_podf", "usdhc1_sel", + imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3)); clk_dm(IMXRT1020_CLK_USDHC2_PODF, - imx_clk_divider("usdhc2_podf", "usdhc2_sel", + imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3)); clk_dm(IMXRT1020_CLK_LPUART_PODF, - imx_clk_divider("lpuart_podf", "lpuart_sel", + imx_clk_divider(dev, "lpuart_podf", "lpuart_sel", base + 0x24, 0, 6)); clk_dm(IMXRT1020_CLK_SEMC_PODF, - imx_clk_divider("semc_podf", "semc_sel", + imx_clk_divider(dev, "semc_podf", "semc_sel", base + 0x14, 16, 3)); clk_dm(IMXRT1020_CLK_USDHC1, diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 02f7b05da5f..c8ac3103dc9 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -85,10 +85,10 @@ static int imxrt1050_clk_probe(struct udevice *dev) CLK_SET_RATE_PARENT)); clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL, - imx_clk_divider("video_post_div_sel", "pll5_video", + imx_clk_divider(dev, "video_post_div_sel", "pll5_video", base + 0xa0, 19, 2)); clk_dm(IMXRT1050_CLK_VIDEO_DIV, - imx_clk_divider("video_div", "video_post_div_sel", + imx_clk_divider(dev, "video_div", "video_post_div_sel", base + 0x170, 30, 2)); clk_dm(IMXRT1050_CLK_PLL3_80M, @@ -113,7 +113,7 @@ static int imxrt1050_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMXRT1050_CLK_ARM_PODF, - imx_clk_divider("arm_podf", "pll1_arm", + imx_clk_divider(dev, "arm_podf", "pll1_arm", base + 0x10, 0, 3)); clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL, @@ -142,28 +142,28 @@ static int imxrt1050_clk_probe(struct udevice *dev) lcdif_sels, ARRAY_SIZE(lcdif_sels))); clk_dm(IMXRT1050_CLK_AHB_PODF, - imx_clk_divider("ahb_podf", "periph_sel", + imx_clk_divider(dev, "ahb_podf", "periph_sel", base + 0x14, 10, 3)); clk_dm(IMXRT1050_CLK_IPG_PDOF, - imx_clk_divider("ipg_podf", "ahb_podf", + imx_clk_divider(dev, "ipg_podf", "ahb_podf", base + 0x14, 8, 2)); clk_dm(IMXRT1050_CLK_USDHC1_PODF, - imx_clk_divider("usdhc1_podf", "usdhc1_sel", + imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3)); clk_dm(IMXRT1050_CLK_USDHC2_PODF, - imx_clk_divider("usdhc2_podf", "usdhc2_sel", + imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3)); clk_dm(IMXRT1050_CLK_LPUART_PODF, - imx_clk_divider("lpuart_podf", "lpuart_sel", + imx_clk_divider(dev, "lpuart_podf", "lpuart_sel", base + 0x24, 0, 6)); clk_dm(IMXRT1050_CLK_SEMC_PODF, - imx_clk_divider("semc_podf", "semc_sel", + imx_clk_divider(dev, "semc_podf", "semc_sel", base + 0x14, 16, 3)); clk_dm(IMXRT1050_CLK_LCDIF_PRED, - imx_clk_divider("lcdif_pred", "lcdif_sel", + imx_clk_divider(dev, "lcdif_pred", "lcdif_sel", base + 0x38, 12, 3)); clk_dm(IMXRT1050_CLK_LCDIF_PODF, - imx_clk_divider("lcdif_podf", "lcdif_pred", + imx_clk_divider(dev, "lcdif_podf", "lcdif_pred", base + 0x18, 23, 3)); clk_dm(IMXRT1050_CLK_USDHC1, diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c index caf34a55459..043c400559e 100644 --- a/drivers/clk/imx/clk-imxrt1170.c +++ b/drivers/clk/imx/clk-imxrt1170.c @@ -160,28 +160,28 @@ static int imxrt1170_clk_probe(struct udevice *dev) imx_clk_mux(dev, "lpuart1_sel", base + (25 * 0x80), 8, 3, lpuart1_sels, ARRAY_SIZE(lpuart1_sels))); clk_dm(IMXRT1170_CLK_LPUART1, - imx_clk_divider("lpuart1", "lpuart1_sel", + imx_clk_divider(dev, "lpuart1", "lpuart1_sel", base + (25 * 0x80), 0, 8)); clk_dm(IMXRT1170_CLK_USDHC1_SEL, imx_clk_mux(dev, "usdhc1_sel", base + (58 * 0x80), 8, 3, usdhc1_sels, ARRAY_SIZE(usdhc1_sels))); clk_dm(IMXRT1170_CLK_USDHC1, - imx_clk_divider("usdhc1", "usdhc1_sel", + imx_clk_divider(dev, "usdhc1", "usdhc1_sel", base + (58 * 0x80), 0, 8)); clk_dm(IMXRT1170_CLK_GPT1_SEL, imx_clk_mux(dev, "gpt1_sel", base + (14 * 0x80), 8, 3, gpt1_sels, ARRAY_SIZE(gpt1_sels))); clk_dm(IMXRT1170_CLK_GPT1, - imx_clk_divider("gpt1", "gpt1_sel", + imx_clk_divider(dev, "gpt1", "gpt1_sel", base + (14 * 0x80), 0, 8)); clk_dm(IMXRT1170_CLK_SEMC_SEL, imx_clk_mux(dev, "semc_sel", base + (4 * 0x80), 8, 3, semc_sels, ARRAY_SIZE(semc_sels))); clk_dm(IMXRT1170_CLK_SEMC, - imx_clk_divider("semc", "semc_sel", + imx_clk_divider(dev, "semc", "semc_sel", base + (4 * 0x80), 0, 8)); struct clk *clk, *clk1; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 4caf3b053d4..32fa832f856 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -138,25 +138,28 @@ static inline struct clk *imx_clk_fixed_factor(const char *name, CLK_SET_RATE_PARENT, mult, div); } -static inline struct clk *imx_clk_divider(const char *name, const char *parent, - void __iomem *reg, u8 shift, u8 width) +static inline struct clk *imx_clk_divider(struct udevice *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift, u8 width) { - return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, + return clk_register_divider(dev, name, parent, CLK_SET_RATE_PARENT, reg, shift, width, 0); } static inline struct clk * -imx_clk_busy_divider(const char *name, const char *parent, void __iomem *reg, - u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift) +imx_clk_busy_divider(struct udevice *dev, const char *name, + const char *parent, void __iomem *reg, u8 shift, u8 width, + void __iomem *busy_reg, u8 busy_shift) { - return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, + return clk_register_divider(dev, name, parent, CLK_SET_RATE_PARENT, reg, shift, width, 0); } -static inline struct clk *imx_clk_divider2(const char *name, const char *parent, - void __iomem *reg, u8 shift, u8 width) +static inline struct clk *imx_clk_divider2(struct udevice *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift, u8 width) { - return clk_register_divider(NULL, name, parent, + return clk_register_divider(dev, name, parent, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, reg, shift, width, 0); } From 09fa54f6dad2b5b6c5237881e2d377b45f9e751d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:50 +0100 Subject: [PATCH 21/33] clk: clk-divider: Resolve parent clock by name Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut --- drivers/clk/clk-divider.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 3b4b3c4fa5f..e692b9c2167 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -218,7 +218,8 @@ static struct clk *_register_divider(struct udevice *dev, const char *name, clk = &div->clk; clk->flags = flags; - ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name); + ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, + clk_resolve_parent_clk(dev, parent_name)); if (ret) { kfree(div); return ERR_PTR(ret); From 1987fa7b344bdde12e0b07194b462388fe562954 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:51 +0100 Subject: [PATCH 22/33] clk: clk-fixed-factor: Use struct udevice instead of struct device Use U-Boot specific struct udevice instead of Linux compatibility struct device in clk-fixed-factor registration. Signed-off-by: Marek Vasut --- drivers/clk/clk-fixed-factor.c | 4 ++-- include/linux/clk-provider.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 068798cf9b0..ff61fb4d706 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -37,7 +37,7 @@ const struct clk_ops ccf_clk_fixed_factor_ops = { .get_rate = clk_factor_recalc_rate, }; -struct clk *clk_hw_register_fixed_factor(struct device *dev, +struct clk *clk_hw_register_fixed_factor(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { @@ -65,7 +65,7 @@ struct clk *clk_hw_register_fixed_factor(struct device *dev, return clk; } -struct clk *clk_register_fixed_factor(struct device *dev, const char *name, +struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 198f3ff0e42..5ea2171492e 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -233,7 +233,7 @@ struct clk *clk_register_composite(struct udevice *dev, const char *name, int clk_register(struct clk *clk, const char *drv_name, const char *name, const char *parent_name); -struct clk *clk_register_fixed_factor(struct device *dev, const char *name, +struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); From b185878b32f5c8993c023e0c564b1e9c9ff8def6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:52 +0100 Subject: [PATCH 23/33] clk: clk-fixed-factor: Resolve parent clock by name Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut --- drivers/clk/clk-fixed-factor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index ff61fb4d706..4eb8be728e6 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -56,7 +56,7 @@ struct clk *clk_hw_register_fixed_factor(struct udevice *dev, clk->flags = flags; ret = clk_register(clk, UBOOT_DM_CLK_IMX_FIXED_FACTOR, name, - parent_name); + clk_resolve_parent_clk(dev, parent_name)); if (ret) { kfree(fix); return ERR_PTR(ret); From 2a7ab5f6c644e28387ac6d0111bc66d7fb49679a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Mar 2025 16:58:53 +0100 Subject: [PATCH 24/33] clk: imx: Pass struct udevice into imx_clk_fixed_factor*() Pass struct udevice * into imx_clk_fixed_factor*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut --- drivers/clk/imx/clk-imx6q.c | 4 ++-- drivers/clk/imx/clk-imx8mm.c | 36 +++++++++++++++---------------- drivers/clk/imx/clk-imx8mn.c | 36 +++++++++++++++---------------- drivers/clk/imx/clk-imx8mp.c | 38 ++++++++++++++++----------------- drivers/clk/imx/clk-imx8mq.c | 38 ++++++++++++++++----------------- drivers/clk/imx/clk-imx93.c | 6 +++--- drivers/clk/imx/clk-imxrt1020.c | 2 +- drivers/clk/imx/clk-imxrt1050.c | 2 +- drivers/clk/imx/clk-imxrt1170.c | 8 +++---- drivers/clk/imx/clk.h | 7 +++--- 10 files changed, 89 insertions(+), 88 deletions(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 5313db9e757..13239f2f64d 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -52,7 +52,7 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3)); clk_dm(IMX6QDL_CLK_PLL3_60M, - imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8)); + imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0)); clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M, @@ -159,7 +159,7 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); clk_dm(IMX6QDL_CLK_ENET_REF, - imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1)); + imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1)); return 0; } diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 05b864dd34b..b81db516a69 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -249,42 +249,42 @@ static int imx8mm_clk_probe(struct udevice *dev) /* SYS PLL fixed output */ clk_dm(IMX8MM_SYS_PLL1_40M, - imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20)); + imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20)); clk_dm(IMX8MM_SYS_PLL1_80M, - imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10)); + imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10)); clk_dm(IMX8MM_SYS_PLL1_100M, - imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8)); + imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8)); clk_dm(IMX8MM_SYS_PLL1_133M, - imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6)); + imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6)); clk_dm(IMX8MM_SYS_PLL1_160M, - imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5)); + imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5)); clk_dm(IMX8MM_SYS_PLL1_200M, - imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4)); + imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4)); clk_dm(IMX8MM_SYS_PLL1_266M, - imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3)); + imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3)); clk_dm(IMX8MM_SYS_PLL1_400M, - imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2)); clk_dm(IMX8MM_SYS_PLL1_800M, - imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1)); + imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1)); clk_dm(IMX8MM_SYS_PLL2_50M, - imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20)); + imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20)); clk_dm(IMX8MM_SYS_PLL2_100M, - imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10)); + imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10)); clk_dm(IMX8MM_SYS_PLL2_125M, - imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8)); + imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8)); clk_dm(IMX8MM_SYS_PLL2_166M, - imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6)); + imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6)); clk_dm(IMX8MM_SYS_PLL2_200M, - imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5)); + imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5)); clk_dm(IMX8MM_SYS_PLL2_250M, - imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4)); + imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4)); clk_dm(IMX8MM_SYS_PLL2_333M, - imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3)); + imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3)); clk_dm(IMX8MM_SYS_PLL2_500M, - imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2)); clk_dm(IMX8MM_SYS_PLL2_1000M, - imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); + imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1)); base = dev_read_addr_ptr(dev); if (!base) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 540726f0c9c..be5b7933a8d 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -241,42 +241,42 @@ static int imx8mn_clk_probe(struct udevice *dev) /* SYS PLL fixed output */ clk_dm(IMX8MN_SYS_PLL1_40M, - imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20)); + imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20)); clk_dm(IMX8MN_SYS_PLL1_80M, - imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10)); + imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10)); clk_dm(IMX8MN_SYS_PLL1_100M, - imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8)); + imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8)); clk_dm(IMX8MN_SYS_PLL1_133M, - imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6)); + imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6)); clk_dm(IMX8MN_SYS_PLL1_160M, - imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5)); + imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5)); clk_dm(IMX8MN_SYS_PLL1_200M, - imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4)); + imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4)); clk_dm(IMX8MN_SYS_PLL1_266M, - imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3)); + imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3)); clk_dm(IMX8MN_SYS_PLL1_400M, - imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2)); clk_dm(IMX8MN_SYS_PLL1_800M, - imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1)); + imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1)); clk_dm(IMX8MN_SYS_PLL2_50M, - imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20)); + imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20)); clk_dm(IMX8MN_SYS_PLL2_100M, - imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10)); + imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10)); clk_dm(IMX8MN_SYS_PLL2_125M, - imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8)); + imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8)); clk_dm(IMX8MN_SYS_PLL2_166M, - imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6)); + imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6)); clk_dm(IMX8MN_SYS_PLL2_200M, - imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5)); + imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5)); clk_dm(IMX8MN_SYS_PLL2_250M, - imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4)); + imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4)); clk_dm(IMX8MN_SYS_PLL2_333M, - imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3)); + imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3)); clk_dm(IMX8MN_SYS_PLL2_500M, - imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2)); clk_dm(IMX8MN_SYS_PLL2_1000M, - imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); + imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1)); ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk); if (ret) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index ed11d751af0..bad579f8d5e 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -228,25 +228,25 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11)); clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11)); - clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20)); - clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10)); - clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8)); - clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6)); - clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5)); - clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4)); - clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3)); - clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2)); - clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1)); + clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20)); + clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10)); + clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8)); + clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6)); + clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5)); + clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4)); + clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3)); + clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2)); + clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1)); - clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20)); - clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10)); - clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8)); - clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6)); - clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5)); - clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4)); - clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3)); - clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2)); - clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); + clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20)); + clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10)); + clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8)); + clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6)); + clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5)); + clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4)); + clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3)); + clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2)); + clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1)); ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk); if (ret) @@ -313,7 +313,7 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite(dev, "wdog", imx8mp_wdog_sels, base + 0xb900)); clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite(dev, "usdhc3", imx8mp_usdhc3_sels, base + 0xbc80)); - clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4)); + clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor(dev, "dram_alt_root", "dram_alt", 1, 4)); clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags(dev, "dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL)); clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags(dev, "dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL)); diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 7632ffe72e7..fe6cba19758 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -275,42 +275,42 @@ static int imx8mq_clk_probe(struct udevice *dev) /* SYS PLL fixed output */ clk_dm(IMX8MQ_SYS1_PLL_40M, - imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20)); + imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20)); clk_dm(IMX8MQ_SYS1_PLL_80M, - imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10)); + imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10)); clk_dm(IMX8MQ_SYS1_PLL_100M, - imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8)); + imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8)); clk_dm(IMX8MQ_SYS1_PLL_133M, - imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6)); + imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6)); clk_dm(IMX8MQ_SYS1_PLL_160M, - imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5)); + imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5)); clk_dm(IMX8MQ_SYS1_PLL_200M, - imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4)); + imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4)); clk_dm(IMX8MQ_SYS1_PLL_266M, - imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3)); + imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3)); clk_dm(IMX8MQ_SYS1_PLL_400M, - imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2)); clk_dm(IMX8MQ_SYS1_PLL_800M, - imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1)); + imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1)); clk_dm(IMX8MQ_SYS2_PLL_50M, - imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20)); + imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20)); clk_dm(IMX8MQ_SYS2_PLL_100M, - imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10)); + imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10)); clk_dm(IMX8MQ_SYS2_PLL_125M, - imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8)); + imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8)); clk_dm(IMX8MQ_SYS2_PLL_166M, - imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6)); + imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6)); clk_dm(IMX8MQ_SYS2_PLL_200M, - imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5)); + imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5)); clk_dm(IMX8MQ_SYS2_PLL_250M, - imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4)); + imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4)); clk_dm(IMX8MQ_SYS2_PLL_333M, - imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3)); + imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3)); clk_dm(IMX8MQ_SYS2_PLL_500M, - imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2)); clk_dm(IMX8MQ_SYS2_PLL_1000M, - imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); + imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1)); clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL1_DIV, imx_clk_divider(dev, "audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3)); @@ -482,7 +482,7 @@ static int imx8mq_clk_probe(struct udevice *dev) base + 0x40a0, 0)); clk_dm(IMX8MQ_CLK_DRAM_ALT_ROOT, - imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4)); + imx_clk_fixed_factor(dev, "dram_alt_root", "dram_alt", 1, 4)); return 0; } diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 0caec91fd9a..c3112968c17 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -291,15 +291,15 @@ static int imx93_clk_probe(struct udevice *dev) clk_dm(IMX93_CLK_SYS_PLL_PFD0, clk_register_fixed_rate(NULL, "sys_pll_pfd0", 1000000000)); clk_dm(IMX93_CLK_SYS_PLL_PFD0_DIV2, - imx_clk_fixed_factor("sys_pll_pfd0_div2", "sys_pll_pfd0", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll_pfd0_div2", "sys_pll_pfd0", 1, 2)); clk_dm(IMX93_CLK_SYS_PLL_PFD1, clk_register_fixed_rate(NULL, "sys_pll_pfd1", 800000000)); clk_dm(IMX93_CLK_SYS_PLL_PFD1_DIV2, - imx_clk_fixed_factor("sys_pll_pfd1_div2", "sys_pll_pfd1", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll_pfd1_div2", "sys_pll_pfd1", 1, 2)); clk_dm(IMX93_CLK_SYS_PLL_PFD2, clk_register_fixed_rate(NULL, "sys_pll_pfd2", 625000000)); clk_dm(IMX93_CLK_SYS_PLL_PFD2_DIV2, - imx_clk_fixed_factor("sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2)); anatop_base = (void *)ANATOP_BASE_ADDR; diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c index 775cc73b4db..c14afdaf236 100644 --- a/drivers/clk/imx/clk-imxrt1020.c +++ b/drivers/clk/imx/clk-imxrt1020.c @@ -57,7 +57,7 @@ static int imxrt1020_clk_probe(struct udevice *dev) CLK_SET_RATE_PARENT)); clk_dm(IMXRT1020_CLK_PLL3_80M, - imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6)); + imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); clk_dm(IMXRT1020_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0)); diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index c8ac3103dc9..ba5b48748ef 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -92,7 +92,7 @@ static int imxrt1050_clk_probe(struct udevice *dev) base + 0x170, 30, 2)); clk_dm(IMXRT1050_CLK_PLL3_80M, - imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6)); + imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0)); diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c index 043c400559e..3f55d0d0127 100644 --- a/drivers/clk/imx/clk-imxrt1170.c +++ b/drivers/clk/imx/clk-imxrt1170.c @@ -114,11 +114,11 @@ static int imxrt1170_clk_probe(struct udevice *dev) base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop")); clk_dm(IMXRT1170_CLK_RCOSC_48M, - imx_clk_fixed_factor("rcosc48M", "rcosc16M", 3, 1)); + imx_clk_fixed_factor(dev, "rcosc48M", "rcosc16M", 3, 1)); clk_dm(IMXRT1170_CLK_RCOSC_400M, - imx_clk_fixed_factor("rcosc400M", "rcosc16M", 25, 1)); + imx_clk_fixed_factor(dev, "rcosc400M", "rcosc16M", 25, 1)); clk_dm(IMXRT1170_CLK_RCOSC_48M_DIV2, - imx_clk_fixed_factor("rcosc48M_div2", "rcosc48M", 1, 2)); + imx_clk_fixed_factor(dev, "rcosc48M_div2", "rcosc48M", 1, 2)); clk_dm(IMXRT1170_CLK_PLL_ARM, imx_clk_pllv3(dev, IMX_PLLV3_SYS, "pll_arm", "osc", @@ -149,7 +149,7 @@ static int imxrt1170_clk_probe(struct udevice *dev) imx_clk_pfd("pll2_pfd3", "pll2_sys", base + 0x270, 3)); clk_dm(IMXRT1170_CLK_PLL3_DIV2, - imx_clk_fixed_factor("pll3_div2", "pll3_sys", 1, 2)); + imx_clk_fixed_factor(dev, "pll3_div2", "pll3_sys", 1, 2)); /* CCM clocks */ base = dev_read_addr_ptr(dev); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 32fa832f856..7d14dbc395f 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -131,10 +131,11 @@ static inline struct clk *imx_clk_gate4_flags(struct udevice *dev, const char *n reg, shift, 0x3, 0, NULL); } -static inline struct clk *imx_clk_fixed_factor(const char *name, - const char *parent, unsigned int mult, unsigned int div) +static inline struct clk * +imx_clk_fixed_factor(struct udevice *dev, const char *name, const char *parent, + unsigned int mult, unsigned int div) { - return clk_register_fixed_factor(NULL, name, parent, + return clk_register_fixed_factor(dev, name, parent, CLK_SET_RATE_PARENT, mult, div); } From 31896508d8df4a87ecc09af6c6c61d8b1b5046af Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Mar 2025 04:28:27 +0100 Subject: [PATCH 25/33] arm64: imx8mp: Gracefully handle disabled ENV_IS_IN_SPI_FLASH In case ENV_IS_IN_SPI_FLASH is disabled, returning ENVL_SPI_FLASH leads to failure to find environment driver on start up. Fix this by testing whether ENV_IS_IN_SPI_FLASH is enabled and if not, then return ENVL_NOWHERE instead. Signed-off-by: Marek Vasut --- board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 4af3cbe9fe2..4275436b128 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -186,5 +186,7 @@ int board_late_init(void) enum env_location env_get_location(enum env_operation op, int prio) { - return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH; + return prio ? ENVL_UNKNOWN : CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH, + (ENVL_SPI_FLASH), + (ENVL_NOWHERE)); } From 99843fe42d6746a23e6b24447675c06c1a0c83e4 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 24 Mar 2025 18:27:25 -0500 Subject: [PATCH 26/33] board: beacon: imx8mp: Fix GIC clock for Overdrive mode There is a config option to run the PMIC at nominal voltages which is not enabled on the i.MX8MP Beacon kit, so it the PMIC runs at overdrive voltages. Unfortuately, the check for this condition to set the GIC clock parent and rate is backwards from what it should be, and accidentally sets the GIC clock to nominal if the PMIC is in overdrive, and sets the GIC clock to overdrive if the PMIC is in nominal. Fix this by inverting the logic on the check. Fixes: ab53bd43dbde ("arm64: imx: Add support for imx8mp-beacon-kit") Signed-off-by: Adam Ford --- board/beacon/imx8mp/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c index 6b357d90a3f..027fae38278 100644 --- a/board/beacon/imx8mp/spl.c +++ b/board/beacon/imx8mp/spl.c @@ -50,7 +50,7 @@ void spl_board_init(void) * setting done. Default is 400Mhz (system_pll1_800m with div = 2) * set by ROM for ND VDD_SOC */ - if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) { + if (!IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) { clock_enable(CCGR_GIC, 0); clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); clock_enable(CCGR_GIC, 1); From 19c5bff6d9a5d363c15f3561e645e6ff6297922d Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 24 Mar 2025 21:54:42 -0500 Subject: [PATCH 27/33] imx: imx9: Imply IMX_TMU If the CPU Information is displayed from imx8_cpu, it displays the cpu temperature grade and operating temperature if CONFIG_IMX9 is defined. This behavior is similar to what happens arch/arm/mach-imx/cpu.c except that the latter checks for CONFIG_IMX_THERMAL or CONFIG_IMX_TMU. In preparation to make imx8_cpu act like the previous implementation for any CPU, make IMX9 imply IMX_TMU, so it will be always displayed unless a user decides to disable it. Signed-off-by: Adam Ford Reviewed-by: Marek Vasut --- arch/arm/mach-imx/imx9/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 49220c0955e..c3e758e103a 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -10,6 +10,7 @@ config IMX9 select BINMAN select HAS_CAAM select ROM_UNIFIED_SECTIONS + imply IMX_TMU config IMX93 bool From 055d7cf5d7920af3ec3b1d0b00f89da9f4cc0a73 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 24 Mar 2025 21:54:43 -0500 Subject: [PATCH 28/33] cpu: imx8_cpu: Expand get_imx_type_str list of supported CPUs The imx8_cpu is capable of running on IMX8, IMX8M, and IMX9 families, but the CPU list is limited on the 8M variants. Expand this list to show more variants and their respective names. Signed-off-by: Adam Ford Reviewed-by: Marek Vasut --- drivers/cpu/imx8_cpu.c | 44 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 53d31b3c0bf..39b3c194131 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -35,11 +35,49 @@ static const char *get_imx_type_str(u32 imxtype) { switch (imxtype) { case MXC_CPU_IMX8MM: - return "8MM"; + return "8MMQ"; /* Quad-core version of the imx8mm */ + case MXC_CPU_IMX8MML: + return "8MMQL"; /* Quad-core Lite version of the imx8mm */ + case MXC_CPU_IMX8MMD: + return "8MMD"; /* Dual-core version of the imx8mm */ + case MXC_CPU_IMX8MMDL: + return "8MMDL"; /* Dual-core Lite version of the imx8mm */ + case MXC_CPU_IMX8MMS: + return "8MMS"; /* Single-core version of the imx8mm */ + case MXC_CPU_IMX8MMSL: + return "8MMSL"; /* Single-core Lite version of the imx8mm */ case MXC_CPU_IMX8MN: - return "8MN"; + return "8MNano Quad"; /* Quad-core version */ + case MXC_CPU_IMX8MND: + return "8MNano Dual"; /* Dual-core version */ + case MXC_CPU_IMX8MNS: + return "8MNano Solo"; /* Single-core version */ + case MXC_CPU_IMX8MNL: + return "8MNano QuadLite"; /* Quad-core Lite version */ + case MXC_CPU_IMX8MNDL: + return "8MNano DualLite"; /* Dual-core Lite version */ + case MXC_CPU_IMX8MNSL: + return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */ + case MXC_CPU_IMX8MNUQ: + return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */ + case MXC_CPU_IMX8MNUD: + return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */ + case MXC_CPU_IMX8MNUS: + return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */ case MXC_CPU_IMX8MP: - return "8MP"; + return "8MP[8]"; /* Quad-core version of the imx8mp */ + case MXC_CPU_IMX8MPD: + return "8MP Dual[3]"; /* Dual-core version of the imx8mp */ + case MXC_CPU_IMX8MPL: + return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */ + case MXC_CPU_IMX8MP6: + return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */ + case MXC_CPU_IMX8MQ: + return "8MQ"; /* Quad-core version of the imx8mq */ + case MXC_CPU_IMX8MQL: + return "8MQLite"; /* Quad-core Lite version of the imx8mq */ + case MXC_CPU_IMX8MD: + return "8MD"; /* Dual-core version of the imx8mq */ case MXC_CPU_IMX8QXP: case MXC_CPU_IMX8QXP_A0: return "8QXP"; From b554f04ebfb0040866fe7d46e6aaf7ff551dc40a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 24 Mar 2025 21:54:44 -0500 Subject: [PATCH 29/33] imx: imx8m: Imply IMX_TMU If the CPU Information is displayed from imx8_cpu, it displays the cpu temperature grade and operating temperature if CONFIG_IMX9 is defined. This behavior is similar to what happens mach-imx/cpu.c, except that the latter checks for IMX_THERMAL or IMX_TMU. In preparation to make imx8_cpu act like the previous implementation for any CPU, make IMX8M imply IMX_TMU so it will be always displayed unless a user decides to disable it. Signed-off-by: Adam Ford Reviewed-by: Marek Vasut --- arch/arm/mach-imx/imx8m/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 89f2b50c8a2..8ee699a343c 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -8,6 +8,7 @@ config IMX8M select LTO select ROM_UNIFIED_SECTIONS select ARMV8_CRYPTO + imply IMX_TMU config IMX8MQ bool From 4edfe1bbc4007659cfaed46372c6e31f1a9d6d79 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 24 Mar 2025 21:54:45 -0500 Subject: [PATCH 30/33] cpu: imx8_cpu: Print Speed grade if IMX_TMU Much of the data that is display by imx8_cpu.c is also displayed from arch/arm/mach-imx/cpu.c, except the temperature grade and active temperature are only displayed when SoC is an i.MX9. Since IMX9 now implies IMX_TMU, change this to check for IMX_TMU in the same way it's done in mach-imx/cpu.c to enable displaying this information for any SoC with either of this config enabled. Since additional text may appear due to this commit, remove the extra space in the message displaying the temperature grade. Before: CPU: NXP i.MX8MP Rev1.1 A53 at 1200 MHz Model: Beacon EmbeddedWorks i.MX8MPlus Development kit After: CPU: NXP i.MX8MP Rev1.1 A53 at 1200 MHz CPU: Industrial temperature grade (-40C to 105C) at 28C Model: Beacon EmbeddedWorks i.MX8MPlus Development kit Signed-off-by: Adam Ford Reviewed-by: Marek Vasut --- drivers/cpu/imx8_cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 39b3c194131..4e1eccaa5b0 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -215,19 +215,19 @@ static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size) ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz", plat->type, plat->rev, plat->name, plat->freq_mhz); - if (IS_ENABLED(CONFIG_IMX9)) { + if (IS_ENABLED(CONFIG_IMX_TMU)) { switch (get_cpu_temp_grade(&minc, &maxc)) { case TEMP_AUTOMOTIVE: - grade = "Automotive temperature grade "; + grade = "Automotive temperature grade"; break; case TEMP_INDUSTRIAL: - grade = "Industrial temperature grade "; + grade = "Industrial temperature grade"; break; case TEMP_EXTCOMMERCIAL: - grade = "Extended Consumer temperature grade "; + grade = "Extended Consumer temperature grade"; break; default: - grade = "Consumer temperature grade "; + grade = "Consumer temperature grade"; break; } From c2397b7c8213c30fcf1f7e3ca9e2356ed9e6b4df Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 24 Mar 2025 21:54:46 -0500 Subject: [PATCH 31/33] imx: imx8m: Imply CPU_IMX by default The imx8_cpu driver is a CPU Driver that supports the i.MX8M family, and when it is enabled, it acts as an alternative to arch/arm/mach-imx/cpu.c, but the imx8_cpu supports the driver model where cpu.c does not. Imply this newer driver by default. Signed-off-by: Adam Ford Reviewed-by: Marek Vasut --- arch/arm/mach-imx/imx8m/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 8ee699a343c..31f2f003d35 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -8,6 +8,8 @@ config IMX8M select LTO select ROM_UNIFIED_SECTIONS select ARMV8_CRYPTO + imply CPU + imply CPU_IMX imply IMX_TMU config IMX8MQ From 9dc3ae5ab85fe1bc78edad3037be1f18ee7a4423 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 24 Mar 2025 21:54:47 -0500 Subject: [PATCH 32/33] imx: imx8: Imply CPU_IMX by default The imx8_cpu driver is a CPU Driver that supports the i.MX8Q family. When it is enabled, it acts as an alternative to arch/arm/mach-imx/cpu.c, but the imx8_cpu supports the driver model where cpu.c does not. Imply this newer driver by default. Signed-off-by: Adam Ford Reviewed-by: Marek Vasut --- arch/arm/mach-imx/imx8/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 9a43beda6fa..257c14e61b6 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -9,6 +9,8 @@ config AHAB_BOOT config IMX8 bool select HAS_CAAM + imply CPU + imply CPU_IMX config MU_BASE_SPL hex "MU base address used in SPL" From 6bd1b740dd09f852ed3f313bd05f31c2324a916a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 24 Mar 2025 21:54:48 -0500 Subject: [PATCH 33/33] imx: imx9: Imply CPU_IMX by default The imx8_cpu driver is a CPU Driver that supports the i.MX9 family to display the CPU type, temperature grade and current operating temperature. The older file, arch/arm/mach-imx/cpu.c, does not support i.MX9, so this config is enabled in various IMX9 boards. Instead of having this option enabled in every IMX9, select this driver by default for the platform. Signed-off-by: Adam Ford Reviewed-by: Marek Vasut --- arch/arm/mach-imx/imx9/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index c3e758e103a..1ccdb1cf64f 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -8,6 +8,8 @@ config AHAB_BOOT config IMX9 bool select BINMAN + select CPU + select CPU_IMX select HAS_CAAM select ROM_UNIFIED_SECTIONS imply IMX_TMU