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watchdog: designware: Make this depend on WDT

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As this driver can dynamically determine the values set in
CONFIG_DW_WDT_BASE when using WDT, so make this depend on WDT rather
than migrate CONFIG_DW_WDT_BASE to Kconfig.

Cc: Chee Tien Fong <tien.fong.chee@intel.com>
Cc: Chin-Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinh.nguyen@intel.com>
Cc: Holger Brunck <holger.brunck@hitachienergy.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Stefan Roese <sr@denx.de>
Cc: hee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Tom Rini 2022-06-15 12:03:46 -04:00
parent fbc3621fb5
commit 0285455d90
4 changed files with 2 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/watchdog/Kconfig
View File

@ -64,8 +64,8 @@ config ULP_WATCHDOG
config DESIGNWARE_WATCHDOG config DESIGNWARE_WATCHDOG
bool "Designware watchdog timer support" bool "Designware watchdog timer support"
select HW_WATCHDOG if !WDT depends on WDT
default y if WDT && ROCKCHIP_RK3399 default y if ROCKCHIP_RK3399
help help
Enable this to support Designware Watchdog Timer IP, present e.g. Enable this to support Designware Watchdog Timer IP, present e.g.
on Altera SoCFPGA SoCs. on Altera SoCFPGA SoCs.

21
drivers/watchdog/designware_wdt.c
View File

@ -60,26 +60,6 @@ static void designware_wdt_reset_common(void __iomem *base)
writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR); writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
} }
#if !CONFIG_IS_ENABLED(WDT)
void hw_watchdog_reset(void)
{
designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
}
void hw_watchdog_init(void)
{
/* reset to disable the watchdog */
hw_watchdog_reset();
/* set timer in miliseconds */
designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
CONFIG_DW_WDT_CLOCK_KHZ,
CONFIG_WATCHDOG_TIMEOUT_MSECS);
/* enable the watchdog */
designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
/* reset the watchdog */
hw_watchdog_reset();
}
#else
static int designware_wdt_reset(struct udevice *dev) static int designware_wdt_reset(struct udevice *dev)
{ {
struct designware_wdt_priv *priv = dev_get_priv(dev); struct designware_wdt_priv *priv = dev_get_priv(dev);
@ -195,4 +175,3 @@ U_BOOT_DRIVER(designware_wdt) = {
.ops = &designware_wdt_ops, .ops = &designware_wdt_ops,
.flags = DM_FLAG_PRE_RELOC, .flags = DM_FLAG_PRE_RELOC,
}; };
#endif

1
include/configs/socfpga_common.h
View File

@ -66,7 +66,6 @@
/* /*
* L4 Watchdog * L4 Watchdog
*/ */
#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
#define CONFIG_DW_WDT_CLOCK_KHZ 25000 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
/* /*

1
include/configs/socfpga_soc64_common.h
View File

@ -92,7 +92,6 @@
/* /*
* L4 Watchdog * L4 Watchdog
*/ */
#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
unsigned int cm_get_l4_sys_free_clk_hz(void); unsigned int cm_get_l4_sys_free_clk_hz(void);