diff --git a/target/linux/realtek/files-6.12/Documentation/devicetree/bindings/i2c/i2c-gpio-shared.yaml b/target/linux/realtek/files-6.12/Documentation/devicetree/bindings/i2c/i2c-gpio-shared.yaml new file mode 100644 index 0000000000..f496f957b7 --- /dev/null +++ b/target/linux/realtek/files-6.12/Documentation/devicetree/bindings/i2c/i2c-gpio-shared.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-gpio-shared.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: mulitple GPIO bitbanged I2C busses with shared SCL + +maintainers: + - Markus Stockhausen + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + items: + - const: i2c-gpio-shared + + scl-gpios: + description: + gpio used for the shared scl signal, this should be flagged as + active high using open drain with (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) + from since the signal is by definition + open drain. + maxItems: 1 + +examples: + - | + #include + + i2c-gpio-shared { + compatible = "i2c-gpio-shared"; + scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + i2c0: i2c@0 { + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + }; + + i2c1: i2c@1 { + sda-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + }; + }; + +required: + - compatible + - scl-gpios \ No newline at end of file diff --git a/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl-otto/ioremap.h b/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl-otto/ioremap.h new file mode 100644 index 0000000000..c49a095792 --- /dev/null +++ b/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl-otto/ioremap.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef RTL838X_IOREMAP_H_ +#define RTL838X_IOREMAP_H_ + +static inline int is_rtl838x_internal_registers(phys_addr_t offset) +{ + /* IO-Block */ + if (offset >= 0xb8000000 && offset < 0xb9000000) + return 1; + /* Switch block */ + if (offset >= 0xbb000000 && offset < 0xbc000000) + return 1; + return 0; +} + +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, + unsigned long flags) +{ + if (is_rtl838x_internal_registers(offset)) + return (void __iomem *)offset; + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return is_rtl838x_internal_registers((unsigned long)addr); +} + +#endif diff --git a/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl-otto/mach-rtl-otto.h b/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl-otto/mach-rtl-otto.h new file mode 100644 index 0000000000..f85dee6591 --- /dev/null +++ b/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl-otto/mach-rtl-otto.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * Copyright (C) 2020 B. Koblitz + */ +#ifndef _MACH_RTL838X_H_ +#define _MACH_RTL838X_H_ + +#include +#include + +/* + * Register access macros + */ + +#define RTL838X_SW_BASE ((volatile void *) 0xBB000000) + +#define sw_r32(reg) readl(RTL838X_SW_BASE + reg) +#define sw_w32(val, reg) writel(val, RTL838X_SW_BASE + reg) +#define sw_w32_mask(clear, set, reg) sw_w32((sw_r32(reg) & ~(clear)) | (set), reg) + +#define RTL838X_MODEL_NAME_INFO (0x00D4) +#define RTL838X_CHIP_INFO (0x00D8) +#define RTL839X_MODEL_NAME_INFO (0x0FF0) +#define RTL839X_CHIP_INFO (0x0FF4) +#define RTL93XX_MODEL_NAME_INFO (0x0004) +#define RTL93XX_CHIP_INFO (0x0008) + +#define RTL838X_INT_RW_CTRL (0x0058) +#define RTL838X_EXT_VERSION (0x00D0) +#define RTL838X_PLL_CML_CTRL (0x0ff8) + +#define RTL931X_LED_GLB_CTRL (0x0600) +#define RTL931X_MAC_L2_GLOBAL_CTRL2 (0x1358) + +/* Definition of family IDs */ +#define RTL8380_FAMILY_ID (0x8380) +#define RTL8390_FAMILY_ID (0x8390) +#define RTL9300_FAMILY_ID (0x9300) +#define RTL9310_FAMILY_ID (0x9310) + +/* Basic SoC Features */ +#define RTL838X_CPU_PORT 28 +#define RTL839X_CPU_PORT 52 +#define RTL930X_CPU_PORT 28 +#define RTL931X_CPU_PORT 56 + +struct rtl83xx_soc_info { + unsigned char *name; + unsigned int id; + unsigned int family; + unsigned int revision; + unsigned int cpu; + bool testchip; + int cpu_port; + int memory_size; +}; + +#endif /* _MACH_RTL838X_H_ */ diff --git a/target/linux/realtek/files-6.12/arch/mips/rtl-otto/Makefile b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/Makefile new file mode 100644 index 0000000000..a9d1666d46 --- /dev/null +++ b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the rtl838x specific parts of the kernel +# + +obj-y := setup.o prom.o diff --git a/target/linux/realtek/files-6.12/arch/mips/rtl-otto/Platform b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/Platform new file mode 100644 index 0000000000..0b98b3927b --- /dev/null +++ b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/Platform @@ -0,0 +1,5 @@ +# +# Realtek RTL838x SoCs +# +cflags-$(CONFIG_MACH_REALTEK_RTL) += -I$(srctree)/arch/mips/include/asm/mach-rtl-otto/ +load-$(CONFIG_MACH_REALTEK_RTL) += 0xffffffff80100000 diff --git a/target/linux/realtek/files-6.12/arch/mips/rtl-otto/prom.c b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/prom.c new file mode 100644 index 0000000000..2ec2b3f0dd --- /dev/null +++ b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/prom.c @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * prom.c + * Early initialization code for the Realtek RTL838X SoC + * + * based on the original BSP by + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * Copyright (C) 2020 B. Koblitz + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define RTL_SOC_BASE ((volatile void *) 0xB8000000) + +#define RTL83XX_DRAM_CONFIG 0x1004 + +#define RTL9300_SRAMSAR0 0x4000 +#define RTL9300_SRAMSAR1 0x4010 +#define RTL9300_SRAMSAR2 0x4020 +#define RTL9300_SRAMSAR3 0x4030 +#define RTL9300_UMSAR0 0x1300 +#define RTL9300_UMSAR1 0x1310 +#define RTL9300_UMSAR2 0x1320 +#define RTL9300_UMSAR3 0x1330 +#define RTL9300_O0DOR2 0x4220 +#define RTL9300_O0DMAR2 0x4224 + +#define RTL931X_DRAM_CONFIG 0x14304c + +#define soc_r32(reg) readl(RTL_SOC_BASE + reg) +#define soc_w32(val, reg) writel(val, RTL_SOC_BASE + reg) + +struct rtl83xx_soc_info soc_info; +EXPORT_SYMBOL(soc_info); + +const void *fdt; + +static char rtl_soc_name[16]; +static char rtl_system_type[48]; + +#ifdef CONFIG_MIPS_MT_SMP + +extern const struct plat_smp_ops vsmp_smp_ops; +static struct plat_smp_ops rtl_smp_ops; + +static void rtlsmp_init_secondary(void) +{ + /* + * Enable all CPU interrupts, as everything is managed by the external controller. + * TODO: Standard vsmp_init_secondary() has special treatment for Malta if external + * GIC is available. Maybe we need this too. + */ + if (mips_gic_present()) + pr_warn("%s: GIC present. Maybe interrupt enabling required.\n", __func__); + else + set_c0_status(ST0_IM); +} + +static void rtlsmp_finish(void) +{ + /* These devices are low on resources. There might be the chance that CEVT_R4K is + * not enabled in kernel build. Nevertheless the timer and interrupt 7 might be + * active by default after startup of secondary VPEs. With no registered handler + * that leads to continuous unhandeled interrupts. Disable it but keep the counter + * running so it can still be used as an entropy source. + */ + if (!IS_ENABLED(CONFIG_CEVT_R4K)) { + write_c0_status(read_c0_status() & ~CAUSEF_IP7); + write_c0_compare(read_c0_count() - 1); + } + + local_irq_enable(); +} + +static int rtlsmp_register(void) +{ + if (!cpu_has_mipsmt) + return 1; + + rtl_smp_ops = vsmp_smp_ops; + rtl_smp_ops.init_secondary = rtlsmp_init_secondary; + rtl_smp_ops.smp_finish = rtlsmp_finish; + register_smp_ops(&rtl_smp_ops); + + return 0; +} + +#else /* !CONFIG_MIPS_MT_SMP */ + +#define rtlsmp_register() (1) + +#endif + +static void __init apply_early_quirks(void) +{ + if (soc_info.family == RTL8380_FAMILY_ID) { + /* + * Open up write protected registers. SDK opens/closes this whenever needed. For + * simplicity always work with an "open" register set. + */ + sw_w32(0x3, RTL838X_INT_RW_CTRL); + /* + * Disable 4 byte address mode of flash controller. If this bit is not cleared + * the watchdog cannot reset the SoC. The SDK changes this short before restart. + * Until this quirk was implemented all RTL838x devices ran with this disabled + * because of a coding error. As no issues were detected keep the behaviour + * until more details are known. + */ + sw_w32_mask(BIT(30), 0, RTL838X_PLL_CML_CTRL); + } +} + +static void __init apply_dts_quirks(void) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "diodes,pt7a75xx-wdt"); + if (node) { + if (soc_info.family == RTL9310_FAMILY_ID) { + pr_info("apply quirk for diodes pt7a75xx watchdog\n"); + sw_w32_mask(GENMASK(13, 12), BIT(12), RTL931X_LED_GLB_CTRL); + sw_w32_mask(0x0, BIT(8), RTL931X_MAC_L2_GLOBAL_CTRL2); + }; + of_node_put(node); + } +} + +void __init device_tree_init(void) +{ + if (!fdt_check_header(&__appended_dtb)) { + fdt = &__appended_dtb; + pr_info("Using appended Device Tree.\n"); + } + initial_boot_params = (void *)fdt; + unflatten_and_copy_device_tree(); + apply_dts_quirks(); + + /* delay cpc & smp probing to allow devicetree access */ + mips_cpc_probe(); + + if (!register_cps_smp_ops()) + return; + + if (!rtlsmp_register()) + return; + + register_up_smp_ops(); +} + +const char *get_system_type(void) +{ + return rtl_system_type; +} + +static void __init rtl838x_read_details(u32 model) +{ + u32 chip_info, ext_version, tmp; + + sw_w32(0xa << 28, RTL838X_CHIP_INFO); + + chip_info = sw_r32(RTL838X_CHIP_INFO); + soc_info.cpu = chip_info & 0xffff; + + ext_version = sw_r32(RTL838X_EXT_VERSION); + tmp = ext_version & 0x1f; + + if (tmp == 2) { + soc_info.revision = 1; + } else { + tmp = (chip_info >> 16) & 0x1f; + if (soc_info.cpu == 0x0477) { + soc_info.revision = tmp; + soc_info.testchip = true; + } else { + soc_info.revision = tmp - 1; + } + } +} + +static void __init rtl839x_read_details(u32 model) +{ + u32 chip_info; + + sw_w32(0xa << 28, RTL839X_CHIP_INFO); + + chip_info = sw_r32(RTL839X_CHIP_INFO); + soc_info.cpu = chip_info & 0xffff; + + soc_info.revision = (model >> 1) & 0x1f; + + if (!(model & 0x3e)) + soc_info.testchip = true; +} + +static void __init rtl93xx_read_details(u32 model) +{ + u32 chip_info; + + sw_w32(0xa << 16, RTL93XX_CHIP_INFO); + + chip_info = sw_r32(RTL93XX_CHIP_INFO); + soc_info.cpu = chip_info & 0xffff; + + soc_info.revision = model & 0xf; + + if (model & 0x30) + soc_info.testchip = true; +} + +static u32 __init read_model(void) +{ + u32 model, id; + + model = sw_r32(RTL838X_MODEL_NAME_INFO); + id = model >> 16 & 0xffff; + if ((id >= 0x8380 && id <= 0x8382) || id == 0x8330 || id == 0x8332) { + soc_info.id = id; + soc_info.family = RTL8380_FAMILY_ID; + soc_info.cpu_port = RTL838X_CPU_PORT; + apply_early_quirks(); + rtl838x_read_details(model); + return model; + } + + model = sw_r32(RTL839X_MODEL_NAME_INFO); + id = model >> 16 & 0xffff; + if ((id >= 0x8391 && id <= 0x8396) || (id >= 0x8351 && id <= 0x8353)) { + soc_info.id = id; + soc_info.family = RTL8390_FAMILY_ID; + soc_info.cpu_port = RTL839X_CPU_PORT; + apply_early_quirks(); + rtl839x_read_details(model); + return model; + } + + model = sw_r32(RTL93XX_MODEL_NAME_INFO); + id = model >> 16 & 0xffff; + if (id >= 0x9301 && id <= 0x9303) { + soc_info.id = id; + soc_info.family = RTL9300_FAMILY_ID; + soc_info.cpu_port = RTL930X_CPU_PORT; + apply_early_quirks(); + rtl93xx_read_details(model); + return model; + } else if (id >= 0x9311 && id <= 0x9313) { + soc_info.id = id; + soc_info.family = RTL9310_FAMILY_ID; + soc_info.cpu_port = RTL931X_CPU_PORT; + apply_early_quirks(); + rtl93xx_read_details(model); + return model; + } + + return 0; +} + +static void __init parse_model(u32 model) +{ + int val; + char suffix = 0; + + val = (model >> 11) & 0x1f; + if (val > 0 && val <= 26) + suffix = 'A' + (val - 1); + + snprintf(rtl_soc_name, sizeof(rtl_soc_name), "RTL%04X%c", + soc_info.id, suffix); + + soc_info.name = rtl_soc_name; +} + +static void __init set_system_type(void) +{ + char revision = '?'; + char *es = ""; + + if (soc_info.revision >= 0 && soc_info.revision < 26) + revision = 'A' + soc_info.revision; + + if (soc_info.testchip) + es = " ES"; + + snprintf(rtl_system_type, sizeof(rtl_system_type), + "Realtek %s%s rev %c (%04X)", + soc_info.name, es, revision, soc_info.cpu); +} + +static void get_system_memory(void) +{ + unsigned int dcr, bits; + + if (soc_info.family == RTL9310_FAMILY_ID) { + dcr = soc_r32(RTL931X_DRAM_CONFIG); + bits = (dcr >> 12) + ((dcr >> 6) & 0x3f) + (dcr & 0x3f); + } else { + dcr = soc_r32(RTL83XX_DRAM_CONFIG); + bits = ((dcr >> 28) & 0x3) + ((dcr >> 24) & 0x3) + + ((dcr >> 20) & 0xf) + ((dcr >> 16) & 0xf) + 20; + } + + soc_info.memory_size = 1 << bits; +} + +static void prepare_highmem(void) +{ + if ((soc_info.family != RTL9300_FAMILY_ID) || + (soc_info.memory_size <= 256 * 1024 * 1024) || + !IS_ENABLED(CONFIG_HIGHMEM)) + return; + + /* + * The RTL930x provides 3 logical adressing zones that can be configured individually + * and offer an additional memory access indirection. Memory is accessed via the OCP + * bus that checks these regions and maps logical addresses to physical ones. They are + * + * zone 1: logical address 0x00000000-0x0fffffff (256 MB) - map register 0xb8004200 + * zone 2: logical address 0x10000000-0x13ffffff (64 MB) - map register 0xb8004210 + * zone 3: logical address 0x20000000-0x9fffffff (2 GB) - map register 0xb8004220 + * + * Whenever CPU accesses memory the normal MIPS translation is applied and afterwards + * the bus adds the zone mapping. E.g. a read to 0x81230000 is converted to an cached + * memory access to logical address 0x01230000. It is issued to the OCP bus and the + * mapping from zone 1 register is added. That allows for two memory topologies: + * + * Linear memory with a maximum of 320 MB: + * + * Zone | map content | logical | physical + * -------------------+-----------------------+----------------------- + * 1 | 0x00000000 | 0x00000000-0x0fffffff | 0x00000000-0x0fffffff + * 2 | 0x00000000 | 0x10000000-0x13ffffff | 0x10000000-0x13ffffff + * + * 256MB low memory plus up to 2GB high memory: + * + * Zone | map content | logical | physical + * -------------------+-----------------------+----------------------- + * 1 | 0x00000000 | 0x00000000-0x0fffffff | 0x00000000-0x0fffffff + * 3 | 0x70000000 | 0x20000000-0x9fffffff | 0x10000000-0x7fffffff + */ + + pr_info("highmem kernel on RTL930x with > 256 MB RAM, adapt SoC memory mapping\n"); + + soc_w32(0, RTL9300_UMSAR0); + soc_w32(0, RTL9300_UMSAR1); + soc_w32(0, RTL9300_UMSAR2); + soc_w32(0, RTL9300_UMSAR3); + soc_w32(0, RTL9300_SRAMSAR0); + soc_w32(0, RTL9300_SRAMSAR1); + soc_w32(0, RTL9300_SRAMSAR2); + soc_w32(0, RTL9300_SRAMSAR3); + __sync(); + + soc_w32(0x70000000, RTL9300_O0DOR2); + soc_w32(0x7fffffff, RTL9300_O0DMAR2); + __sync(); +} + +void __init prom_init(void) +{ + u32 model = read_model(); + + parse_model(model); + set_system_type(); + get_system_memory(); + + pr_info("%s SoC with %d MB\n", get_system_type(), soc_info.memory_size >> 20); + + prepare_highmem(); + + /* + * fw_arg2 is be the pointer to the environment. Some devices (e.g. HP JG924A) hand + * over other than expected kernel boot arguments. Something like 0xfffdffff looks + * suspicous. Do extra cleanup for fw_init_cmdline() to avoid a hang during boot. + */ + if (fw_arg2 >= CKSEG2) + fw_arg2 = 0; + + fw_init_cmdline(); +} diff --git a/target/linux/realtek/files-6.12/arch/mips/rtl-otto/setup.c b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/setup.c new file mode 100644 index 0000000000..b02d2530ab --- /dev/null +++ b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/setup.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 B. Koblitz + * based on the original BSP by + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + */ + +#include +#include +#include +#include +#include +#include + +void __init plat_mem_setup(void) +{ + void *dtb; + + set_io_port_base(KSEG1); + + dtb = get_fdt(); + if (!dtb) + panic("no dtb found"); + + /* Load the devicetree to let the memory appear. */ + __dt_setup_arch(dtb); +} + +static void plat_time_init_fallback(void) +{ + struct device_node *np; + u32 freq = 500000000; + + np = of_find_node_by_name(NULL, "cpus"); + if (!np) { + pr_err("Missing 'cpus' DT node, using default frequency."); + } else { + if (of_property_read_u32(np, "frequency", &freq) < 0) + pr_err("No 'frequency' property in DT, using default."); + else + pr_info("CPU frequency from device tree: %dMHz", freq / 1000000); + of_node_put(np); + } + mips_hpt_frequency = freq / 2; +} + +void __init plat_time_init(void) +{ + /* + * Initialization routine resembles generic MIPS plat_time_init() with lazy error + * handling. The final fallback is needed until all device trees use new clock syntax. + */ + struct device_node *np; + struct clk *clk; + + of_clk_init(NULL); + + mips_hpt_frequency = 0; + np = of_get_cpu_node(0, NULL); + if (!np) { + pr_err("Failed to get CPU node\n"); + } else { + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); + } else { + mips_hpt_frequency = clk_get_rate(clk) / 2; + clk_put(clk); + } + } + + if (!mips_hpt_frequency) + plat_time_init_fallback(); + + timer_probe(); +} + +void __init arch_init_irq(void) +{ + irqchip_init(); +} diff --git a/target/linux/realtek/files-6.12/drivers/clk/realtek/Kconfig b/target/linux/realtek/files-6.12/drivers/clk/realtek/Kconfig new file mode 100644 index 0000000000..f11c4d92a5 --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/clk/realtek/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-only + +menuconfig COMMON_CLK_REALTEK + bool "Support for Realtek's clock controllers" + depends on MACH_REALTEK_RTL + +if COMMON_CLK_REALTEK + +config COMMON_CLK_RTL83XX + bool "Clock driver for Realtek RTL83XX and RTL960X" + depends on MACH_REALTEK_RTL + select SRAM + help + This driver adds support for the Realtek RTL83xx series basic clocks. + This includes chips in the RTL838x series, such as RTL8380, RTL8381, + RTL832, chips from the RTL839x series, such as RTL8390, RT8391, + RTL8392, RTL8393 and RTL8396 as well as chips from the RTL960X + series, such as RTL9607C, RTL8198D. + +endif diff --git a/target/linux/realtek/files-6.12/drivers/clk/realtek/Makefile b/target/linux/realtek/files-6.12/drivers/clk/realtek/Makefile new file mode 100644 index 0000000000..7bc4ed910c --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/clk/realtek/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_COMMON_CLK_RTL83XX) += clk-rtl83xx.o clk-rtl838x-sram.o clk-rtl839x-sram.o diff --git a/target/linux/realtek/files-6.12/drivers/clk/realtek/clk-rtl838x-sram.S b/target/linux/realtek/files-6.12/drivers/clk/realtek/clk-rtl838x-sram.S new file mode 100644 index 0000000000..2431723133 --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/clk/realtek/clk-rtl838x-sram.S @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Realtek RTL838X SRAM clock setters + * Copyright (C) 2022 Markus Stockhausen + */ + +#include + +#include "clk-rtl83xx.h" + +#define rGLB $t0 +#define rCTR $t1 +#define rMSK $t2 +#define rSLP $t3 +#define rTMP $t4 + +.set noreorder + +.globl rtcl_838x_dram_start +rtcl_838x_dram_start: + +/* + * Functions start here and should avoid access to normal memory. REMARK! Do not forget about + * stack pointer and dirty caches that might interfere. + */ + +.globl rtcl_838x_dram_set_rate +.ent rtcl_838x_dram_set_rate +rtcl_838x_dram_set_rate: + +#ifdef CONFIG_RTL838X + + li rCTR, RTL_SW_CORE_BASE + addiu rGLB, rCTR, RTL838X_PLL_GLB_CTRL + ori rTMP, $0, CLK_CPU + beq $a0, rTMP, pre_cpu + ori rTMP, $0, CLK_MEM + beq $a0, rTMP, pre_mem + nop +pre_lxb: + ori rSLP, $0, RTL838X_GLB_CTRL_LXB_PLL_READY_MASK + addiu rCTR, rCTR, RTL838X_PLL_LXB_CTRL0 + b main_set + ori rMSK, $0, RTL838X_GLB_CTRL_EN_LXB_PLL_MASK +pre_mem: + /* simple 64K data cache flush to avoid unexpected memory access */ + li rMSK, RTL_SRAM_BASE + li rTMP, 2048 +pre_flush: + lw $0, 0(rMSK) + addiu rMSK, rMSK, 32 + addiu rTMP, rTMP, -1 + bne rTMP, $0, pre_flush + lw $0, -4(rMSK) + + ori rSLP, $0, RTL838X_GLB_CTRL_MEM_PLL_READY_MASK + addiu rCTR, rCTR, RTL838X_PLL_MEM_CTRL0 + b main_set + ori rMSK, $0, RTL838X_GLB_CTRL_EN_MEM_PLL_MASK +pre_cpu: + /* switch CPU to LXB clock */ + ori rMSK, $0, RTL838X_GLB_CTRL_CPU_PLL_SC_MUX_MASK + nor rMSK, rMSK, $0 + sync + lw rTMP, 0(rGLB) + and rTMP, rTMP, rMSK + sw rTMP, 0(rGLB) + sync + + ori rSLP, $0, RTL838X_GLB_CTRL_CPU_PLL_READY_MASK + addiu rCTR, rCTR, RTL838X_PLL_CPU_CTRL0 + ori rMSK, $0, RTL838X_GLB_CTRL_EN_CPU_PLL_MASK +main_set: + /* disable PLL */ + nor rMSK, rMSK, 0 + sync + lw rTMP, 0(rGLB) + sync + and rTMP, rTMP, rMSK + sync + sw rTMP, 0(rGLB) + + /* set new PLL values */ + sync + sw $a1, 0(rCTR) + sw $a2, 4(rCTR) + sync + + /* enable PLL (will reset it and clear ready status) */ + nor rMSK, rMSK, 0 + sync + lw rTMP, 0(rGLB) + sync + or rTMP, rTMP, rMSK + sync + sw rTMP, 0(rGLB) + + /* wait for PLL to become ready */ +wait_ready: + lw rTMP, 0(rGLB) + and rTMP, rTMP, rSLP + bne rTMP, $0, wait_ready + sync + + /* branch to post processing */ + ori rTMP, $0, CLK_CPU + beq $a0, rTMP, post_cpu + ori rTMP, $0, CLK_MEM + beq $a0, rTMP, post_mem + nop +post_lxb: + jr $ra + nop +post_mem: + jr $ra + nop +post_cpu: + /* stabilize clock to avoid crash, empirically determined */ + ori rSLP, $0, 0x3000 +wait_cpu: + bnez rSLP, wait_cpu + addiu rSLP, rSLP, -1 + + /* switch CPU to PLL clock */ + ori rMSK, $0, RTL838X_GLB_CTRL_CPU_PLL_SC_MUX_MASK + sync + lw rTMP, 0(rGLB) + or rTMP, rTMP, rMSK + sw rTMP, 0(rGLB) + sync + jr $ra + nop + +#else /* !CONFIG_RTL838X */ + + jr $ra + nop + +#endif + +.end rtcl_838x_dram_set_rate + +/* + * End marker. Do not delete. + */ + .word RTL_SRAM_MARKER +.globl rtcl_838x_dram_size +rtcl_838x_dram_size: + .word .-rtcl_838x_dram_start diff --git a/target/linux/realtek/files-6.12/drivers/clk/realtek/clk-rtl839x-sram.S b/target/linux/realtek/files-6.12/drivers/clk/realtek/clk-rtl839x-sram.S new file mode 100644 index 0000000000..fd8f8c4b1a --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/clk/realtek/clk-rtl839x-sram.S @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Realtek RTL839X SRAM clock setters + * Copyright (C) 2022 Markus Stockhausen + */ + +#include +#include + +#include "clk-rtl83xx.h" + +#define rGLB $t0 +#define rCTR $t1 +#define rMSK $t2 +#define rSLP1 $t3 +#define rSLP2 $t4 +#define rSLP3 $t5 +#define rTMP $t6 +#define rCP0 $t7 + +.set noreorder + +.globl rtcl_839x_dram_start +rtcl_839x_dram_start: + +/* + * Functions start here and should avoid access to normal memory. REMARK! Do not forget about + * stack pointer and dirty caches that might interfere. + */ + +.globl rtcl_839x_dram_set_rate +.ent rtcl_839x_dram_set_rate +rtcl_839x_dram_set_rate: + +#ifdef CONFIG_RTL839X + + /* disable MIPS 34K branch and return prediction */ + mfc0 rCP0, CP0_CONFIG, 7 + ori rTMP, rCP0, 0xc + mtc0 rTMP, CP0_CONFIG, 7 + + li rCTR, RTL_SW_CORE_BASE + addiu rGLB, rCTR, RTL839X_PLL_GLB_CTRL + ori rTMP, $0, CLK_CPU + beq $a0, rTMP, pre_cpu + ori rTMP, $0, CLK_MEM + beq $a0, rTMP, pre_mem + nop +pre_lxb: + li rSLP1, 0x400000 + li rSLP2, 0x400000 + li rSLP3, 0x400000 + addiu rCTR, rCTR, RTL839X_PLL_LXB_CTRL0 + b main_set + ori rMSK, $0, RTL839X_GLB_CTRL_LXB_CLKSEL_MASK +pre_mem: + /* try to avoid memory access with simple 64K data cache flush */ + li rMSK, RTL_SRAM_BASE + li rTMP, 2048 +pre_flush: + lw $0, 0(rMSK) + addiu rMSK, rMSK, 32 + addiu rTMP, rTMP, -1 + bne rTMP, $0, pre_flush + lw $0, -4(rMSK) + + li rSLP1, 0x10000 + li rSLP2, 0x10000 + li rSLP3, 0x10000 + addiu rCTR, rCTR, RTL839X_PLL_MEM_CTRL0 + b main_set + ori rMSK, $0, RTL839X_GLB_CTRL_MEM_CLKSEL_MASK +pre_cpu: + li rSLP1, 0x1000 + li rSLP2, 0x1000 + li rSLP3, 0x200 + addiu rCTR, rCTR, RTL839X_PLL_CPU_CTRL0 + ori rMSK, $0, RTL839X_GLB_CTRL_CPU_CLKSEL_MASK +main_set: + /* switch to fixed clock */ + sync + lw rTMP, 0(rGLB) + sync + or rTMP, rTMP, rMSK + sync + sw rTMP, 0(rGLB) + + /* wait until fixed clock in use */ + or rTMP, rSLP1, $0 +wait_fixclock: + bnez rTMP, wait_fixclock + addiu rTMP, rTMP, -1 + + /* set new PLL values */ + sync + sw $a1, 0(rCTR) + sw $a2, 4(rCTR) + sync + + /* wait for value takeover */ + or rTMP, rSLP2, $0 +wait_pll: + bnez rTMP, wait_pll + addiu rTMP, rTMP, -1 + + /* switch back to PLL clock*/ + nor rMSK, rMSK, $0 + sync + lw rTMP, 0(rGLB) + sync + and rTMP, rTMP, rMSK + sync + sw rTMP, 0(rGLB) + + /* wait until PLL clock in use */ + or rTMP, rSLP3, $0 +wait_pllclock: + bnez rTMP, wait_pllclock + addiu rTMP, rTMP, -1 + + /* restore branch prediction */ + mtc0 rCP0, CP0_CONFIG, 7 + jr $ra + nop + +#else /* !CONFIG_RTL839X */ + + jr $ra + nop + +#endif + +.end rtcl_839x_dram_set_rate + +/* + * End marker. Do not delete. + */ + .word RTL_SRAM_MARKER +.globl rtcl_839x_dram_size +rtcl_839x_dram_size: + .word .-rtcl_839x_dram_start diff --git a/target/linux/realtek/files-6.12/drivers/clk/realtek/clk-rtl83xx.c b/target/linux/realtek/files-6.12/drivers/clk/realtek/clk-rtl83xx.c new file mode 100644 index 0000000000..76ba942551 --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/clk/realtek/clk-rtl83xx.c @@ -0,0 +1,870 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Realtek RTL83XX clock driver + * Copyright (C) 2022 Markus Stockhausen + * + * This driver provides basic clock support for the central core clock unit (CCU) and its PLLs + * inside the RTL838X and RTL8389X SOC. Currently CPU, memory and LXB clock information can be + * accessed. To make use of the driver add the following devices and configurations at the + * appropriate locations to the DT. + * + * #include + * + * sram0: sram@9f000000 { + * compatible = "mmio-sram"; + * reg = <0x9f000000 0x18000>; + * #address-cells = <1>; + * #size-cells = <1>; + * ranges = <0 0x9f000000 0x18000>; + * }; + * + * osc: oscillator { + * compatible = "fixed-clock"; + * #clock-cells = <0>; + * clock-frequency = <25000000>; + * }; + * + * ccu: clock-controller { + * compatible = "realtek,rtl8380-clock"; + * #clock-cells = <1>; + * clocks = <&osc>; + * clock-names = "ref_clk"; + * }; + * + * + * The SRAM part is needed to be able to set clocks. When changing clocks the code must not run + * from DRAM. Otherwise system might freeze. Take care to adjust CCU compatibility, SRAM address + * and size to the target SOC device. Afterwards one can access/identify the clocks in the other + * DT devices with <&ccu CLK_CPU>, <&ccu CLK_MEM> or <&ccu CLK_LXB>. Additionally the clocks can + * be used inside the kernel with + * + * cpu_clk = clk_get(NULL, "cpu_clk"); + * mem_clk = clk_get(NULL, "mem_clk"); + * lxb_clk = clk_get(NULL, "lxb_clk"); + * + * This driver can be directly used by the DT based cpufreq driver (CONFIG_CPUFREQ_DT) if CPU + * references the right clock and sane operating points (OPP) are provided. E.g. + * + * cpu@0 { + * compatible = "mips,mips4KEc"; + * reg = <0>; + * clocks = <&ccu CLK_CPU>; + * operating-points-v2 = <&cpu_opp_table>; + * }; + * + * cpu_opp_table: opp-table-0 { + * compatible = "operating-points-v2"; + * opp-shared; + * opp00 { + * opp-hz = /bits/ 64 <425000000>; + * }; + * ... + * } + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-rtl83xx.h" + +#define read_sw(reg) ioread32(((void *)RTL_SW_CORE_BASE) + reg) +#define read_soc(reg) ioread32(((void *)RTL_SOC_BASE) + reg) + +#define write_sw(val, reg) iowrite32(val, ((void *)RTL_SW_CORE_BASE) + reg) +#define write_soc(val, reg) iowrite32(val, ((void *)RTL_SOC_BASE) + reg) + +/* + * some hardware specific definitions + */ + +#define SOC_RTL838X 0 +#define SOC_RTL839X 1 +#define SOC_RTL960X 2 +#define SOC_COUNT 3 + +#define MEM_DDR1 1 +#define MEM_DDR2 2 +#define MEM_DDR3 3 + +#define REG_CTRL0 0 +#define REG_CTRL1 1 +#define REG_COUNT 2 + +#define OSC_RATE 25000000 + +static const int rtcl_regs[SOC_COUNT][REG_COUNT][CLK_COUNT] = { + { + { RTL838X_PLL_CPU_CTRL0, RTL838X_PLL_MEM_CTRL0, RTL838X_PLL_LXB_CTRL0 }, + { RTL838X_PLL_CPU_CTRL1, RTL838X_PLL_MEM_CTRL1, RTL838X_PLL_LXB_CTRL1 }, + }, { + { RTL839X_PLL_CPU_CTRL0, RTL839X_PLL_MEM_CTRL0, RTL839X_PLL_LXB_CTRL0 }, + { RTL839X_PLL_CPU_CTRL1, RTL839X_PLL_MEM_CTRL1, RTL839X_PLL_LXB_CTRL1 }, + } +}; + +#define RTCL_REG_SET(_rate, _ctrl0, _ctrl1) \ + { \ + .rate = _rate, \ + .ctrl0 = _ctrl0, \ + .ctrl1 = _ctrl1, \ + } + +struct rtcl_reg_set { + unsigned int rate; + unsigned int ctrl0; + unsigned int ctrl1; +}; + +/* + * The following configuration tables are valid operation points for their + * corresponding PLLs. The magic numbers are precalculated mulitpliers and + * dividers to keep the driver simple. They also provide rates outside the + * allowed physical specifications. E.g. DDR3 memory has a lower limit of 303 + * MHz or the CPU might get unstable if set to anything above its startup + * frequency. Additionally the Realtek SOCs tend to expect CPU speed larger + * than MEM speed larger than LXB speed. The caller or DT configuration must + * take care that only valid operating points are selected. + */ + +static const struct rtcl_reg_set rtcl_838x_cpu_reg_set[] = { + RTCL_REG_SET(300000000, 0x045c8, 0x1414530e), + RTCL_REG_SET(325000000, 0x04648, 0x1414530e), + RTCL_REG_SET(350000000, 0x046c8, 0x1414530e), + RTCL_REG_SET(375000000, 0x04748, 0x1414530e), + RTCL_REG_SET(400000000, 0x045c8, 0x0c14530e), + RTCL_REG_SET(425000000, 0x04628, 0x0c14530e), + RTCL_REG_SET(450000000, 0x04688, 0x0c14530e), + RTCL_REG_SET(475000000, 0x046e8, 0x0c14530e), + RTCL_REG_SET(500000000, 0x04748, 0x0c14530e), + RTCL_REG_SET(525000000, 0x047a8, 0x0c14530e), + RTCL_REG_SET(550000000, 0x04808, 0x0c14530e), + RTCL_REG_SET(575000000, 0x04868, 0x0c14530e), + RTCL_REG_SET(600000000, 0x048c8, 0x0c14530e), + RTCL_REG_SET(625000000, 0x04928, 0x0c14530e) +}; + +static const struct rtcl_reg_set rtcl_838x_mem_reg_set[] = { + RTCL_REG_SET(200000000, 0x041bc, 0x14018C80), + RTCL_REG_SET(225000000, 0x0417c, 0x0c018C80), + RTCL_REG_SET(250000000, 0x041ac, 0x0c018C80), + RTCL_REG_SET(275000000, 0x0412c, 0x04018C80), + RTCL_REG_SET(300000000, 0x0414c, 0x04018c80), + RTCL_REG_SET(325000000, 0x0416c, 0x04018c80), + RTCL_REG_SET(350000000, 0x0418c, 0x04018c80), + RTCL_REG_SET(375000000, 0x041ac, 0x04018c80) +}; + +static const struct rtcl_reg_set rtcl_838x_lxb_reg_set[] = { + RTCL_REG_SET(100000000, 0x043c8, 0x001ad30e), + RTCL_REG_SET(125000000, 0x043c8, 0x001ad30e), + RTCL_REG_SET(150000000, 0x04508, 0x1c1ad30e), + RTCL_REG_SET(175000000, 0x04508, 0x1c1ad30e), + RTCL_REG_SET(200000000, 0x047c8, 0x001ad30e) +}; + +static const struct rtcl_reg_set rtcl_839x_cpu_reg_set[] = { + RTCL_REG_SET(400000000, 0x0414c, 0x00000005), + RTCL_REG_SET(425000000, 0x041ec, 0x00000006), + RTCL_REG_SET(450000000, 0x0417c, 0x00000005), + RTCL_REG_SET(475000000, 0x0422c, 0x00000006), + RTCL_REG_SET(500000000, 0x041ac, 0x00000005), + RTCL_REG_SET(525000000, 0x0426c, 0x00000006), + RTCL_REG_SET(550000000, 0x0412c, 0x00000004), + RTCL_REG_SET(575000000, 0x042ac, 0x00000006), + RTCL_REG_SET(600000000, 0x0414c, 0x00000004), + RTCL_REG_SET(625000000, 0x042ec, 0x00000006), + RTCL_REG_SET(650000000, 0x0416c, 0x00000004), + RTCL_REG_SET(675000000, 0x04324, 0x00000006), + RTCL_REG_SET(700000000, 0x0418c, 0x00000004), + RTCL_REG_SET(725000000, 0x0436c, 0x00000006), + RTCL_REG_SET(750000000, 0x0438c, 0x00000006), + RTCL_REG_SET(775000000, 0x043ac, 0x00000006), + RTCL_REG_SET(800000000, 0x043cc, 0x00000006), + RTCL_REG_SET(825000000, 0x043ec, 0x00000006), + RTCL_REG_SET(850000000, 0x0440c, 0x00000006) +}; + +static const struct rtcl_reg_set rtcl_839x_mem_reg_set[] = { + RTCL_REG_SET(100000000, 0x041cc, 0x00000000), + RTCL_REG_SET(125000000, 0x041ac, 0x00000007), + RTCL_REG_SET(150000000, 0x0414c, 0x00000006), + RTCL_REG_SET(175000000, 0x0418c, 0x00000006), + RTCL_REG_SET(200000000, 0x041cc, 0x00000006), + RTCL_REG_SET(225000000, 0x0417c, 0x00000005), + RTCL_REG_SET(250000000, 0x041ac, 0x00000005), + RTCL_REG_SET(275000000, 0x0412c, 0x00000004), + RTCL_REG_SET(300000000, 0x0414c, 0x00000004), + RTCL_REG_SET(325000000, 0x0416c, 0x00000004), + RTCL_REG_SET(350000000, 0x0418c, 0x00000004), + RTCL_REG_SET(375000000, 0x041ac, 0x00000004), + RTCL_REG_SET(400000000, 0x041cc, 0x00000004) +}; + +static const struct rtcl_reg_set rtcl_839x_lxb_reg_set[] = { + RTCL_REG_SET(50000000, 0x1414c, 0x00000003), + RTCL_REG_SET(100000000, 0x0814c, 0x00000003), + RTCL_REG_SET(150000000, 0x0414c, 0x00000003), + RTCL_REG_SET(200000000, 0x0414c, 0x00000007) +}; + +struct rtcl_rtab_set { + int count; + const struct rtcl_reg_set *rset; +}; + +#define RTCL_RTAB_SET(_rset) \ + { \ + .count = ARRAY_SIZE(_rset), \ + .rset = _rset, \ + } + +static const struct rtcl_rtab_set rtcl_rtab_set[SOC_COUNT][CLK_COUNT] = { + { + RTCL_RTAB_SET(rtcl_838x_cpu_reg_set), + RTCL_RTAB_SET(rtcl_838x_mem_reg_set), + RTCL_RTAB_SET(rtcl_838x_lxb_reg_set) + }, { + RTCL_RTAB_SET(rtcl_839x_cpu_reg_set), + RTCL_RTAB_SET(rtcl_839x_mem_reg_set), + RTCL_RTAB_SET(rtcl_839x_lxb_reg_set) + } +}; + +#define RTCL_ROUND_SET(_min, _max, _step) \ + { \ + .min = _min, \ + .max = _max, \ + .step = _step, \ + } + +struct rtcl_round_set { + unsigned long min; + unsigned long max; + unsigned long step; +}; + +static const struct rtcl_round_set rtcl_round_set[SOC_COUNT][CLK_COUNT] = { + { + RTCL_ROUND_SET(300000000, 625000000, 25000000), + RTCL_ROUND_SET(200000000, 375000000, 25000000), + RTCL_ROUND_SET(100000000, 200000000, 25000000) + }, { + RTCL_ROUND_SET(400000000, 850000000, 25000000), + RTCL_ROUND_SET(100000000, 400000000, 25000000), + RTCL_ROUND_SET(50000000, 200000000, 50000000) + }, { + RTCL_ROUND_SET(500000000, 1200000000, 25000000) + } +}; + +static const int rtcl_divn3[] = { 2, 3, 4, 6 }; +static const int rtcl_xdiv[] = { 2, 4, 2 }; + +/* + * module data structures + */ + +#define RTCL_CLK_INFO(_idx, _name, _pname, _dname) \ + { \ + .idx = _idx, \ + .name = _name, \ + .parent_name = _pname, \ + .display_name = _dname, \ + } + +struct rtcl_clk_info { + unsigned int idx; + const char *name; + const char *parent_name; + const char *display_name; +}; + +struct rtcl_clk { + struct clk_hw hw; + unsigned int idx; + unsigned long min; + unsigned long max; + unsigned long rate; + unsigned long startup; +}; + +static const struct rtcl_clk_info rtcl_clk_info[CLK_COUNT] = { + RTCL_CLK_INFO(CLK_CPU, "cpu_clk", "ref_clk", "CPU"), + RTCL_CLK_INFO(CLK_MEM, "mem_clk", "ref_clk", "MEM"), + RTCL_CLK_INFO(CLK_LXB, "lxb_clk", "ref_clk", "LXB") +}; + +struct rtcl_dram { + int type; + int buswidth; +}; + +struct rtcl_sram { + int *pmark; + unsigned long vbase; +}; + +struct rtcl_ccu { + spinlock_t lock; + unsigned int soc; + struct rtcl_sram sram; + struct rtcl_dram dram; + struct device_node *np; + struct platform_device *pdev; + struct rtcl_clk clks[CLK_COUNT]; +}; + +struct rtcl_ccu *rtcl_ccu; + +#define rtcl_hw_to_clk(_hw) container_of(_hw, struct rtcl_clk, hw) + +/* + * SRAM relocatable assembler functions. The dram() parts point to normal kernel + * memory while the sram() parts are the same functions but relocated to SRAM. + */ + +extern void rtcl_838x_dram_start(void); +extern int rtcl_838x_dram_size; + +extern void (*rtcl_838x_dram_set_rate)(int clk_idx, int ctrl0, int ctrl1); +static void (*rtcl_838x_sram_set_rate)(int clk_idx, int ctrl0, int ctrl1); + +extern void rtcl_839x_dram_start(void); +extern int rtcl_839x_dram_size; + +extern void (*rtcl_839x_dram_set_rate)(int clk_idx, int ctrl0, int ctrl1); +static void (*rtcl_839x_sram_set_rate)(int clk_idx, int ctrl0, int ctrl1); + +/* + * clock setter/getter functions + */ + +static unsigned long rtcl_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct rtcl_clk *clk = rtcl_hw_to_clk(hw); + unsigned int ctrl0, ctrl1, div1, div2, cmu_ncode_in; + unsigned int cmu_sel_prediv, cmu_sel_div4, cmu_divn2, cmu_divn2_selb, cmu_divn3_sel; + + if ((clk->idx >= CLK_COUNT) || (!rtcl_ccu) || (rtcl_ccu->soc >= SOC_COUNT)) + return 0; + + ctrl0 = read_sw(rtcl_regs[rtcl_ccu->soc][REG_CTRL0][clk->idx]); + ctrl1 = read_sw(rtcl_regs[rtcl_ccu->soc][REG_CTRL1][clk->idx]); + + cmu_sel_prediv = 1 << RTL_PLL_CTRL0_CMU_SEL_PREDIV(ctrl0); + cmu_sel_div4 = RTL_PLL_CTRL0_CMU_SEL_DIV4(ctrl0) ? 4 : 1; + cmu_ncode_in = RTL_PLL_CTRL0_CMU_NCODE_IN(ctrl0) + 4; + cmu_divn2 = RTL_PLL_CTRL0_CMU_DIVN2(ctrl0) + 4; + + switch (rtcl_ccu->soc) { + case SOC_RTL838X: + if ((ctrl0 == 0) && (ctrl1 == 0) && (clk->idx == CLK_LXB)) + return 200000000; + + cmu_divn2_selb = RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(ctrl1); + cmu_divn3_sel = rtcl_divn3[RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(ctrl1)]; + break; + case SOC_RTL839X: + cmu_divn2_selb = RTL839X_PLL_CTRL1_CMU_DIVN2_SELB(ctrl1); + cmu_divn3_sel = rtcl_divn3[RTL839X_PLL_CTRL1_CMU_DIVN3_SEL(ctrl1)]; + break; + } + div1 = cmu_divn2_selb ? cmu_divn3_sel : cmu_divn2; + div2 = rtcl_xdiv[clk->idx]; + + return (((parent_rate / 16) * cmu_ncode_in) / (div1 * div2)) * + cmu_sel_prediv * cmu_sel_div4 * 16; +} + +static int rtcl_838x_set_rate(int clk_idx, const struct rtcl_reg_set *reg) +{ + unsigned long irqflags; +/* + * Runtime of this function (including locking) + * CPU: up to 14000 cycles / up to 56 us at 250 MHz (half default speed) + */ + spin_lock_irqsave(&rtcl_ccu->lock, irqflags); + rtcl_838x_sram_set_rate(clk_idx, reg->ctrl0, reg->ctrl1); + spin_unlock_irqrestore(&rtcl_ccu->lock, irqflags); + + return 0; +} + +static int rtcl_839x_set_rate(int clk_idx, const struct rtcl_reg_set *reg) +{ + unsigned long vpflags; + unsigned long irqflags; +/* + * Runtime of this function (including locking) + * CPU: up to 31000 cycles / up to 89 us at 350 MHz (half default speed) + */ + spin_lock_irqsave(&rtcl_ccu->lock, irqflags); + vpflags = dvpe(); + rtcl_839x_sram_set_rate(clk_idx, reg->ctrl0, reg->ctrl1); + evpe(vpflags); + spin_unlock_irqrestore(&rtcl_ccu->lock, irqflags); + + return 0; +} + +static int rtcl_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) +{ + int tab_idx; + struct rtcl_clk *clk = rtcl_hw_to_clk(hw); + const struct rtcl_rtab_set *rtab = &rtcl_rtab_set[rtcl_ccu->soc][clk->idx]; + const struct rtcl_round_set *round = &rtcl_round_set[rtcl_ccu->soc][clk->idx]; + + if ((parent_rate != OSC_RATE) || (!rtcl_ccu->sram.vbase)) + return -EINVAL; +/* + * Currently we do not know if SRAM is stable on these devices. Maybe someone + * changes memory in this region and does not care about proper allocation. So + * check if something might go wrong. + */ + if (unlikely(*rtcl_ccu->sram.pmark != RTL_SRAM_MARKER)) { + dev_err(&rtcl_ccu->pdev->dev, "SRAM code lost\n"); + return -EINVAL; + } + + tab_idx = (rate - round->min) / round->step; + if ((tab_idx < 0) || (tab_idx >= rtab->count) || (rtab->rset[tab_idx].rate != rate)) + return -EINVAL; + + rtcl_ccu->clks[clk->idx].rate = rate; + + switch (rtcl_ccu->soc) { + case SOC_RTL838X: + return rtcl_838x_set_rate(clk->idx, &rtab->rset[tab_idx]); + case SOC_RTL839X: + return rtcl_839x_set_rate(clk->idx, &rtab->rset[tab_idx]); + } + + return -ENXIO; +} + +static long rtcl_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) +{ + struct rtcl_clk *clk = rtcl_hw_to_clk(hw); + unsigned long rrate = max(clk->min, min(clk->max, rate)); + const struct rtcl_round_set *round = &rtcl_round_set[rtcl_ccu->soc][clk->idx]; + + rrate = ((rrate + (round->step >> 1)) / round->step) * round->step; + rrate -= (rrate > clk->max) ? round->step : 0; + rrate += (rrate < clk->min) ? round->step : 0; + + return rrate; +} + +static unsigned long rtcl_960x_cpu_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + u32 ocp_pll_ctrl0, ocp_pll_ctrl3, cmu_gcr; + u32 cpu_freq_sel0, en_div2_cpu0, cmu_mode, freq_div; + unsigned long rate; + + ocp_pll_ctrl0 = read_soc(RTL960X_OCP_PLL_CTRL0); + ocp_pll_ctrl3 = read_soc(RTL960X_OCP_PLL_CTRL3); + cmu_gcr = read_soc(RTL960X_CMU_GCR); + + cpu_freq_sel0 = RTL960X_OCP_CTRL0_CPU_FREQ_SEL0(ocp_pll_ctrl0); + en_div2_cpu0 = RTL960X_OCP_CTRL3_EN_DIV2_CPU0(ocp_pll_ctrl3); + cmu_mode = RTL960X_CMU_GCR_CMU_MODE(cmu_gcr); + freq_div = RTL960X_CMU_GCR_FREQ_DIV(cmu_gcr); + + rate = ((cpu_freq_sel0 + 2) * 2 * parent_rate) >> en_div2_cpu0; + if (cmu_mode != 0) + rate >>= freq_div; + + return rate; +} + +static unsigned long rtcl_960x_lxb_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + u32 phy_rg5x_pll, lx_freq_sel; + unsigned long rate; + + phy_rg5x_pll = read_sw(RTL960X_PHY_RG5X_PLL); + lx_freq_sel = RTL960X_LX_FREQ_SEL(phy_rg5x_pll); + + rate = (40 * parent_rate) / (lx_freq_sel + 5); + + return rate; +} + +static unsigned long rtcl_960x_mem_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + u32 mem_pll_ctrl2, mem_pll_ctrl3, mem_pll_ctrl5; + u32 n_code, pdiv, f_code; + unsigned long rate; + u64 t; + + mem_pll_ctrl2 = read_soc(RTL960X_MEM_PLL_CTRL2); + mem_pll_ctrl3 = read_soc(RTL960X_MEM_PLL_CTRL3); + mem_pll_ctrl5 = read_soc(RTL960X_MEM_PLL_CTRL5); + + pdiv = RTL960X_MEM_CTRL2_PDIV(mem_pll_ctrl2); + n_code = RTL960X_MEM_CTRL3_N_CODE(mem_pll_ctrl3); + f_code = RTL960X_MEM_CTRL5_F_CODE(mem_pll_ctrl5); + + rate = (parent_rate * (n_code + 3)) / (2 * (1 << pdiv)); + t = parent_rate; + t *= f_code; + t /= 16384; + rate += t; + + return rate; +} + +static unsigned long rtcl_960x_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct rtcl_clk *clk = rtcl_hw_to_clk(hw); + unsigned long rate; + + if ((clk->idx >= CLK_COUNT) || (!rtcl_ccu) || (rtcl_ccu->soc >= SOC_COUNT)) + return 0; + + switch (clk->idx) { + case CLK_CPU: + rate = rtcl_960x_cpu_recalc_rate(hw, parent_rate); + break; + case CLK_MEM: + rate = rtcl_960x_mem_recalc_rate(hw, parent_rate); + break; + case CLK_LXB: + rate = rtcl_960x_lxb_recalc_rate(hw, parent_rate); + break; + } + + return rate; +} + +/* + * Initialization functions to register the CCU and its clocks + */ + +#define RTCL_SRAM_FUNC(SOC, PBASE, FN) ({ \ + rtcl_##SOC##_sram_##FN = ((void *)&rtcl_##SOC##_dram_##FN - \ + (void *)&rtcl_##SOC##_dram_start) + \ + (void *)PBASE; }) + +static const struct clk_ops rtcl_960x_clk_ops = { + .recalc_rate = rtcl_960x_recalc_rate, +}; + +static const struct clk_ops rtcl_clk_ops = { + .set_rate = rtcl_set_rate, + .round_rate = rtcl_round_rate, + .recalc_rate = rtcl_recalc_rate, +}; + +static int rtcl_ccu_create(struct device_node *np) +{ + int soc; + + if (of_device_is_compatible(np, "realtek,rtl8380-clock")) + soc = SOC_RTL838X; + else if (of_device_is_compatible(np, "realtek,rtl8390-clock")) + soc = SOC_RTL839X; + else if (of_device_is_compatible(np, "realtek,rtl9607-clock")) + soc = SOC_RTL960X; + else + return -ENXIO; + + rtcl_ccu = kzalloc(sizeof(*rtcl_ccu), GFP_KERNEL); + if (!rtcl_ccu) + return -ENOMEM; + + rtcl_ccu->np = np; + rtcl_ccu->soc = soc; + rtcl_ccu->dram.type = RTL_MC_MCR_DRAMTYPE(read_soc(RTL_MC_MCR)); + rtcl_ccu->dram.buswidth = RTL_MC_DCR_BUSWIDTH(read_soc(RTL_MC_DCR)); + spin_lock_init(&rtcl_ccu->lock); + + return 0; +} + +static int rtcl_register_clkhw(int clk_idx) +{ + int ret; + struct clk *clk; + struct clk_init_data hw_init = { }; + struct rtcl_clk *rclk = &rtcl_ccu->clks[clk_idx]; + struct clk_parent_data parent_data = { .fw_name = rtcl_clk_info[clk_idx].parent_name }; + + rclk->idx = clk_idx; + rclk->hw.init = &hw_init; + + hw_init.num_parents = 1; + hw_init.parent_data = &parent_data; + hw_init.name = rtcl_clk_info[clk_idx].name; + + if (rtcl_ccu->soc == SOC_RTL960X) + hw_init.ops = &rtcl_960x_clk_ops; + else + hw_init.ops = &rtcl_clk_ops; + + ret = of_clk_hw_register(rtcl_ccu->np, &rclk->hw); + if (ret) + return ret; + + clk_hw_register_clkdev(&rclk->hw, rtcl_clk_info[clk_idx].name, NULL); + + clk = clk_get(NULL, rtcl_clk_info[clk_idx].name); + rclk->startup = clk_get_rate(clk); + clk_put(clk); + + switch (clk_idx) { + case CLK_CPU: + rclk->min = rtcl_round_set[rtcl_ccu->soc][clk_idx].min; + rclk->max = rtcl_round_set[rtcl_ccu->soc][clk_idx].max; + break; + default: +/* + * TODO: This driver supports PLL reclocking and nothing else. Additional + * required steps for non CPU PLLs are missing. E.g. if we want to change memory + * clocks the right way we must adapt a lot of other settings. This includes + * MCR and DTRx timing registers (0xb80001000, 0xb8001008, ...) and a DLL reset + * so that hardware operates in the allowed limits. This is far too complex + * without official support. Avoid this for now. + */ + rclk->min = rclk->max = rclk->startup; + break; + } + + return 0; +} + +static struct clk_hw *rtcl_get_clkhw(struct of_phandle_args *clkspec, void *prv) +{ + unsigned int idx = clkspec->args[0]; + + if (idx >= CLK_COUNT) { + pr_err("%s: Invalid index %u\n", __func__, idx); + return ERR_PTR(-EINVAL); + } + + return &rtcl_ccu->clks[idx].hw; +} + +static int rtcl_ccu_register_clocks(void) +{ + int clk_idx, ret; + + for (clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) { + ret = rtcl_register_clkhw(clk_idx); + if (ret) { + pr_err("%s: Couldn't register %s clock\n", + __func__, rtcl_clk_info[clk_idx].display_name); + goto err_hw_unregister; + } + } + + ret = of_clk_add_hw_provider(rtcl_ccu->np, rtcl_get_clkhw, rtcl_ccu); + if (ret) { + pr_err("%s: Couldn't register clock provider of %s\n", + __func__, of_node_full_name(rtcl_ccu->np)); + goto err_hw_unregister; + } + + return 0; + +err_hw_unregister: + for (--clk_idx; clk_idx >= 0; --clk_idx) + clk_hw_unregister(&rtcl_ccu->clks[clk_idx].hw); + + return ret; +} + +static int rtcl_init_sram(void) +{ + struct gen_pool *sram_pool; + phys_addr_t sram_pbase; + unsigned long sram_vbase; + struct device_node *node; + struct platform_device *pdev = NULL; + void *dram_start; + int dram_size; + const char *wrn = ", rate setting disabled.\n"; + + switch (rtcl_ccu->soc) { + case SOC_RTL838X: + dram_start = &rtcl_838x_dram_start; + dram_size = rtcl_838x_dram_size; + break; + case SOC_RTL839X: + dram_start = &rtcl_839x_dram_start; + dram_size = rtcl_839x_dram_size; + break; + default: + return -ENXIO; + } + + for_each_compatible_node(node, NULL, "mmio-sram") { + pdev = of_find_device_by_node(node); + if (pdev) { + of_node_put(node); + break; + } + } + + if (!pdev) { + dev_warn(&rtcl_ccu->pdev->dev, "no SRAM device found%s", wrn); + return -ENXIO; + } + + sram_pool = gen_pool_get(&pdev->dev, NULL); + if (!sram_pool) { + dev_warn(&rtcl_ccu->pdev->dev, "SRAM pool unavailable%s", wrn); + goto err_put_device; + } + + sram_vbase = gen_pool_alloc(sram_pool, dram_size); + if (!sram_vbase) { + dev_warn(&rtcl_ccu->pdev->dev, "can not allocate SRAM%s", wrn); + goto err_put_device; + } + + sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_vbase); + memcpy((void *)sram_pbase, dram_start, dram_size); + flush_icache_range((unsigned long)sram_pbase, (unsigned long)(sram_pbase + dram_size)); + + switch (rtcl_ccu->soc) { + case SOC_RTL838X: + RTCL_SRAM_FUNC(838x, sram_pbase, set_rate); + break; + case SOC_RTL839X: + RTCL_SRAM_FUNC(839x, sram_pbase, set_rate); + break; + } + + rtcl_ccu->sram.pmark = (int *)((void *)sram_pbase + (dram_size - 4)); + rtcl_ccu->sram.vbase = sram_vbase; + + put_device(&pdev->dev); + return 0; + +err_put_device: + put_device(&pdev->dev); + + return -ENXIO; +} + +static void rtcl_ccu_log_early(void) +{ + char meminfo[80], clkinfo[255], msg[255] = "rtl83xx-clk: initialized"; + + sprintf(meminfo, " (%d Bit DDR%d)", rtcl_ccu->dram.buswidth, rtcl_ccu->dram.type); + for (int clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) { + sprintf(clkinfo, ", %s %lu MHz", rtcl_clk_info[clk_idx].display_name, + rtcl_ccu->clks[clk_idx].startup / 1000000); + if (clk_idx == CLK_MEM) + strcat(clkinfo, meminfo); + strcat(msg, clkinfo); + } + pr_info("%s\n", msg); +} + +static void rtcl_ccu_log_late(void) +{ + struct rtcl_clk *rclk; + bool overclock = false; + char clkinfo[80], msg[255] = "rate setting enabled"; + + for (int clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) { + rclk = &rtcl_ccu->clks[clk_idx]; + overclock |= rclk->max > rclk->startup; + sprintf(clkinfo, ", %s %lu-%lu MHz", rtcl_clk_info[clk_idx].display_name, + rclk->min / 1000000, rclk->max / 1000000); + strcat(msg, clkinfo); + } + if (overclock) + strcat(msg, ", OVERCLOCK AT OWN RISK"); + + dev_info(&rtcl_ccu->pdev->dev, "%s\n", msg); +} + +/* + * Early registration: This module provides core startup clocks that are needed + * for generic SOC init and for further builtin devices (e.g. UART). Register + * asap via clock framework. + */ + +static void __init rtcl_probe_early(struct device_node *np) +{ + if (rtcl_ccu_create(np)) + return; + + if (rtcl_ccu_register_clocks()) + kfree(rtcl_ccu); + else + rtcl_ccu_log_early(); +} + +CLK_OF_DECLARE_DRIVER(rtl838x_clk, "realtek,rtl8380-clock", rtcl_probe_early); +CLK_OF_DECLARE_DRIVER(rtl839x_clk, "realtek,rtl8390-clock", rtcl_probe_early); +CLK_OF_DECLARE_DRIVER(rtl960x_clk, "realtek,rtl9607-clock", rtcl_probe_early); + +/* + * Late registration: Finally register as normal platform driver. At this point + * we can make use of other modules like SRAM. + */ + +static const struct of_device_id rtcl_dt_ids[] = { + { .compatible = "realtek,rtl8380-clock" }, + { .compatible = "realtek,rtl8390-clock" }, + {} +}; + +static int rtcl_probe_late(struct platform_device *pdev) +{ + int ret; + + if (!rtcl_ccu) { + dev_err(&pdev->dev, "early initialization not run"); + return -ENXIO; + } + rtcl_ccu->pdev = pdev; + ret = rtcl_init_sram(); + if (ret) + return ret; + + rtcl_ccu_log_late(); + + return 0; +} + +static struct platform_driver rtcl_platform_driver = { + .driver = { + .name = "rtl83xx-clk", + .of_match_table = rtcl_dt_ids, + }, + .probe = rtcl_probe_late, +}; + +static int __init rtcl_init_subsys(void) +{ + return platform_driver_register(&rtcl_platform_driver); +} + +/* + * The driver does not know when SRAM module has finally loaded. With an + * arch_initcall() we might overtake SRAM initialization. Be polite and give the + * system a little more time. + */ + +subsys_initcall(rtcl_init_subsys); diff --git a/target/linux/realtek/files-6.12/drivers/clk/realtek/clk-rtl83xx.h b/target/linux/realtek/files-6.12/drivers/clk/realtek/clk-rtl83xx.h new file mode 100644 index 0000000000..37318b071f --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/clk/realtek/clk-rtl83xx.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Realtek RTL83XX clock headers + * Copyright (C) 2022 Markus Stockhausen + */ + +/* + * Switch registers (e.g. PLL) + */ + +#define RTL_SW_CORE_BASE (0xbb000000) + +#define RTL838X_PLL_GLB_CTRL (0x0fc0) +#define RTL838X_PLL_CPU_CTRL0 (0x0fc4) +#define RTL838X_PLL_CPU_CTRL1 (0x0fc8) +#define RTL838X_PLL_LXB_CTRL0 (0x0fd0) +#define RTL838X_PLL_LXB_CTRL1 (0x0fd4) +#define RTL838X_PLL_MEM_CTRL0 (0x0fdc) +#define RTL838X_PLL_MEM_CTRL1 (0x0fe0) + +#define RTL839X_PLL_GLB_CTRL (0x0024) +#define RTL839X_PLL_CPU_CTRL0 (0x0028) +#define RTL839X_PLL_CPU_CTRL1 (0x002c) +#define RTL839X_PLL_LXB_CTRL0 (0x0038) +#define RTL839X_PLL_LXB_CTRL1 (0x003c) +#define RTL839X_PLL_MEM_CTRL0 (0x0048) +#define RTL839X_PLL_MEM_CTRL1 (0x004c) + +#define RTL960X_PHY_RG5X_PLL (0x1f054) + +#define RTL_PLL_CTRL0_CMU_SEL_PREDIV(v) (((v) >> 0) & 0x3) +#define RTL_PLL_CTRL0_CMU_SEL_DIV4(v) (((v) >> 2) & 0x1) +#define RTL_PLL_CTRL0_CMU_NCODE_IN(v) (((v) >> 4) & 0xff) +#define RTL_PLL_CTRL0_CMU_DIVN2(v) (((v) >> 12) & 0xff) + +#define RTL838X_GLB_CTRL_EN_CPU_PLL_MASK (1 << 0) +#define RTL838X_GLB_CTRL_EN_LXB_PLL_MASK (1 << 1) +#define RTL838X_GLB_CTRL_EN_MEM_PLL_MASK (1 << 2) +#define RTL838X_GLB_CTRL_CPU_PLL_READY_MASK (1 << 8) +#define RTL838X_GLB_CTRL_LXB_PLL_READY_MASK (1 << 9) +#define RTL838X_GLB_CTRL_MEM_PLL_READY_MASK (1 << 10) +#define RTL838X_GLB_CTRL_CPU_PLL_SC_MUX_MASK (1 << 12) + +#define RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(v) (((v) >> 26) & 0x1) +#define RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(v) (((v) >> 27) & 0x3) + +#define RTL839X_GLB_CTRL_CPU_CLKSEL_MASK (1 << 11) +#define RTL839X_GLB_CTRL_MEM_CLKSEL_MASK (1 << 12) +#define RTL839X_GLB_CTRL_LXB_CLKSEL_MASK (1 << 13) + +#define RTL839X_PLL_CTRL1_CMU_DIVN2_SELB(v) (((v) >> 2) & 0x1) +#define RTL839X_PLL_CTRL1_CMU_DIVN3_SEL(v) (((v) >> 0) & 0x3) + +#define RTL960X_LX_FREQ_SEL(v) ((v) & 0xf) + +/* + * Core registers (e.g. memory controller) + */ + +#define RTL_SOC_BASE (0xB8000000) + +#define RTL_MC_MCR (0x1000) +#define RTL_MC_DCR (0x1004) +#define RTL_MC_DTR0 (0x1008) +#define RTL_MC_DTR1 (0x100c) +#define RTL_MC_DTR2 (0x1010) +#define RTL_MC_DMCR (0x101c) +#define RTL_MC_DACCR (0x1500) +#define RTL_MC_DCDR (0x1060) + +#define RTL_MC_MCR_DRAMTYPE(v) ((((v) >> 28) & 0xf) + 1) +#define RTL_MC_DCR_BUSWIDTH(v) (8 << (((v) >> 24) & 0xf)) + +#define RTL960X_OCP_PLL_CTRL0 (0x0200) +#define RTL960X_OCP_PLL_CTRL3 (0x020c) +#define RTL960X_CMU_GCR (0x0380) +#define RTL960X_MEM_PLL_CTRL2 (0x023c) +#define RTL960X_MEM_PLL_CTRL3 (0x0240) +#define RTL960X_MEM_PLL_CTRL5 (0x0248) + +#define RTL960X_OCP_CTRL0_CPU_FREQ_SEL0(v) (((v) >> 16) & 0x3f) + +#define RTL960X_OCP_CTRL3_EN_DIV2_CPU0(v) (((v) >> 18) & 0x1) + +#define RTL960X_CMU_GCR_CMU_MODE(v) ((v) & 0x3) +#define RTL960X_CMU_GCR_FREQ_DIV(v) (((v) >> 4) & 0x7) + +#define RTL960X_MEM_CTRL2_PDIV(v) (((v) >> 14) & 0x3) +#define RTL960X_MEM_CTRL3_N_CODE(v) (((v) >> 24) & 0xff) +#define RTL960X_MEM_CTRL5_F_CODE(v) ((v) & 0x1fff) + +/* + * Other stuff + */ + +#define RTL_SRAM_MARKER (0x5eaf00d5) +#define RTL_SRAM_BASE (0x9f000000) diff --git a/target/linux/realtek/files-6.12/drivers/i2c/busses/i2c-gpio-shared.c b/target/linux/realtek/files-6.12/drivers/i2c/busses/i2c-gpio-shared.c new file mode 100644 index 0000000000..37930af726 --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/i2c/busses/i2c-gpio-shared.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Bitbanging driver for multiple I2C busses with shared SCL pin using the GPIO API + * Copyright (c) 2025 Markus Stockhausen + */ + +#include +#include +#include +#include +#include + +#define GPIO_SHARED_MAX_BUS 4 + +struct gpio_shared_ctx; + +struct gpio_shared_bus { + int num; + struct gpio_desc *sda; + struct i2c_adapter adap; + struct i2c_algo_bit_data bit_data; + struct gpio_shared_ctx *ctx; +}; + +struct gpio_shared_ctx { + struct device *dev; + struct gpio_desc *scl; + struct mutex lock; + struct gpio_shared_bus bus[GPIO_SHARED_MAX_BUS]; +}; + +static void gpio_shared_setsda(void *data, int state) +{ + struct gpio_shared_bus *bus = data; + + gpiod_set_value_cansleep(bus->sda, state); +} + +static void gpio_shared_setscl(void *data, int state) +{ + struct gpio_shared_bus *bus = data; + struct gpio_shared_ctx *ctx = bus->ctx; + + gpiod_set_value_cansleep(ctx->scl, state); +} + +static int gpio_shared_getsda(void *data) +{ + struct gpio_shared_bus *bus = data; + + return gpiod_get_value_cansleep(bus->sda); +} + +static int gpio_shared_getscl(void *data) +{ + struct gpio_shared_bus *bus = data; + struct gpio_shared_ctx *ctx = bus->ctx; + + return gpiod_get_value_cansleep(ctx->scl); +} + +static int gpio_shared_pre_xfer(struct i2c_adapter *adap) +{ + struct gpio_shared_bus *bus = container_of(adap, typeof(*bus), adap); + struct gpio_shared_ctx *ctx = bus->ctx; + + mutex_lock(&ctx->lock); + dev_dbg(ctx->dev, "lock before transfer to bus %d\n", bus->num); + + return 0; +} + +static void gpio_shared_post_xfer(struct i2c_adapter *adap) +{ + struct gpio_shared_bus *bus = container_of(adap, typeof(*bus), adap); + struct gpio_shared_ctx *ctx = bus->ctx; + + dev_dbg(ctx->dev, "unlock after transfer to bus %d\n", bus->num); + mutex_unlock(&ctx->lock); +} + +static int gpio_shared_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct fwnode_handle *child; + struct gpio_shared_ctx *ctx; + int msecs, ret, bus_num = -1; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->dev = dev; + mutex_init(&ctx->lock); + + ctx->scl = devm_gpiod_get(dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN); + if (IS_ERR(ctx->scl)) + return dev_err_probe(dev, PTR_ERR(ctx->scl), "shared SCL node not found\n"); + + if (device_get_child_node_count(dev) > GPIO_SHARED_MAX_BUS) + return dev_err_probe(dev, -EINVAL, "Too many channels\n"); + + device_for_each_child_node(dev, child) { + struct gpio_shared_bus *bus = &ctx->bus[++bus_num]; + struct i2c_adapter *adap = &bus->adap; + struct i2c_algo_bit_data *bit_data = &bus->bit_data; + + bus->sda = devm_fwnode_gpiod_get(dev, child, "sda", GPIOD_OUT_HIGH_OPEN_DRAIN, + fwnode_get_name(child)); + if (IS_ERR(bus->sda)) { + fwnode_handle_put(child); + dev_err(dev, "SDA node for bus %d not found\n", bus_num); + continue; + } + + bus->num = bus_num; + bus->ctx = ctx; + + bit_data->data = bus; + bit_data->setsda = gpio_shared_setsda; + bit_data->setscl = gpio_shared_setscl; + bit_data->pre_xfer = gpio_shared_pre_xfer; + bit_data->post_xfer = gpio_shared_post_xfer; + + if (fwnode_property_read_u32(child, "i2c-gpio,delay-us", &bit_data->udelay)) + bit_data->udelay = 5; + if (!fwnode_property_read_bool(child, "i2c-gpio,sda-output-only")) + bit_data->getsda = gpio_shared_getsda; + if (!device_property_read_bool(dev, "i2c-gpio,scl-output-only")) + bit_data->getscl = gpio_shared_getscl; + + if (!device_property_read_u32(dev, "i2c-gpio,timeout-ms", &msecs)) + bit_data->timeout = msecs_to_jiffies(msecs); + else + bit_data->timeout = HZ / 10; /* 100ms */ + + if (gpiod_cansleep(bus->sda) || gpiod_cansleep(ctx->scl)) + dev_warn(dev, "Slow GPIO pins might wreak havoc into I2C/SMBus bus timing"); + else + bit_data->can_do_atomic = true; + + adap->owner = THIS_MODULE; + strscpy(adap->name, KBUILD_MODNAME, sizeof(adap->name)); + adap->dev.parent = dev; + device_set_node(&adap->dev, child); + adap->algo_data = &bus->bit_data; + adap->class = I2C_CLASS_HWMON; + + ret = i2c_bit_add_bus(adap); + if (ret) + return ret; + + dev_info(dev, "shared I2C bus %u using lines %u (SDA) and %u (SCL) delay=%d\n", + bus_num, desc_to_gpio(bus->sda), desc_to_gpio(ctx->scl), + bit_data->udelay); + } + + return 0; +} + +static const struct of_device_id gpio_shared_of_match[] = { + { .compatible = "i2c-gpio-shared" }, + {} +}; +MODULE_DEVICE_TABLE(of, gpio_shared_of_match); + +static struct platform_driver gpio_shared_driver = { + .probe = gpio_shared_probe, + .driver = { + .name = "i2c-gpio-shared", + .of_match_table = gpio_shared_of_match, + }, +}; + +module_platform_driver(gpio_shared_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Markus Stockhausen "); +MODULE_DESCRIPTION("bitbanging multi I2C driver for shared SCL"); diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/Kconfig b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/Kconfig new file mode 100644 index 0000000000..5808ad11e0 --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only +config NET_DSA_RTL83XX + tristate "Realtek RTL838x/RTL839x switch support" + depends on MACH_REALTEK_RTL + select NET_DSA_TAG_RTL_OTTO + help + This driver adds support for Realtek RTL83xx series switching. + +config NET_DSA_RTL83XX_RTL930X_L3_OFFLOAD + bool "Realtek RTL930x layer 3 offload (experimental)" + depends on NET_DSA_RTL83XX diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/Makefile b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/Makefile new file mode 100644 index 0000000000..1511dae8ea --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_NET_DSA_RTL83XX) += rtl_otto_dsa.o +rtl_otto_dsa-objs := common.o dsa.o rtl838x.o rtl839x.o rtl930x.o rtl931x.o debugfs.o qos.o tc.o diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c new file mode 100644 index 0000000000..b946558513 --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c @@ -0,0 +1,1886 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rtl83xx.h" + +struct phylink_pcs *rtpcs_create(struct device *dev, struct device_node *np, int port); + +int rtldsa_port_get_stp_state(struct rtl838x_switch_priv *priv, int port) +{ + u32 table[4]; + u32 msti = 0; + int state; + + if (port >= priv->cpu_port) + return -EINVAL; + + mutex_lock(&priv->reg_mutex); + state = priv->r->stp_get(priv, msti, port, table); + mutex_unlock(&priv->reg_mutex); + + return state; +} + +static struct table_reg rtl838x_tbl_regs[] = { + TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), /* RTL8380_TBL_L2 */ + TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), /* RTL8380_TBL_0 */ + TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), /* RTL8380_TBL_1 */ + + TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), /* RTL8390_TBL_L2 */ + TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), /* RTL8390_TBL_0 */ + TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), /* RTL8390_TBL_1 */ + TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), /* RTL8390_TBL_2 */ + + TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), /* RTL9300_TBL_L2 */ + TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), /* RTL9300_TBL_0 */ + TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), /* RTL9300_TBL_1 */ + TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), /* RTL9300_TBL_2 */ + TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), /* RTL9300_TBL_HSB */ + TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), /* RTL9300_TBL_HSA */ + + TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), /* RTL9310_TBL_0 */ + TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), /* RTL9310_TBL_1 */ + TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), /* RTL9310_TBL_2 */ + TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), /* RTL9310_TBL_3 */ + TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), /* RTL9310_TBL_4 */ + TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), /* RTL9310_TBL_5 */ +}; + +void rtl_table_init(void) +{ + for (int i = 0; i < RTL_TBL_END; i++) + mutex_init(&rtl838x_tbl_regs[i].lock); +} + +/* Request access to table t in table access register r + * Returns a handle to a lock for that table + */ +struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t) +{ + if (r >= RTL_TBL_END) + return NULL; + + if (t >= BIT(rtl838x_tbl_regs[r].c_bit - rtl838x_tbl_regs[r].t_bit)) + return NULL; + + mutex_lock(&rtl838x_tbl_regs[r].lock); + rtl838x_tbl_regs[r].tbl = t; + + return &rtl838x_tbl_regs[r]; +} + +/* Release a table r, unlock the corresponding lock */ +void rtl_table_release(struct table_reg *r) +{ + if (!r) + return; + +/* pr_info("Unlocking %08x\n", (u32)r); */ + mutex_unlock(&r->lock); +/* pr_info("Unlock done\n"); */ +} + +static int rtl_table_exec(struct table_reg *r, bool is_write, int idx) +{ + int ret = 0; + u32 cmd, val; + + /* Read/write bit has inverted meaning on RTL838x */ + if (r->rmode) + cmd = is_write ? 0 : BIT(r->c_bit); + else + cmd = is_write ? BIT(r->c_bit) : 0; + + cmd |= BIT(r->c_bit + 1); /* Execute bit */ + cmd |= r->tbl << r->t_bit; /* Table type */ + cmd |= idx & (BIT(r->t_bit) - 1); /* Index */ + + sw_w32(cmd, r->addr); + + ret = readx_poll_timeout(sw_r32, r->addr, val, + !(val & BIT(r->c_bit + 1)), 20, 10000); + if (ret) + pr_err("%s: timeout\n", __func__); + + return ret; +} + +/* Reads table index idx into the data registers of the table */ +int rtl_table_read(struct table_reg *r, int idx) +{ + return rtl_table_exec(r, false, idx); +} + +/* Writes the content of the table data registers into the table at index idx */ +int rtl_table_write(struct table_reg *r, int idx) +{ + return rtl_table_exec(r, true, idx); +} + +/* Returns the address of the ith data register of table register r + * the address is relative to the beginning of the Switch-IO block at 0xbb000000 + */ +inline u16 rtl_table_data(struct table_reg *r, int i) +{ + if (i >= r->max_data) + i = r->max_data - 1; + return r->data + i * 4; +} + +inline u32 rtl_table_data_r(struct table_reg *r, int i) +{ + return sw_r32(rtl_table_data(r, i)); +} + +inline void rtl_table_data_w(struct table_reg *r, u32 v, int i) +{ + sw_w32(v, rtl_table_data(r, i)); +} + +/* Port register accessor functions for the RTL838x and RTL930X SoCs */ +void rtl838x_mask_port_reg(u64 clear, u64 set, int reg) +{ + sw_w32_mask((u32)clear, (u32)set, reg); +} + +void rtl838x_set_port_reg(u64 set, int reg) +{ + sw_w32((u32)set, reg); +} + +u64 rtl838x_get_port_reg(int reg) +{ + return ((u64)sw_r32(reg)); +} + +/* Port register accessor functions for the RTL839x and RTL931X SoCs */ +void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg) +{ + sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg); + sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4); +} + +u64 rtl839x_get_port_reg_be(int reg) +{ + u64 v = sw_r32(reg); + + v <<= 32; + v |= sw_r32(reg + 4); + + return v; +} + +void rtl839x_set_port_reg_be(u64 set, int reg) +{ + sw_w32(set >> 32, reg); + sw_w32(set & 0xffffffff, reg + 4); +} + +void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg) +{ + sw_w32_mask((u32)clear, (u32)set, reg); + sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4); +} + +void rtl839x_set_port_reg_le(u64 set, int reg) +{ + sw_w32(set, reg); + sw_w32(set >> 32, reg + 4); +} + +u64 rtl839x_get_port_reg_le(int reg) +{ + u64 v = sw_r32(reg + 4); + + v <<= 32; + v |= sw_r32(reg); + + return v; +} + +static int rtldsa_bus_read(struct mii_bus *bus, int addr, int regnum) +{ + struct rtl838x_switch_priv *priv = bus->priv; + + return mdiobus_read_nested(priv->parent_bus, addr, regnum); +} + +static int rtldsa_bus_write(struct mii_bus *bus, int addr, int regnum, u16 val) +{ + struct rtl838x_switch_priv *priv = bus->priv; + + return mdiobus_write_nested(priv->parent_bus, addr, regnum, val); +} + +static int rtldsa_bus_c45_read(struct mii_bus *bus, int addr, int devad, int regnum) +{ + struct rtl838x_switch_priv *priv = bus->priv; + + return mdiobus_c45_read_nested(priv->parent_bus, addr, devad, regnum); +} + +static int rtldsa_bus_c45_write(struct mii_bus *bus, int addr, int devad, int regnum, u16 val) +{ + struct rtl838x_switch_priv *priv = bus->priv; + + return mdiobus_c45_write_nested(priv->parent_bus, addr, devad, regnum, val); +} + +static int rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv) +{ + struct device_node *dn, *phy_node, *pcs_node, *led_node; + struct device *dev = priv->dev; + struct mii_bus *bus; + int ret; + u32 pn; + + dn = of_find_compatible_node(NULL, NULL, "realtek,otto-mdio"); + if (!dn) + return -ENODEV; + + if (!of_device_is_available(dn)) + ret = -ENODEV; + + priv->parent_bus = of_mdio_find_bus(dn); + if (!priv->parent_bus) + return -EPROBE_DEFER; + + bus = devm_mdiobus_alloc(priv->ds->dev); + if (!bus) + return -ENOMEM; + + bus->name = "rtldsa_mdio"; + bus->read = rtldsa_bus_read; + bus->write = rtldsa_bus_write; + bus->read_c45 = rtldsa_bus_c45_read; + bus->write_c45 = rtldsa_bus_c45_write; + bus->phy_mask = priv->parent_bus->phy_mask; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id); + + bus->parent = dev; + priv->ds->user_mii_bus = bus; + priv->ds->user_mii_bus->priv = priv; + + ret = mdiobus_register(priv->ds->user_mii_bus); + if (ret) + return ret; + + dn = of_find_compatible_node(NULL, NULL, "realtek,otto-switch"); + if (!dn) { + dev_err(priv->dev, "No RTL switch node in DTS\n"); + return -ENODEV; + } + + led_node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds"); + + for_each_node_by_name(dn, "port") { + u32 led_set; + char led_set_str[16] = {0}; + + if (!of_device_is_available(dn)) + continue; + + if (of_property_read_u32(dn, "reg", &pn)) + continue; + + pcs_node = of_parse_phandle(dn, "pcs-handle", 0); + phy_node = of_parse_phandle(dn, "phy-handle", 0); + if (pn != priv->cpu_port && !phy_node && !pcs_node) { + dev_err(priv->dev, "Port node %d has neither pcs-handle nor phy-handle\n", pn); + continue; + } + + if (pcs_node) { + priv->ports[pn].pcs = rtpcs_create(priv->dev, pcs_node, pn); + if (IS_ERR(priv->ports[pn].pcs)) { + dev_err(priv->dev, "port %u failed to create PCS instance: %ld\n", + pn, PTR_ERR(priv->ports[pn].pcs)); + priv->ports[pn].pcs = NULL; + continue; + } + } + + priv->ports[pn].leds_on_this_port = 0; + if (led_node) { + if (of_property_read_u32(dn, "led-set", &led_set)) + led_set = 0; + priv->ports[pn].led_set = led_set; + sprintf(led_set_str, "led_set%d", led_set); + priv->ports[pn].leds_on_this_port = of_property_count_u32_elems(led_node, led_set_str); + if (priv->ports[pn].leds_on_this_port > 4) { + of_node_put(dn); + dev_err(priv->dev, "led_set %d for port %d configuration is invalid\n", led_set, pn); + return -ENODEV; + } + } + + if (!phy_node) { + if (priv->ports[pn].pcs) + priv->ports[pn].phy_is_integrated = true; + + continue; + } + + if (of_property_read_bool(phy_node, "phy-is-integrated") && + !of_property_read_bool(phy_node, "sfp")) { + priv->ports[pn].phy = PHY_RTL8218B_INT; + continue; + } + + if (!of_property_read_bool(phy_node, "phy-is-integrated") && + of_property_read_bool(phy_node, "sfp")) { + priv->ports[pn].phy = PHY_RTL8214FC; + continue; + } + + if (!of_property_read_bool(phy_node, "phy-is-integrated") && + !of_property_read_bool(phy_node, "sfp")) { + priv->ports[pn].phy = PHY_RTL8218B_EXT; + continue; + } + } + + /* Disable MAC polling the PHY so that we can start configuration */ + priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl); + + /* Disable PHY polling via SoC */ + if (priv->family_id == RTL8390_FAMILY_ID) + sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL); + + return 0; +} + +static int rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv) +{ + int t = sw_r32(priv->r->l2_ctrl_1); + + t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF; + + if (priv->family_id == RTL8380_FAMILY_ID) + t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */ + else + t = (t * 3) / 5; + + pr_debug("L2 AGING time: %d sec\n", t); + pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out)); + + return t; +} + +/* Caller must hold priv->reg_mutex */ +int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_lag_upper_info *info) +{ + struct rtl838x_switch_priv *priv = ds->priv; + int ret; + int i; + + for (i = 0; i < priv->ds->num_lag_ids; i++) { + if (priv->lags_port_members[i] & BIT_ULL(port)) + break; + } + if (i != priv->ds->num_lag_ids) { + pr_err("%s: Port %d already member of LAG %d.\n", __func__, port, i); + return -ENOSPC; + } + + if (priv->r->lag_setup_algomask) { + ret = priv->r->lag_setup_algomask(priv, group, info); + if (ret) + return ret; + } + + ret = priv->r->lag_set_port_members(priv, group, + priv->lags_port_members[group] | BIT_ULL(port), info); + if (ret) + return ret; + + pr_info("%s: Added port %d to LAG %d. Members now %016llx.\n", + __func__, port, group, priv->lags_port_members[group]); + + return 0; +} + +/* Caller must hold priv->reg_mutex */ +int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port) +{ + struct rtl838x_switch_priv *priv = ds->priv; + int ret; + + if (group >= priv->ds->num_lag_ids) { + pr_err("%s: LAG %d invalid.\n", __func__, group); + return -EINVAL; + } + + if (!(priv->lags_port_members[group] & BIT_ULL(port))) { + pr_err("%s: Port %d not member of LAG %d.\n", __func__, port, group); + return -ENOSPC; + } + + /* Don't touch hash mask bits, as only the port might be removed from + * the LAG group. This means the lag group stays valid with existing + * mask algo bits. If there are no lag members left, then + * rtl83xx_lag_add will reconfigure hash mask when new LAG group is + * created. + */ + ret = priv->r->lag_set_port_members(priv, group, + priv->lags_port_members[group] & ~BIT_ULL(port), + NULL); + if (ret) + return ret; + + pr_info("%s: Removed port %d from LAG %d. Members now %016llx.\n", + __func__, port, group, priv->lags_port_members[group]); + + return 0; +} + +int rtldsa_93xx_lag_set_distribution_algorithm(struct rtl838x_switch_priv *priv, + int group, int algoidx, u32 algomsk) +{ + bool is_l3 = false; + u32 newmask = 0; + + if (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) { + is_l3 = true; + newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT; + } + if (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) { + is_l3 = true; + newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT; + } + if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) { + is_l3 = true; + newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT; + } + + if (algomsk & TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT) { + is_l3 = true; + newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DST_L4PORT_BIT; + } + + if (is_l3) { + if (algomsk & TRUNK_DISTRIBUTION_ALGO_SPA_BIT) + newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SPA_BIT; + if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT) + newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT; + if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT) + newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT; + if (algomsk & TRUNK_DISTRIBUTION_ALGO_VLAN_BIT) + newmask |= TRUNK_DISTRIBUTION_ALGO_L3_VLAN_BIT; + } else { + if (algomsk & TRUNK_DISTRIBUTION_ALGO_SPA_BIT) + newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SPA_BIT; + if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT) + newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT; + if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT) + newmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT; + if (algomsk & TRUNK_DISTRIBUTION_ALGO_VLAN_BIT) + newmask |= TRUNK_DISTRIBUTION_ALGO_L2_VLAN_BIT; + } + + sw_w32(newmask, priv->r->trk_hash_ctrl + (algoidx << 2)); + + return 0; +} + +int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group, + struct netdev_lag_upper_info *info) +{ + u32 algomsk = 0; + u32 algoidx = 0; + + switch (info->hash_type) { + case NETDEV_LAG_HASH_L2: + algomsk |= TRUNK_DISTRIBUTION_ALGO_DMAC_BIT; + algomsk |= TRUNK_DISTRIBUTION_ALGO_SMAC_BIT; + break; + case NETDEV_LAG_HASH_L23: + algomsk |= TRUNK_DISTRIBUTION_ALGO_DMAC_BIT; + algomsk |= TRUNK_DISTRIBUTION_ALGO_SMAC_BIT; + algomsk |= TRUNK_DISTRIBUTION_ALGO_SIP_BIT; /* source ip */ + algomsk |= TRUNK_DISTRIBUTION_ALGO_DIP_BIT; /* dest ip */ + algoidx = 1; + break; + case NETDEV_LAG_HASH_L34: + algomsk |= TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT; /* sport */ + algomsk |= TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT; /* dport */ + algomsk |= TRUNK_DISTRIBUTION_ALGO_SIP_BIT; /* source ip */ + algomsk |= TRUNK_DISTRIBUTION_ALGO_DIP_BIT; /* dest ip */ + algoidx = 2; + break; + default: + algomsk |= TRUNK_DISTRIBUTION_ALGO_MASKALL; + } + + return priv->r->lag_set_distribution_algorithm(priv, group, algoidx, algomsk); +} + +static int rtldsa_93xx_lag_set_group2ports(struct rtl838x_switch_priv *priv, int group, + struct netdev_lag_upper_info *info) +{ + DECLARE_BITMAP(ports, ARRAY_SIZE(priv->ports)); + struct rtldsa_93xx_lag_entry e; + unsigned int table_pos = 0; + u8 num_of_lag_ports = 0; + u8 group_ports[8]; + u32 data[3]; + int i; + + /* Read lag table using Table control register 2 */ + struct table_reg *r = priv->r->lag_table(); + + rtl_table_read(r, group); + + bitmap_clear(ports, 0, ARRAY_SIZE(priv->ports)); + bitmap_from_arr64(ports, &priv->lags_port_members[group], + ARRAY_SIZE(priv->ports)); + + for (i = 0; i < 3; i++) + data[i] = sw_r32(rtl_table_data(r, i)); + + priv->r->lag_fill_data(data, &e); + + num_of_lag_ports = bitmap_weight(ports, ARRAY_SIZE(priv->ports)); + if (num_of_lag_ports > ARRAY_SIZE(group_ports)) { + pr_err("%s: Number of LAG ports too high: %u", __func__, + num_of_lag_ports); + + return -ENOSPC; + } + + memset(group_ports, 0x3f, sizeof(group_ports)); + + table_pos = 0; + for_each_set_bit(i, ports, ARRAY_SIZE(priv->ports)) { + if (!priv->ports[i].dp->lag_tx_enabled) + continue; + + group_ports[table_pos] = i; + table_pos++; + } + + /* Remove tx disabled ports */ + num_of_lag_ports = table_pos; + + e.trk_dev0 = 0; + e.trk_port0 = group_ports[0]; + e.trk_dev1 = 0; + e.trk_port1 = group_ports[1]; + e.trk_dev2 = 0; + e.trk_port2 = group_ports[2]; + e.trk_dev3 = 0; + e.trk_port3 = group_ports[3]; + e.trk_dev4 = 0; + e.trk_port4 = group_ports[4]; + e.trk_dev5 = 0; + e.trk_port5 = group_ports[5]; + e.trk_dev6 = 0; + e.trk_port6 = group_ports[6]; + e.trk_dev7 = 0; + e.trk_port7 = group_ports[7]; + + e.num_tx_candi = num_of_lag_ports; + + /* set hash_mask_idx to 0 if we are deleting lag group */ + if (info) { + if (info->hash_type == NETDEV_LAG_HASH_L2) { + e.l2_hash_mask_idx = RTL93XX_HASH_MASK_INDEX_L2; + e.ip4_hash_mask_idx = RTL93XX_HASH_MASK_INDEX_L2; + e.ip6_hash_mask_idx = RTL93XX_HASH_MASK_INDEX_L2; + } else if (info->hash_type == NETDEV_LAG_HASH_L23) { + e.l2_hash_mask_idx = RTL93XX_HASH_MASK_INDEX_L23; + e.ip4_hash_mask_idx = RTL93XX_HASH_MASK_INDEX_L23; + e.ip6_hash_mask_idx = RTL93XX_HASH_MASK_INDEX_L23; + } else { + return -EOPNOTSUPP; + } + } + + priv->r->lag_write_data(data, &e); + + for (i = 0; i < 3; i++) + sw_w32(data[i], rtl_table_data(r, i)); + rtl_table_write(r, group); + rtl_table_release(r); + + return 0; +} + +static inline void rtldsa_93xx_lag_set_local_group2ports(struct rtl838x_switch_priv *priv, int group, + u64 ports) +{ + priv->r->set_port_reg_be(ports, priv->r->trk_mbr_ctr(group)); +} + +int rtldsa_93xx_lag_set_port_members(struct rtl838x_switch_priv *priv, int group, + u64 members, struct netdev_lag_upper_info *info) +{ + DECLARE_BITMAP(affected_members, ARRAY_SIZE(priv->ports)); + bool valid_group; + u64 old_members; + u64 affected; + size_t port; + int ret; + + /* calculate modifications of the LAG group */ + old_members = priv->lags_port_members[group]; + priv->lags_port_members[group] = members; + + affected = old_members | priv->lags_port_members[group]; + + bitmap_clear(affected_members, 0, ARRAY_SIZE(priv->ports)); + bitmap_from_arr64(affected_members, &affected, BITS_PER_TYPE(affected)); + + valid_group = __sw_hweight64(priv->lags_port_members[group]); + + /* apply global group and port settings */ + ret = rtldsa_93xx_lag_set_group2ports(priv, group, info); + if (ret) + return ret; + + for_each_set_bit(port, affected_members, ARRAY_SIZE(priv->ports)) { + bool valid = priv->lags_port_members[group] & BIT_ULL(port); + + priv->r->lag_set_port2group(group, port, valid); + } + + /* apply local group and port settings */ + priv->r->lag_set_local_group_id(group, group, valid_group); + rtldsa_93xx_lag_set_local_group2ports(priv, group, priv->lags_port_members[group]); + + for_each_set_bit(port, affected_members, ARRAY_SIZE(priv->ports)) { + bool valid = priv->lags_port_members[group] & BIT_ULL(port); + + priv->r->lag_set_local_port2group(group, port, valid); + } + + /* write lag table (and maybe additional information) to SRAM */ + priv->r->lag_sync_tables(); + + return 0; +} + +// Currently Unused +// /* Allocate a 64 bit octet counter located in the LOG HW table */ +// static int rtl83xx_octet_cntr_alloc(struct rtl838x_switch_priv *priv) +// { +// int idx; + +// mutex_lock(&priv->reg_mutex); + +// idx = find_first_zero_bit(priv->octet_cntr_use_bm, MAX_COUNTERS); +// if (idx >= priv->r->n_counters) { +// mutex_unlock(&priv->reg_mutex); +// return -1; +// } + +// set_bit(idx, priv->octet_cntr_use_bm); +// mutex_unlock(&priv->reg_mutex); + +// return idx; +// } + +/* Allocate a 32-bit packet counter + * 2 32-bit packet counters share the location of a 64-bit octet counter + * Initially there are no free packet counters and 2 new ones need to be freed + * by allocating the corresponding octet counter + */ +int rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv *priv) +{ + int idx, j; + + mutex_lock(&priv->reg_mutex); + + /* Because initially no packet counters are free, the logic is reversed: + * a 0-bit means the counter is already allocated (for octets) + */ + idx = find_first_bit(priv->packet_cntr_use_bm, MAX_COUNTERS * 2); + if (idx >= priv->r->n_counters * 2) { + j = find_first_zero_bit(priv->octet_cntr_use_bm, MAX_COUNTERS); + if (j >= priv->r->n_counters) { + mutex_unlock(&priv->reg_mutex); + return -1; + } + set_bit(j, priv->octet_cntr_use_bm); + idx = j * 2; + set_bit(j * 2 + 1, priv->packet_cntr_use_bm); + + } else { + clear_bit(idx, priv->packet_cntr_use_bm); + } + + mutex_unlock(&priv->reg_mutex); + + return idx; +} + +/* Add an L2 nexthop entry for the L3 routing system / PIE forwarding in the SoC + * Use VID and MAC in rtl838x_l2_entry to identify either a free slot in the L2 hash table + * or mark an existing entry as a nexthop by setting it's nexthop bit + * Called from the L3 layer + * The index in the L2 hash table is filled into nh->l2_id; + */ +static int rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh) +{ + struct rtl838x_l2_entry e; + u64 seed = priv->r->l2_hash_seed(nh->mac, nh->rvid); + u32 key = priv->r->l2_hash_key(priv, seed); + int idx = -1; + u64 entry; + + pr_debug("%s searching for %08llx vid %d with key %d, seed: %016llx\n", + __func__, nh->mac, nh->rvid, key, seed); + + e.type = L2_UNICAST; + u64_to_ether_addr(nh->mac, &e.mac[0]); + e.port = nh->port; + + /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */ + for (int i = 0; i < priv->l2_bucket_size; i++) { + entry = priv->r->read_l2_entry_using_hash(key, i, &e); + + if (!e.valid || ((entry & 0x0fffffffffffffffULL) == seed)) { + idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 + : ((key << 2) | i) & 0xffff; + break; + } + } + + if (idx < 0) { + pr_err("%s: No more L2 forwarding entries available\n", __func__); + return -1; + } + + /* Found an existing (e->valid is true) or empty entry, make it a nexthop entry */ + nh->l2_id = idx; + if (e.valid) { + nh->port = e.port; + nh->vid = e.vid; /* Save VID */ + nh->rvid = e.rvid; + nh->dev_id = e.stack_dev; + /* If the entry is already a valid next hop entry, don't change it */ + if (e.next_hop) + return 0; + } else { + e.valid = true; + e.is_static = true; + e.rvid = nh->rvid; + e.is_ip_mc = false; + e.is_ipv6_mc = false; + e.block_da = false; + e.block_sa = false; + e.suspended = false; + e.age = 0; /* With port-ignore */ + e.port = priv->r->port_ignore; + u64_to_ether_addr(nh->mac, &e.mac[0]); + } + e.next_hop = true; + e.nh_route_id = nh->id; /* NH route ID takes place of VID */ + e.nh_vlan_target = false; + + priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); + + return 0; +} + +/* Removes a Layer 2 next hop entry in the forwarding database + * If it was static, the entire entry is removed, otherwise the nexthop bit is cleared + * and we wait until the entry ages out + */ +static int rtl83xx_l2_nexthop_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh) +{ + struct rtl838x_l2_entry e; + u32 key = nh->l2_id >> 2; + int i = nh->l2_id & 0x3; + u64 entry = entry = priv->r->read_l2_entry_using_hash(key, i, &e); + + pr_debug("%s: id %d, key %d, index %d\n", __func__, nh->l2_id, key, i); + if (!e.valid) { + dev_err(priv->dev, "unknown nexthop, id %x\n", nh->l2_id); + return -1; + } + + if (e.is_static) + e.valid = false; + e.next_hop = false; + e.vid = nh->vid; /* Restore VID */ + e.rvid = nh->rvid; + + priv->r->write_l2_entry_using_hash(key, i, &e); + + return 0; +} + +int rtl83xx_port_is_under(const struct net_device *dev, struct rtl838x_switch_priv *priv) +{ + /* Is the lower network device a DSA user network device of our RTL930X-switch? + * Unfortunately we cannot just follow dev->dsa_prt as this is only set for the + * DSA conduit device. TODO: since 6.12: + * + * if(!dsa_user_dev_check(dev)) { + * netdev_info(dev, "%s: not a DSA device.\n", __func__); + * return -EINVAL; + * } + */ + + for (int i = 0; i < priv->cpu_port; i++) { + if (!priv->ports[i].dp) + continue; + if (priv->ports[i].dp->user == dev) + return i; + } + + return -EINVAL; +} + +static const struct rhashtable_params route_ht_params = { + .key_len = sizeof(u32), + .key_offset = offsetof(struct rtl83xx_route, gw_ip), + .head_offset = offsetof(struct rtl83xx_route, linkage), +}; + +/* Updates an L3 next hop entry in the ROUTING table */ +static int rtl83xx_l3_nexthop_update(struct rtl838x_switch_priv *priv, __be32 ip_addr, u64 mac) +{ + struct rtl83xx_route *r; + struct rhlist_head *tmp, *list; + + rcu_read_lock(); + list = rhltable_lookup(&priv->routes, &ip_addr, route_ht_params); + if (!list) { + rcu_read_unlock(); + return -ENOENT; + } + + rhl_for_each_entry_rcu(r, tmp, list, linkage) { + pr_debug("%s: Setting up fwding: ip %pI4, GW mac %016llx\n", + __func__, &ip_addr, mac); + + /* Reads the ROUTING table entry associated with the route */ + priv->r->route_read(r->id, r); + pr_debug("Route with id %d to %pI4 / %d\n", r->id, &r->dst_ip, r->prefix_len); + + r->nh.mac = r->nh.gw = mac; + r->nh.port = priv->r->port_ignore; + r->nh.id = r->id; + + /* Do we need to explicitly add a DMAC entry with the route's nh index? */ + if (priv->r->set_l3_egress_mac) + priv->r->set_l3_egress_mac(r->id, mac); + + /* Update ROUTING table: map gateway-mac and switch-mac id to route id */ + rtl83xx_l2_nexthop_add(priv, &r->nh); + + r->attr.valid = true; + r->attr.action = ROUTE_ACT_FORWARD; + r->attr.type = 0; + r->attr.hit = false; /* Reset route-used indicator */ + + /* Add PIE entry with dst_ip and prefix_len */ + r->pr.dip = r->dst_ip; + r->pr.dip_m = inet_make_mask(r->prefix_len); + + if (r->is_host_route) { + int slot = priv->r->find_l3_slot(r, false); + + pr_info("%s: Got slot for route: %d\n", __func__, slot); + priv->r->host_route_write(slot, r); + } else { + priv->r->route_write(r->id, r); + r->pr.fwd_sel = true; + r->pr.fwd_data = r->nh.l2_id; + r->pr.fwd_act = PIE_ACT_ROUTE_UC; + } + + if (priv->r->set_l3_nexthop) + priv->r->set_l3_nexthop(r->nh.id, r->nh.l2_id, r->nh.if_id); + + if (r->pr.id < 0) { + r->pr.packet_cntr = rtl83xx_packet_cntr_alloc(priv); + if (r->pr.packet_cntr >= 0) { + pr_info("Using packet counter %d\n", r->pr.packet_cntr); + r->pr.log_sel = true; + r->pr.log_data = r->pr.packet_cntr; + } + priv->r->pie_rule_add(priv, &r->pr); + } else { + int pkts = priv->r->packet_cntr_read(r->pr.packet_cntr); + + pr_debug("%s: total packets: %d\n", __func__, pkts); + + priv->r->pie_rule_write(priv, r->pr.id, &r->pr); + } + } + rcu_read_unlock(); + + return 0; +} + +static int rtl83xx_port_ipv4_resolve(struct rtl838x_switch_priv *priv, + struct net_device *dev, __be32 ip_addr) +{ + struct neighbour *n = neigh_lookup(&arp_tbl, &ip_addr, dev); + int err = 0; + u64 mac; + + if (!n) { + n = neigh_create(&arp_tbl, &ip_addr, dev); + if (IS_ERR(n)) + return PTR_ERR(n); + } + + /* If the neigh is already resolved, then go ahead and + * install the entry, otherwise start the ARP process to + * resolve the neigh. + */ + if (n->nud_state & NUD_VALID) { + mac = ether_addr_to_u64(n->ha); + pr_info("%s: resolved mac: %016llx\n", __func__, mac); + rtl83xx_l3_nexthop_update(priv, ip_addr, mac); + } else { + pr_info("%s: need to wait\n", __func__); + neigh_event_send(n, NULL); + } + + neigh_release(n); + + return err; +} + +struct rtl83xx_walk_data { + struct rtl838x_switch_priv *priv; + int port; +}; + +static int rtl83xx_port_lower_walk(struct net_device *lower, struct netdev_nested_priv *_priv) +{ + struct rtl83xx_walk_data *data = (struct rtl83xx_walk_data *)_priv->data; + struct rtl838x_switch_priv *priv = data->priv; + int ret = 0; + int index; + + index = rtl83xx_port_is_under(lower, priv); + data->port = index; + if (index >= 0) { + pr_debug("Found DSA-port, index %d\n", index); + ret = 1; + } + + return ret; +} + +static int rtl83xx_port_dev_lower_find(struct net_device *dev, struct rtl838x_switch_priv *priv) +{ + struct rtl83xx_walk_data data; + struct netdev_nested_priv _priv; + + data.priv = priv; + data.port = 0; + _priv.data = (void *)&data; + + netdev_walk_all_lower_dev(dev, rtl83xx_port_lower_walk, &_priv); + + return data.port; +} + +static struct rtl83xx_route *rtl83xx_route_alloc(struct rtl838x_switch_priv *priv, u32 ip) +{ + struct rtl83xx_route *r; + int idx = 0, err; + + mutex_lock(&priv->reg_mutex); + + idx = find_first_zero_bit(priv->route_use_bm, MAX_ROUTES); + pr_debug("%s id: %d, ip %pI4\n", __func__, idx, &ip); + + r = kzalloc(sizeof(*r), GFP_KERNEL); + if (!r) { + mutex_unlock(&priv->reg_mutex); + return r; + } + + r->id = idx; + r->gw_ip = ip; + r->pr.id = -1; /* We still need to allocate a rule in HW */ + r->is_host_route = false; + + err = rhltable_insert(&priv->routes, &r->linkage, route_ht_params); + if (err) { + pr_err("Could not insert new rule\n"); + mutex_unlock(&priv->reg_mutex); + goto out_free; + } + + set_bit(idx, priv->route_use_bm); + + mutex_unlock(&priv->reg_mutex); + + return r; + +out_free: + kfree(r); + + return NULL; +} + +static struct rtl83xx_route *rtl83xx_host_route_alloc(struct rtl838x_switch_priv *priv, u32 ip) +{ + struct rtl83xx_route *r; + int idx = 0, err; + + mutex_lock(&priv->reg_mutex); + + idx = find_first_zero_bit(priv->host_route_use_bm, MAX_HOST_ROUTES); + pr_debug("%s id: %d, ip %pI4\n", __func__, idx, &ip); + + r = kzalloc(sizeof(*r), GFP_KERNEL); + if (!r) { + mutex_unlock(&priv->reg_mutex); + return r; + } + + /* We require a unique route ID irrespective of whether it is a prefix or host + * route (on RTL93xx) as we use this ID to associate a DMAC and next-hop entry + */ + r->id = idx + MAX_ROUTES; + + r->gw_ip = ip; + r->pr.id = -1; /* We still need to allocate a rule in HW */ + r->is_host_route = true; + + err = rhltable_insert(&priv->routes, &r->linkage, route_ht_params); + if (err) { + pr_err("Could not insert new rule\n"); + mutex_unlock(&priv->reg_mutex); + goto out_free; + } + + set_bit(idx, priv->host_route_use_bm); + + mutex_unlock(&priv->reg_mutex); + + return r; + +out_free: + kfree(r); + + return NULL; +} + +static void rtl83xx_route_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_route *r) +{ + int id; + + if (rhltable_remove(&priv->routes, &r->linkage, route_ht_params)) + dev_warn(priv->dev, "Could not remove route\n"); + + if (r->is_host_route) { + id = priv->r->find_l3_slot(r, false); + pr_debug("%s: Got id for host route: %d\n", __func__, id); + r->attr.valid = false; + priv->r->host_route_write(id, r); + clear_bit(r->id - MAX_ROUTES, priv->host_route_use_bm); + } else { + /* If there is a HW representation of the route, delete it */ + if (priv->r->route_lookup_hw) { + id = priv->r->route_lookup_hw(r); + pr_info("%s: Got id for prefix route: %d\n", __func__, id); + r->attr.valid = false; + priv->r->route_write(id, r); + } + clear_bit(r->id, priv->route_use_bm); + } + + kfree(r); +} + +static int rtldsa_fib4_check(struct rtl838x_switch_priv *priv, + struct fib_entry_notifier_info *info, + enum fib_event_type event) +{ + struct net_device *ndev = fib_info_nh(info->fi, 0)->fib_nh_dev; + int vlan = is_vlan_dev(ndev) ? vlan_dev_vlan_id(ndev) : 0; + struct fib_nh *nh = fib_info_nh(info->fi, 0); + char gw_message[32] = ""; + + if (nh->fib_nh_gw4) + snprintf(gw_message, sizeof(gw_message), "via %pI4 ", &nh->fib_nh_gw4); + + dev_info(priv->dev, "%s IPv4 route %pI4/%d %s(VLAN %d, MAC %pM)\n", + event == FIB_EVENT_ENTRY_ADD ? "add" : "delete", + &info->dst, info->dst_len, gw_message, vlan, ndev->dev_addr); + + if ((info->type == RTN_BROADCAST) || ipv4_is_loopback(info->dst) || !info->dst) { + dev_warn(priv->dev, "skip loopback/broadcast addresses and default routes\n"); + return -EINVAL; + } + + return 0; +} + +static int rtldsa_fib4_del(struct rtl838x_switch_priv *priv, + struct fib_entry_notifier_info *info) +{ + struct fib_nh *nh = fib_info_nh(info->fi, 0); + struct rhlist_head *tmp, *list; + struct rtl83xx_route *route; + + if (rtldsa_fib4_check(priv, info, FIB_EVENT_ENTRY_DEL)) + return 0; + + rcu_read_lock(); + list = rhltable_lookup(&priv->routes, &nh->fib_nh_gw4, route_ht_params); + if (!list) { + rcu_read_unlock(); + dev_err(priv->dev, "no such gateway: %pI4\n", &nh->fib_nh_gw4); + return -ENOENT; + } + rhl_for_each_entry_rcu(route, tmp, list, linkage) { + if (route->dst_ip == info->dst && route->prefix_len == info->dst_len) { + dev_info(priv->dev, "found a route with id %d, nh-id %d\n", + route->id, route->nh.id); + break; + } + } + rcu_read_unlock(); + + rtl83xx_l2_nexthop_rm(priv, &route->nh); + + dev_info(priv->dev, "releasing packet counter %d\n", route->pr.packet_cntr); + set_bit(route->pr.packet_cntr, priv->packet_cntr_use_bm); + priv->r->pie_rule_rm(priv, &route->pr); + + rtl83xx_route_rm(priv, route); + + nh->fib_nh_flags &= ~RTNH_F_OFFLOAD; + + return 0; +} + +/* On the RTL93xx, an L3 termination endpoint MAC address on which the router waits + * for packets to be routed needs to be allocated. + */ +static int rtl83xx_alloc_router_mac(struct rtl838x_switch_priv *priv, u64 mac) +{ + int free_mac = -1; + struct rtl93xx_rt_mac m; + + mutex_lock(&priv->reg_mutex); + for (int i = 0; i < MAX_ROUTER_MACS; i++) { + priv->r->get_l3_router_mac(i, &m); + if (free_mac < 0 && !m.valid) { + free_mac = i; + continue; + } + if (m.valid && m.mac == mac) { + free_mac = i; + break; + } + } + + if (free_mac < 0) { + pr_err("No free router MACs, cannot offload\n"); + mutex_unlock(&priv->reg_mutex); + return -1; + } + + m.valid = true; + m.mac = mac; + m.p_type = 0; /* An individual port, not a trunk port */ + m.p_id = 0x3f; /* Listen on any port */ + m.p_id_mask = 0; + m.vid = 0; /* Listen on any VLAN... */ + m.vid_mask = 0; /* ... so mask needs to be 0 */ + m.mac_mask = 0xffffffffffffULL; /* We want an exact match of the interface MAC */ + m.action = L3_FORWARD; /* Route the packet */ + priv->r->set_l3_router_mac(free_mac, &m); + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtl83xx_alloc_egress_intf(struct rtl838x_switch_priv *priv, u64 mac, int vlan) +{ + int free_mac = -1; + struct rtl838x_l3_intf intf; + u64 m; + + mutex_lock(&priv->reg_mutex); + for (int i = 0; i < MAX_SMACS; i++) { + m = priv->r->get_l3_egress_mac(L3_EGRESS_DMACS + i); + if (free_mac < 0 && !m) { + free_mac = i; + continue; + } + if (m == mac) { + mutex_unlock(&priv->reg_mutex); + return i; + } + } + + if (free_mac < 0) { + pr_err("No free egress interface, cannot offload\n"); + return -1; + } + + /* Set up default egress interface 1 */ + intf.vid = vlan; + intf.smac_idx = free_mac; + intf.ip4_mtu_id = 1; + intf.ip6_mtu_id = 1; + intf.ttl_scope = 1; /* TTL */ + intf.hl_scope = 1; /* Hop Limit */ + intf.ip4_icmp_redirect = intf.ip6_icmp_redirect = 2; /* FORWARD */ + intf.ip4_pbr_icmp_redirect = intf.ip6_pbr_icmp_redirect = 2; /* FORWARD; */ + priv->r->set_l3_egress_intf(free_mac, &intf); + + priv->r->set_l3_egress_mac(L3_EGRESS_DMACS + free_mac, mac); + + mutex_unlock(&priv->reg_mutex); + + return free_mac; +} + +static int rtldsa_fib4_add(struct rtl838x_switch_priv *priv, + struct fib_entry_notifier_info *info) +{ + struct net_device *ndev = fib_info_nh(info->fi, 0)->fib_nh_dev; + int vlan = is_vlan_dev(ndev) ? vlan_dev_vlan_id(ndev) : 0; + struct fib_nh *nh = fib_info_nh(info->fi, 0); + struct rtl83xx_route *route; + int port; + + if (rtldsa_fib4_check(priv, info, FIB_EVENT_ENTRY_ADD)) + return 0; + + port = rtl83xx_port_dev_lower_find(ndev, priv); + if (port < 0) { + dev_err(priv->dev, "lower interface %s not found\n", ndev->name); + return -ENODEV; + } + + /* Allocate route or host-route entry (if hardware supports this) */ + if (info->dst_len == 32 && priv->r->host_route_write) + route = rtl83xx_host_route_alloc(priv, nh->fib_nh_gw4); + else + route = rtl83xx_route_alloc(priv, nh->fib_nh_gw4); + + if (route) + dev_info(priv->dev, "route hashtable extended for gw %pI4\n", &nh->fib_nh_gw4); + else { + dev_err(priv->dev, "could not extend route hashtable for gw %pI4\n", &nh->fib_nh_gw4); + return -ENOSPC; + } + + route->dst_ip = info->dst; + route->prefix_len = info->dst_len; + route->nh.rvid = vlan; + + if (priv->r->set_l3_router_mac) { + u64 mac = ether_addr_to_u64(ndev->dev_addr); + + pr_debug("Local route and router MAC %pM\n", ndev->dev_addr); + if (rtl83xx_alloc_router_mac(priv, mac)) + goto out_free_rt; + + /* vid = 0: Do not care about VID */ + route->nh.if_id = rtl83xx_alloc_egress_intf(priv, mac, vlan); + if (route->nh.if_id < 0) + goto out_free_rmac; + + if (!nh->fib_nh_gw4) { + int slot; + + route->nh.mac = mac; + route->nh.port = priv->r->port_ignore; + route->attr.valid = true; + route->attr.action = ROUTE_ACT_TRAP2CPU; + route->attr.type = 0; + + slot = priv->r->find_l3_slot(route, false); + pr_debug("%s: Got slot for route: %d\n", __func__, slot); + priv->r->host_route_write(slot, route); + } + } + + /* We need to resolve the mac address of the GW */ + if (nh->fib_nh_gw4) + rtl83xx_port_ipv4_resolve(priv, ndev, nh->fib_nh_gw4); + + nh->fib_nh_flags |= RTNH_F_OFFLOAD; + + return 0; + +out_free_rmac: +out_free_rt: + return 0; +} + +static int rtl83xx_fib6_add(struct rtl838x_switch_priv *priv, + struct fib6_entry_notifier_info *info) +{ + pr_debug("In %s\n", __func__); +/* nh->fib_nh_flags |= RTNH_F_OFFLOAD; */ + + return 0; +} + +struct net_event_work { + struct work_struct work; + struct rtl838x_switch_priv *priv; + u64 mac; + u32 gw_addr; +}; + +static void rtl83xx_net_event_work_do(struct work_struct *work) +{ + struct net_event_work *net_work = + container_of(work, struct net_event_work, work); + struct rtl838x_switch_priv *priv = net_work->priv; + + rtl83xx_l3_nexthop_update(priv, net_work->gw_addr, net_work->mac); + + kfree(net_work); +} + +static int rtl83xx_netevent_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + struct rtl838x_switch_priv *priv; + struct net_device *dev; + struct neighbour *n = ptr; + int err, port; + struct net_event_work *net_work; + + priv = container_of(this, struct rtl838x_switch_priv, ne_nb); + + switch (event) { + case NETEVENT_NEIGH_UPDATE: + /* ignore events for HW with missing L3 offloading implementation */ + if (!priv->r->l3_setup) + return NOTIFY_DONE; + + if (n->tbl != &arp_tbl) + return NOTIFY_DONE; + dev = n->dev; + port = rtl83xx_port_dev_lower_find(dev, priv); + if (port < 0 || !(n->nud_state & NUD_VALID)) { + pr_debug("%s: Neigbour invalid, not updating\n", __func__); + return NOTIFY_DONE; + } + + net_work = kzalloc(sizeof(*net_work), GFP_ATOMIC); + if (!net_work) + return NOTIFY_BAD; + + INIT_WORK(&net_work->work, rtl83xx_net_event_work_do); + net_work->priv = priv; + + net_work->mac = ether_addr_to_u64(n->ha); + net_work->gw_addr = *(__be32 *)n->primary_key; + + pr_debug("%s: updating neighbour on port %d, mac %016llx\n", + __func__, port, net_work->mac); + queue_work(priv->wq, &net_work->work); + if (err) + netdev_warn(dev, "failed to handle neigh update (err %d)\n", err); + break; + } + + return NOTIFY_DONE; +} + +struct rtl83xx_fib_event_work { + struct work_struct work; + union { + struct fib_entry_notifier_info fen_info; + struct fib6_entry_notifier_info fen6_info; + struct fib_rule_notifier_info fr_info; + }; + struct rtl838x_switch_priv *priv; + bool is_fib6; + unsigned long event; +}; + +static void rtl83xx_fib_event_work_do(struct work_struct *work) +{ + struct rtl83xx_fib_event_work *fib_work = + container_of(work, struct rtl83xx_fib_event_work, work); + struct rtl838x_switch_priv *priv = fib_work->priv; + struct fib_rule *rule; + int err; + + /* Protect internal structures from changes */ + rtnl_lock(); + pr_debug("%s: doing work, event %ld\n", __func__, fib_work->event); + switch (fib_work->event) { + case FIB_EVENT_ENTRY_ADD: + case FIB_EVENT_ENTRY_REPLACE: + case FIB_EVENT_ENTRY_APPEND: + if (fib_work->is_fib6) + err = rtl83xx_fib6_add(priv, &fib_work->fen6_info); + else + err = rtldsa_fib4_add(priv, &fib_work->fen_info); + if (err) + dev_err(priv->dev, "fib_add() failed\n"); + + fib_info_put(fib_work->fen_info.fi); + break; + case FIB_EVENT_ENTRY_DEL: + err = rtldsa_fib4_del(priv, &fib_work->fen_info); + if (err) + dev_err(priv->dev, "fib_del() failed\n"); + + fib_info_put(fib_work->fen_info.fi); + break; + case FIB_EVENT_RULE_ADD: + case FIB_EVENT_RULE_DEL: + rule = fib_work->fr_info.rule; + if (!fib4_rule_default(rule)) + pr_err("%s: FIB4 default rule failed\n", __func__); + fib_rule_put(rule); + break; + } + rtnl_unlock(); + kfree(fib_work); +} + +/* Called with rcu_read_lock() */ +static int rtl83xx_fib_event(struct notifier_block *this, unsigned long event, void *ptr) +{ + struct fib_notifier_info *info = ptr; + struct rtl838x_switch_priv *priv; + struct rtl83xx_fib_event_work *fib_work; + + if ((info->family != AF_INET && info->family != AF_INET6 && + info->family != RTNL_FAMILY_IPMR && + info->family != RTNL_FAMILY_IP6MR)) + return NOTIFY_DONE; + + priv = container_of(this, struct rtl838x_switch_priv, fib_nb); + + /* ignore FIB events for HW with missing L3 offloading implementation */ + if (!priv->r->l3_setup) + return NOTIFY_DONE; + + fib_work = kzalloc(sizeof(*fib_work), GFP_ATOMIC); + if (!fib_work) + return NOTIFY_BAD; + + INIT_WORK(&fib_work->work, rtl83xx_fib_event_work_do); + fib_work->priv = priv; + fib_work->event = event; + fib_work->is_fib6 = false; + + switch (event) { + case FIB_EVENT_ENTRY_ADD: + case FIB_EVENT_ENTRY_REPLACE: + case FIB_EVENT_ENTRY_APPEND: + case FIB_EVENT_ENTRY_DEL: + pr_debug("%s: FIB_ENTRY ADD/DEL, event %ld\n", __func__, event); + if (info->family == AF_INET) { + struct fib_entry_notifier_info *fen_info = ptr; + + if (fen_info->fi->fib_nh_is_v6) { + NL_SET_ERR_MSG_MOD(info->extack, + "IPv6 gateway with IPv4 route is not supported"); + kfree(fib_work); + return notifier_from_errno(-EINVAL); + } + + memcpy(&fib_work->fen_info, ptr, sizeof(fib_work->fen_info)); + /* Take referece on fib_info to prevent it from being + * freed while work is queued. Release it afterwards. + */ + fib_info_hold(fib_work->fen_info.fi); + + } else if (info->family == AF_INET6) { + //struct fib6_entry_notifier_info *fen6_info = ptr; + pr_warn("%s: FIB_RULE ADD/DEL for IPv6 not supported\n", __func__); + kfree(fib_work); + return NOTIFY_DONE; + } + break; + + case FIB_EVENT_RULE_ADD: + case FIB_EVENT_RULE_DEL: + pr_debug("%s: FIB_RULE ADD/DEL, event: %ld\n", __func__, event); + memcpy(&fib_work->fr_info, ptr, sizeof(fib_work->fr_info)); + fib_rule_get(fib_work->fr_info.rule); + break; + } + + queue_work(priv->wq, &fib_work->work); + + return NOTIFY_DONE; +} + +static irqreturn_t rtldsa_switch_irq(int irq, void *dev_id) +{ + struct rtl838x_switch_priv *priv; + struct dsa_switch *ds = dev_id; + u64 link, ports; + + priv = ds->priv; + ports = priv->r->get_port_reg_le(priv->r->isr_port_link_sts_chg); + priv->r->set_port_reg_le(ports, priv->r->isr_port_link_sts_chg); + + /* read latched */ + link = priv->r->get_port_reg_le(priv->r->mac_link_sts); + link = priv->r->get_port_reg_le(priv->r->mac_link_sts); + + for (int port = 0; port < priv->cpu_port; port++) + if (ports & BIT_ULL(port)) + dsa_port_phylink_mac_change(ds, port, link & BIT_ULL(port)); + + return IRQ_HANDLED; +} + +/* + * TODO: This check is usually built into the DSA initialization functions. After carving + * out the mdio driver from the ethernet driver, there are two drivers that must be loaded + * before the DSA setup can start. This driver has severe issues with handling of deferred + * probing. For now provide this function for early dependency checks. + */ +static int rtldsa_ethernet_loaded(struct platform_device *pdev) +{ + struct platform_device *eth_pdev; + struct device_node *port_np; + struct device_node *eth_np; + int ret = -EPROBE_DEFER; + + for_each_node_with_property(port_np, "ethernet") { + eth_np = of_parse_phandle(port_np, "ethernet", 0); + if (!eth_np) + continue; + + eth_pdev = of_find_device_by_node(eth_np); + of_node_put(eth_np); + + if (!eth_pdev) + continue; + + if (eth_pdev->dev.driver) + ret = 0; + + put_device(ð_pdev->dev); + } + + return ret; +} + +static int rtl83xx_sw_probe(struct platform_device *pdev) +{ + struct rtl838x_switch_priv *priv; + struct device *dev = &pdev->dev; + u64 bpdu_mask; + int err = 0; + + pr_debug("Probing RTL838X switch device\n"); + if (!pdev->dev.of_node) { + dev_err(dev, "No DT found\n"); + return -EINVAL; + } + + err = rtldsa_ethernet_loaded(pdev); + if (err) + return err; + + /* Initialize access to RTL switch tables */ + rtl_table_init(); + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); + + if (!priv->ds) + return -ENOMEM; + priv->ds->dev = dev; + priv->ds->priv = priv; + priv->ds->ops = &rtldsa_83xx_switch_ops; + priv->ds->needs_standalone_vlan_filtering = true; + priv->dev = dev; + dev_set_drvdata(dev, priv); + + err = devm_mutex_init(dev, &priv->reg_mutex); + if (err) + return err; + + err = devm_mutex_init(dev, &priv->counters_lock); + if (err) + return err; + + priv->r = device_get_match_data(&pdev->dev); + priv->family_id = soc_info.family; + priv->id = soc_info.id; + switch (soc_info.family) { + case RTL8380_FAMILY_ID: + priv->ds->ops = &rtldsa_83xx_switch_ops; + priv->cpu_port = RTL838X_CPU_PORT; + priv->port_mask = 0x1f; + priv->port_width = 1; + priv->fib_entries = 8192; + priv->ds->num_lag_ids = 8; + priv->l2_bucket_size = 4; + priv->n_mst = 64; + break; + case RTL8390_FAMILY_ID: + priv->ds->ops = &rtldsa_83xx_switch_ops; + priv->cpu_port = RTL839X_CPU_PORT; + priv->port_mask = 0x3f; + priv->port_width = 2; + priv->fib_entries = 16384; + priv->ds->num_lag_ids = 16; + priv->l2_bucket_size = 4; + priv->n_mst = 256; + break; + case RTL9300_FAMILY_ID: + priv->ds->ops = &rtldsa_93xx_switch_ops; + priv->cpu_port = RTL930X_CPU_PORT; + priv->port_mask = 0x1f; + priv->port_width = 1; + priv->fib_entries = 16384; + priv->ds->num_lag_ids = 16; + sw_w32(0, RTL930X_ST_CTRL); + priv->l2_bucket_size = 8; + priv->n_mst = 64; + break; + case RTL9310_FAMILY_ID: + priv->ds->ops = &rtldsa_93xx_switch_ops; + priv->cpu_port = RTL931X_CPU_PORT; + priv->port_mask = 0x3f; + priv->port_width = 2; + priv->fib_entries = 16384; + priv->ds->num_lag_ids = 16; + sw_w32(0, RTL931x_ST_CTRL); + priv->l2_bucket_size = 8; + priv->n_mst = 128; + break; + } + priv->ds->num_ports = priv->cpu_port + 1; + priv->irq_mask = GENMASK_ULL(priv->cpu_port - 1, 0); + + err = rtl83xx_mdio_probe(priv); + if (err) { + /* Probing fails the 1st time because of missing ethernet driver + * initialization. Use this to disable traffic in case the bootloader left if on + */ + return err; + } + + priv->msts = devm_kcalloc(priv->dev, + priv->n_mst - 1, sizeof(struct rtldsa_mst), + GFP_KERNEL); + if (!priv->msts) + return -ENOMEM; + + priv->wq = create_singlethread_workqueue("rtl83xx"); + if (!priv->wq) { + dev_err(dev, "Error creating workqueue: %d\n", err); + return -ENOMEM; + } + + err = dsa_register_switch(priv->ds); + if (err) { + dev_err(dev, "Error registering switch: %d\n", err); + goto err_register_switch; + } + + /* dsa_to_port returns dsa_port from the port list in + * dsa_switch_tree, the tree is built when the switch + * is registered by dsa_register_switch + */ + for (int i = 0; i <= priv->cpu_port; i++) + priv->ports[i].dp = dsa_to_port(priv->ds, i); + + /* Enable link and media change interrupts. Are the SERDES masks needed? */ + sw_w32_mask(0, 3, priv->r->isr_glb_src); + + priv->r->set_port_reg_le(priv->irq_mask, priv->r->isr_port_link_sts_chg); + priv->r->set_port_reg_le(priv->irq_mask, priv->r->imr_port_link_sts_chg); + + priv->link_state_irq = platform_get_irq(pdev, 0); + pr_info("LINK state irq: %d\n", priv->link_state_irq); + err = request_irq(priv->link_state_irq, rtldsa_switch_irq, + IRQF_SHARED, "rtldsa-link-state", priv->ds); + if (err) { + dev_err(dev, "Error setting up switch interrupt.\n"); + /* Need to free allocated switch here */ + } + + /* Enable interrupts for switch, on RTL931x, the IRQ is always on globally */ + if (soc_info.family != RTL9310_FAMILY_ID) + sw_w32(0x1, priv->r->imr_glb); + + rtl83xx_get_l2aging(priv); + + if (priv->r->qos_init) + priv->r->qos_init(priv); + + if (priv->r->l3_setup) + priv->r->l3_setup(priv); + + /* Clear all destination ports for mirror groups */ + for (int i = 0; i < 4; i++) + priv->mirror_group_ports[i] = -1; + + /* Initialize hash table for L3 routing */ + rhltable_init(&priv->routes, &route_ht_params); + + /* Register netevent notifier callback to catch notifications about neighboring + * changes to update nexthop entries for L3 routing. + */ + priv->ne_nb.notifier_call = rtl83xx_netevent_event; + if (register_netevent_notifier(&priv->ne_nb)) { + priv->ne_nb.notifier_call = NULL; + dev_err(dev, "Failed to register netevent notifier\n"); + goto err_register_ne_nb; + } + + priv->fib_nb.notifier_call = rtl83xx_fib_event; + + /* Register Forwarding Information Base notifier to offload routes where + * possible + * Only FIBs pointing to our own netdevs are programmed into + * the device, so no need to pass a callback. + */ + err = register_fib_notifier(&init_net, &priv->fib_nb, NULL, NULL); + if (err) + goto err_register_fib_nb; + + /* TODO: put this into l2_setup() */ + switch (soc_info.family) { + default: + /* Flood BPDUs to all ports including cpu-port */ + bpdu_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x1FFFFFFF : 0x1FFFFFFFFFFFFF; + priv->r->set_port_reg_be(bpdu_mask, priv->r->rma_bpdu_fld_pmask); + + /* TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs */ + sw_w32(7, priv->r->spcl_trap_eapol_ctrl); + + rtl838x_dbgfs_init(priv); + break; + case RTL9300_FAMILY_ID: + case RTL9310_FAMILY_ID: + rtl930x_dbgfs_init(priv); + break; + } + + if (priv->r->lag_switch_init) + priv->r->lag_switch_init(priv); + + return 0; + +err_register_fib_nb: + unregister_netevent_notifier(&priv->ne_nb); +err_register_ne_nb: + dsa_switch_shutdown(priv->ds); +err_register_switch: + destroy_workqueue(priv->wq); + + return err; +} + +void rtldsa_93xx_lag_switch_init(struct rtl838x_switch_priv *priv) +{ + u32 trk_ctrlmask = 0; + u32 algomask; + + trk_ctrlmask |= RTL93XX_TRK_CTRL_NON_TMN_TUNNEL_HASH_SEL; + trk_ctrlmask |= RTL93XX_TRK_CTRL_TRK_STAND_ALONE_MODE; + trk_ctrlmask |= RTL93XX_TRK_CTRL_LOCAL_FIRST; + + sw_w32(trk_ctrlmask, priv->r->trk_ctrl); + + /* Setup NETDEV_LAG_HASH_L2 on slot 0 */ + algomask = TRUNK_DISTRIBUTION_ALGO_SMAC_BIT | + TRUNK_DISTRIBUTION_ALGO_DMAC_BIT; + priv->r->lag_set_distribution_algorithm(priv, 0, RTL93XX_HASH_MASK_INDEX_L2, algomask); + + /* Setup NETDEV_LAG_HASH_L23 on slot 1 */ + algomask = TRUNK_DISTRIBUTION_ALGO_SMAC_BIT | + TRUNK_DISTRIBUTION_ALGO_DMAC_BIT | + TRUNK_DISTRIBUTION_ALGO_SIP_BIT | + TRUNK_DISTRIBUTION_ALGO_DIP_BIT; + priv->r->lag_set_distribution_algorithm(priv, 0, RTL93XX_HASH_MASK_INDEX_L23, algomask); +} + +static void rtl83xx_sw_remove(struct platform_device *pdev) +{ + struct rtl838x_switch_priv *priv = platform_get_drvdata(pdev); + + if (!priv) + return; + + /* TODO: */ + pr_debug("Removing platform driver for rtl83xx-sw\n"); + + /* unregister notifiers which will create workqueue entries with + * references to the switch structures. Also stop self-arming delayed + * work items to avoid them still accessing the DSA structures + * when they are getting shut down. + */ + unregister_fib_notifier(&init_net, &priv->fib_nb); + unregister_netevent_notifier(&priv->ne_nb); + cancel_delayed_work_sync(&priv->counters_work); + + dsa_switch_shutdown(priv->ds); + + destroy_workqueue(priv->wq); + + dev_set_drvdata(&pdev->dev, NULL); +} + +static const struct of_device_id rtl83xx_switch_of_ids[] = { + { + .compatible = "realtek,rtl8380-switch", + .data = &rtldsa_838x_cfg, + }, + { + .compatible = "realtek,rtl8392-switch", + .data = &rtldsa_839x_cfg, + }, + { + .compatible = "realtek,rtl9301-switch", + .data = &rtldsa_930x_cfg, + }, + { + .compatible = "realtek,rtl9311-switch", + .data = &rtldsa_931x_cfg, + }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids); + +static struct platform_driver rtl83xx_switch_driver = { + .probe = rtl83xx_sw_probe, + .remove = rtl83xx_sw_remove, + .driver = { + .name = "rtl83xx-switch", + .pm = NULL, + .of_match_table = rtl83xx_switch_of_ids, + }, +}; + +module_platform_driver(rtl83xx_switch_driver); + +MODULE_AUTHOR("B. Koblitz"); +MODULE_DESCRIPTION("RTL83XX SoC Switch Driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/debugfs.c new file mode 100644 index 0000000000..e8085eb709 --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/debugfs.c @@ -0,0 +1,977 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include "rtl83xx.h" + +#define RTL838X_DRIVER_NAME "rtl838x" + +#define RTL8390_LED_GLB_CTRL (0x00E4) +#define RTL8390_LED_SET_2_3_CTRL (0x00E8) +#define RTL8390_LED_SET_0_1_CTRL (0x00EC) +#define RTL8390_LED_COPR_SET_SEL_CTRL(p) (0x00F0 + (((p >> 4) << 2))) +#define RTL8390_LED_FIB_SET_SEL_CTRL(p) (0x0100 + (((p >> 4) << 2))) +#define RTL8390_LED_COPR_PMASK_CTRL(p) (0x0110 + (((p >> 5) << 2))) +#define RTL8390_LED_FIB_PMASK_CTRL(p) (0x00118 + (((p >> 5) << 2))) +#define RTL8390_LED_COMBO_CTRL(p) (0x0120 + (((p >> 5) << 2))) +#define RTL8390_LED_SW_CTRL (0x0128) +#define RTL8390_LED_SW_P_EN_CTRL(p) (0x012C + (((p / 10) << 2))) +#define RTL8390_LED_SW_P_CTRL(p) (0x0144 + (((p) << 2))) + +#define RTL838X_MIR_QID_CTRL(grp) (0xAD44 + (((grp) << 2))) +#define RTL838X_MIR_RSPAN_VLAN_CTRL(grp) (0xA340 + (((grp) << 2))) +#define RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(grp) (0xAA70 + (((grp) << 2))) +#define RTL838X_MIR_RSPAN_TX_CTRL (0xA350) +#define RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL (0xAA80) +#define RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL (0xAA84) +#define RTL839X_MIR_RSPAN_VLAN_CTRL(grp) (0xA340 + (((grp) << 2))) +#define RTL839X_MIR_RSPAN_TX_CTRL (0x69b0) +#define RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL (0x2550) +#define RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL (0x2554) +#define RTL839X_MIR_SAMPLE_RATE_CTRL (0x2558) + +#define RTL838X_STAT_PRVTE_DROP_COUNTERS (0x6A00) +#define RTL839X_STAT_PRVTE_DROP_COUNTERS (0x3E00) +#define RTL930X_STAT_PRVTE_DROP_COUNTERS (0xB5B8) +#define RTL931X_STAT_PRVTE_DROP_COUNTERS (0xd800) + +const char *rtl838x_drop_cntr[] = { + "ALE_TX_GOOD_PKTS", "MAC_RX_DROP", "ACL_FWD_DROP", "HW_ATTACK_PREVENTION_DROP", + "RMA_DROP", "VLAN_IGR_FLTR_DROP", "INNER_OUTER_CFI_EQUAL_1_DROP", "PORT_MOVE_DROP", + "NEW_SA_DROP", "MAC_LIMIT_SYS_DROP", "MAC_LIMIT_VLAN_DROP", "MAC_LIMIT_PORT_DROP", + "SWITCH_MAC_DROP", "ROUTING_EXCEPTION_DROP", "DA_LKMISS_DROP", "RSPAN_DROP", + "ACL_LKMISS_DROP", "ACL_DROP", "INBW_DROP", "IGR_METER_DROP", + "ACCEPT_FRAME_TYPE_DROP", "STP_IGR_DROP", "INVALID_SA_DROP", "SA_BLOCKING_DROP", + "DA_BLOCKING_DROP", "L2_INVALID_DPM_DROP", "MCST_INVALID_DPM_DROP", "RX_FLOW_CONTROL_DROP", + "STORM_SPPRS_DROP", "LALS_DROP", "VLAN_EGR_FILTER_DROP", "STP_EGR_DROP", + "SRC_PORT_FILTER_DROP", "PORT_ISOLATION_DROP", "ACL_FLTR_DROP", "MIRROR_FLTR_DROP", + "TX_MAX_DROP", "LINK_DOWN_DROP", "FLOW_CONTROL_DROP", "BRIDGE .1d discards" +}; + +const char *rtl839x_drop_cntr[] = { + "ALE_TX_GOOD_PKTS", "ERROR_PKTS", "EGR_ACL_DROP", "EGR_METER_DROP", + "OAM", "CFM", "VLAN_IGR_FLTR", "VLAN_ERR", + "INNER_OUTER_CFI_EQUAL_1", "VLAN_TAG_FORMAT", "SRC_PORT_SPENDING_TREE", "INBW", + "RMA", "HW_ATTACK_PREVENTION", "PROTO_STORM", "MCAST_SA", + "IGR_ACL_DROP", "IGR_METER_DROP", "DFLT_ACTION_FOR_MISS_ACL_AND_C2SC", "NEW_SA", + "PORT_MOVE", "SA_BLOCKING", "ROUTING_EXCEPTION", "SRC_PORT_SPENDING_TREE_NON_FWDING", + "MAC_LIMIT", "UNKNOW_STORM", "MISS_DROP", "CPU_MAC_DROP", + "DA_BLOCKING", "SRC_PORT_FILTER_BEFORE_EGR_ACL", "VLAN_EGR_FILTER", "SPANNING_TRE", + "PORT_ISOLATION", "OAM_EGRESS_DROP", "MIRROR_ISOLATION", "MAX_LEN_BEFORE_EGR_ACL", + "SRC_PORT_FILTER_BEFORE_MIRROR", "MAX_LEN_BEFORE_MIRROR", "SPECIAL_CONGEST_BEFORE_MIRROR", + "LINK_STATUS_BEFORE_MIRROR", + "WRED_BEFORE_MIRROR", "MAX_LEN_AFTER_MIRROR", "SPECIAL_CONGEST_AFTER_MIRROR", + "LINK_STATUS_AFTER_MIRROR", + "WRED_AFTER_MIRROR" +}; + +const char *rtl930x_drop_cntr[] = { + "OAM_PARSER", "UC_RPF", "DEI_CFI", "MAC_IP_SUBNET_BASED_VLAN", "VLAN_IGR_FILTER", + "L2_UC_MC", "IPV_IP6_MC_BRIDGE", "PTP", "USER_DEF_0_3", "RESERVED", + "RESERVED1", "RESERVED2", "BPDU_RMA", "LACP", "LLDP", + "EAPOL", "XX_RMA", "L3_IPUC_NON_IP", "IP4_IP6_HEADER_ERROR", "L3_BAD_IP", + "L3_DIP_DMAC_MISMATCH", "IP4_IP_OPTION", "IP_UC_MC_ROUTING_LOOK_UP_MISS", "L3_DST_NULL_INTF", + "L3_PBR_NULL_INTF", + "HOST_NULL_INTF", "ROUTE_NULL_INTF", "BRIDGING_ACTION", "ROUTING_ACTION", "IPMC_RPF", + "L2_NEXTHOP_AGE_OUT", "L3_UC_TTL_FAIL", "L3_MC_TTL_FAIL", "L3_UC_MTU_FAIL", "L3_MC_MTU_FAIL", + "L3_UC_ICMP_REDIR", "IP6_MLD_OTHER_ACT", "ND", "IP_MC_RESERVED", "IP6_HBH", + "INVALID_SA", "L2_HASH_FULL", "NEW_SA", "PORT_MOVE_FORBID", "STATIC_PORT_MOVING", + "DYNMIC_PORT_MOVING", "L3_CRC", "MAC_LIMIT", "ATTACK_PREVENT", "ACL_FWD_ACTION", + "OAMPDU", "OAM_MUX", "TRUNK_FILTER", "ACL_DROP", "IGR_BW", + "ACL_METER", "VLAN_ACCEPT_FRAME_TYPE", "MSTP_SRC_DROP_DISABLED_BLOCKING", "SA_BLOCK", "DA_BLOCK", + "STORM_CONTROL", "VLAN_EGR_FILTER", "MSTP_DESTINATION_DROP", "SRC_PORT_FILTER", "PORT_ISOLATION", + "TX_MAX_FRAME_SIZE", "EGR_LINK_STATUS", "MAC_TX_DISABLE", "MAC_PAUSE_FRAME", "MAC_RX_DROP", + "MIRROR_ISOLATE", "RX_FC", "EGR_QUEUE", "HSM_RUNOUT", "ROUTING_DISABLE", "INVALID_L2_NEXTHOP_ENTRY", + "L3_MC_SRC_FLT", "CPUTAG_FLT", "FWD_PMSK_NULL", "IPUC_ROUTING_LOOKUP_MISS", "MY_DEV_DROP", + "STACK_NONUC_BLOCKING_PMSK", "STACK_PORT_NOT_FOUND", "ACL_LOOPBACK_DROP", "IP6_ROUTING_EXT_HEADER" +}; + +const char *rtl931x_drop_cntr[] = { + "ALE_RX_GOOD_PKTS", "RX_MAX_FRAME_SIZE", "MAC_RX_DROP", "OPENFLOW_IP_MPLS_TTL", "OPENFLOW_TBL_MISS", + "IGR_BW", "SPECIAL_CONGEST", "EGR_QUEUE", "RESERVED", "EGR_LINK_STATUS", "STACK_UCAST_NONUCAST_TTL", /* 10 */ + "STACK_NONUC_BLOCKING_PMSK", "L2_CRC", "SRC_PORT_FILTER", "PARSER_PACKET_TOO_LONG", "PARSER_MALFORM_PACKET", + "MPLS_OVER_2_LBL", "EACL_METER", "IACL_METER", "PROTO_STORM", "INVALID_CAPWAP_HEADER", /* 20 */ + "MAC_IP_SUBNET_BASED_VLAN", "OAM_PARSER", "UC_MC_RPF", "IP_MAC_BINDING_MATCH_MISMATCH", "SA_BLOCK", + "TUNNEL_IP_ADDRESS_CHECK", "EACL_DROP", "IACL_DROP", "ATTACK_PREVENT", "SYSTEM_PORT_LIMIT_LEARN", /* 30 */ + "OAMPDU", "CCM_RX", "CFM_UNKNOWN_TYPE", "LBM_LBR_LTM_LTR", "Y_1731", "VLAN_LIMIT_LEARN", + "VLAN_ACCEPT_FRAME_TYPE", "CFI_1", "STATIC_DYNAMIC_PORT_MOVING", "PORT_MOVE_FORBID", /* 40 */ + "L3_CRC", "BPDU_PTP_LLDP_EAPOL_RMA", "MSTP_SRC_DROP_DISABLED_BLOCKING", "INVALID_SA", "NEW_SA", + "VLAN_IGR_FILTER", "IGR_VLAN_CONVERT", "GRATUITOUS_ARP", "MSTP_SRC_DROP", "L2_HASH_FULL", /* 50 */ + "MPLS_UNKNOWN_LBL", "L3_IPUC_NON_IP", "TTL", "MTU", "ICMP_REDIRECT", "STORM_CONTROL", "L3_DIP_DMAC_MISMATCH", + "IP4_IP_OPTION", "IP6_HBH_EXT_HEADER", "IP4_IP6_HEADER_ERROR", /* 60 */ + "ROUTING_IP_ADDR_CHECK", "ROUTING_EXCEPTION", "DA_BLOCK", "OAM_MUX", "PORT_ISOLATION", "VLAN_EGR_FILTER", + "MIRROR_ISOLATE", "MSTP_DESTINATION_DROP", "L2_MC_BRIDGE", "IP_UC_MC_ROUTING_LOOK_UP_MISS", /* 70 */ + "L2_UC", "L2_MC", "IP4_MC", "IP6_MC", "L3_UC_MC_ROUTE", "UNKNOWN_L2_UC_FLPM", "BC_FLPM", + "VLAN_PRO_UNKNOWN_L2_MC_FLPM", "VLAN_PRO_UNKNOWN_IP4_MC_FLPM", "VLAN_PROFILE_UNKNOWN_IP6_MC_FLPM", /* 80 */ +}; + +static ssize_t rtl838x_common_read(char __user *buffer, size_t count, + loff_t *ppos, unsigned int value) +{ + char *buf; + ssize_t len; + + if (*ppos != 0) + return 0; + + buf = kasprintf(GFP_KERNEL, "0x%08x\n", value); + if (!buf) + return -ENOMEM; + + if (count < strlen(buf)) { + kfree(buf); + return -ENOSPC; + } + + len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf)); + kfree(buf); + + return len; +} + +static ssize_t rtl838x_common_write(const char __user *buffer, size_t count, + loff_t *ppos, unsigned int *value) +{ + char b[32]; + ssize_t len; + int ret; + + if (*ppos != 0) + return -EINVAL; + + if (count >= sizeof(b)) + return -ENOSPC; + + len = simple_write_to_buffer(b, sizeof(b) - 1, ppos, + buffer, count); + if (len < 0) + return len; + + b[len] = '\0'; + ret = kstrtouint(b, 16, value); + if (ret) + return -EIO; + + return len; +} + +static ssize_t stp_state_read(struct file *filp, char __user *buffer, size_t count, + loff_t *ppos) +{ + struct rtldsa_port *p = filp->private_data; + struct dsa_switch *ds = p->dp->ds; + int state = rtldsa_port_get_stp_state(ds->priv, p->dp->index); + + if (state < 0) + return state; + + return rtl838x_common_read(buffer, count, ppos, (u32)state); +} + +static ssize_t stp_state_write(struct file *filp, const char __user *buffer, + size_t count, loff_t *ppos) +{ + struct rtldsa_port *p = filp->private_data; + u32 value; + size_t res = rtl838x_common_write(buffer, count, ppos, &value); + + if (res < 0) + return res; + + rtldsa_port_stp_state_set(p->dp->ds, p->dp->index, (u8)value); + + return res; +} + +static const struct file_operations stp_state_fops = { + .owner = THIS_MODULE, + .open = simple_open, + .read = stp_state_read, + .write = stp_state_write, +}; + +static ssize_t drop_counter_read(struct file *filp, char __user *buffer, size_t count, + loff_t *ppos) +{ + struct rtl838x_switch_priv *priv = filp->private_data; + const char **d; + u32 v; + char *buf; + int n = 0, len, offset; + int num; + + switch (priv->family_id) { + case RTL8380_FAMILY_ID: + d = rtl838x_drop_cntr; + offset = RTL838X_STAT_PRVTE_DROP_COUNTERS; + num = ARRAY_SIZE(rtl838x_drop_cntr); + BUILD_BUG_ON(num != 40); + break; + case RTL8390_FAMILY_ID: + d = rtl839x_drop_cntr; + offset = RTL839X_STAT_PRVTE_DROP_COUNTERS; + num = ARRAY_SIZE(rtl839x_drop_cntr); + BUILD_BUG_ON(num != 45); + break; + case RTL9300_FAMILY_ID: + d = rtl930x_drop_cntr; + offset = RTL930X_STAT_PRVTE_DROP_COUNTERS; + num = ARRAY_SIZE(rtl930x_drop_cntr); + BUILD_BUG_ON(num != 85); + break; + case RTL9310_FAMILY_ID: + d = rtl931x_drop_cntr; + offset = RTL931X_STAT_PRVTE_DROP_COUNTERS; + num = ARRAY_SIZE(rtl931x_drop_cntr); + BUILD_BUG_ON(num != 81); + break; + } + + buf = kmalloc(30 * num, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + for (int i = 0; i < num; i++) { + v = sw_r32(offset + (i << 2)) & 0xffff; + n += sprintf(buf + n, "%s: %d\n", d[i], v); + } + + if (count < strlen(buf)) { + kfree(buf); + return -ENOSPC; + } + + len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf)); + kfree(buf); + + return len; +} + +static const struct file_operations drop_counter_fops = { + .owner = THIS_MODULE, + .open = simple_open, + .read = drop_counter_read, +}; + +static void l2_table_print_entry(struct seq_file *m, struct rtl838x_switch_priv *priv, + struct rtl838x_l2_entry *e) +{ + u64 portmask; + + if (e->type == L2_UNICAST) { + seq_puts(m, "L2_UNICAST\n"); + + seq_printf(m, " mac %02x:%02x:%02x:%02x:%02x:%02x vid %u rvid %u\n", + e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5], + e->vid, e->rvid); + + seq_printf(m, " port %d age %d", e->port, e->age); + if (e->is_trunk) { + seq_printf(m, " trunk %d trunk_members: 0x%08llx non-primary: 0x%08llx primary-port: %d", + e->trunk, + priv->lags_port_members[e->trunk], + priv->lag_non_primary, + priv->lag_primary[e->trunk]); + } + if (e->is_static) + seq_puts(m, " static"); + if (e->block_da) + seq_puts(m, " block_da"); + if (e->block_sa) + seq_puts(m, " block_sa"); + if (e->suspended) + seq_puts(m, " suspended"); + if (e->next_hop) + seq_printf(m, " next_hop route_id %u", e->nh_route_id); + seq_puts(m, "\n"); + + } else { + if (e->type == L2_MULTICAST) { + seq_puts(m, "L2_MULTICAST\n"); + + seq_printf(m, " mac %02x:%02x:%02x:%02x:%02x:%02x vid %u rvid %u\n", + e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5], + e->vid, e->rvid); + } + + if (e->type == IP4_MULTICAST || e->type == IP6_MULTICAST) { + seq_puts(m, (e->type == IP4_MULTICAST) ? + "IP4_MULTICAST\n" : "IP6_MULTICAST\n"); + + seq_printf(m, " gip %08x sip %08x vid %u rvid %u\n", + e->mc_gip, e->mc_sip, e->vid, e->rvid); + } + + portmask = priv->r->read_mcast_pmask(e->mc_portmask_index); + seq_printf(m, " index %u ports", e->mc_portmask_index); + for (int i = 0; i < 64; i++) { + if (portmask & BIT_ULL(i)) + seq_printf(m, " %d", i); + } + seq_puts(m, "\n"); + } + + seq_puts(m, "\n"); +} + +static int l2_table_show(struct seq_file *m, void *v) +{ + struct rtl838x_switch_priv *priv = m->private; + struct rtl838x_l2_entry e; + int bucket, index; + + mutex_lock(&priv->reg_mutex); + + for (int i = 0; i < priv->fib_entries; i++) { + bucket = i >> 2; + index = i & 0x3; + priv->r->read_l2_entry_using_hash(bucket, index, &e); + + if (!e.valid) + continue; + + seq_printf(m, "Hash table bucket %d index %d ", bucket, index); + l2_table_print_entry(m, priv, &e); + + if (!((i + 1) % 64)) + cond_resched(); + } + + for (int i = 0; i < 64; i++) { + priv->r->read_cam(i, &e); + + if (!e.valid) + continue; + + seq_printf(m, "CAM index %d ", i); + l2_table_print_entry(m, priv, &e); + } + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int l2_table_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, l2_table_show, inode->i_private); +} + +static const struct file_operations l2_table_fops = { + .owner = THIS_MODULE, + .open = l2_table_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int rtldsa_pmsks_table_raw_show(struct seq_file *m, void *v) +{ + struct rtl838x_switch_priv *priv = m->private; + u64 all_ports; + + mutex_lock(&priv->reg_mutex); + + for (int i = 0; i < MAX_MC_PMASKS; i += 4) { + seq_printf(m, "%04i: ", i); + for (int j = 0; j < 4; j++) { + bool is_set = test_bit(i + j, priv->mc_group_bm); + seq_printf(m, " %c0x%016llx%c", is_set ? ' ' : '(', + priv->r->read_mcast_pmask(i + j), + is_set ? ' ' : ')'); + } + seq_printf(m, "\n"); + } + + all_ports = priv->r->read_mcast_pmask(MC_PMASK_ALL_PORTS_IDX); + seq_printf(m, "MC_PMASK_ALL_PORTS (%i): 0x%016llx\n", + MC_PMASK_ALL_PORTS_IDX, all_ports); + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtldsa_pmsks_table_raw_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, rtldsa_pmsks_table_raw_show, inode->i_private); +} + +static const struct file_operations rtldsa_pmsks_table_raw_fops = { + .owner = THIS_MODULE, + .open = rtldsa_pmsks_table_raw_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int rtldsa_pmsks_table_show(struct seq_file *m, void *v) +{ + struct rtl838x_switch_priv *priv = m->private; + u64 ports; + + mutex_lock(&priv->reg_mutex); + + for (int i = 0; i < MC_PMASK_ALL_PORTS_IDX; i++) { + if (!test_bit(i, priv->mc_group_bm)) + continue; + + ports = priv->r->read_mcast_pmask(i); + seq_printf(m, "%04i:", i); + for (int j = 0; j < sizeof(ports)*8; j++) + if (ports & BIT_ULL(j)) + seq_printf(m, " %i", j); + seq_printf(m, "\n"); + } + + ports = priv->r->read_mcast_pmask(MC_PMASK_ALL_PORTS_IDX); + seq_printf(m, "MC_PMASK_ALL_PORTS (%i):", MC_PMASK_ALL_PORTS_IDX); + for (int i = 0; i < sizeof(ports)*8; i++) + if (ports & BIT_ULL(i)) + seq_printf(m, " %i", i); + seq_printf(m, "\n"); + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtldsa_pmsks_table_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, rtldsa_pmsks_table_show, inode->i_private); +} + +static const struct file_operations rtldsa_pmsks_table_fops = { + .owner = THIS_MODULE, + .open = rtldsa_pmsks_table_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int rtldsa_vlan_profiles_show(struct seq_file *m, void *v) +{ + struct rtl838x_switch_priv *priv = m->private; + struct rtldsa_vlan_profile profile; + int ret, profiles_max; + + if (!priv->r->vlan_profile_get) + return -ENOTSUPP; + + profiles_max = max(RTL838X_VLAN_PROFILE_MAX, RTL839X_VLAN_PROFILE_MAX); + profiles_max = max(profiles_max, RTL930X_VLAN_PROFILE_MAX); + profiles_max = max(profiles_max, RTL931X_VLAN_PROFILE_MAX); + + mutex_lock(&priv->reg_mutex); + + seq_printf(m, + "prof-idx: L2 learn | UNKN L2MC FLD PMSK (IDX) | UNKN IPMC FLD PMSK (IDX) | UNKN IPv6MC FLD PMSK (IDX)\n"); + for (int i = 0; i <= profiles_max; i++) { + ret = priv->r->vlan_profile_get(i, &profile); + if (ret < 0) + break; + + if (profile.pmsk_is_idx) + seq_printf(m, "%i: %i %03i %03i %03i\n", i, + profile.l2_learn, + profile.unkn_mc_fld.pmsks_idx.l2, + profile.unkn_mc_fld.pmsks_idx.ip, + profile.unkn_mc_fld.pmsks_idx.ip6); + else + seq_printf(m, "%i: %i 0x%016llx 0x%016llx 0x%016llx\n", i, + profile.l2_learn, + profile.unkn_mc_fld.pmsks.l2, + profile.unkn_mc_fld.pmsks.ip, + profile.unkn_mc_fld.pmsks.ip6); + } + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtldsa_vlan_profiles_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, rtldsa_vlan_profiles_show, inode->i_private); +} + +static const struct file_operations rtldsa_vlan_profiles_fops = { + .owner = THIS_MODULE, + .open = rtldsa_vlan_profiles_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int rtldsa_vlan_table_raw_show(struct seq_file *m, void *v) +{ + struct rtl838x_switch_priv *priv = m->private; + struct rtl838x_vlan_info info; + + if (!priv->r->vlan_tables_read) + return -ENOTSUPP; + + mutex_lock(&priv->reg_mutex); + + seq_printf(m, "VID: profile-index untagged-ports member-ports\n"); + + for (int i = 0; i < MAX_VLANS; i++) { + priv->r->vlan_tables_read(i, &info); + + if (!info.member_ports) + continue; + + seq_printf(m, "%i: %2i 0x%016llx 0x%016llx\n", i, + info.profile_id, + info.untagged_ports, + info.member_ports); + } + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtldsa_vlan_table_raw_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, rtldsa_vlan_table_raw_show, inode->i_private); +} + +static const struct file_operations rtldsa_vlan_table_raw_fops = { + .owner = THIS_MODULE, + .open = rtldsa_vlan_table_raw_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + + +static int rtldsa_vlan_table_show(struct seq_file *m, void *v) +{ + struct rtl838x_switch_priv *priv = m->private; + struct rtl838x_vlan_info info; + + if (!priv->r->vlan_tables_read) + return -ENOTSUPP; + + mutex_lock(&priv->reg_mutex); + + for (int i = 0; i < MAX_VLANS; i++) { + priv->r->vlan_tables_read(i, &info); + + if (!info.member_ports) + continue; + + seq_printf(m, "%i: %i |", i, info.profile_id); + for (int j = 0; j < sizeof(info.member_ports)*8; j++) + if (info.member_ports & BIT_ULL(j)) + seq_printf(m, " %i%s", j, + (info.untagged_ports & BIT_ULL(j)) ? "" : "t"); + seq_printf(m, "\n"); + } + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtldsa_vlan_table_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, rtldsa_vlan_table_show, inode->i_private); +} + +static const struct file_operations rtldsa_vlan_table_fops = { + .owner = THIS_MODULE, + .open = rtldsa_vlan_table_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static ssize_t age_out_read(struct file *filp, char __user *buffer, size_t count, + loff_t *ppos) +{ + struct rtldsa_port *p = filp->private_data; + struct dsa_switch *ds = p->dp->ds; + struct rtl838x_switch_priv *priv = ds->priv; + int value = sw_r32(priv->r->l2_port_aging_out); + + if (value < 0) + return -EINVAL; + + return rtl838x_common_read(buffer, count, ppos, (u32)value); +} + +static ssize_t age_out_write(struct file *filp, const char __user *buffer, + size_t count, loff_t *ppos) +{ + struct rtldsa_port *p = filp->private_data; + u32 value; + size_t res = rtl838x_common_write(buffer, count, ppos, &value); + + if (res < 0) + return res; + + rtldsa_port_fast_age(p->dp->ds, p->dp->index); + + return res; +} + +static const struct file_operations age_out_fops = { + .owner = THIS_MODULE, + .open = simple_open, + .read = age_out_read, + .write = age_out_write, +}; + +static ssize_t port_egress_rate_read(struct file *filp, char __user *buffer, size_t count, + loff_t *ppos) +{ + struct rtldsa_port *p = filp->private_data; + struct dsa_switch *ds = p->dp->ds; + struct rtl838x_switch_priv *priv = ds->priv; + int value; + + if (priv->family_id == RTL8380_FAMILY_ID) + value = rtl838x_get_egress_rate(priv, p->dp->index); + else + value = rtl839x_get_egress_rate(priv, p->dp->index); + + if (value < 0) + return -EINVAL; + + return rtl838x_common_read(buffer, count, ppos, (u32)value); +} + +static ssize_t port_egress_rate_write(struct file *filp, const char __user *buffer, + size_t count, loff_t *ppos) +{ + struct rtldsa_port *p = filp->private_data; + struct dsa_switch *ds = p->dp->ds; + struct rtl838x_switch_priv *priv = ds->priv; + u32 value; + size_t res = rtl838x_common_write(buffer, count, ppos, &value); + + if (res < 0) + return res; + + if (priv->family_id == RTL8380_FAMILY_ID) + rtl838x_set_egress_rate(priv, p->dp->index, value); + else + rtl839x_set_egress_rate(priv, p->dp->index, value); + + return res; +} + +static const struct file_operations port_egress_fops = { + .owner = THIS_MODULE, + .open = simple_open, + .read = port_egress_rate_read, + .write = port_egress_rate_write, +}; + +static const struct debugfs_reg32 port_ctrl_regs[] = { + { .name = "port_isolation", .offset = RTL838X_PORT_ISO_CTRL(0), }, + { .name = "mac_force_mode", .offset = RTL838X_MAC_FORCE_MODE_CTRL, }, +}; + +static void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv) +{ + debugfs_remove_recursive(priv->dbgfs_dir); + +/* kfree(priv->dbgfs_entries); */ +} + +static int rtl838x_dbgfs_port_init(struct dentry *parent, struct rtl838x_switch_priv *priv, + int port) +{ + struct dentry *port_dir; + struct debugfs_regset32 *port_ctrl_regset; + + port_dir = debugfs_create_dir(priv->ports[port].dp->name, parent); + + if (priv->family_id == RTL8380_FAMILY_ID) { + debugfs_create_x32("storm_rate_uc", 0644, port_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_UC(port))); + + debugfs_create_x32("storm_rate_mc", 0644, port_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_MC(port))); + + debugfs_create_x32("storm_rate_bc", 0644, port_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port))); + } else { + debugfs_create_x32("storm_rate_uc", 0644, port_dir, + (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_UC_0(port))); + + debugfs_create_x32("storm_rate_mc", 0644, port_dir, + (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_MC_0(port))); + + debugfs_create_x32("storm_rate_bc", 0644, port_dir, + (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_BC_0(port))); + } + + debugfs_create_u32("id", 0444, port_dir, (u32 *)&priv->ports[port].dp->index); + + port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL); + if (!port_ctrl_regset) + return -ENOMEM; + + port_ctrl_regset->regs = port_ctrl_regs; + port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs); + port_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (port << 2)); + debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset); + + debugfs_create_file("stp_state", 0600, port_dir, &priv->ports[port], &stp_state_fops); + debugfs_create_file("age_out", 0600, port_dir, &priv->ports[port], &age_out_fops); + debugfs_create_file("port_egress_rate", 0600, port_dir, &priv->ports[port], + &port_egress_fops); + return 0; +} + +static int rtl838x_dbgfs_leds(struct dentry *parent, struct rtl838x_switch_priv *priv) +{ + struct dentry *led_dir; + + led_dir = debugfs_create_dir("led", parent); + + if (priv->family_id == RTL8380_FAMILY_ID) { + debugfs_create_x32("led_glb_ctrl", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_LED_GLB_CTRL)); + debugfs_create_x32("led_mode_sel", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_LED_MODE_SEL)); + debugfs_create_x32("led_mode_ctrl", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_LED_MODE_CTRL)); + debugfs_create_x32("led_p_en_ctrl", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_LED_P_EN_CTRL)); + debugfs_create_x32("led_sw_ctrl", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_LED_SW_CTRL)); + debugfs_create_x32("led0_sw_p_en_ctrl", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_LED0_SW_P_EN_CTRL)); + debugfs_create_x32("led1_sw_p_en_ctrl", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_LED1_SW_P_EN_CTRL)); + debugfs_create_x32("led2_sw_p_en_ctrl", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_LED2_SW_P_EN_CTRL)); + for (int p = 0; p < 28; p++) { + char led_sw_p_ctrl_name[20]; + + snprintf(led_sw_p_ctrl_name, sizeof(led_sw_p_ctrl_name), + "led_sw_p_ctrl.%02d", p); + debugfs_create_x32(led_sw_p_ctrl_name, 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_LED_SW_P_CTRL_PORT(p))); + } + } else if (priv->family_id == RTL8390_FAMILY_ID) { + char port_led_name[20]; + + debugfs_create_x32("led_glb_ctrl", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL8390_LED_GLB_CTRL)); + debugfs_create_x32("led_set_2_3", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_2_3_CTRL)); + debugfs_create_x32("led_set_0_1", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_0_1_CTRL)); + for (int p = 0; p < 4; p++) { + snprintf(port_led_name, sizeof(port_led_name), "led_copr_set_sel.%1d", p); + debugfs_create_x32(port_led_name, 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_SET_SEL_CTRL(p << 4))); + snprintf(port_led_name, sizeof(port_led_name), "led_fib_set_sel.%1d", p); + debugfs_create_x32(port_led_name, 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_SET_SEL_CTRL(p << 4))); + } + debugfs_create_x32("led_copr_pmask_ctrl_0", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(0))); + debugfs_create_x32("led_copr_pmask_ctrl_1", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(32))); + debugfs_create_x32("led_fib_pmask_ctrl_0", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(0))); + debugfs_create_x32("led_fib_pmask_ctrl_1", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(32))); + debugfs_create_x32("led_combo_ctrl_0", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(0))); + debugfs_create_x32("led_combo_ctrl_1", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(32))); + debugfs_create_x32("led_sw_ctrl", 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_CTRL)); + for (int p = 0; p < 5; p++) { + snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_en_ctrl.%1d", p); + debugfs_create_x32(port_led_name, 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_EN_CTRL(p * 10))); + } + for (int p = 0; p < 28; p++) { + snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_ctrl.%02d", p); + debugfs_create_x32(port_led_name, 0644, led_dir, + (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_CTRL(p))); + } + } + return 0; +} + +void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv) +{ + struct dentry *rtl838x_dir; + struct dentry *port_dir; + struct dentry *mirror_dir; + struct debugfs_regset32 *port_ctrl_regset; + int ret; + char lag_name[10]; + char mirror_name[10]; + + pr_info("%s called\n", __func__); + rtl838x_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL); + if (!rtl838x_dir) + rtl838x_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL); + + priv->dbgfs_dir = rtl838x_dir; + + debugfs_create_x32("soc", 0444, rtl838x_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_MODEL_NAME_INFO)); + + /* Create one directory per port */ + for (int i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy) { + ret = rtl838x_dbgfs_port_init(rtl838x_dir, priv, i); + if (ret) + goto err; + } + } + + /* Create directory for CPU-port */ + port_dir = debugfs_create_dir("cpu_port", rtl838x_dir); + port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL); + if (!port_ctrl_regset) { + ret = -ENOMEM; + goto err; + } + + port_ctrl_regset->regs = port_ctrl_regs; + port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs); + port_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (priv->cpu_port << 2)); + debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset); + debugfs_create_u8("id", 0444, port_dir, &priv->cpu_port); + + /* Create entries for LAGs */ + for (int i = 0; i < priv->ds->num_lag_ids; i++) { + snprintf(lag_name, sizeof(lag_name), "lag.%02d", i); + if (priv->family_id == RTL8380_FAMILY_ID) + debugfs_create_x32(lag_name, 0644, rtl838x_dir, + (u32 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i))); + else + debugfs_create_x64(lag_name, 0644, rtl838x_dir, + (u64 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i))); + } + + /* Create directories for mirror groups */ + for (int i = 0; i < 4; i++) { + snprintf(mirror_name, sizeof(mirror_name), "mirror.%1d", i); + mirror_dir = debugfs_create_dir(mirror_name, rtl838x_dir); + if (priv->family_id == RTL8380_FAMILY_ID) { + debugfs_create_x32("ctrl", 0644, mirror_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_CTRL + i * 4)); + debugfs_create_x32("ingress_pm", 0644, mirror_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_SPM_CTRL + i * 4)); + debugfs_create_x32("egress_pm", 0644, mirror_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_DPM_CTRL + i * 4)); + debugfs_create_x32("qid", 0644, mirror_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_QID_CTRL(i))); + debugfs_create_x32("rspan_vlan", 0644, mirror_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL(i))); + debugfs_create_x32("rspan_vlan_mac", 0644, mirror_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(i))); + debugfs_create_x32("rspan_tx", 0644, mirror_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_CTRL)); + debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL)); + debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL)); + } else { + debugfs_create_x32("ctrl", 0644, mirror_dir, + (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_CTRL + i * 4)); + debugfs_create_x64("ingress_pm", 0644, mirror_dir, + (u64 *)(RTL838X_SW_BASE + RTL839X_MIR_SPM_CTRL + i * 8)); + debugfs_create_x64("egress_pm", 0644, mirror_dir, + (u64 *)(RTL838X_SW_BASE + RTL839X_MIR_DPM_CTRL + i * 8)); + debugfs_create_x32("rspan_vlan", 0644, mirror_dir, + (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_VLAN_CTRL(i))); + debugfs_create_x32("rspan_tx", 0644, mirror_dir, + (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_CTRL)); + debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir, + (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL)); + debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir, + (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL)); + debugfs_create_x64("sample_rate", 0644, mirror_dir, + (u64 *)(RTL838X_SW_BASE + RTL839X_MIR_SAMPLE_RATE_CTRL)); + } + } + + if (priv->family_id == RTL8380_FAMILY_ID) + debugfs_create_x32("bpdu_flood_mask", 0644, rtl838x_dir, + (u32 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask)); + else + debugfs_create_x64("bpdu_flood_mask", 0644, rtl838x_dir, + (u64 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask)); + + if (priv->family_id == RTL8380_FAMILY_ID) + debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_CTRL)); + else + debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir, + (u32 *)(RTL838X_SW_BASE + RTL839X_VLAN_CTRL)); + + ret = rtl838x_dbgfs_leds(rtl838x_dir, priv); + if (ret) + goto err; + + debugfs_create_file("drop_counters", 0400, rtl838x_dir, priv, &drop_counter_fops); + + debugfs_create_file("l2_table", 0400, rtl838x_dir, priv, &l2_table_fops); + + debugfs_create_file("port_masks_table_raw", 0400, rtl838x_dir, priv, + &rtldsa_pmsks_table_raw_fops); + + debugfs_create_file("port_masks_table", 0400, rtl838x_dir, priv, + &rtldsa_pmsks_table_fops); + + debugfs_create_file("vlan_profiles", 0400, rtl838x_dir, priv, + &rtldsa_vlan_profiles_fops); + + debugfs_create_file("vlan_table_raw", 0400, rtl838x_dir, priv, + &rtldsa_vlan_table_raw_fops); + + debugfs_create_file("vlan_table", 0400, rtl838x_dir, priv, + &rtldsa_vlan_table_fops); + + return; +err: + rtl838x_dbgfs_cleanup(priv); +} + +void rtl930x_dbgfs_init(struct rtl838x_switch_priv *priv) +{ + struct dentry *dbg_dir; + + pr_info("%s called\n", __func__); + dbg_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL); + if (!dbg_dir) + dbg_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL); + + priv->dbgfs_dir = dbg_dir; + + debugfs_create_file("drop_counters", 0400, dbg_dir, priv, &drop_counter_fops); + + debugfs_create_file("l2_table", 0400, dbg_dir, priv, &l2_table_fops); + + debugfs_create_file("port_masks_table_raw", 0400, dbg_dir, priv, + &rtldsa_pmsks_table_raw_fops); + + debugfs_create_file("port_masks_table", 0400, dbg_dir, priv, + &rtldsa_pmsks_table_fops); + + debugfs_create_file("vlan_profiles", 0400, dbg_dir, priv, + &rtldsa_vlan_profiles_fops); + + debugfs_create_file("vlan_table_raw", 0400, dbg_dir, priv, + &rtldsa_vlan_table_raw_fops); + + debugfs_create_file("vlan_table", 0400, dbg_dir, priv, + &rtldsa_vlan_table_fops); +} diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c new file mode 100644 index 0000000000..ca3252c1ed --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c @@ -0,0 +1,2744 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include + +#include "rtl83xx.h" + +static const u8 ipv4_ll_mcast_addr_base[ETH_ALEN] = { + 0x01, 0x00, 0x5e, 0x00, 0x00, 0x00 +}; + +static const u8 ipv4_ll_mcast_addr_mask[ETH_ALEN] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 +}; + +static const u8 ipv6_all_hosts_mcast_addr_base[ETH_ALEN] = { + 0x33, 0x33, 0x00, 0x00, 0x00, 0x01 +}; + +static const u8 ipv6_all_hosts_mcast_addr_mask[ETH_ALEN] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff +}; + +static void rtldsa_init_counters(struct rtl838x_switch_priv *priv); +static void rtldsa_port_xstp_state_set(struct rtl838x_switch_priv *priv, int port, + u8 state, u16 mst_slot); + +static void rtldsa_83xx_init_stats(struct rtl838x_switch_priv *priv) +{ + mutex_lock(&priv->reg_mutex); + + /* Enable statistics module: all counters plus debug. + * On RTL839x all counters are enabled by default + */ + if (priv->family_id == RTL8380_FAMILY_ID) + sw_w32_mask(0, 3, RTL838X_STAT_CTRL); + + /* Reset statistics counters */ + sw_w32_mask(0, 1, priv->r->stat_rst); + + mutex_unlock(&priv->reg_mutex); +} + +static void rtldsa_enable_phy_polling(struct rtl838x_switch_priv *priv) +{ + u64 v = 0; + + msleep(1000); + /* Enable all ports with a PHY, including the SFP-ports */ + for (int i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy || priv->ports[i].pcs) + v |= BIT_ULL(i); + } + + pr_info("%s: %16llx\n", __func__, v); + priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl); + + /* PHY update complete, there is no global PHY polling enable bit on the 93xx */ + if (priv->family_id == RTL8390_FAMILY_ID) + sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL); +} + +/* DSA callbacks */ + +static enum dsa_tag_protocol rtldsa_get_tag_protocol(struct dsa_switch *ds, + int port, + enum dsa_tag_protocol mprot) +{ + /* The switch does not tag the frames, instead internally the header + * structure for each packet is tagged accordingly. + */ + return DSA_TAG_PROTO_RTL_OTTO; +} + +static void rtldsa_vlan_set_pvid(struct rtl838x_switch_priv *priv, + int port, int pvid) +{ + /* Set both inner and outer PVID of the port */ + priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, pvid); + priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, pvid); + priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER, + PBVLAN_MODE_UNTAG_AND_PRITAG); + priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER, + PBVLAN_MODE_UNTAG_AND_PRITAG); + + priv->ports[port].pvid = pvid; +} + +static void rtldsa_83xx_mc_pmasks_setup(struct rtl838x_switch_priv *priv) +{ + /* RTL8380 and RTL8390 use an index into the portmask table to set the + * unknown multicast portmask, setup a default at a safe location + * On RTL93XX, the portmask is directly set in the profile, + * see e.g. rtl9300_vlan_profile_setup + */ + priv->r->write_mcast_pmask(MC_PMASK_ALL_PORTS_IDX, ~0); +} + +/* Initialize all VLANS */ +static void rtldsa_vlan_setup(struct rtl838x_switch_priv *priv) +{ + struct rtl838x_vlan_info info; + + pr_info("In %s\n", __func__); + + priv->r->vlan_profile_setup(0); + priv->r->vlan_profile_dump(priv, 0); + + info.fid = 0; /* Default Forwarding ID / MSTI */ + info.hash_uc_fid = false; /* Do not build the L2 lookup hash with FID, but VID */ + info.hash_mc_fid = false; /* Do the same for Multicast packets */ + info.profile_id = 0; /* Use default Vlan Profile 0 */ + info.member_ports = 0; /* Initially no port members */ + if (priv->family_id == RTL9310_FAMILY_ID) { + info.if_id = 0; + info.multicast_grp_mask = 0; + info.l2_tunnel_list_id = -1; + } + + /* Initialize normal VLANs 1-4095 */ + for (int i = 1; i < MAX_VLANS; i++) + priv->r->vlan_set_tagged(i, &info); + + /* + * Initialize the special VLAN 0 and reset PVIDs. The CPU port PVID + * is applied to packets from the CPU for untagged destinations, + * regardless if the actual ingress VID. Any port with untagged + * egress VLAN(s) must therefore be a member of VLAN 0 to support + * CPU port as ingress when VLAN filtering is enabled. + */ + for (int i = 0; i <= priv->cpu_port; i++) { + rtldsa_vlan_set_pvid(priv, i, 0); + info.member_ports |= BIT_ULL(i); + } + priv->r->vlan_set_tagged(0, &info); + + /* Set forwarding action based on inner VLAN tag */ + for (int i = 0; i < priv->cpu_port; i++) + priv->r->vlan_fwd_on_inner(i, true); +} + +static void rtldsa_setup_bpdu_traps(struct rtl838x_switch_priv *priv) +{ + for (int i = 0; i < priv->cpu_port; i++) + priv->r->set_receive_management_action(i, BPDU, TRAP2CPU); +} + +static void rtldsa_setup_lldp_traps(struct rtl838x_switch_priv *priv) +{ + for (int i = 0; i < priv->cpu_port; i++) + priv->r->set_receive_management_action(i, LLDP, TRAP2CPU); +} + +static void rtldsa_port_set_salrn(struct rtl838x_switch_priv *priv, + int port, bool enable) +{ + int shift = SALRN_PORT_SHIFT(port); + int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED; + + sw_w32_mask(SALRN_MODE_MASK << shift, val << shift, + priv->r->l2_port_new_salrn(port)); +} + +static int rtldsa_83xx_setup(struct dsa_switch *ds) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_debug("%s called\n", __func__); + + /* Disable MAC polling the PHY so that we can start configuration */ + priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl); + + for (int i = 0; i < ds->num_ports; i++) + priv->ports[i].enable = false; + priv->ports[priv->cpu_port].enable = true; + + /* Configure ports so they are disabled by default, but once enabled + * they will work in isolated mode (only traffic between port and CPU). + */ + for (int i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy || priv->ports[i].pcs) { + priv->ports[i].pm = BIT_ULL(priv->cpu_port); + priv->r->traffic_set(i, BIT_ULL(i)); + } + } + priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port)); + + /* For standalone ports, forward packets even if a static fdb + * entry for the source address exists on another port. + */ + if (priv->r->set_static_move_action) { + for (int i = 0; i <= priv->cpu_port; i++) + priv->r->set_static_move_action(i, true); + } + + priv->r->print_matrix(); + rtldsa_83xx_init_stats(priv); + rtldsa_init_counters(priv); + + rtldsa_83xx_mc_pmasks_setup(priv); + rtldsa_vlan_setup(priv); + + rtldsa_setup_bpdu_traps(priv); + rtldsa_setup_lldp_traps(priv); + + ds->configure_vlan_while_not_filtering = true; + + priv->r->l2_learning_setup(); + + rtldsa_port_set_salrn(priv, priv->cpu_port, false); + ds->assisted_learning_on_cpu_port = true; + + /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port + * 0: FWD, 1: DROP, 2: TRAP2CPU + */ + if (priv->family_id == RTL8380_FAMILY_ID) + sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL); + else + sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL); + + /* Enable MAC Polling PHY again */ + rtldsa_enable_phy_polling(priv); + pr_debug("Please wait until PHY is settled\n"); + msleep(1000); + priv->r->pie_init(priv); + + return 0; +} + +static int rtldsa_93xx_setup(struct dsa_switch *ds) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s called\n", __func__); + + /* Disable MAC polling the PHY so that we can start configuration */ + if (priv->family_id == RTL9300_FAMILY_ID) + sw_w32(0, RTL930X_SMI_POLL_CTRL); + + if (priv->family_id == RTL9310_FAMILY_ID) { + sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL); + sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4); + } + + /* Disable all ports except CPU port */ + for (int i = 0; i < ds->num_ports; i++) + priv->ports[i].enable = false; + priv->ports[priv->cpu_port].enable = true; + + /* Configure ports so they are disabled by default, but once enabled + * they will work in isolated mode (only traffic between port and CPU). + */ + for (int i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy || priv->ports[i].pcs) { + priv->ports[i].pm = BIT_ULL(priv->cpu_port); + priv->r->traffic_set(i, BIT_ULL(i)); + } + } + priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port)); + priv->r->print_matrix(); + + /* TODO: Initialize statistics */ + rtldsa_init_counters(priv); + + rtldsa_vlan_setup(priv); + + rtldsa_setup_bpdu_traps(priv); + rtldsa_setup_lldp_traps(priv); + + ds->configure_vlan_while_not_filtering = true; + + priv->r->l2_learning_setup(); + + rtldsa_port_set_salrn(priv, priv->cpu_port, false); + ds->assisted_learning_on_cpu_port = true; + + rtldsa_enable_phy_polling(priv); + + priv->r->pie_init(priv); + + priv->r->led_init(priv); + + return 0; +} + +static struct phylink_pcs *rtldsa_phylink_mac_select_pcs(struct dsa_switch *ds, + int port, + phy_interface_t interface) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + return priv->ports[port].pcs; +} + +static void rtldsa_83xx_phylink_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) +{ + /* + * TODO: This needs to take into account the MAC to SERDES mapping and the + * specific SoC capabilities. Right now we just assume all RTL83xx ports + * support up to 1G standalone and QSGMII as that covers most real-world + * use cases. + */ + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | + MAC_1000FD; + + __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_QSGMII, config->supported_interfaces); +} + +static void rtldsa_93xx_phylink_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) +{ + /* + * TODO: This needs to take into account the MAC to SERDES mapping and the + * specific SoC capabilities. Right now we just assume all RTL93xx ports + * support up to 10G standalone and up to USXGMII as that covers most + * real-world use cases. + */ + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | + MAC_1000FD | MAC_2500FD | MAC_5000FD | MAC_10000FD; + + __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_QSGMII, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_2500BASEX, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_USXGMII, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_10G_QXGMII, config->supported_interfaces); +} + +static void rtldsa_83xx_phylink_mac_config(struct dsa_switch *ds, int port, + unsigned int mode, + const struct phylink_link_state *state) +{ + struct dsa_port *dp = dsa_to_port(ds, port); + struct rtl838x_switch_priv *priv = ds->priv; + u32 mcr; + + pr_debug("%s port %d, mode %x\n", __func__, port, mode); + + /* currently only needed for RTL8380 */ + if (priv->family_id != RTL8380_FAMILY_ID) + return; + + if (dsa_port_is_cpu(dp)) { + /* allow CRC errors on CPU-port */ + sw_w32_mask(0, 0x8, priv->r->mac_port_ctrl(port)); + return; + } + + mcr = sw_r32(priv->r->mac_force_mode_ctrl(port)); + if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) { + pr_debug("port %d PHY autonegotiates\n", port); + + mcr |= RTL838X_NWAY_EN; + } else { + mcr &= ~RTL838X_NWAY_EN; + } + sw_w32(mcr, priv->r->mac_force_mode_ctrl(port)); +} + +static void rtldsa_93xx_phylink_mac_config(struct dsa_switch *ds, int port, + unsigned int mode, + const struct phylink_link_state *state) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + /* Nothing to be done for the CPU-port */ + if (port == priv->cpu_port) + return; + + /* Disable MAC completely */ + sw_w32(0, priv->r->mac_force_mode_ctrl(port)); +} + +static void rtldsa_83xx_phylink_mac_link_down(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface) +{ + struct rtl838x_switch_priv *priv = ds->priv; + int mask = 0; + + /* Stop TX/RX to port */ + sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port)); + + /* No longer force link */ + mask = RTL83XX_FORCE_EN | RTL83XX_FORCE_LINK_EN; + sw_w32_mask(mask, 0, priv->r->mac_force_mode_ctrl(port)); +} + +static void rtldsa_93xx_phylink_mac_link_down(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u32 v = 0; + + /* Stop TX/RX to port */ + sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port)); + + /* No longer force link */ + if (priv->family_id == RTL9300_FAMILY_ID) + v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN; + else if (priv->family_id == RTL9310_FAMILY_ID) + v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN; + sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port)); +} + +static void rtldsa_83xx_phylink_mac_link_up(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface, + struct phy_device *phydev, + int speed, int duplex, + bool tx_pause, bool rx_pause) +{ + struct dsa_port *dp = dsa_to_port(ds, port); + struct rtl838x_switch_priv *priv = ds->priv; + u32 mcr, spdsel; + + if (speed == SPEED_1000) + spdsel = RTL_SPEED_1000; + else if (speed == SPEED_100) + spdsel = RTL_SPEED_100; + else + spdsel = RTL_SPEED_10; + + mcr = sw_r32(priv->r->mac_force_mode_ctrl(port)); + + if (priv->family_id == RTL8380_FAMILY_ID) { + mcr &= ~RTL838X_RX_PAUSE_EN; + mcr &= ~RTL838X_TX_PAUSE_EN; + mcr &= ~RTL838X_DUPLEX_MODE; + mcr &= ~RTL838X_SPEED_MASK; + mcr |= RTL83XX_FORCE_LINK_EN; + mcr |= spdsel << RTL838X_SPEED_SHIFT; + + if (tx_pause) + mcr |= RTL838X_TX_PAUSE_EN; + if (rx_pause) + mcr |= RTL838X_RX_PAUSE_EN; + if (duplex == DUPLEX_FULL || priv->lagmembers & BIT_ULL(port)) + mcr |= RTL838X_DUPLEX_MODE; + if (dsa_port_is_cpu(dp)) + mcr |= RTL83XX_FORCE_EN; + + } else if (priv->family_id == RTL8390_FAMILY_ID) { + mcr &= ~RTL839X_RX_PAUSE_EN; + mcr &= ~RTL839X_TX_PAUSE_EN; + mcr &= ~RTL839X_DUPLEX_MODE; + mcr &= ~RTL839X_SPEED_MASK; + mcr |= RTL83XX_FORCE_LINK_EN; + mcr |= spdsel << RTL839X_SPEED_SHIFT; + + if (tx_pause) + mcr |= RTL839X_TX_PAUSE_EN; + if (rx_pause) + mcr |= RTL839X_RX_PAUSE_EN; + if (duplex == DUPLEX_FULL || priv->lagmembers & BIT_ULL(port)) + mcr |= RTL839X_DUPLEX_MODE; + if (dsa_port_is_cpu(dp)) + mcr |= RTL83XX_FORCE_EN; + } + + pr_debug("%s port %d, mode %x, speed %d, duplex %d, txpause %d, rxpause %d: set mcr=%08x\n", + __func__, port, mode, speed, duplex, tx_pause, rx_pause, mcr); + sw_w32(mcr, priv->r->mac_force_mode_ctrl(port)); + + /* Restart TX/RX to port */ + sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port)); +} + +static void rtldsa_93xx_phylink_mac_link_up(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface, + struct phy_device *phydev, + int speed, int duplex, + bool tx_pause, bool rx_pause) +{ + struct dsa_port *dp = dsa_to_port(ds, port); + struct rtl838x_switch_priv *priv = ds->priv; + u32 mcr, spdsel; + + if (speed == SPEED_10000) + spdsel = RTL_SPEED_10000; + else if (speed == SPEED_5000) + spdsel = RTL_SPEED_5000; + else if (speed == SPEED_2500) + spdsel = RTL_SPEED_2500; + else if (speed == SPEED_1000) + spdsel = RTL_SPEED_1000; + else if (speed == SPEED_100) + spdsel = RTL_SPEED_100; + else + spdsel = RTL_SPEED_10; + + mcr = sw_r32(priv->r->mac_force_mode_ctrl(port)); + + if (priv->family_id == RTL9300_FAMILY_ID) { + mcr &= ~RTL930X_RX_PAUSE_EN; + mcr &= ~RTL930X_TX_PAUSE_EN; + mcr &= ~RTL930X_DUPLEX_MODE; + mcr &= ~RTL930X_SPEED_MASK; + mcr |= RTL930X_FORCE_LINK_EN; + mcr |= spdsel << RTL930X_SPEED_SHIFT; + + if (tx_pause) + mcr |= RTL930X_TX_PAUSE_EN; + if (rx_pause) + mcr |= RTL930X_RX_PAUSE_EN; + if (duplex == DUPLEX_FULL || priv->lagmembers & BIT_ULL(port)) + mcr |= RTL930X_DUPLEX_MODE; + if (dsa_port_is_cpu(dp) || !priv->ports[port].phy_is_integrated) + mcr |= RTL930X_FORCE_EN; + } + + pr_debug("%s port %d, mode %x, speed %d, duplex %d, txpause %d, rxpause %d: set mcr=%08x\n", + __func__, port, mode, speed, duplex, tx_pause, rx_pause, mcr); + sw_w32(mcr, priv->r->mac_force_mode_ctrl(port)); + + /* Restart TX/RX to port */ + sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port)); +} + +static bool rtldsa_read_mib_item(struct rtl838x_switch_priv *priv, int port, + const struct rtldsa_mib_item *mib_item, + u64 *data) +{ + u32 high1, high2; + int reg, reg_offset, addr_low; + + switch (mib_item->reg) { + case MIB_REG_STD: + reg = priv->r->stat_port_std_mib; + reg_offset = 256; + break; + case MIB_REG_PRV: + reg = priv->r->stat_port_prv_mib; + reg_offset = 128; + break; + case MIB_TBL_STD: + case MIB_TBL_PRV: + if (!priv->r->stat_port_table_read) + return false; + + *data = priv->r->stat_port_table_read(port, mib_item->size, mib_item->offset, + mib_item->reg == MIB_TBL_PRV); + + return true; + default: + return false; + } + + addr_low = reg + (port + 1) * reg_offset - 4 - mib_item->offset; + + if (mib_item->size == 2) { + high1 = sw_r32(addr_low - 4); + *data = sw_r32(addr_low); + high2 = sw_r32(addr_low - 4); + if (high1 != high2) { + /* Low must have wrapped and overflowed into high, read again */ + *data = sw_r32(addr_low); + } + *data |= (u64)high2 << 32; + } else { + *data = sw_r32(addr_low); + } + + return true; +} + +static void rtldsa_update_counter(struct rtl838x_switch_priv *priv, int port, + struct rtldsa_counter *counter, + const struct rtldsa_mib_item *mib_item) +{ + u64 val; + u32 val32, diff; + + if (!rtldsa_read_mib_item(priv, port, mib_item, &val)) + return; + + if (mib_item->size == 2) { + counter->val = val; + } else { + val32 = (u32)val; + diff = val32 - counter->last; + counter->val += diff; + counter->last = val32; + } +} + +static void rtldsa_update_link_stat(struct rtnl_link_stats64 *s, + const struct rtldsa_counter_state *counters) +{ + s->rx_packets = counters->if_in_ucast_pkts.val + + counters->if_in_mcast_pkts.val + + counters->if_in_bcast_pkts.val + + counters->rx_pkts_over_max_octets.val; + + s->tx_packets = counters->if_out_ucast_pkts.val + + counters->if_out_mcast_pkts.val + + counters->if_out_bcast_pkts.val - + counters->if_out_discards.val; + + /* Subtract FCS for each packet, and pause frames */ + s->rx_bytes = counters->if_in_octets.val - + 4 * s->rx_packets - + 64 * counters->rx_pause_frames.val; + s->tx_bytes = counters->if_out_octets.val - + 4 * s->tx_packets - + 64 * counters->tx_pause_frames.val; + + s->collisions = counters->collisions.val; + + s->rx_dropped = counters->drop_events.val; + s->tx_dropped = counters->if_out_discards.val; + + s->rx_crc_errors = counters->crc_align_errors.val; + s->rx_errors = s->rx_crc_errors; + + s->tx_aborted_errors = counters->excessive_collisions.val; + s->tx_window_errors = counters->late_collisions.val; + s->tx_errors = s->tx_aborted_errors + s->tx_window_errors; +} + +static void rtldsa_update_port_counters(struct rtl838x_switch_priv *priv, int port) +{ + struct rtldsa_counter_state *counters = &priv->ports[port].counters; + const struct rtldsa_mib_desc *mib_desc; + ktime_t now; + + mib_desc = priv->r->mib_desc; + + /* Prevent unnecessary updates when the user accesses different stats quickly. + * This compensates a bit for always updating all stats, even when just a + * subset is actually requested. + */ + now = ktime_get(); + if (ktime_before(now, ktime_add_ms(counters->last_update, 100))) + return; + counters->last_update = now; + + rtldsa_update_counter(priv, port, &counters->symbol_errors, + &mib_desc->symbol_errors); + + rtldsa_update_counter(priv, port, &counters->if_in_octets, + &mib_desc->if_in_octets); + rtldsa_update_counter(priv, port, &counters->if_out_octets, + &mib_desc->if_out_octets); + rtldsa_update_counter(priv, port, &counters->if_in_ucast_pkts, + &mib_desc->if_in_ucast_pkts); + rtldsa_update_counter(priv, port, &counters->if_in_mcast_pkts, + &mib_desc->if_in_mcast_pkts); + rtldsa_update_counter(priv, port, &counters->if_in_bcast_pkts, + &mib_desc->if_in_bcast_pkts); + rtldsa_update_counter(priv, port, &counters->if_out_ucast_pkts, + &mib_desc->if_out_ucast_pkts); + rtldsa_update_counter(priv, port, &counters->if_out_mcast_pkts, + &mib_desc->if_out_mcast_pkts); + rtldsa_update_counter(priv, port, &counters->if_out_bcast_pkts, + &mib_desc->if_out_bcast_pkts); + rtldsa_update_counter(priv, port, &counters->if_out_discards, + &mib_desc->if_out_discards); + rtldsa_update_counter(priv, port, &counters->single_collisions, + &mib_desc->single_collisions); + rtldsa_update_counter(priv, port, &counters->multiple_collisions, + &mib_desc->multiple_collisions); + rtldsa_update_counter(priv, port, &counters->deferred_transmissions, + &mib_desc->deferred_transmissions); + rtldsa_update_counter(priv, port, &counters->late_collisions, + &mib_desc->late_collisions); + rtldsa_update_counter(priv, port, &counters->excessive_collisions, + &mib_desc->excessive_collisions); + rtldsa_update_counter(priv, port, &counters->crc_align_errors, + &mib_desc->crc_align_errors); + rtldsa_update_counter(priv, port, &counters->rx_pkts_over_max_octets, + &mib_desc->rx_pkts_over_max_octets); + + rtldsa_update_counter(priv, port, &counters->unsupported_opcodes, + &mib_desc->unsupported_opcodes); + + rtldsa_update_counter(priv, port, &counters->rx_undersize_pkts, + &mib_desc->rx_undersize_pkts); + rtldsa_update_counter(priv, port, &counters->rx_oversize_pkts, + &mib_desc->rx_oversize_pkts); + rtldsa_update_counter(priv, port, &counters->rx_fragments, + &mib_desc->rx_fragments); + rtldsa_update_counter(priv, port, &counters->rx_jabbers, + &mib_desc->rx_jabbers); + + for (int i = 0; i < ARRAY_SIZE(mib_desc->tx_pkts); i++) { + if (mib_desc->tx_pkts[i].reg == MIB_REG_INVALID) + break; + + rtldsa_update_counter(priv, port, &counters->tx_pkts[i], + &mib_desc->tx_pkts[i]); + } + for (int i = 0; i < ARRAY_SIZE(mib_desc->rx_pkts); i++) { + if (mib_desc->rx_pkts[i].reg == MIB_REG_INVALID) + break; + + rtldsa_update_counter(priv, port, &counters->rx_pkts[i], + &mib_desc->rx_pkts[i]); + } + + rtldsa_update_counter(priv, port, &counters->drop_events, + &mib_desc->drop_events); + rtldsa_update_counter(priv, port, &counters->collisions, + &mib_desc->collisions); + + rtldsa_update_counter(priv, port, &counters->rx_pause_frames, + &mib_desc->rx_pause_frames); + rtldsa_update_counter(priv, port, &counters->tx_pause_frames, + &mib_desc->tx_pause_frames); + + /* prepare get_stats64 reply without requiring caller waiting for mutex */ + spin_lock(&counters->link_stat_lock); + rtldsa_update_link_stat(&counters->link_stat, counters); + spin_unlock(&counters->link_stat_lock); +} + +void rtldsa_counters_lock_register(struct rtl838x_switch_priv *priv, int port) + __acquires(&priv->ports[port].counters.lock) +{ + spin_lock(&priv->ports[port].counters.lock); +} + +void rtldsa_counters_unlock_register(struct rtl838x_switch_priv *priv, int port) + __releases(&priv->ports[port].counters.lock) +{ + spin_unlock(&priv->ports[port].counters.lock); +} + +void rtldsa_counters_lock_table(struct rtl838x_switch_priv *priv, int port __maybe_unused) + __acquires(&priv->counters_lock) +{ + mutex_lock(&priv->counters_lock); +} + +void rtldsa_counters_unlock_table(struct rtl838x_switch_priv *priv, int port __maybe_unused) + __releases(&priv->ports[port].counters.lock) +{ + mutex_unlock(&priv->counters_lock); +} + +static void rtldsa_counters_lock(struct rtl838x_switch_priv *priv, int port) +{ + priv->r->stat_counters_lock(priv, port); +} + +static void rtldsa_counters_unlock(struct rtl838x_switch_priv *priv, int port) +{ + priv->r->stat_counters_unlock(priv, port); +} + +static void rtldsa_poll_counters(struct work_struct *work) +{ + struct rtl838x_switch_priv *priv = container_of(to_delayed_work(work), + struct rtl838x_switch_priv, + counters_work); + + for (int port = 0; port < priv->cpu_port; port++) { + if (!priv->ports[port].phy && !priv->ports[port].pcs) + continue; + + rtldsa_counters_lock(priv, port); + rtldsa_update_port_counters(priv, port); + rtldsa_counters_unlock(priv, port); + } + + queue_delayed_work(priv->wq, &priv->counters_work, + priv->r->stat_counter_poll_interval); +} + +static void rtldsa_init_counters(struct rtl838x_switch_priv *priv) +{ + struct rtldsa_counter_state *counters; + + for (int port = 0; port < priv->cpu_port; port++) { + if (!priv->ports[port].phy && !priv->ports[port].pcs) + continue; + + counters = &priv->ports[port].counters; + + memset(counters, 0, sizeof(*counters)); + spin_lock_init(&counters->lock); + spin_lock_init(&counters->link_stat_lock); + } + + INIT_DELAYED_WORK(&priv->counters_work, rtldsa_poll_counters); + queue_delayed_work(priv->wq, &priv->counters_work, + priv->r->stat_counter_poll_interval); +} + +static void rtldsa_get_strings(struct dsa_switch *ds, + int port, u32 stringset, u8 *data) +{ + struct rtl838x_switch_priv *priv = ds->priv; + const struct rtldsa_mib_desc *mib_desc; + + if (stringset != ETH_SS_STATS) + return; + + if (port < 0 || port >= priv->cpu_port) + return; + + mib_desc = priv->r->mib_desc; + + for (int i = 0; i < mib_desc->list_count; i++) + ethtool_puts(&data, mib_desc->list[i].name); +} + +static void rtldsa_get_ethtool_stats(struct dsa_switch *ds, int port, + u64 *data) +{ + struct rtl838x_switch_priv *priv = ds->priv; + const struct rtldsa_mib_desc *mib_desc; + const struct rtldsa_mib_item *mib_item; + + if (port < 0 || port >= priv->cpu_port) + return; + + mib_desc = priv->r->mib_desc; + for (int i = 0; i < mib_desc->list_count; i++) { + mib_item = &mib_desc->list[i].item; + rtldsa_read_mib_item(priv, port, mib_item, &data[i]); + } +} + +static int rtldsa_get_sset_count(struct dsa_switch *ds, int port, int sset) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + if (sset != ETH_SS_STATS) + return 0; + + if (port < 0 || port >= priv->cpu_port) + return 0; + + return priv->r->mib_desc->list_count; +} + +static void rtldsa_get_eth_phy_stats(struct dsa_switch *ds, int port, + struct ethtool_eth_phy_stats *phy_stats) +{ + struct rtl838x_switch_priv *priv = ds->priv; + struct rtldsa_counter_state *counters = &priv->ports[port].counters; + + if (port < 0 || port >= priv->cpu_port) + return; + + rtldsa_counters_lock(priv, port); + + rtldsa_update_port_counters(priv, port); + + phy_stats->SymbolErrorDuringCarrier = counters->symbol_errors.val; + + rtldsa_counters_unlock(priv, port); +} + +static void rtldsa_get_eth_mac_stats(struct dsa_switch *ds, int port, + struct ethtool_eth_mac_stats *mac_stats) +{ + struct rtl838x_switch_priv *priv = ds->priv; + struct rtldsa_counter_state *counters = &priv->ports[port].counters; + + if (port < 0 || port >= priv->cpu_port) + return; + + rtldsa_counters_lock(priv, port); + + rtldsa_update_port_counters(priv, port); + + /* Frame and octet counters are calculated based on RFC3635, while also + * taking into account that the behaviour of the hardware counters differs + * in some places. + */ + + mac_stats->FramesReceivedOK = counters->if_in_ucast_pkts.val + + counters->if_in_mcast_pkts.val + + counters->if_in_bcast_pkts.val + + counters->rx_pause_frames.val + + counters->rx_pkts_over_max_octets.val; + + mac_stats->FramesTransmittedOK = counters->if_out_ucast_pkts.val + + counters->if_out_mcast_pkts.val + + counters->if_out_bcast_pkts.val + + counters->tx_pause_frames.val - + counters->if_out_discards.val; + + mac_stats->OctetsReceivedOK = counters->if_in_octets.val - + 18 * mac_stats->FramesReceivedOK; + mac_stats->OctetsTransmittedOK = counters->if_out_octets.val - + 18 * mac_stats->FramesTransmittedOK; + + mac_stats->SingleCollisionFrames = counters->single_collisions.val; + mac_stats->MultipleCollisionFrames = counters->multiple_collisions.val; + mac_stats->FramesWithDeferredXmissions = counters->deferred_transmissions.val; + mac_stats->LateCollisions = counters->late_collisions.val; + mac_stats->FramesAbortedDueToXSColls = counters->excessive_collisions.val; + + mac_stats->FrameCheckSequenceErrors = counters->crc_align_errors.val; + + rtldsa_counters_unlock(priv, port); +} + +static void rtldsa_get_eth_ctrl_stats(struct dsa_switch *ds, int port, + struct ethtool_eth_ctrl_stats *ctrl_stats) +{ + struct rtl838x_switch_priv *priv = ds->priv; + struct rtldsa_counter_state *counters = &priv->ports[port].counters; + + if (port < 0 || port >= priv->cpu_port) + return; + + rtldsa_counters_lock(priv, port); + + rtldsa_update_port_counters(priv, port); + + ctrl_stats->UnsupportedOpcodesReceived = counters->unsupported_opcodes.val; + + rtldsa_counters_unlock(priv, port); +} + +static void rtldsa_get_rmon_stats(struct dsa_switch *ds, int port, + struct ethtool_rmon_stats *rmon_stats, + const struct ethtool_rmon_hist_range **ranges) +{ + struct rtl838x_switch_priv *priv = ds->priv; + const struct rtldsa_mib_desc *mib_desc; + struct rtldsa_counter_state *counters = &priv->ports[port].counters; + + if (port < 0 || port >= priv->cpu_port) + return; + + mib_desc = priv->r->mib_desc; + + rtldsa_counters_lock(priv, port); + + rtldsa_update_port_counters(priv, port); + + rmon_stats->undersize_pkts = counters->rx_undersize_pkts.val; + rmon_stats->oversize_pkts = counters->rx_oversize_pkts.val; + rmon_stats->fragments = counters->rx_fragments.val; + rmon_stats->jabbers = counters->rx_jabbers.val; + + for (int i = 0; i < ARRAY_SIZE(mib_desc->rx_pkts); i++) { + if (mib_desc->rx_pkts[i].reg == MIB_REG_INVALID) + break; + + rmon_stats->hist[i] = counters->rx_pkts[i].val; + } + + for (int i = 0; i < ARRAY_SIZE(mib_desc->tx_pkts); i++) { + if (mib_desc->tx_pkts[i].reg == MIB_REG_INVALID) + break; + + rmon_stats->hist_tx[i] = counters->tx_pkts[i].val; + } + + *ranges = mib_desc->rmon_ranges; + + rtldsa_counters_unlock(priv, port); +} + +void rtldsa_update_counters_atomically(struct rtl838x_switch_priv *priv, int port) +{ + rtldsa_counters_lock(priv, port); + rtldsa_update_port_counters(priv, port); + rtldsa_counters_unlock(priv, port); +} + +static void rtldsa_get_stats64(struct dsa_switch *ds, int port, + struct rtnl_link_stats64 *s) +{ + struct rtl838x_switch_priv *priv = ds->priv; + struct rtldsa_counter_state *counters = &priv->ports[port].counters; + + if (port < 0 || port >= priv->cpu_port) + return; + + if (priv->r->stat_update_counters_atomically) + priv->r->stat_update_counters_atomically(priv, port); + + /* retrieve prepared return data without potentially sleeping via mutex */ + spin_lock(&counters->link_stat_lock); + memcpy(s, &counters->link_stat, sizeof(*s)); + spin_unlock(&counters->link_stat_lock); +} + +static void rtldsa_get_pause_stats(struct dsa_switch *ds, int port, + struct ethtool_pause_stats *pause_stats) +{ + struct rtl838x_switch_priv *priv = ds->priv; + struct rtldsa_counter_state *counters = &priv->ports[port].counters; + + if (port < 0 || port >= priv->cpu_port) + return; + + rtldsa_counters_lock(priv, port); + + rtldsa_update_port_counters(priv, port); + + pause_stats->tx_pause_frames = counters->tx_pause_frames.val; + pause_stats->rx_pause_frames = counters->rx_pause_frames.val; + + rtldsa_counters_unlock(priv, port); +} + +static int rtldsa_mc_group_alloc(struct rtl838x_switch_priv *priv, int port) +{ + int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1); + u64 portmask; + + if (mc_group >= MAX_MC_GROUPS - 1) + return -1; + + set_bit(mc_group, priv->mc_group_bm); + portmask = BIT_ULL(port); + priv->r->write_mcast_pmask(mc_group, portmask); + + return mc_group; +} + +static u64 rtldsa_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port) +{ + u64 portmask = priv->r->read_mcast_pmask(mc_group); + + pr_debug("%s: %d\n", __func__, port); + + portmask |= BIT_ULL(port); + priv->r->write_mcast_pmask(mc_group, portmask); + + return portmask; +} + +static u64 rtldsa_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port) +{ + u64 portmask = priv->r->read_mcast_pmask(mc_group); + + pr_debug("%s: %d\n", __func__, port); + + portmask &= ~BIT_ULL(port); + priv->r->write_mcast_pmask(mc_group, portmask); + if (!portmask) + clear_bit(mc_group, priv->mc_group_bm); + + return portmask; +} + +static int rtldsa_port_enable(struct dsa_switch *ds, int port, struct phy_device *phydev) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_debug("%s: %x %d", __func__, (u32)priv, port); + priv->ports[port].enable = true; + + /* enable inner tagging on egress, do not keep any tags */ + priv->r->vlan_port_keep_tag_set(port, 0, 1); + + if (dsa_is_cpu_port(ds, port)) + return 0; + + /* add port to switch mask of CPU_PORT */ + priv->r->traffic_enable(priv->cpu_port, port); + + /* add all other ports in the same bridge to switch mask of port */ + priv->r->traffic_set(port, priv->ports[port].pm); + + /* TODO: Figure out if this is necessary */ + if (priv->family_id == RTL9300_FAMILY_ID) { + sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL); + sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL); + } + + return 0; +} + +static void rtldsa_port_disable(struct dsa_switch *ds, int port) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_debug("%s %x: %d", __func__, (u32)priv, port); + /* you can only disable user ports */ + if (!dsa_is_user_port(ds, port)) + return; + + /* BUG: This does not work on RTL931X */ + /* remove port from switch mask of CPU_PORT */ + priv->r->traffic_disable(priv->cpu_port, port); + + /* remove all other ports from switch mask of port */ + priv->r->traffic_set(port, 0); + + priv->ports[port].enable = false; +} + +static int rtldsa_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + if (e->eee_enabled && !priv->eee_enabled) { + pr_info("Globally enabling EEE\n"); + priv->r->init_eee(priv, true); + } + + priv->r->set_mac_eee(priv, port, e->eee_enabled); + + if (e->eee_enabled) + pr_info("Enabled EEE for port %d\n", port); + else + pr_info("Disabled EEE for port %d\n", port); + + return 0; +} + +static int rtldsa_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *eee) +{ + /* + * Until kernel 6.6 the Realtek device specific get_mac_eee() functions filled many + * fields of the eee structure manually. That came from the fact, that the phy + * driver could not report EEE capabilities on its own. Upstream will replace this + * function with a simple boolean support_eee() getter starting from 6.14. That only + * checks if a port can provide EEE or not. In the best case it can be replaced with + * dsa_supports_eee() in the future. For now align to other upstream DSA drivers. + */ + + return 0; +} + +static int rtldsa_set_ageing_time(struct dsa_switch *ds, unsigned int msec) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + priv->r->set_ageing_time(msec); + + return 0; +} + +/** + * rtldsa_mst_init() - Initialize newly "allocated" MST HW slot + * @priv: private data of rtldsa switch + * @mst_slot: MST slot of MSTI + */ +static void rtldsa_mst_init(struct rtl838x_switch_priv *priv, u16 mst_slot) + __must_hold(&priv->reg_mutex) +{ + struct dsa_port *dp; + unsigned int port; + u8 state; + + dsa_switch_for_each_user_port(dp, priv->ds) { + if (dp->bridge) + state = BR_STATE_DISABLED; + else + state = dp->stp_state; + + port = dp->index; + + rtldsa_port_xstp_state_set(priv, port, state, mst_slot); + } +} + +/** + * rtldsa_mst_find() - Find HW MST slot for MSTI (without reference counting) + * @priv: private data of rtldsa switch + * @msti: MSTI to search + * + * Return: found HW slot (unmodified reference count) or negative encoded error value + */ +static int rtldsa_mst_find(struct rtl838x_switch_priv *priv, u16 msti) + __must_hold(&priv->reg_mutex) +{ + unsigned int i; + + /* CIST is always mapped to 0 */ + if (msti == 0) + return 0; + + if (msti > 4095) + return -EINVAL; + + /* search for existing entry */ + for (i = 0; i < priv->n_mst - 1; i++) { + if (priv->msts[i].msti != msti) + continue; + + return i + 1; + } + + return -ENOENT; +} + +/** + * rtldsa_mst_get() - Get (or allocate) HW MST slot for MSTI + * @priv: private data of rtldsa switch + * @msti: MSTI for which a HW slot is needed + * + * Return: allocated slot (with increased reference count) or negative encoded error value + */ +static int rtldsa_mst_get(struct rtl838x_switch_priv *priv, u16 msti) + __must_hold(&priv->reg_mutex) +{ + unsigned int i; + int ret; + + ret = rtldsa_mst_find(priv, msti); + + /* CIST doesn't need reference counting */ + if (ret == 0) + return ret; + + /* valid HW slot was found - refcount needs to be adjusted */ + if (ret > 0) { + u16 index = ret - 1; + + kref_get(&priv->msts[index].refcount); + return ret; + } + + /* any error except "no entry found" cannot be handled */ + if (ret != -ENOENT) + return ret; + + /* search for free slot */ + for (i = 0; i < priv->n_mst - 1; i++) { + if (priv->msts[i].msti != 0) + continue; + + kref_init(&priv->msts[i].refcount); + priv->msts[i].msti = msti; + + rtldsa_mst_init(priv, i + 1); + return i + 1; + } + + return -ENOSPC; +} + +/** + * rtldsa_mst_recycle_slot() - Try to recycle old MST slot in case of -ENOSPC of rtldsa_mst_get() + * @priv: private data of rtldsa switch + * @msti: MSTI for which a HW slot is needed + * @old_mst_slot: old mst slot which will be released "soon" + * + * If a VLAN should be moved from one MSTI to another one, it is possible that there are currently + * not enough slots still available to perform a get+put operation. But if this slot is used + * by a single VLAN anyway, it is not needed to really allocate a new slow - reassigning it to + * the new MSTI is good enough. + * + * This is only allowed when holding the reg_mutex over both calls rtldsa_mst_get() and + * rtldsa_mst_recycle(). After a rtldsa_mst_recycle() call, rtldsa_mst_put_slot() must no longer + * be called for @old_mst_slot. + * + * Return: allocated slot (with increased reference count) or negative encoded error value + */ +static int rtldsa_mst_recycle_slot(struct rtl838x_switch_priv *priv, u16 msti, u16 old_mst_slot) + __must_hold(&priv->reg_mutex) +{ + u16 index; + + /* CIST is always mapped to 0 */ + if (msti == 0) + return 0; + + if (old_mst_slot == 0) + return -ENOSPC; + + if (msti > 4095) + return -EINVAL; + + if (old_mst_slot >= priv->n_mst) + return -EINVAL; + + index = old_mst_slot - 1; + + /* this slot is unused - should not happen because rtldsa_mst_get() searches for it */ + if (priv->msts[index].msti == 0) + return -EINVAL; + + /* it is only allowed to swap when no other VLAN is using this MST slot */ + if (kref_read(&priv->msts[index].refcount) != 1) + return -ENOSPC; + + priv->msts[index].msti = msti; + return old_mst_slot; +} + +static void rtldsa_mst_release_slot(struct kref *ref) +{ + struct rtldsa_mst *slot = container_of(ref, struct rtldsa_mst, refcount); + + slot->msti = 0; +} + +/** + * rtldsa_mst_put_slot() - Decrement VLAN use counter for MST slot + * @priv: private data of rtldsa switch + * @mst_slot: MST slot which should be put + * + * Return: false when MST slot reference counter was only decreased or an invalid @mst_slot was + * given, true when @mst_slot is now unused + */ +static bool rtldsa_mst_put_slot(struct rtl838x_switch_priv *priv, u16 mst_slot) + __must_hold(&priv->reg_mutex) +{ + unsigned int index; + + /* CIST is always mapped to 0 and cannot be put */ + if (mst_slot == 0) + return 0; + + if (mst_slot >= priv->n_mst) + return 0; + + index = mst_slot - 1; + + /* this slot is unused and must not release a reference */ + if (priv->msts[index].msti == 0) + return 0; + + return kref_put(&priv->msts[index].refcount, rtldsa_mst_release_slot); +} + +/** + * rtldsa_mst_replace() - Get HW slot for @msti and drop old HW slot + * @priv: private data of rtldsa switch + * @msti: MSTI for which a HW slot is needed + * @old_mst_slot: old mst slot which will no longer be assigned to VLAN + * + * Return: allocated slot (with increased reference count) or negative encoded error value + */ +static int rtldsa_mst_replace(struct rtl838x_switch_priv *priv, u16 msti, u16 old_mst_slot) + __must_hold(&priv->reg_mutex) +{ + int mst_slot_new; + + mst_slot_new = rtldsa_mst_get(priv, msti); + if (mst_slot_new == -ENOSPC) + return rtldsa_mst_recycle_slot(priv, msti, old_mst_slot); + + /* directly return errors and don't free old slot */ + if (mst_slot_new < 0) + return mst_slot_new; + + rtldsa_mst_put_slot(priv, old_mst_slot); + + return mst_slot_new; +} + +static void rtldsa_update_port_member(struct rtl838x_switch_priv *priv, int port, + const struct net_device *bridge_dev, bool join) + __must_hold(&priv->reg_mutex) +{ + struct dsa_port *dp = dsa_to_port(priv->ds, port); + struct rtldsa_port *p = &priv->ports[port]; + struct dsa_port *cpu_dp = dp->cpu_dp; + u64 port_mask = BIT_ULL(cpu_dp->index); + struct rtldsa_port *other_p; + struct dsa_port *other_dp; + int other_port; + bool isolated; + + dsa_switch_for_each_user_port(other_dp, priv->ds) { + other_port = other_dp->index; + other_p = &priv->ports[other_port]; + + if (dp == other_dp) + continue; + + if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev)) + continue; + + isolated = p->isolated && other_p->isolated; + + if (join && !isolated) { + port_mask |= BIT_ULL(other_port); + other_p->pm |= BIT_ULL(port); + } else { + other_p->pm &= ~BIT_ULL(port); + } + + if (other_p->enable) + priv->r->traffic_set(other_port, other_p->pm); + } + + p->pm = port_mask; + + if (p->enable) + priv->r->traffic_set(port, port_mask); +} + +static int rtldsa_port_bridge_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, + bool *tx_fwd_offload, struct netlink_ext_ack *extack) +{ + struct rtl838x_switch_priv *priv = ds->priv; + unsigned int i; + + pr_debug("%s %x: %d", __func__, (u32)priv, port); + + /* reset to default flags for new net_bridge_port */ + priv->ports[port].isolated = false; + + mutex_lock(&priv->reg_mutex); + + rtldsa_update_port_member(priv, port, bridge.dev, true); + + if (priv->r->set_static_move_action) + priv->r->set_static_move_action(port, false); + + /* Set to disabled in all MSTs, common code will take care of CIST */ + for (i = 1; i < priv->n_mst; i++) + rtldsa_port_xstp_state_set(priv, port, BR_STATE_DISABLED, i); + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static void rtldsa_port_bridge_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge) +{ + struct rtl838x_switch_priv *priv = ds->priv; + unsigned int i; + + pr_debug("%s %x: %d", __func__, (u32)priv, port); + + mutex_lock(&priv->reg_mutex); + + rtldsa_update_port_member(priv, port, bridge.dev, false); + + if (priv->r->set_static_move_action) + priv->r->set_static_move_action(port, true); + + /* Set to forwarding in all MSTs, common code will take care of CIST */ + for (i = 1; i < priv->n_mst; i++) + rtldsa_port_xstp_state_set(priv, port, BR_STATE_FORWARDING, i); + + mutex_unlock(&priv->reg_mutex); +} + +static void rtldsa_port_xstp_state_set(struct rtl838x_switch_priv *priv, int port, + u8 state, u16 mst_slot) + __must_hold(&priv->reg_mutex) +{ + u32 port_state[4]; + int index, bit; + int pos = port; + int n = priv->port_width << 1; + + /* Ports above or equal CPU port can never be configured */ + if (port >= priv->cpu_port) + return; + + /* For the RTL839x and following, the bits are left-aligned, 838x and 930x + * have 64 bit fields, 839x and 931x have 128 bit fields + */ + if (priv->family_id == RTL8390_FAMILY_ID) + pos += 12; + if (priv->family_id == RTL9300_FAMILY_ID) + pos += 3; + if (priv->family_id == RTL9310_FAMILY_ID) + pos += 8; + + index = n - (pos >> 4) - 1; + bit = (pos << 1) % 32; + + priv->r->stp_get(priv, mst_slot, port, port_state); + + pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3); + port_state[index] &= ~(3 << bit); + + switch (state) { + case BR_STATE_DISABLED: /* 0 */ + port_state[index] |= (0 << bit); + break; + case BR_STATE_BLOCKING: /* 4 */ + case BR_STATE_LISTENING: /* 1 */ + port_state[index] |= (1 << bit); + break; + case BR_STATE_LEARNING: /* 2 */ + port_state[index] |= (2 << bit); + break; + case BR_STATE_FORWARDING: /* 3 */ + port_state[index] |= (3 << bit); + default: + break; + } + + priv->r->stp_set(priv, mst_slot, port_state); +} + +void rtldsa_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) +{ + struct rtl838x_switch_priv *priv = ds->priv; + struct dsa_port *dp = dsa_to_port(ds, port); + unsigned int i; + + mutex_lock(&priv->reg_mutex); + rtldsa_port_xstp_state_set(priv, port, state, 0); + + if (dp->bridge) + goto unlock; + + /* for unbridged ports, also force the same state to the MSTIs */ + for (i = 1; i < priv->n_mst; i++) + rtldsa_port_xstp_state_set(priv, port, state, i); + +unlock: + mutex_unlock(&priv->reg_mutex); +} + +static int rtldsa_port_mst_state_set(struct dsa_switch *ds, int port, + const struct switchdev_mst_state *st) +{ + struct rtl838x_switch_priv *priv = ds->priv; + int mst_slot; + + mutex_lock(&priv->reg_mutex); + + mst_slot = rtldsa_mst_find(priv, st->msti); + if (mst_slot < 0) { + mutex_unlock(&priv->reg_mutex); + return mst_slot; + } + + rtldsa_port_xstp_state_set(priv, port, st->state, mst_slot); + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtldsa_vlan_filtering(struct dsa_switch *ds, int port, + bool vlan_filtering, + struct netlink_ext_ack *extack) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_debug("%s: port %d\n", __func__, port); + mutex_lock(&priv->reg_mutex); + + if (vlan_filtering) { + /* Enable ingress and egress filtering + * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define + * the filter action: + * 0: Always Forward + * 1: Drop packet + * 2: Trap packet to CPU port + * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED) + */ + if (port != priv->cpu_port) { + priv->r->set_vlan_igr_filter(port, IGR_DROP); + priv->r->set_vlan_egr_filter(port, EGR_ENABLE); + } else { + priv->r->set_vlan_igr_filter(port, IGR_TRAP); + priv->r->set_vlan_egr_filter(port, EGR_DISABLE); + } + + } else { + /* Disable ingress and egress filtering */ + if (port != priv->cpu_port) + priv->r->set_vlan_igr_filter(port, IGR_FORWARD); + + priv->r->set_vlan_egr_filter(port, EGR_DISABLE); + } + + /* Do we need to do something to the CPU-Port, too? */ + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtldsa_vlan_prepare(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct rtl838x_vlan_info info; + struct rtl838x_switch_priv *priv = ds->priv; + + priv->r->vlan_tables_read(0, &info); + + pr_debug("VLAN 0: Member ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n", + info.member_ports, info.untagged_ports, info.profile_id, + info.hash_mc_fid, info.hash_uc_fid, info.fid); + + priv->r->vlan_tables_read(1, &info); + pr_debug("VLAN 1: Member ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n", + info.member_ports, info.untagged_ports, info.profile_id, + info.hash_mc_fid, info.hash_uc_fid, info.fid); + priv->r->vlan_set_untagged(1, info.untagged_ports); + pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports); + + priv->r->vlan_set_tagged(1, &info); + pr_debug("SET: Member ports, VLAN %d: %llx\n", 1, info.member_ports); + + return 0; +} + +static int rtldsa_vlan_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan, + struct netlink_ext_ack *extack) +{ + struct rtl838x_vlan_info info; + struct rtl838x_switch_priv *priv = ds->priv; + int err; + + pr_debug("%s port %d, vid %d, flags %x\n", + __func__, port, vlan->vid, vlan->flags); + + /* Let no one mess with our special VLAN 0 */ + if (!vlan->vid) + return 0; + + if (vlan->vid >= MAX_VLANS) { + dev_err(priv->dev, "VLAN out of range: %d", vlan->vid); + return -ENOTSUPP; + } + + err = rtldsa_vlan_prepare(ds, port, vlan); + if (err) + return err; + + mutex_lock(&priv->reg_mutex); + + /* + * Realtek switches copy frames as-is to/from the CPU. For a proper + * VLAN handling the 12 bit RVID field (= VLAN id) for incoming traffic + * and the 1 bit RVID_SEL field (0 = use inner tag, 1 = use outer tag) + * for outgoing traffic of the CPU tag structure need to be handled. As + * of now no such logic is in place. So for the CPU port keep the fixed + * PVID=0 from initial setup in place and ignore all subsequent settings. + */ + if (port != priv->cpu_port) { + if (vlan->flags & BRIDGE_VLAN_INFO_PVID) + rtldsa_vlan_set_pvid(priv, port, vlan->vid); + else if (priv->ports[port].pvid == vlan->vid) + rtldsa_vlan_set_pvid(priv, port, 0); + } + + /* Get port memberships of this vlan */ + priv->r->vlan_tables_read(vlan->vid, &info); + + /* new VLAN? */ + if (!info.member_ports) { + info.fid = 0; + info.hash_mc_fid = false; + info.hash_uc_fid = false; + info.profile_id = 0; + } + + /* sanitize untagged_ports - must be a subset */ + if (info.untagged_ports & ~info.member_ports) + info.untagged_ports = 0; + + info.member_ports |= BIT_ULL(port); + if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED) + info.untagged_ports |= BIT_ULL(port); + else + info.untagged_ports &= ~BIT_ULL(port); + + priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports); + pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports); + + priv->r->vlan_set_tagged(vlan->vid, &info); + pr_debug("Member ports, VLAN %d: %llx\n", vlan->vid, info.member_ports); + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtldsa_vlan_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct rtl838x_vlan_info info; + struct rtl838x_switch_priv *priv = ds->priv; + u16 pvid; + + pr_debug("%s: port %d, vid %d, flags %x\n", + __func__, port, vlan->vid, vlan->flags); + + /* Let no one mess with our special VLAN 0 */ + if (!vlan->vid) + return 0; + + if (vlan->vid >= MAX_VLANS) { + dev_err(priv->dev, "VLAN out of range: %d", vlan->vid); + return -ENOTSUPP; + } + + mutex_lock(&priv->reg_mutex); + pvid = priv->ports[port].pvid; + + /* Reset to default if removing the current PVID */ + if (vlan->vid == pvid) + rtldsa_vlan_set_pvid(priv, port, 0); + + /* Get port memberships of this vlan */ + priv->r->vlan_tables_read(vlan->vid, &info); + + /* remove port from both tables */ + info.untagged_ports &= (~BIT_ULL(port)); + info.member_ports &= (~BIT_ULL(port)); + + /* VLANs without members are set back (implicitly) to CIST by DSA */ + if (!info.member_ports) { + u16 mst = info.fid; + + info.fid = 0; + + rtldsa_mst_put_slot(priv, mst); + } + + priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports); + pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports); + + priv->r->vlan_set_tagged(vlan->vid, &info); + pr_debug("Member ports, VLAN %d: %llx\n", vlan->vid, info.member_ports); + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +void rtldsa_port_fast_age(struct dsa_switch *ds, int port) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + mutex_lock(&priv->reg_mutex); + if (!priv->r->fast_age) + priv->r->fast_age(priv, port, -1); + mutex_unlock(&priv->reg_mutex); +} + +static int rtldsa_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) +{ + struct rtl838x_switch_priv *priv = ds->priv; + int ret; + + if (!priv->r->fast_age) + return -EOPNOTSUPP; + + mutex_lock(&priv->reg_mutex); + ret = priv->r->fast_age(priv, port, vid); + mutex_unlock(&priv->reg_mutex); + + return ret; +} + +static int rtldsa_vlan_msti_set(struct dsa_switch *ds, struct dsa_bridge bridge, + const struct switchdev_vlan_msti *msti) +{ + struct rtl838x_switch_priv *priv = ds->priv; + struct rtl838x_vlan_info info; + u16 mst_slot_old; + int mst_slot; + + priv->r->vlan_tables_read(msti->vid, &info); + mst_slot_old = info.fid; + + /* find HW slot for MSTI */ + mutex_lock(&priv->reg_mutex); + mst_slot = rtldsa_mst_replace(priv, msti->msti, mst_slot_old); + mutex_unlock(&priv->reg_mutex); + + if (mst_slot < 0) + return mst_slot; + + info.fid = mst_slot; + priv->r->vlan_set_tagged(msti->vid, &info); + + return 0; +} + +static void rtldsa_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, + int vid, u64 mac) +{ + memset(e, 0, sizeof(*e)); + + e->type = L2_UNICAST; + e->valid = true; + + e->age = 3; + e->is_static = true; + + e->port = port; + + e->rvid = e->vid = vid; + e->is_ip_mc = e->is_ipv6_mc = false; + u64_to_ether_addr(mac, e->mac); +} + +static void rtldsa_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group) +{ + memset(e, 0, sizeof(*e)); + + e->type = L2_MULTICAST; + e->valid = true; + + e->mc_portmask_index = mc_group; + + e->rvid = e->vid = vid; + e->is_ip_mc = e->is_ipv6_mc = false; + u64_to_ether_addr(mac, e->mac); +} + +/* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops + * over the entries in the bucket until either a matching entry is found or an empty slot + * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found + * when an empty slot was found and must exist is false, the index of the slot is returned + * when no slots are available returns -1 + */ +static int rtldsa_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed, + bool must_exist, struct rtl838x_l2_entry *e) +{ + int idx = -1; + u32 key = priv->r->l2_hash_key(priv, seed); + u64 entry; + + pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed); + /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */ + for (int i = 0; i < priv->l2_bucket_size; i++) { + entry = priv->r->read_l2_entry_using_hash(key, i, e); + pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0])); + if (must_exist && !e->valid) + continue; + if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) { + idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff; + break; + } + } + + return idx; +} + +/* Uses the seed to identify an entry in the CAM by looping over all its entries + * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found + * when an empty slot was found the index of the slot is returned + * when no slots are available returns -1 + */ +static int rtldsa_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed, + bool must_exist, struct rtl838x_l2_entry *e) +{ + int idx = -1; + u64 entry; + + for (int i = 0; i < 64; i++) { + entry = priv->r->read_cam(i, e); + if (!must_exist && !e->valid) { + if (idx < 0) /* First empty entry? */ + idx = i; + break; + } else if ((entry & 0x0fffffffffffffffULL) == seed) { + pr_debug("Found entry in CAM\n"); + idx = i; + break; + } + } + + return idx; +} + +/** + * rtldsa_find_lag_group_from_port() - Find lag group of current port + * @priv: private data of rtldsa switch + * @port: port id of potential LAG member + * Return: -ENOENT when port does not belong to any lag group, lag id otherwise + */ +static int rtldsa_find_lag_group_from_port(struct rtl838x_switch_priv *priv, int port) +{ + if (!(priv->lagmembers & BIT_ULL(port))) + return -ENOENT; + + /* port is a lag member */ + for (int lag_group = 0; lag_group < MAX_LAGS; lag_group++) { + if (priv->lags_port_members[lag_group] & BIT_ULL(port)) + return lag_group; + } + + return -ENOENT; +} + +/** + * rtldsa_93xx_prepare_lag_fdb() - Prepare fdb entry for LAG + * @e: L2 entry data + * @lag_group: lag id of the trunk group + */ +inline void rtldsa_93xx_prepare_lag_fdb(struct rtl838x_l2_entry *e, int lag_group) +{ + if (e && lag_group >= 0) { + e->is_trunk = true; + e->trunk = lag_group; + } +} + +static int rtldsa_port_fdb_add(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid, + const struct dsa_db db) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 mac = ether_addr_to_u64(addr); + struct rtl838x_l2_entry e; + int err = 0, idx; + u64 seed = priv->r->l2_hash_seed(mac, vid); + int lag_group = rtldsa_find_lag_group_from_port(priv, port); + + if (lag_group >= 0 && priv->r->prepare_lag_fdb) { + priv->r->prepare_lag_fdb(&e, lag_group); + } else { + if (priv->lag_non_primary & BIT_ULL(port)) { + pr_debug("%s: %d is lag slave but prepare_lag_fdb is not supported. ignore\n", + __func__, port); + return 0; + } + } + + mutex_lock(&priv->reg_mutex); + + idx = rtldsa_find_l2_hash_entry(priv, seed, false, &e); + + /* Found an existing or empty entry */ + if (idx >= 0) { + rtldsa_setup_l2_uc_entry(&e, port, vid, mac); + priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); + goto out; + } + + /* Hash buckets full, try CAM */ + idx = rtldsa_find_l2_cam_entry(priv, seed, false, &e); + + if (idx >= 0) { + rtldsa_setup_l2_uc_entry(&e, port, vid, mac); + priv->r->write_cam(idx, &e); + goto out; + } + + err = -ENOTSUPP; + +out: + mutex_unlock(&priv->reg_mutex); + + return err; +} + +static int rtldsa_port_fdb_del(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid, + const struct dsa_db db) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 mac = ether_addr_to_u64(addr); + struct rtl838x_l2_entry e; + int err = 0, idx; + u64 seed = priv->r->l2_hash_seed(mac, vid); + int lag_group = rtldsa_find_lag_group_from_port(priv, port); + + if (lag_group >= 0 && priv->r->prepare_lag_fdb) + priv->r->prepare_lag_fdb(&e, lag_group); + + pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid); + + mutex_lock(&priv->reg_mutex); + + idx = rtldsa_find_l2_hash_entry(priv, seed, true, &e); + + if (idx >= 0) { + pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3); + e.valid = false; + priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); + goto out; + } + + /* Check CAM for spillover from hash buckets */ + idx = rtldsa_find_l2_cam_entry(priv, seed, true, &e); + + if (idx >= 0) { + e.valid = false; + priv->r->write_cam(idx, &e); + goto out; + } + err = -ENOENT; + +out: + mutex_unlock(&priv->reg_mutex); + + return err; +} + +static int rtldsa_port_fdb_dump(struct dsa_switch *ds, int port, + dsa_fdb_dump_cb_t *cb, void *data) +{ + struct rtl838x_l2_entry e; + struct rtl838x_switch_priv *priv = ds->priv; + + mutex_lock(&priv->reg_mutex); + + for (int i = 0; i < priv->fib_entries; i++) { + priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e); + + if (!e.valid) + continue; + + // Ignore trunk fdb entries + if (e.is_trunk) + continue; + + if (e.port == port || e.port == RTL930X_PORT_IGNORE) + cb(e.mac, e.vid, e.is_static, data); + + if (!((i + 1) % 64)) + cond_resched(); + } + + for (int i = 0; i < 64; i++) { + priv->r->read_cam(i, &e); + + if (!e.valid) + continue; + + // Ignore trunk fdb entries + if (e.is_trunk) + continue; + + if (e.port == port) + cb(e.mac, e.vid, e.is_static, data); + } + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static bool rtldsa_mac_is_unsnoop(const unsigned char *addr) +{ + /* + * RFC4541, section 2.1.2.2 + section 3: + * Unsnoopable address ranges must always be flooded. + * + * mapped MAC for 224.0.0.x -> 01:00:5e:00:00:xx + * mapped MAC for ff02::1 -> 33:33:00:00:00:01 + */ + if (ether_addr_equal_masked(addr, ipv4_ll_mcast_addr_base, + ipv4_ll_mcast_addr_mask) || + ether_addr_equal_masked(addr, ipv6_all_hosts_mcast_addr_base, + ipv6_all_hosts_mcast_addr_mask)) + return true; + + return false; +} + +static int rtldsa_port_mdb_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_mdb *mdb, + const struct dsa_db db) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 mac = ether_addr_to_u64(mdb->addr); + struct rtl838x_l2_entry e; + int err = 0, idx; + int vid = mdb->vid; + u64 seed = priv->r->l2_hash_seed(mac, vid); + int mc_group; + + if (priv->id >= 0x9300) + return -EOPNOTSUPP; + + pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid); + + if (priv->lag_non_primary & BIT_ULL(port)) { + pr_debug("%s: %d is lag slave. ignore\n", __func__, port); + return -EINVAL; + } + + if (rtldsa_mac_is_unsnoop(mdb->addr)) { + dev_dbg(priv->dev, + "%s: %pM might belong to an unsnoopable IP. ignore\n", + __func__, mdb->addr); + return -EADDRNOTAVAIL; + } + + mutex_lock(&priv->reg_mutex); + + idx = rtldsa_find_l2_hash_entry(priv, seed, false, &e); + + /* Found an existing or empty entry */ + if (idx >= 0) { + if (e.valid) { + pr_debug("Found an existing entry %016llx, mc_group %d\n", + ether_addr_to_u64(e.mac), e.mc_portmask_index); + rtldsa_mc_group_add_port(priv, e.mc_portmask_index, port); + } else { + pr_debug("New entry for seed %016llx\n", seed); + mc_group = rtldsa_mc_group_alloc(priv, port); + if (mc_group < 0) { + err = -ENOTSUPP; + goto out; + } + rtldsa_setup_l2_mc_entry(&e, vid, mac, mc_group); + priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); + } + goto out; + } + + /* Hash buckets full, try CAM */ + idx = rtldsa_find_l2_cam_entry(priv, seed, false, &e); + + if (idx >= 0) { + if (e.valid) { + pr_debug("Found existing CAM entry %016llx, mc_group %d\n", + ether_addr_to_u64(e.mac), e.mc_portmask_index); + rtldsa_mc_group_add_port(priv, e.mc_portmask_index, port); + } else { + pr_debug("New entry\n"); + mc_group = rtldsa_mc_group_alloc(priv, port); + if (mc_group < 0) { + err = -ENOTSUPP; + goto out; + } + rtldsa_setup_l2_mc_entry(&e, vid, mac, mc_group); + priv->r->write_cam(idx, &e); + } + goto out; + } + + err = -ENOTSUPP; + +out: + mutex_unlock(&priv->reg_mutex); + if (err) + dev_err(ds->dev, "failed to add MDB entry\n"); + + return err; +} + +static int rtldsa_port_mdb_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_mdb *mdb, + const struct dsa_db db) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 mac = ether_addr_to_u64(mdb->addr); + struct rtl838x_l2_entry e; + int err = 0, idx; + int vid = mdb->vid; + u64 seed = priv->r->l2_hash_seed(mac, vid); + u64 portmask; + + pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid); + + if (priv->lag_non_primary & BIT_ULL(port)) { + pr_info("%s: %d is lag slave. ignore\n", __func__, port); + return 0; + } + + if (rtldsa_mac_is_unsnoop(mdb->addr)) { + dev_dbg(priv->dev, + "%s: %pM might belong to an unsnoopable IP. ignore\n", + __func__, mdb->addr); + return 0; + } + + mutex_lock(&priv->reg_mutex); + + idx = rtldsa_find_l2_hash_entry(priv, seed, true, &e); + + if (idx >= 0) { + pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3); + portmask = rtldsa_mc_group_del_port(priv, e.mc_portmask_index, port); + if (!portmask) { + e.valid = false; + priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); + } + goto out; + } + + /* Check CAM for spillover from hash buckets */ + idx = rtldsa_find_l2_cam_entry(priv, seed, true, &e); + + if (idx >= 0) { + portmask = rtldsa_mc_group_del_port(priv, e.mc_portmask_index, port); + if (!portmask) { + e.valid = false; + priv->r->write_cam(idx, &e); + } + goto out; + } + /* TODO: Re-enable with a newer kernel: err = -ENOENT; */ + +out: + mutex_unlock(&priv->reg_mutex); + + return err; +} + +static int rtldsa_port_mirror_add(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror, + bool ingress, struct netlink_ext_ack *extack) +{ + /* We support 4 mirror groups, one destination port per group */ + struct rtl838x_switch_priv *priv = ds->priv; + struct rtldsa_mirror_config config; + int err = 0; + int pm_reg; + int group; + int r; + + if (!priv->r->get_mirror_config) + return -EOPNOTSUPP; + + pr_debug("In %s\n", __func__); + + mutex_lock(&priv->reg_mutex); + + for (group = 0; group < 4; group++) { + if (priv->mirror_group_ports[group] == mirror->to_local_port) + break; + } + if (group >= 4) { + for (group = 0; group < 4; group++) { + if (priv->mirror_group_ports[group] < 0) + break; + } + } + + if (group >= 4) { + err = -ENOSPC; + goto out_unlock; + } + + pr_debug("Using group %d\n", group); + + r = priv->r->get_mirror_config(&config, group, mirror->to_local_port); + if (r < 0) { + err = r; + goto out_unlock; + } + + if (ingress) + pm_reg = config.spm; + else + pm_reg = config.dpm; + + sw_w32(config.val, config.ctrl); + + if (priv->r->get_port_reg_be(pm_reg) & (1ULL << port)) { + err = -EEXIST; + goto out_unlock; + } + + priv->r->mask_port_reg_be(0, 1ULL << port, pm_reg); + priv->mirror_group_ports[group] = mirror->to_local_port; + +out_unlock: + mutex_unlock(&priv->reg_mutex); + + return err; +} + +static void rtldsa_port_mirror_del(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror) +{ + struct rtl838x_switch_priv *priv = ds->priv; + struct rtldsa_mirror_config config; + int group = 0; + int r; + + if (!priv->r->get_mirror_config) + return; + + pr_debug("In %s\n", __func__); + + mutex_lock(&priv->reg_mutex); + + for (group = 0; group < 4; group++) { + if (priv->mirror_group_ports[group] == mirror->to_local_port) + break; + } + if (group >= 4) + goto out_unlock; + + r = priv->r->get_mirror_config(&config, group, mirror->to_local_port); + if (r < 0) + goto out_unlock; + + if (mirror->ingress) { + /* Ingress, clear source port matrix */ + priv->r->mask_port_reg_be(1ULL << port, 0, config.spm); + } else { + /* Egress, clear destination port matrix */ + priv->r->mask_port_reg_be(1ULL << port, 0, config.dpm); + } + + if (!(sw_r32(config.spm) || sw_r32(config.dpm))) { + priv->mirror_group_ports[group] = -1; + sw_w32(0, config.ctrl); + } + +out_unlock: + mutex_unlock(&priv->reg_mutex); +} + +static int rtldsa_port_pre_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + struct rtl838x_switch_priv *priv = ds->priv; + unsigned long features = BR_ISOLATED; + + pr_debug("%s: %d %lX\n", __func__, port, flags.val); + if (priv->r->enable_learning) + features |= BR_LEARNING; + if (priv->r->enable_flood) + features |= BR_FLOOD; + if (priv->r->enable_mcast_flood) + features |= BR_MCAST_FLOOD; + if (priv->r->enable_bcast_flood) + features |= BR_BCAST_FLOOD; + if (flags.mask & ~(features)) + return -EINVAL; + + return 0; +} + +static int rtldsa_port_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_debug("%s: %d %lX\n", __func__, port, flags.val); + if (priv->r->enable_learning && (flags.mask & BR_LEARNING)) + priv->r->enable_learning(port, !!(flags.val & BR_LEARNING)); + + if (priv->r->enable_flood && (flags.mask & BR_FLOOD)) + priv->r->enable_flood(port, !!(flags.val & BR_FLOOD)); + + if (priv->r->enable_mcast_flood && (flags.mask & BR_MCAST_FLOOD)) + priv->r->enable_mcast_flood(port, !!(flags.val & BR_MCAST_FLOOD)); + + if (priv->r->enable_bcast_flood && (flags.mask & BR_BCAST_FLOOD)) + priv->r->enable_bcast_flood(port, !!(flags.val & BR_BCAST_FLOOD)); + + if (flags.mask & BR_ISOLATED) { + struct dsa_port *dp = dsa_to_port(ds, port); + struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp); + + priv->ports[port].isolated = !!(flags.val & BR_ISOLATED); + + mutex_lock(&priv->reg_mutex); + rtldsa_update_port_member(priv, port, bridge_dev, true); + mutex_unlock(&priv->reg_mutex); + } + + return 0; +} + +static bool rtldsa_83xx_lag_can_offload(struct dsa_switch *ds, + struct net_device *lag, + struct netdev_lag_upper_info *info) +{ + int id; + + id = dsa_lag_id(ds->dst, lag); + if (id < 0 || id >= ds->num_lag_ids) + return false; + + if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) + return false; + + if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23) + return false; + + return true; +} + +static int rtldsa_port_lag_change(struct dsa_switch *ds, int port) +{ + struct dsa_port *dp = dsa_to_port(ds, port); + struct rtl838x_switch_priv *priv = ds->priv; + int lag_group; + int ret; + + if (!dp) + return -EINVAL; + + lag_group = rtldsa_find_lag_group_from_port(priv, port); + if (lag_group < 0) + return lag_group; + + if (priv->r->lag_set_port_members) { + /* Set same port members again, the function should check against + * lag_tx_enabled and set egress ports accordingly. + */ + ret = priv->r->lag_set_port_members(priv, lag_group, + priv->lags_port_members[lag_group], + NULL); + if (ret) + return ret; + } + + return 0; +} + +static int rtldsa_port_lag_join(struct dsa_switch *ds, + int port, + struct dsa_lag lag, + struct netdev_lag_upper_info *info, + struct netlink_ext_ack *extack) +{ + struct rtl838x_switch_priv *priv = ds->priv; + int err = 0; + int group; + + if (!rtldsa_83xx_lag_can_offload(ds, lag.dev, info)) + return -EOPNOTSUPP; + + mutex_lock(&priv->reg_mutex); + + if (port >= priv->cpu_port) { + err = -EINVAL; + goto out; + } + + group = dsa_lag_id(ds->dst, lag.dev); + + pr_info("port_lag_join: group %d, port %d\n", group, port); + + if (priv->lag_primary[group] == -1) + priv->lag_primary[group] = port; + else + priv->lag_non_primary |= BIT_ULL(port); + + priv->lagmembers |= BIT_ULL(port); + + pr_debug("lag_members = %llX\n", priv->lagmembers); + err = rtl83xx_lag_add(priv->ds, group, port, info); + if (err) { + err = -EINVAL; + goto out; + } + +out: + mutex_unlock(&priv->reg_mutex); + + return err; +} + +static int rtldsa_port_lag_leave(struct dsa_switch *ds, int port, + struct dsa_lag lag) +{ + int group, err; + struct rtl838x_switch_priv *priv = ds->priv; + + mutex_lock(&priv->reg_mutex); + + group = dsa_lag_id(ds->dst, lag.dev); + if (group == -1) { + pr_info("port_lag_leave: group %d not set\n", port); + err = -EINVAL; + goto out; + } + + if (port >= priv->cpu_port) { + err = -EINVAL; + goto out; + } + pr_info("port_lag_del: group %d, port %d\n", group, port); + priv->lagmembers &= ~BIT_ULL(port); + priv->lag_non_primary &= ~BIT_ULL(port); + pr_debug("lag_members = %llX\n", priv->lagmembers); + err = rtl83xx_lag_del(priv->ds, group, port); + if (err) { + err = -EINVAL; + goto out; + } + + /* To re-elect primary interface, just remove the first interface in + * this-group's interfaces from non-primary + */ + if (priv->lags_port_members[group]) { + priv->lag_primary[group] = fls64(priv->lags_port_members[group]); + priv->lag_non_primary &= ~BIT_ULL(priv->lag_primary[group]); + } + + /* No need to update fdb entries since they make use of trunk_id for entry. + * The primary interface is only calculated at time of + * port_fdb_dump + */ + +out: + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static int rtldsa_phy_read(struct dsa_switch *ds, int addr, int regnum) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + return mdiobus_read_nested(priv->parent_bus, addr, regnum); +} + +static int rtldsa_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + return mdiobus_write_nested(priv->parent_bus, addr, regnum, val); +} + +static const struct flow_action_entry *rtldsa_rate_policy_extract(struct flow_cls_offload *cls) +{ + struct flow_rule *rule; + + /* only simple rules with a single action are supported */ + rule = flow_cls_offload_flow_rule(cls); + + if (!flow_action_basic_hw_stats_check(&cls->rule->action, + cls->common.extack)) + return NULL; + + if (!flow_offload_has_one_action(&rule->action)) + return NULL; + + return &rule->action.entries[0]; +} + +static bool rtldsa_port_rate_police_validate(const struct flow_action_entry *act) +{ + if (!act) + return false; + + /* only allow action which just limit rate with by dropping packets */ + if (act->id != FLOW_ACTION_POLICE) + return false; + + if (act->police.rate_pkt_ps > 0) + return false; + + if (act->police.exceed.act_id != FLOW_ACTION_DROP) + return false; + + if (act->police.notexceed.act_id != FLOW_ACTION_ACCEPT) + return false; + + return true; +} + +static int rtldsa_cls_flower_add(struct dsa_switch *ds, int port, + struct flow_cls_offload *cls, + bool ingress) +{ + struct rtl838x_switch_priv *priv = ds->priv; + struct rtldsa_port *p = &priv->ports[port]; + const struct flow_action_entry *act; + int ret; + + if (!priv->r->port_rate_police_add) + return -EOPNOTSUPP; + + /* the single action must be a rate/bandwidth limiter */ + act = rtldsa_rate_policy_extract(cls); + + if (!rtldsa_port_rate_police_validate(act)) + return -EOPNOTSUPP; + + mutex_lock(&priv->reg_mutex); + + /* only allow one offloaded police for ingress/egress */ + if (ingress && p->rate_police_ingress) { + ret = -EOPNOTSUPP; + goto unlock; + } + + if (!ingress && p->rate_police_egress) { + ret = -EOPNOTSUPP; + goto unlock; + } + + ret = priv->r->port_rate_police_add(ds, port, act, ingress); + if (ret < 0) + goto unlock; + + if (ingress) + p->rate_police_ingress = true; + else + p->rate_police_egress = true; + +unlock: + mutex_unlock(&priv->reg_mutex); + + return ret; +} + +static int rtldsa_cls_flower_del(struct dsa_switch *ds, int port, + struct flow_cls_offload *cls, + bool ingress) +{ + struct rtl838x_switch_priv *priv = ds->priv; + struct rtldsa_port *p = &priv->ports[port]; + int ret; + + if (!priv->r->port_rate_police_del) + return -EOPNOTSUPP; + + mutex_lock(&priv->reg_mutex); + + ret = priv->r->port_rate_police_del(ds, port, cls, ingress); + if (ret < 0) + goto unlock; + + if (ingress) + p->rate_police_ingress = false; + else + p->rate_police_egress = false; + +unlock: + mutex_unlock(&priv->reg_mutex); + + return ret; +} + +const struct dsa_switch_ops rtldsa_83xx_switch_ops = { + .get_tag_protocol = rtldsa_get_tag_protocol, + .setup = rtldsa_83xx_setup, + + .phy_read = rtldsa_phy_read, + .phy_write = rtldsa_phy_write, + + .phylink_get_caps = rtldsa_83xx_phylink_get_caps, + .phylink_mac_config = rtldsa_83xx_phylink_mac_config, + .phylink_mac_link_down = rtldsa_83xx_phylink_mac_link_down, + .phylink_mac_link_up = rtldsa_83xx_phylink_mac_link_up, + .phylink_mac_select_pcs = rtldsa_phylink_mac_select_pcs, + + .get_strings = rtldsa_get_strings, + .get_ethtool_stats = rtldsa_get_ethtool_stats, + .get_sset_count = rtldsa_get_sset_count, + .get_eth_phy_stats = rtldsa_get_eth_phy_stats, + .get_eth_mac_stats = rtldsa_get_eth_mac_stats, + .get_eth_ctrl_stats = rtldsa_get_eth_ctrl_stats, + .get_rmon_stats = rtldsa_get_rmon_stats, + .get_stats64 = rtldsa_get_stats64, + .get_pause_stats = rtldsa_get_pause_stats, + + .port_enable = rtldsa_port_enable, + .port_disable = rtldsa_port_disable, + + .get_mac_eee = rtldsa_get_mac_eee, + .set_mac_eee = rtldsa_set_mac_eee, + + .set_ageing_time = rtldsa_set_ageing_time, + .port_bridge_join = rtldsa_port_bridge_join, + .port_bridge_leave = rtldsa_port_bridge_leave, + .port_stp_state_set = rtldsa_port_stp_state_set, + .port_fast_age = rtldsa_port_fast_age, + .port_mst_state_set = rtldsa_port_mst_state_set, + + .port_vlan_filtering = rtldsa_vlan_filtering, + .port_vlan_add = rtldsa_vlan_add, + .port_vlan_del = rtldsa_vlan_del, + .port_vlan_fast_age = rtldsa_port_vlan_fast_age, + .vlan_msti_set = rtldsa_vlan_msti_set, + + .port_fdb_add = rtldsa_port_fdb_add, + .port_fdb_del = rtldsa_port_fdb_del, + .port_fdb_dump = rtldsa_port_fdb_dump, + + .port_mdb_add = rtldsa_port_mdb_add, + .port_mdb_del = rtldsa_port_mdb_del, + + .port_mirror_add = rtldsa_port_mirror_add, + .port_mirror_del = rtldsa_port_mirror_del, + + .port_lag_change = rtldsa_port_lag_change, + .port_lag_join = rtldsa_port_lag_join, + .port_lag_leave = rtldsa_port_lag_leave, + + .port_pre_bridge_flags = rtldsa_port_pre_bridge_flags, + .port_bridge_flags = rtldsa_port_bridge_flags, +}; + +const struct dsa_switch_ops rtldsa_93xx_switch_ops = { + .get_tag_protocol = rtldsa_get_tag_protocol, + .setup = rtldsa_93xx_setup, + + .phy_read = rtldsa_phy_read, + .phy_write = rtldsa_phy_write, + + .phylink_get_caps = rtldsa_93xx_phylink_get_caps, + .phylink_mac_config = rtldsa_93xx_phylink_mac_config, + .phylink_mac_link_down = rtldsa_93xx_phylink_mac_link_down, + .phylink_mac_link_up = rtldsa_93xx_phylink_mac_link_up, + .phylink_mac_select_pcs = rtldsa_phylink_mac_select_pcs, + + .get_strings = rtldsa_get_strings, + .get_ethtool_stats = rtldsa_get_ethtool_stats, + .get_sset_count = rtldsa_get_sset_count, + .get_eth_phy_stats = rtldsa_get_eth_phy_stats, + .get_eth_mac_stats = rtldsa_get_eth_mac_stats, + .get_eth_ctrl_stats = rtldsa_get_eth_ctrl_stats, + .get_rmon_stats = rtldsa_get_rmon_stats, + .get_stats64 = rtldsa_get_stats64, + .get_pause_stats = rtldsa_get_pause_stats, + + .port_enable = rtldsa_port_enable, + .port_disable = rtldsa_port_disable, + + .get_mac_eee = rtldsa_get_mac_eee, + .set_mac_eee = rtldsa_set_mac_eee, + + .set_ageing_time = rtldsa_set_ageing_time, + .port_bridge_join = rtldsa_port_bridge_join, + .port_bridge_leave = rtldsa_port_bridge_leave, + .port_stp_state_set = rtldsa_port_stp_state_set, + .port_fast_age = rtldsa_port_fast_age, + .port_mst_state_set = rtldsa_port_mst_state_set, + + .port_vlan_filtering = rtldsa_vlan_filtering, + .port_vlan_add = rtldsa_vlan_add, + .port_vlan_del = rtldsa_vlan_del, + .port_vlan_fast_age = rtldsa_port_vlan_fast_age, + .vlan_msti_set = rtldsa_vlan_msti_set, + + .port_fdb_add = rtldsa_port_fdb_add, + .port_fdb_del = rtldsa_port_fdb_del, + .port_fdb_dump = rtldsa_port_fdb_dump, + + .port_mdb_add = rtldsa_port_mdb_add, + .port_mdb_del = rtldsa_port_mdb_del, + + .port_mirror_add = rtldsa_port_mirror_add, + .port_mirror_del = rtldsa_port_mirror_del, + + .port_lag_change = rtldsa_port_lag_change, + .port_lag_join = rtldsa_port_lag_join, + .port_lag_leave = rtldsa_port_lag_leave, + + .port_pre_bridge_flags = rtldsa_port_pre_bridge_flags, + .port_bridge_flags = rtldsa_port_bridge_flags, + + .cls_flower_add = rtldsa_cls_flower_add, + .cls_flower_del = rtldsa_cls_flower_del, +}; diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/qos.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/qos.c new file mode 100644 index 0000000000..b620cc6350 --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/qos.c @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include "rtl83xx.h" + +enum scheduler_type { + WEIGHTED_FAIR_QUEUE = 0, + WEIGHTED_ROUND_ROBIN, +}; + +int rtldsa_max_available_queue[] = {0, 1, 2, 3, 4, 5, 6, 7}; +int rtldsa_default_queue_weights[] = {1, 1, 1, 1, 1, 1, 1, 1}; +int dot1p_priority_remapping[] = {0, 1, 2, 3, 4, 5, 6, 7}; + +static void rtl839x_read_scheduling_table(int port) +{ + u32 cmd = 1 << 9 | /* Execute cmd */ + 0 << 8 | /* Read */ + 0 << 6 | /* Table type 0b00 */ + (port & 0x3f); + rtl839x_exec_tbl2_cmd(cmd); +} + +static void rtl839x_write_scheduling_table(int port) +{ + u32 cmd = 1 << 9 | /* Execute cmd */ + 1 << 8 | /* Write */ + 0 << 6 | /* Table type 0b00 */ + (port & 0x3f); + rtl839x_exec_tbl2_cmd(cmd); +} + +static void rtl839x_read_out_q_table(int port) +{ + u32 cmd = 1 << 9 | /* Execute cmd */ + 0 << 8 | /* Read */ + 2 << 6 | /* Table type 0b10 */ + (port & 0x3f); + rtl839x_exec_tbl2_cmd(cmd); +} + +u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port) +{ + if (port > priv->cpu_port) + return 0; + + return sw_r32(RTL838X_SCHED_P_EGR_RATE_CTRL(port)) & 0x3fff; +} + +/* Sets the rate limit, 10MBit/s is equal to a rate value of 625 */ +int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate) +{ + u32 old_rate; + + if (port > priv->cpu_port) + return -1; + + old_rate = sw_r32(RTL838X_SCHED_P_EGR_RATE_CTRL(port)); + sw_w32(rate, RTL838X_SCHED_P_EGR_RATE_CTRL(port)); + + return old_rate; +} + +/* Sets the rate limit, 10MBit/s is equal to a rate value of 625 */ +u32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port) +{ + u32 rate; + + pr_debug("%s: Getting egress rate on port %d to %d\n", __func__, port, rate); + if (port >= priv->cpu_port) + return 0; + + mutex_lock(&priv->reg_mutex); + + rtl839x_read_scheduling_table(port); + + rate = sw_r32(RTL839X_TBL_ACCESS_DATA_2(7)); + rate <<= 12; + rate |= sw_r32(RTL839X_TBL_ACCESS_DATA_2(8)) >> 20; + + mutex_unlock(&priv->reg_mutex); + + return rate; +} + +/* Sets the rate limit, 10MBit/s is equal to a rate value of 625, returns previous rate */ +int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate) +{ + u32 old_rate; + + pr_debug("%s: Setting egress rate on port %d to %d\n", __func__, port, rate); + if (port >= priv->cpu_port) + return -1; + + mutex_lock(&priv->reg_mutex); + + rtl839x_read_scheduling_table(port); + + old_rate = sw_r32(RTL839X_TBL_ACCESS_DATA_2(7)) & 0xff; + old_rate <<= 12; + old_rate |= sw_r32(RTL839X_TBL_ACCESS_DATA_2(8)) >> 20; + sw_w32_mask(0xff, (rate >> 12) & 0xff, RTL839X_TBL_ACCESS_DATA_2(7)); + sw_w32_mask(0xfff << 20, rate << 20, RTL839X_TBL_ACCESS_DATA_2(8)); + + rtl839x_write_scheduling_table(port); + + mutex_unlock(&priv->reg_mutex); + + return old_rate; +} + +static void rtl838x_setup_prio2queue_matrix(int *min_queues) +{ + u32 v = 0; + + pr_info("Current Intprio2queue setting: %08x\n", sw_r32(RTL838X_QM_INTPRI2QID_CTRL)); + for (int i = 0; i < MAX_PRIOS; i++) + v |= i << (min_queues[i] * 3); + sw_w32(v, RTL838X_QM_INTPRI2QID_CTRL); +} + +static void rtl839x_setup_prio2queue_matrix(int *min_queues) +{ + pr_info("Current Intprio2queue setting: %08x\n", sw_r32(RTL839X_QM_INTPRI2QID_CTRL(0))); + for (int i = 0; i < MAX_PRIOS; i++) { + int q = min_queues[i]; + + sw_w32(i << (q * 3), RTL839X_QM_INTPRI2QID_CTRL(q)); + } +} + +/* Sets the CPU queue depending on the internal priority of a packet */ +static void rtl83xx_setup_prio2queue_cpu_matrix(int *max_queues) +{ + int reg = soc_info.family == RTL8380_FAMILY_ID ? RTL838X_QM_PKT2CPU_INTPRI_MAP + : RTL839X_QM_PKT2CPU_INTPRI_MAP; + u32 v = 0; + + pr_info("QM_PKT2CPU_INTPRI_MAP: %08x\n", sw_r32(reg)); + for (int i = 0; i < MAX_PRIOS; i++) + v |= max_queues[i] << (i * 3); + sw_w32(v, reg); +} + +static void rtl83xx_setup_default_prio2queue(void) +{ + if (soc_info.family == RTL8380_FAMILY_ID) + rtl838x_setup_prio2queue_matrix(rtldsa_max_available_queue); + else + rtl839x_setup_prio2queue_matrix(rtldsa_max_available_queue); + + rtl83xx_setup_prio2queue_cpu_matrix(rtldsa_max_available_queue); +} + +/* Sets the output queue assigned to a port, the port can be the CPU-port */ +void rtl839x_set_egress_queue(int port, int queue) +{ + sw_w32(queue << ((port % 10) * 3), RTL839X_QM_PORT_QNUM(port)); +} + +/* Sets the priority assigned of an ingress port, the port can be the CPU-port */ +static void rtl83xx_set_ingress_priority(int port, int priority) +{ + if (soc_info.family == RTL8380_FAMILY_ID) + sw_w32(priority << ((port % 10) * 3), RTL838X_PRI_SEL_PORT_PRI(port)); + else + sw_w32(priority << ((port % 10) * 3), RTL839X_PRI_SEL_PORT_PRI(port)); +} + +static int rtl839x_get_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port) +{ + u32 v; + + mutex_lock(&priv->reg_mutex); + + rtl839x_read_scheduling_table(port); + v = sw_r32(RTL839X_TBL_ACCESS_DATA_2(8)); + + mutex_unlock(&priv->reg_mutex); + + if (v & BIT(19)) + return WEIGHTED_ROUND_ROBIN; + + return WEIGHTED_FAIR_QUEUE; +} + +static void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port, + enum scheduler_type sched) +{ + enum scheduler_type t = rtl839x_get_scheduling_algorithm(priv, port); + u32 v, oam_state, oam_port_state; + u32 count; + int i, egress_rate; + + mutex_lock(&priv->reg_mutex); + /* Check whether we need to empty the egress queue of that port due to Errata E0014503 */ + if (sched == WEIGHTED_FAIR_QUEUE && t == WEIGHTED_ROUND_ROBIN && port != priv->cpu_port) { + /* Read Operations, Adminstatrion and Management control register */ + oam_state = sw_r32(RTL839X_OAM_CTRL); + + /* Get current OAM state */ + oam_port_state = sw_r32(RTL839X_OAM_PORT_ACT_CTRL(port)); + + /* Disable OAM to block traffice */ + v = sw_r32(RTL839X_OAM_CTRL); + sw_w32_mask(0, 1, RTL839X_OAM_CTRL); + v = sw_r32(RTL839X_OAM_CTRL); + + /* Set to trap action OAM forward (bits 1, 2) and OAM Mux Action Drop (bit 0) */ + sw_w32(0x2, RTL839X_OAM_PORT_ACT_CTRL(port)); + + /* Set port egress rate to unlimited */ + egress_rate = rtl839x_set_egress_rate(priv, port, 0xFFFFF); + + /* Wait until the egress used page count of that port is 0 */ + i = 0; + do { + usleep_range(100, 200); + rtl839x_read_out_q_table(port); + count = sw_r32(RTL839X_TBL_ACCESS_DATA_2(6)); + count >>= 20; + i++; + } while (i < 3500 && count > 0); + } + + /* Actually set the scheduling algorithm */ + rtl839x_read_scheduling_table(port); + sw_w32_mask(BIT(19), sched ? BIT(19) : 0, RTL839X_TBL_ACCESS_DATA_2(8)); + rtl839x_write_scheduling_table(port); + + if (sched == WEIGHTED_FAIR_QUEUE && t == WEIGHTED_ROUND_ROBIN && port != priv->cpu_port) { + /* Restore OAM state to control register */ + sw_w32(oam_state, RTL839X_OAM_CTRL); + + /* Restore trap action state */ + sw_w32(oam_port_state, RTL839X_OAM_PORT_ACT_CTRL(port)); + + /* Restore port egress rate */ + rtl839x_set_egress_rate(priv, port, egress_rate); + } + + mutex_unlock(&priv->reg_mutex); +} + +static void rtl839x_set_scheduling_queue_weights(struct rtl838x_switch_priv *priv, int port, + int *queue_weights) +{ + mutex_lock(&priv->reg_mutex); + + rtl839x_read_scheduling_table(port); + + for (int i = 0; i < 8; i++) { + int lsb = 48 + i * 8; + int low_byte = 8 - (lsb >> 5); + int start_bit = lsb - (low_byte << 5); + int high_mask = 0x3ff >> (32 - start_bit); + + sw_w32_mask(0x3ff << start_bit, (queue_weights[i] & 0x3ff) << start_bit, + RTL839X_TBL_ACCESS_DATA_2(low_byte)); + if (high_mask) + sw_w32_mask(high_mask, (queue_weights[i] & 0x3ff) >> (32 - start_bit), + RTL839X_TBL_ACCESS_DATA_2(low_byte - 1)); + } + + rtl839x_write_scheduling_table(port); + mutex_unlock(&priv->reg_mutex); +} + +void rtldsa_838x_qos_init(struct rtl838x_switch_priv *priv) +{ + u32 v; + + pr_info("Setting up RTL838X QoS\n"); + pr_info("RTL838X_PRI_SEL_TBL_CTRL(i): %08x\n", sw_r32(RTL838X_PRI_SEL_TBL_CTRL(0))); + rtl83xx_setup_default_prio2queue(); + + /* Enable inner (bit 12) and outer (bit 13) priority remapping from DSCP */ + sw_w32_mask(0, BIT(12) | BIT(13), RTL838X_PRI_DSCP_INVLD_CTRL0); + + /* Set default weight for calculating internal priority, in prio selection group 0 + * Port based (prio 3), Port outer-tag (4), DSCP (5), Inner Tag (6), Outer Tag (7) + */ + v = 3 | (4 << 3) | (5 << 6) | (6 << 9) | (7 << 12); + sw_w32(v, RTL838X_PRI_SEL_TBL_CTRL(0)); + + /* Set the inner and outer priority one-to-one to re-marked outer dot1p priority */ + v = 0; + for (int p = 0; p < 8; p++) + v |= p << (3 * p); + sw_w32(v, RTL838X_RMK_OPRI_CTRL); + sw_w32(v, RTL838X_RMK_IPRI_CTRL); + + v = 0; + for (int p = 0; p < 8; p++) + v |= (dot1p_priority_remapping[p] & 0x7) << (p * 3); + sw_w32(v, RTL838X_PRI_SEL_IPRI_REMAP); + + /* On all ports set scheduler type to WFQ */ + for (int i = 0; i <= soc_info.cpu_port; i++) + sw_w32(0, RTL838X_SCHED_P_TYPE_CTRL(i)); + + /* Enable egress scheduler for CPU-Port */ + sw_w32_mask(0, BIT(8), RTL838X_SCHED_LB_CTRL(soc_info.cpu_port)); + + /* Enable egress drop allways on */ + sw_w32_mask(0, BIT(11), RTL838X_FC_P_EGR_DROP_CTRL(soc_info.cpu_port)); + + /* Give special trap frames priority 7 (BPDUs) and routing exceptions: */ + sw_w32_mask(0, 7 << 3 | 7, RTL838X_QM_PKT2CPU_INTPRI_2); + /* Give RMA frames priority 7: */ + sw_w32_mask(0, 7, RTL838X_QM_PKT2CPU_INTPRI_1); +} + +void rtldsa_839x_qos_init(struct rtl838x_switch_priv *priv) +{ + u32 v; + + pr_info("Setting up RTL839X QoS\n"); + pr_info("RTL839X_PRI_SEL_TBL_CTRL(i): %08x\n", sw_r32(RTL839X_PRI_SEL_TBL_CTRL(0))); + rtl83xx_setup_default_prio2queue(); + + for (int port = 0; port < soc_info.cpu_port; port++) + sw_w32(7, RTL839X_QM_PORT_QNUM(port)); + + /* CPU-port gets queue number 7 */ + sw_w32(7, RTL839X_QM_PORT_QNUM(soc_info.cpu_port)); + + for (int port = 0; port <= soc_info.cpu_port; port++) { + rtl83xx_set_ingress_priority(port, 0); + rtl839x_set_scheduling_algorithm(priv, port, WEIGHTED_FAIR_QUEUE); + rtl839x_set_scheduling_queue_weights(priv, port, rtldsa_default_queue_weights); + /* Do re-marking based on outer tag */ + sw_w32_mask(0, BIT(port % 32), RTL839X_RMK_PORT_DEI_TAG_CTRL(port)); + } + + /* Remap dot1p priorities to internal priority, for this the outer tag needs be re-marked */ + v = 0; + for (int p = 0; p < 8; p++) + v |= (dot1p_priority_remapping[p] & 0x7) << (p * 3); + sw_w32(v, RTL839X_PRI_SEL_IPRI_REMAP); + + /* Configure Drop Precedence for Drop Eligible Indicator (DEI) + * Index 0: 0 + * Index 1: 2 + * Each indicator is 2 bits long + */ + sw_w32(2 << 2, RTL839X_PRI_SEL_DEI2DP_REMAP); + + /* Re-mark DEI: 4 bit-fields of 2 bits each, field 0 is bits 0-1, ... */ + sw_w32((0x1 << 2) | (0x1 << 4), RTL839X_RMK_DEI_CTRL); + + /* Set Congestion avoidance drop probability to 0 for drop precedences 0-2 (bits 24-31) + * low threshold (bits 0-11) to 4095 and high threshold (bits 12-23) to 4095 + * Weighted Random Early Detection (WRED) is used + */ + sw_w32(4095 << 12 | 4095, RTL839X_WRED_PORT_THR_CTRL(0)); + sw_w32(4095 << 12 | 4095, RTL839X_WRED_PORT_THR_CTRL(1)); + sw_w32(4095 << 12 | 4095, RTL839X_WRED_PORT_THR_CTRL(2)); + + /* Set queue-based congestion avoidance properties, register fields are as + * for forward RTL839X_WRED_PORT_THR_CTRL + */ + for (int q = 0; q < 8; q++) { + sw_w32(255 << 24 | 78 << 12 | 68, RTL839X_WRED_QUEUE_THR_CTRL(q, 0)); + sw_w32(255 << 24 | 74 << 12 | 64, RTL839X_WRED_QUEUE_THR_CTRL(q, 0)); + sw_w32(255 << 24 | 70 << 12 | 60, RTL839X_WRED_QUEUE_THR_CTRL(q, 0)); + } +} diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c new file mode 100644 index 0000000000..4cdcfc50a5 --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c @@ -0,0 +1,1900 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include + +#include "rtl83xx.h" + +#define RTL838X_VLAN_PORT_TAG_STS_UNTAG 0x0 +#define RTL838X_VLAN_PORT_TAG_STS_TAGGED 0x1 +#define RTL838X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x2 + +#define RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE 0xA530 +/* port 0-28 */ +#define RTL838X_VLAN_PORT_TAG_STS_CTRL(port) \ + (RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)) + +#define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(11, 10) +#define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(9, 8) +#define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(7, 6) +#define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(5, 4) +#define RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK GENMASK(3, 2) +#define RTL838X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK GENMASK(1, 0) + +/* see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c */ +/* Definition of the RTL838X-specific template field IDs as used in the PIE */ +enum template_field_id { + TEMPLATE_FIELD_SPMMASK = 0, + TEMPLATE_FIELD_SPM0 = 1, /* Source portmask ports 0-15 */ + TEMPLATE_FIELD_SPM1 = 2, /* Source portmask ports 16-28 */ + TEMPLATE_FIELD_RANGE_CHK = 3, + TEMPLATE_FIELD_DMAC0 = 4, /* Destination MAC [15:0] */ + TEMPLATE_FIELD_DMAC1 = 5, /* Destination MAC [31:16] */ + TEMPLATE_FIELD_DMAC2 = 6, /* Destination MAC [47:32] */ + TEMPLATE_FIELD_SMAC0 = 7, /* Source MAC [15:0] */ + TEMPLATE_FIELD_SMAC1 = 8, /* Source MAC [31:16] */ + TEMPLATE_FIELD_SMAC2 = 9, /* Source MAC [47:32] */ + TEMPLATE_FIELD_ETHERTYPE = 10, /* Ethernet typ */ + TEMPLATE_FIELD_OTAG = 11, /* Outer VLAN tag */ + TEMPLATE_FIELD_ITAG = 12, /* Inner VLAN tag */ + TEMPLATE_FIELD_SIP0 = 13, /* IPv4 or IPv6 source IP[15:0] or ARP/RARP */ + /* source protocol address in header */ + TEMPLATE_FIELD_SIP1 = 14, /* IPv4 or IPv6 source IP[31:16] or ARP/RARP */ + TEMPLATE_FIELD_DIP0 = 15, /* IPv4 or IPv6 destination IP[15:0] */ + TEMPLATE_FIELD_DIP1 = 16, /* IPv4 or IPv6 destination IP[31:16] */ + TEMPLATE_FIELD_IP_TOS_PROTO = 17, /* IPv4 TOS/IPv6 traffic class and */ + /* IPv4 proto/IPv6 next header fields */ + TEMPLATE_FIELD_L34_HEADER = 18, /* packet with extra tag and IPv6 with auth, dest, */ + /* frag, route, hop-by-hop option header, */ + /* IGMP type, TCP flag */ + TEMPLATE_FIELD_L4_SPORT = 19, /* TCP/UDP source port */ + TEMPLATE_FIELD_L4_DPORT = 20, /* TCP/UDP destination port */ + TEMPLATE_FIELD_ICMP_IGMP = 21, + TEMPLATE_FIELD_IP_RANGE = 22, + TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 23, /* Field selector mask */ + TEMPLATE_FIELD_FIELD_SELECTOR_0 = 24, + TEMPLATE_FIELD_FIELD_SELECTOR_1 = 25, + TEMPLATE_FIELD_FIELD_SELECTOR_2 = 26, + TEMPLATE_FIELD_FIELD_SELECTOR_3 = 27, + TEMPLATE_FIELD_SIP2 = 28, /* IPv6 source IP[47:32] */ + TEMPLATE_FIELD_SIP3 = 29, /* IPv6 source IP[63:48] */ + TEMPLATE_FIELD_SIP4 = 30, /* IPv6 source IP[79:64] */ + TEMPLATE_FIELD_SIP5 = 31, /* IPv6 source IP[95:80] */ + TEMPLATE_FIELD_SIP6 = 32, /* IPv6 source IP[111:96] */ + TEMPLATE_FIELD_SIP7 = 33, /* IPv6 source IP[127:112] */ + TEMPLATE_FIELD_DIP2 = 34, /* IPv6 destination IP[47:32] */ + TEMPLATE_FIELD_DIP3 = 35, /* IPv6 destination IP[63:48] */ + TEMPLATE_FIELD_DIP4 = 36, /* IPv6 destination IP[79:64] */ + TEMPLATE_FIELD_DIP5 = 37, /* IPv6 destination IP[95:80] */ + TEMPLATE_FIELD_DIP6 = 38, /* IPv6 destination IP[111:96] */ + TEMPLATE_FIELD_DIP7 = 39, /* IPv6 destination IP[127:112] */ + TEMPLATE_FIELD_FWD_VID = 40, /* Forwarding VLAN-ID */ + TEMPLATE_FIELD_FLOW_LABEL = 41, +}; + +/* The RTL838X SoCs use 5 fixed templates with definitions for which data fields are to + * be copied from the Ethernet Frame header into the 12 User-definable fields of the Packet + * Inspection Engine's buffer. The following defines the field contents for each of the fixed + * templates. Additionally, 3 user-definable templates can be set up via the definitions + * in RTL838X_ACL_TMPLTE_CTRL control registers. + * TODO: See all src/app/diag_v2/src/diag_pie.c + */ +#define N_FIXED_TEMPLATES 5 +static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = { + { + TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_OTAG, + TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2, + TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, + TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_RANGE_CHK + }, { + TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, + TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT, + TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_ITAG, + TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1 + }, { + TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, + TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO, + TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0, + TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1 + }, { + TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2, + TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5, + TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT, + TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO + }, { + TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2, + TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5, + TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_ITAG, + TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1 + }, +}; + +const struct rtldsa_mib_list_item rtldsa_838x_mib_list[] = { + MIB_LIST_ITEM("dot1dTpPortInDiscards", MIB_ITEM(MIB_REG_STD, 0xec, 1)), + MIB_LIST_ITEM("ifOutDiscards", MIB_ITEM(MIB_REG_STD, 0xd0, 1)), + MIB_LIST_ITEM("DropEvents", MIB_ITEM(MIB_REG_STD, 0xa8, 1)), + MIB_LIST_ITEM("tx_BroadcastPkts", MIB_ITEM(MIB_REG_STD, 0xa4, 1)), + MIB_LIST_ITEM("tx_MulticastPkts", MIB_ITEM(MIB_REG_STD, 0xa0, 1)), + MIB_LIST_ITEM("tx_UndersizePkts", MIB_ITEM(MIB_REG_STD, 0x98, 1)), + MIB_LIST_ITEM("rx_UndersizeDropPkts", MIB_ITEM(MIB_REG_STD, 0x90, 1)), + MIB_LIST_ITEM("tx_OversizePkts", MIB_ITEM(MIB_REG_STD, 0x8c, 1)), + MIB_LIST_ITEM("Collisions", MIB_ITEM(MIB_REG_STD, 0x7c, 1)), + MIB_LIST_ITEM("rx_MacDiscards", MIB_ITEM(MIB_REG_STD, 0x40, 1)) +}; + +const struct rtldsa_mib_desc rtldsa_838x_mib_desc = { + .symbol_errors = MIB_ITEM(MIB_REG_STD, 0xb8, 1), + + .if_in_octets = MIB_ITEM(MIB_REG_STD, 0xf8, 2), + .if_out_octets = MIB_ITEM(MIB_REG_STD, 0xf0, 2), + .if_in_ucast_pkts = MIB_ITEM(MIB_REG_STD, 0xe8, 1), + .if_in_mcast_pkts = MIB_ITEM(MIB_REG_STD, 0xe4, 1), + .if_in_bcast_pkts = MIB_ITEM(MIB_REG_STD, 0xe0, 1), + .if_out_ucast_pkts = MIB_ITEM(MIB_REG_STD, 0xdc, 1), + .if_out_mcast_pkts = MIB_ITEM(MIB_REG_STD, 0xd8, 1), + .if_out_bcast_pkts = MIB_ITEM(MIB_REG_STD, 0xd4, 1), + .if_out_discards = MIB_ITEM(MIB_REG_STD, 0xd0, 1), + .single_collisions = MIB_ITEM(MIB_REG_STD, 0xcc, 1), + .multiple_collisions = MIB_ITEM(MIB_REG_STD, 0xc8, 1), + .deferred_transmissions = MIB_ITEM(MIB_REG_STD, 0xc4, 1), + .late_collisions = MIB_ITEM(MIB_REG_STD, 0xc0, 1), + .excessive_collisions = MIB_ITEM(MIB_REG_STD, 0xbc, 1), + .crc_align_errors = MIB_ITEM(MIB_REG_STD, 0x9c, 1), + + .unsupported_opcodes = MIB_ITEM(MIB_REG_STD, 0xb4, 1), + + .rx_undersize_pkts = MIB_ITEM(MIB_REG_STD, 0x94, 1), + .rx_oversize_pkts = MIB_ITEM(MIB_REG_STD, 0x88, 1), + .rx_fragments = MIB_ITEM(MIB_REG_STD, 0x84, 1), + .rx_jabbers = MIB_ITEM(MIB_REG_STD, 0x80, 1), + + .tx_pkts = { + MIB_ITEM(MIB_REG_STD, 0x78, 1), + MIB_ITEM(MIB_REG_STD, 0x70, 1), + MIB_ITEM(MIB_REG_STD, 0x68, 1), + MIB_ITEM(MIB_REG_STD, 0x60, 1), + MIB_ITEM(MIB_REG_STD, 0x58, 1), + MIB_ITEM(MIB_REG_STD, 0x50, 1), + MIB_ITEM(MIB_REG_STD, 0x48, 1) + }, + .rx_pkts = { + MIB_ITEM(MIB_REG_STD, 0x74, 1), + MIB_ITEM(MIB_REG_STD, 0x6c, 1), + MIB_ITEM(MIB_REG_STD, 0x64, 1), + MIB_ITEM(MIB_REG_STD, 0x5c, 1), + MIB_ITEM(MIB_REG_STD, 0x54, 1), + MIB_ITEM(MIB_REG_STD, 0x4c, 1), + MIB_ITEM(MIB_REG_STD, 0x44, 1) + }, + .rmon_ranges = { + { 0, 64 }, + { 65, 127 }, + { 128, 255 }, + { 256, 511 }, + { 512, 1023 }, + { 1024, 1518 }, + { 1519, 10000 } + }, + + .drop_events = MIB_ITEM(MIB_REG_STD, 0xa8, 1), + .collisions = MIB_ITEM(MIB_REG_STD, 0x7c, 1), + + .rx_pause_frames = MIB_ITEM(MIB_REG_STD, 0xb0, 1), + .tx_pause_frames = MIB_ITEM(MIB_REG_STD, 0xac, 1), + + .list_count = ARRAY_SIZE(rtldsa_838x_mib_list), + .list = rtldsa_838x_mib_list +}; + +void rtldsa_838x_print_matrix(void) +{ + unsigned volatile int *ptr8; + + ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0); + for (int i = 0; i < 28; i += 8) + pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n", + ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3], + ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]); + pr_debug("CPU_PORT> %8x\n", ptr8[28]); +} + +static inline int rtl838x_port_iso_ctrl(int p) +{ + return RTL838X_PORT_ISO_CTRL(p); +} + +static inline void rtl838x_exec_tbl0_cmd(u32 cmd) +{ + sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0); + do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15)); +} + +static inline void rtl838x_exec_tbl1_cmd(u32 cmd) +{ + sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1); + do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15)); +} + +static inline int rtl838x_tbl_access_data_0(int i) +{ + return RTL838X_TBL_ACCESS_DATA_0(i); +} + +static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 v; + /* Read VLAN table (0) via register 0 */ + struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0); + + rtl_table_read(r, vlan); + info->member_ports = sw_r32(rtl_table_data(r, 0)); + v = sw_r32(rtl_table_data(r, 1)); + pr_debug("VLAN_READ %d: %016llx %08x\n", vlan, info->member_ports, v); + rtl_table_release(r); + + info->profile_id = v & 0x7; + info->hash_mc_fid = !!(v & 0x8); + info->hash_uc_fid = !!(v & 0x10); + info->fid = (v >> 5) & 0x3f; + + /* Read UNTAG table (0) via table register 1 */ + r = rtl_table_get(RTL8380_TBL_1, 0); + rtl_table_read(r, vlan); + info->untagged_ports = sw_r32(rtl_table_data(r, 0)); + rtl_table_release(r); +} + +static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 v; + /* Access VLAN table (0) via register 0 */ + struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0); + + sw_w32(info->member_ports, rtl_table_data(r, 0)); + + v = info->profile_id; + v |= info->hash_mc_fid ? 0x8 : 0; + v |= info->hash_uc_fid ? 0x10 : 0; + v |= ((u32)info->fid) << 5; + sw_w32(v, rtl_table_data(r, 1)); + + rtl_table_write(r, vlan); + rtl_table_release(r); +} + +static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask) +{ + /* Access UNTAG table (0) via register 1 */ + struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 0); + + sw_w32(portmask & RTL838X_MC_PMASK_ALL_PORTS, rtl_table_data(r, 0)); + rtl_table_write(r, vlan); + rtl_table_release(r); +} + +/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer + */ +static void rtl838x_vlan_fwd_on_inner(int port, bool is_set) +{ + if (is_set) + sw_w32_mask(BIT(port), 0, RTL838X_VLAN_PORT_FWD); + else + sw_w32_mask(0, BIT(port), RTL838X_VLAN_PORT_FWD); +} + +static u64 rtl838x_l2_hash_seed(u64 mac, u32 vid) +{ + return mac << 12 | vid; +} + +/* Applies the same hash algorithm as the one used currently by the ASIC to the seed + * and returns a key into the L2 hash table + */ +static u32 rtl838x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) +{ + u32 h1, h2, h3, h; + + if (sw_r32(priv->r->l2_ctrl_0) & 1) { + h1 = (seed >> 11) & 0x7ff; + h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f); + + h2 = (seed >> 33) & 0x7ff; + h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f); + + h3 = (seed >> 44) & 0x7ff; + h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf); + + h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff); + h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff); + } else { + h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff) ^ + ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) ^ + ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff); + } + + return h; +} + +static inline int rtl838x_mac_force_mode_ctrl(int p) +{ + return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +static inline int rtl838x_mac_port_ctrl(int p) +{ + return RTL838X_MAC_PORT_CTRL(p); +} + +static inline int rtl838x_l2_port_new_salrn(int p) +{ + return RTL838X_L2_PORT_NEW_SALRN(p); +} + +static inline int rtl838x_l2_port_new_sa_fwd(int p) +{ + return RTL838X_L2_PORT_NEW_SA_FWD(p); +} + +static int rtldsa_838x_get_mirror_config(struct rtldsa_mirror_config *config, + int group, int port) +{ + config->ctrl = RTL838X_MIR_CTRL + group * 4; + config->spm = RTL838X_MIR_SPM_CTRL + group * 4; + config->dpm = RTL838X_MIR_DPM_CTRL + group * 4; + + /* Enable mirroring to destination port */ + config->val = BIT(0); + config->val |= port << 4; + + /* Enable mirroring to port across VLANs */ + config->val |= BIT(11); + + return 0; +} + +static inline int rtl838x_trk_mbr_ctr(int group) +{ + return RTL838X_TRK_MBR_CTR + (group << 2); +} + +/* Fills an L2 entry structure from the SoC registers */ +static void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) +{ + /* Table contains different entry types, we need to identify the right one: + * Check for MC entries, first + * In contrast to the RTL93xx SoCs, there is no valid bit, use heuristics to + * identify valid entries + */ + e->is_ip_mc = !!(r[0] & BIT(22)); + e->is_ipv6_mc = !!(r[0] & BIT(21)); + e->type = L2_INVALID; + + if (!e->is_ip_mc && !e->is_ipv6_mc) { + e->mac[0] = (r[1] >> 20); + e->mac[1] = (r[1] >> 12); + e->mac[2] = (r[1] >> 4); + e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28); + e->mac[4] = (r[2] >> 20); + e->mac[5] = (r[2] >> 12); + + e->rvid = r[2] & 0xfff; + e->vid = r[0] & 0xfff; + + /* Is it a unicast entry? check multicast bit */ + if (!(e->mac[0] & 1)) { + e->is_static = !!((r[0] >> 19) & 1); + e->port = (r[0] >> 12) & 0x1f; + e->block_da = !!(r[1] & BIT(30)); + e->block_sa = !!(r[1] & BIT(31)); + e->suspended = !!(r[1] & BIT(29)); + e->next_hop = !!(r[1] & BIT(28)); + if (e->next_hop) { + pr_debug("Found next hop entry, need to read extra data\n"); + e->nh_vlan_target = !!(r[0] & BIT(9)); + e->nh_route_id = r[0] & 0x1ff; + e->vid = e->rvid; + } + e->age = (r[0] >> 17) & 0x3; + e->valid = true; + + /* A valid entry has one of multi-cast, aging, sa/da-blocking, + * next-hop or static entry bit set + */ + if (!(r[0] & 0x007c0000) && !(r[1] & 0xd0000000)) + e->valid = false; + else + e->type = L2_UNICAST; + } else { /* L2 multicast */ + pr_debug("Got L2 MC entry: %08x %08x %08x\n", r[0], r[1], r[2]); + e->valid = true; + e->type = L2_MULTICAST; + e->mc_portmask_index = (r[0] >> 12) & 0x1ff; + } + } else { /* IPv4 and IPv6 multicast */ + e->valid = true; + e->mc_portmask_index = (r[0] >> 12) & 0x1ff; + e->mc_gip = (r[1] << 20) | (r[2] >> 12); + e->rvid = r[2] & 0xfff; + } + if (e->is_ip_mc) + e->type = IP4_MULTICAST; + if (e->is_ipv6_mc) + e->type = IP6_MULTICAST; +} + +/* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */ +static void rtl838x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) +{ + u64 mac = ether_addr_to_u64(e->mac); + + if (!e->valid) { + r[0] = r[1] = r[2] = 0; + return; + } + + r[0] = e->is_ip_mc ? BIT(22) : 0; + r[0] |= e->is_ipv6_mc ? BIT(21) : 0; + + if (!e->is_ip_mc && !e->is_ipv6_mc) { + r[1] = mac >> 20; + r[2] = (mac & 0xfffff) << 12; + + /* Is it a unicast entry? check multicast bit */ + if (!(e->mac[0] & 1)) { + r[0] |= e->is_static ? BIT(19) : 0; + r[0] |= (e->port & 0x3f) << 12; + r[0] |= e->vid; + r[1] |= e->block_da ? BIT(30) : 0; + r[1] |= e->block_sa ? BIT(31) : 0; + r[1] |= e->suspended ? BIT(29) : 0; + r[2] |= e->rvid & 0xfff; + if (e->next_hop) { + r[1] |= BIT(28); + r[0] |= e->nh_vlan_target ? BIT(9) : 0; + r[0] |= e->nh_route_id & 0x1ff; + } + r[0] |= (e->age & 0x3) << 17; + } else { /* L2 Multicast */ + r[0] |= (e->mc_portmask_index & 0x1ff) << 12; + r[2] |= e->rvid & 0xfff; + r[0] |= e->vid & 0xfff; + pr_debug("FILL MC: %08x %08x %08x\n", r[0], r[1], r[2]); + } + } else { /* IPv4 and IPv6 multicast */ + r[0] |= (e->mc_portmask_index & 0x1ff) << 12; + r[1] = e->mc_gip >> 20; + r[2] = e->mc_gip << 12; + r[2] |= e->rvid; + } +} + +/* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table + * hash is the id of the bucket and pos is the position of the entry in that bucket + * The data read from the SoC is filled into rtl838x_l2_entry + */ +static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) +{ + u32 r[3]; + struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); /* Access L2 Table 0 */ + u32 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */ + + rtl_table_read(q, idx); + for (int i = 0; i < 3; i++) + r[i] = sw_r32(rtl_table_data(q, i)); + + rtl_table_release(q); + + rtl838x_fill_l2_entry(r, e); + if (!e->valid) + return 0; + + return (((u64)r[1]) << 32) | (r[2]); /* mac and vid concatenated as hash seed */ +} + +static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) +{ + u32 r[3]; + struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); + + u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */ + + rtl838x_fill_l2_row(r, e); + + for (int i = 0; i < 3; i++) + sw_w32(r[i], rtl_table_data(q, i)); + + rtl_table_write(q, idx); + rtl_table_release(q); +} + +static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e) +{ + u32 r[3]; + struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); /* Access L2 Table 1 */ + + rtl_table_read(q, idx); + for (int i = 0; i < 3; i++) + r[i] = sw_r32(rtl_table_data(q, i)); + + rtl_table_release(q); + + rtl838x_fill_l2_entry(r, e); + if (!e->valid) + return 0; + + pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]); + + /* Return MAC with concatenated VID ac concatenated ID */ + return (((u64)r[1]) << 32) | r[2]; +} + +static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e) +{ + u32 r[3]; + struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); /* Access L2 Table 1 */ + + rtl838x_fill_l2_row(r, e); + + for (int i = 0; i < 3; i++) + sw_w32(r[i], rtl_table_data(q, i)); + + rtl_table_write(q, idx); + rtl_table_release(q); +} + +static u64 rtl838x_read_mcast_pmask(int idx) +{ + u32 portmask; + /* Read MC_PMSK (2) via register RTL8380_TBL_L2 */ + struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2); + + rtl_table_read(q, idx); + portmask = sw_r32(rtl_table_data(q, 0)); + rtl_table_release(q); + + return portmask; +} + +static void rtl838x_write_mcast_pmask(int idx, u64 portmask) +{ + /* Access MC_PMSK (2) via register RTL8380_TBL_L2 */ + struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2); + + sw_w32(((u32)portmask) & RTL838X_MC_PMASK_ALL_PORTS, rtl_table_data(q, 0)); + rtl_table_write(q, idx); + rtl_table_release(q); +} + +static int +rtldsa_838x_vlan_profile_get(int idx, struct rtldsa_vlan_profile *profile) +{ + u32 p; + + if (idx < 0 || idx > RTL838X_VLAN_PROFILE_MAX) + return -EINVAL; + + p = sw_r32(RTL838X_VLAN_PROFILE(idx)); + + *profile = (struct rtldsa_vlan_profile) { + .l2_learn = RTL838X_VLAN_L2_LEARN_EN_R(p), + .unkn_mc_fld.pmsks_idx = { + .l2 = RTL838X_VLAN_L2_UNKN_MC_FLD_PMSK(p), + .ip = RTL838X_VLAN_IP4_UNKN_MC_FLD_PMSK(p), + .ip6 = RTL838X_VLAN_IP6_UNKN_MC_FLD_PMSK(p), + }, + .pmsk_is_idx = 1, + }; + + return 0; +} + +static void rtl838x_vlan_profile_setup(int profile) +{ + u32 p = RTL838X_VLAN_L2_LEARN_EN(1) | + RTL838X_VLAN_L2_UNKN_MC_FLD(MC_PMASK_ALL_PORTS_IDX) | + RTL838X_VLAN_IP4_UNKN_MC_FLD(MC_PMASK_ALL_PORTS_IDX) | + RTL838X_VLAN_IP6_UNKN_MC_FLD(MC_PMASK_ALL_PORTS_IDX); + + sw_w32(p, RTL838X_VLAN_PROFILE(profile)); +} + +static void rtl838x_l2_learning_setup(void) +{ + /* Set portmask for broadcast traffic and unknown unicast address flooding + * to the reserved entry in the portmask table used also for + * multicast flooding + */ + sw_w32(RTL838X_L2_BC_FLD(MC_PMASK_ALL_PORTS_IDX) | + RTL838X_L2_UNKN_UC_FLD(MC_PMASK_ALL_PORTS_IDX), + RTL838X_L2_FLD_PMSK); + + /* Enable learning constraint system-wide (bit 0), per-port (bit 1) + * and per vlan (bit 2) + */ + sw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN); + + /* Limit learning to maximum: 16k entries, after that just flood (bits 0-1) */ + sw_w32((0x3fff << 2) | 0, RTL838X_L2_LRN_CONSTRT); + + /* Do not trap ARP packets to CPU_PORT */ + sw_w32(0, RTL838X_SPCL_TRAP_ARP_CTRL); +} + +static void rtl838x_enable_learning(int port, bool enable) +{ + /* Limit learning to maximum: 16k entries */ + + sw_w32_mask(0x3fff << 2, enable ? (0x3fff << 2) : 0, + RTL838X_L2_PORT_LRN_CONSTRT + (port << 2)); +} + +static void rtl838x_enable_flood(int port, bool enable) +{ + /* 0: Forward + * 1: Disable + * 2: to CPU + * 3: Copy to CPU + */ + sw_w32_mask(0x3, enable ? 0 : 1, + RTL838X_L2_PORT_LRN_CONSTRT + (port << 2)); +} + +static void rtl838x_enable_mcast_flood(int port, bool enable) +{ +} + +static void rtl838x_enable_bcast_flood(int port, bool enable) +{ +} + +static void rtl838x_set_static_move_action(int port, bool forward) +{ + int shift = MV_ACT_PORT_SHIFT(port); + u32 val = forward ? MV_ACT_FORWARD : MV_ACT_DROP; + + sw_w32_mask(MV_ACT_MASK << shift, val << shift, + RTL838X_L2_PORT_STATIC_MV_ACT(port)); +} + +static int rtldsa_838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, int port, u32 port_state[]) +{ + int idx = 1 - (port / 16); + int bit = 2 * (port % 16); + u32 cmd = 1 << 15 | /* Execute cmd */ + 1 << 14 | /* Read */ + 2 << 12 | /* Table type 0b10 */ + (msti & 0xfff); + + priv->r->exec_tbl0_cmd(cmd); + for (int i = 0; i < 2; i++) + port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); + + return (port_state[idx] >> bit) & 3; +} + +static void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) +{ + u32 cmd = 1 << 15 | /* Execute cmd */ + 0 << 14 | /* Write */ + 2 << 12 | /* Table type 0b10 */ + (msti & 0xfff); + + for (int i = 0; i < 2; i++) + sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); + priv->r->exec_tbl0_cmd(cmd); +} + +static void rtl838x_traffic_set(int source, u64 dest_matrix) +{ + rtl838x_set_port_reg(dest_matrix, rtl838x_port_iso_ctrl(source)); +} + +static void rtl838x_traffic_enable(int source, int dest) +{ + rtl838x_mask_port_reg(0, BIT(dest), rtl838x_port_iso_ctrl(source)); +} + +static void rtl838x_traffic_disable(int source, int dest) +{ + rtl838x_mask_port_reg(BIT(dest), 0, rtl838x_port_iso_ctrl(source)); +} + +/* Enables or disables the EEE/EEEP capability of a port */ +static void rtldsa_838x_set_mac_eee(struct rtl838x_switch_priv *priv, int port, bool enable) +{ + u32 v; + + /* This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP */ + if (port >= 24) + return; + + pr_debug("In %s: setting port %d to %d\n", __func__, port, enable); + v = enable ? 0x3 : 0x0; + + /* Set EEE state for 100 (bit 9) & 1000MBit (bit 10) */ + sw_w32_mask(0x3 << 9, v << 9, priv->r->mac_force_mode_ctrl(port)); + + /* Set TX/RX EEE state */ + if (enable) { + sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN); + sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN); + } else { + sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN); + sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN); + } + priv->ports[port].eee_enabled = enable; +} + +static void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable) +{ + pr_debug("Setting up EEE, state: %d\n", enable); + sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL); + + /* Set timers for EEE */ + sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL); + sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL); + + /* Enable EEE MAC support on ports */ + for (int i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy) + priv->r->set_mac_eee(priv, i, enable); + } + priv->eee_enabled = enable; +} + +static void rtl838x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index) +{ + int block = index / PIE_BLOCK_SIZE; + u32 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL); + + /* Make sure rule-lookup is enabled in the block */ + if (!(block_state & BIT(block))) + sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL); +} + +static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to) +{ + int block_from = index_from / PIE_BLOCK_SIZE; + int block_to = index_to / PIE_BLOCK_SIZE; + u32 v = (index_from << 1) | (index_to << 12) | BIT(0); + u32 block_state; + + pr_debug("%s: from %d to %d\n", __func__, index_from, index_to); + mutex_lock(&priv->reg_mutex); + + /* Remember currently active blocks */ + block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL); + + /* Make sure rule-lookup is disabled in the relevant blocks */ + for (int block = block_from; block <= block_to; block++) { + if (block_state & BIT(block)) + sw_w32(block_state & (~BIT(block)), RTL838X_ACL_BLK_LOOKUP_CTRL); + } + + /* Write from-to and execute bit into control register */ + sw_w32(v, RTL838X_ACL_CLR_CTRL); + + /* Wait until command has completed */ + do { + } while (sw_r32(RTL838X_ACL_CLR_CTRL) & BIT(0)); + + /* Re-enable rule lookup */ + for (int block = block_from; block <= block_to; block++) { + if (!(block_state & BIT(block))) + sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL); + } + + mutex_unlock(&priv->reg_mutex); +} + +/* Reads the intermediate representation of the templated match-fields of the + * PIE rule in the pie_rule structure and fills in the raw data fields in the + * raw register space r[]. + * The register space configuration size is identical for the RTL8380/90 and RTL9300, + * however the RTL9310 has 2 more registers / fields and the physical field-ids + * are specific to every platform. + */ +static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) +{ + for (int i = 0; i < N_FIXED_FIELDS; i++) { + enum template_field_id field_type = t[i]; + u16 data = 0, data_m = 0; + + switch (field_type) { + case TEMPLATE_FIELD_SPM0: + data = pr->spm; + data_m = pr->spm_m; + break; + case TEMPLATE_FIELD_SPM1: + data = pr->spm >> 16; + data_m = pr->spm_m >> 16; + break; + case TEMPLATE_FIELD_OTAG: + data = pr->otag; + data_m = pr->otag_m; + break; + case TEMPLATE_FIELD_SMAC0: + data = pr->smac[4]; + data = (data << 8) | pr->smac[5]; + data_m = pr->smac_m[4]; + data_m = (data_m << 8) | pr->smac_m[5]; + break; + case TEMPLATE_FIELD_SMAC1: + data = pr->smac[2]; + data = (data << 8) | pr->smac[3]; + data_m = pr->smac_m[2]; + data_m = (data_m << 8) | pr->smac_m[3]; + break; + case TEMPLATE_FIELD_SMAC2: + data = pr->smac[0]; + data = (data << 8) | pr->smac[1]; + data_m = pr->smac_m[0]; + data_m = (data_m << 8) | pr->smac_m[1]; + break; + case TEMPLATE_FIELD_DMAC0: + data = pr->dmac[4]; + data = (data << 8) | pr->dmac[5]; + data_m = pr->dmac_m[4]; + data_m = (data_m << 8) | pr->dmac_m[5]; + break; + case TEMPLATE_FIELD_DMAC1: + data = pr->dmac[2]; + data = (data << 8) | pr->dmac[3]; + data_m = pr->dmac_m[2]; + data_m = (data_m << 8) | pr->dmac_m[3]; + break; + case TEMPLATE_FIELD_DMAC2: + data = pr->dmac[0]; + data = (data << 8) | pr->dmac[1]; + data_m = pr->dmac_m[0]; + data_m = (data_m << 8) | pr->dmac_m[1]; + break; + case TEMPLATE_FIELD_ETHERTYPE: + data = pr->ethertype; + data_m = pr->ethertype_m; + break; + case TEMPLATE_FIELD_ITAG: + data = pr->itag; + data_m = pr->itag_m; + break; + case TEMPLATE_FIELD_RANGE_CHK: + data = pr->field_range_check; + data_m = pr->field_range_check_m; + break; + case TEMPLATE_FIELD_SIP0: + if (pr->is_ipv6) { + data = pr->sip6.s6_addr16[7]; + data_m = pr->sip6_m.s6_addr16[7]; + } else { + data = pr->sip; + data_m = pr->sip_m; + } + break; + case TEMPLATE_FIELD_SIP1: + if (pr->is_ipv6) { + data = pr->sip6.s6_addr16[6]; + data_m = pr->sip6_m.s6_addr16[6]; + } else { + data = pr->sip >> 16; + data_m = pr->sip_m >> 16; + } + break; + case TEMPLATE_FIELD_SIP2: + case TEMPLATE_FIELD_SIP3: + case TEMPLATE_FIELD_SIP4: + case TEMPLATE_FIELD_SIP5: + case TEMPLATE_FIELD_SIP6: + case TEMPLATE_FIELD_SIP7: + data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; + data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; + break; + case TEMPLATE_FIELD_DIP0: + if (pr->is_ipv6) { + data = pr->dip6.s6_addr16[7]; + data_m = pr->dip6_m.s6_addr16[7]; + } else { + data = pr->dip; + data_m = pr->dip_m; + } + break; + case TEMPLATE_FIELD_DIP1: + if (pr->is_ipv6) { + data = pr->dip6.s6_addr16[6]; + data_m = pr->dip6_m.s6_addr16[6]; + } else { + data = pr->dip >> 16; + data_m = pr->dip_m >> 16; + } + break; + case TEMPLATE_FIELD_DIP2: + case TEMPLATE_FIELD_DIP3: + case TEMPLATE_FIELD_DIP4: + case TEMPLATE_FIELD_DIP5: + case TEMPLATE_FIELD_DIP6: + case TEMPLATE_FIELD_DIP7: + data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; + data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; + break; + case TEMPLATE_FIELD_IP_TOS_PROTO: + data = pr->tos_proto; + data_m = pr->tos_proto_m; + break; + case TEMPLATE_FIELD_L4_SPORT: + data = pr->sport; + data_m = pr->sport_m; + break; + case TEMPLATE_FIELD_L4_DPORT: + data = pr->dport; + data_m = pr->dport_m; + break; + case TEMPLATE_FIELD_ICMP_IGMP: + data = pr->icmp_igmp; + data_m = pr->icmp_igmp_m; + break; + default: + pr_debug("%s: unknown field %d\n", __func__, field_type); + continue; + } + if (!(i % 2)) { + r[5 - i / 2] = data; + r[12 - i / 2] = data_m; + } else { + r[5 - i / 2] |= ((u32)data) << 16; + r[12 - i / 2] |= ((u32)data_m) << 16; + } + } +} + +/* Creates the intermediate representation of the templated match-fields of the + * PIE rule in the pie_rule structure by reading the raw data fields in the + * raw register space r[]. + * The register space configuration size is identical for the RTL8380/90 and RTL9300, + * however the RTL9310 has 2 more registers / fields and the physical field-ids + */ +static void rtl838x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) +{ + for (int i = 0; i < N_FIXED_FIELDS; i++) { + enum template_field_id field_type = t[i]; + u16 data, data_m; + + field_type = t[i]; + if (!(i % 2)) { + data = r[5 - i / 2]; + data_m = r[12 - i / 2]; + } else { + data = r[5 - i / 2] >> 16; + data_m = r[12 - i / 2] >> 16; + } + + switch (field_type) { + case TEMPLATE_FIELD_SPM0: + pr->spm = (pr->spn << 16) | data; + pr->spm_m = (pr->spn << 16) | data_m; + break; + case TEMPLATE_FIELD_SPM1: + pr->spm = data; + pr->spm_m = data_m; + break; + case TEMPLATE_FIELD_OTAG: + pr->otag = data; + pr->otag_m = data_m; + break; + case TEMPLATE_FIELD_SMAC0: + pr->smac[4] = data >> 8; + pr->smac[5] = data; + pr->smac_m[4] = data >> 8; + pr->smac_m[5] = data; + break; + case TEMPLATE_FIELD_SMAC1: + pr->smac[2] = data >> 8; + pr->smac[3] = data; + pr->smac_m[2] = data >> 8; + pr->smac_m[3] = data; + break; + case TEMPLATE_FIELD_SMAC2: + pr->smac[0] = data >> 8; + pr->smac[1] = data; + pr->smac_m[0] = data >> 8; + pr->smac_m[1] = data; + break; + case TEMPLATE_FIELD_DMAC0: + pr->dmac[4] = data >> 8; + pr->dmac[5] = data; + pr->dmac_m[4] = data >> 8; + pr->dmac_m[5] = data; + break; + case TEMPLATE_FIELD_DMAC1: + pr->dmac[2] = data >> 8; + pr->dmac[3] = data; + pr->dmac_m[2] = data >> 8; + pr->dmac_m[3] = data; + break; + case TEMPLATE_FIELD_DMAC2: + pr->dmac[0] = data >> 8; + pr->dmac[1] = data; + pr->dmac_m[0] = data >> 8; + pr->dmac_m[1] = data; + break; + case TEMPLATE_FIELD_ETHERTYPE: + pr->ethertype = data; + pr->ethertype_m = data_m; + break; + case TEMPLATE_FIELD_ITAG: + pr->itag = data; + pr->itag_m = data_m; + break; + case TEMPLATE_FIELD_RANGE_CHK: + pr->field_range_check = data; + pr->field_range_check_m = data_m; + break; + case TEMPLATE_FIELD_SIP0: + pr->sip = data; + pr->sip_m = data_m; + break; + case TEMPLATE_FIELD_SIP1: + pr->sip = (pr->sip << 16) | data; + pr->sip_m = (pr->sip << 16) | data_m; + break; + case TEMPLATE_FIELD_SIP2: + pr->is_ipv6 = true; + /* Make use of limitiations on the position of the match values */ + ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2], + r[4 - i / 2], r[3 - i / 2]); + ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2], + r[4 - i / 2], r[3 - i / 2]); + case TEMPLATE_FIELD_SIP3: + case TEMPLATE_FIELD_SIP4: + case TEMPLATE_FIELD_SIP5: + case TEMPLATE_FIELD_SIP6: + case TEMPLATE_FIELD_SIP7: + break; + case TEMPLATE_FIELD_DIP0: + pr->dip = data; + pr->dip_m = data_m; + break; + case TEMPLATE_FIELD_DIP1: + pr->dip = (pr->dip << 16) | data; + pr->dip_m = (pr->dip << 16) | data_m; + break; + case TEMPLATE_FIELD_DIP2: + pr->is_ipv6 = true; + ipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2], + r[4 - i / 2], r[3 - i / 2]); + ipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2], + r[4 - i / 2], r[3 - i / 2]); + case TEMPLATE_FIELD_DIP3: + case TEMPLATE_FIELD_DIP4: + case TEMPLATE_FIELD_DIP5: + case TEMPLATE_FIELD_DIP6: + case TEMPLATE_FIELD_DIP7: + break; + case TEMPLATE_FIELD_IP_TOS_PROTO: + pr->tos_proto = data; + pr->tos_proto_m = data_m; + break; + case TEMPLATE_FIELD_L4_SPORT: + pr->sport = data; + pr->sport_m = data_m; + break; + case TEMPLATE_FIELD_L4_DPORT: + pr->dport = data; + pr->dport_m = data_m; + break; + case TEMPLATE_FIELD_ICMP_IGMP: + pr->icmp_igmp = data; + pr->icmp_igmp_m = data_m; + break; + default: + pr_debug("%s: unknown field %d\n", __func__, field_type); + } + } +} + +static void rtl838x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr) +{ + pr->spmmask_fix = (r[6] >> 22) & 0x3; + pr->spn = (r[6] >> 16) & 0x3f; + pr->mgnt_vlan = (r[6] >> 15) & 1; + pr->dmac_hit_sw = (r[6] >> 14) & 1; + pr->not_first_frag = (r[6] >> 13) & 1; + pr->frame_type_l4 = (r[6] >> 10) & 7; + pr->frame_type = (r[6] >> 8) & 3; + pr->otag_fmt = (r[6] >> 7) & 1; + pr->itag_fmt = (r[6] >> 6) & 1; + pr->otag_exist = (r[6] >> 5) & 1; + pr->itag_exist = (r[6] >> 4) & 1; + pr->frame_type_l2 = (r[6] >> 2) & 3; + pr->tid = r[6] & 3; + + pr->spmmask_fix_m = (r[13] >> 22) & 0x3; + pr->spn_m = (r[13] >> 16) & 0x3f; + pr->mgnt_vlan_m = (r[13] >> 15) & 1; + pr->dmac_hit_sw_m = (r[13] >> 14) & 1; + pr->not_first_frag_m = (r[13] >> 13) & 1; + pr->frame_type_l4_m = (r[13] >> 10) & 7; + pr->frame_type_m = (r[13] >> 8) & 3; + pr->otag_fmt_m = (r[13] >> 7) & 1; + pr->itag_fmt_m = (r[13] >> 6) & 1; + pr->otag_exist_m = (r[13] >> 5) & 1; + pr->itag_exist_m = (r[13] >> 4) & 1; + pr->frame_type_l2_m = (r[13] >> 2) & 3; + pr->tid_m = r[13] & 3; + + pr->valid = r[14] & BIT(31); + pr->cond_not = r[14] & BIT(30); + pr->cond_and1 = r[14] & BIT(29); + pr->cond_and2 = r[14] & BIT(28); + pr->ivalid = r[14] & BIT(27); + + pr->drop = (r[17] >> 14) & 3; + pr->fwd_sel = r[17] & BIT(13); + pr->ovid_sel = r[17] & BIT(12); + pr->ivid_sel = r[17] & BIT(11); + pr->flt_sel = r[17] & BIT(10); + pr->log_sel = r[17] & BIT(9); + pr->rmk_sel = r[17] & BIT(8); + pr->meter_sel = r[17] & BIT(7); + pr->tagst_sel = r[17] & BIT(6); + pr->mir_sel = r[17] & BIT(5); + pr->nopri_sel = r[17] & BIT(4); + pr->cpupri_sel = r[17] & BIT(3); + pr->otpid_sel = r[17] & BIT(2); + pr->itpid_sel = r[17] & BIT(1); + pr->shaper_sel = r[17] & BIT(0); +} + +static void rtl838x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr) +{ + r[6] = ((u32)(pr->spmmask_fix & 0x3)) << 22; + r[6] |= ((u32)(pr->spn & 0x3f)) << 16; + r[6] |= pr->mgnt_vlan ? BIT(15) : 0; + r[6] |= pr->dmac_hit_sw ? BIT(14) : 0; + r[6] |= pr->not_first_frag ? BIT(13) : 0; + r[6] |= ((u32)(pr->frame_type_l4 & 0x7)) << 10; + r[6] |= ((u32)(pr->frame_type & 0x3)) << 8; + r[6] |= pr->otag_fmt ? BIT(7) : 0; + r[6] |= pr->itag_fmt ? BIT(6) : 0; + r[6] |= pr->otag_exist ? BIT(5) : 0; + r[6] |= pr->itag_exist ? BIT(4) : 0; + r[6] |= ((u32)(pr->frame_type_l2 & 0x3)) << 2; + r[6] |= ((u32)(pr->tid & 0x3)); + + r[13] = ((u32)(pr->spmmask_fix_m & 0x3)) << 22; + r[13] |= ((u32)(pr->spn_m & 0x3f)) << 16; + r[13] |= pr->mgnt_vlan_m ? BIT(15) : 0; + r[13] |= pr->dmac_hit_sw_m ? BIT(14) : 0; + r[13] |= pr->not_first_frag_m ? BIT(13) : 0; + r[13] |= ((u32)(pr->frame_type_l4_m & 0x7)) << 10; + r[13] |= ((u32)(pr->frame_type_m & 0x3)) << 8; + r[13] |= pr->otag_fmt_m ? BIT(7) : 0; + r[13] |= pr->itag_fmt_m ? BIT(6) : 0; + r[13] |= pr->otag_exist_m ? BIT(5) : 0; + r[13] |= pr->itag_exist_m ? BIT(4) : 0; + r[13] |= ((u32)(pr->frame_type_l2_m & 0x3)) << 2; + r[13] |= ((u32)(pr->tid_m & 0x3)); + + r[14] = pr->valid ? BIT(31) : 0; + r[14] |= pr->cond_not ? BIT(30) : 0; + r[14] |= pr->cond_and1 ? BIT(29) : 0; + r[14] |= pr->cond_and2 ? BIT(28) : 0; + r[14] |= pr->ivalid ? BIT(27) : 0; + + if (pr->drop) + r[17] = 0x1 << 14; /* Standard drop action */ + else + r[17] = 0; + r[17] |= pr->fwd_sel ? BIT(13) : 0; + r[17] |= pr->ovid_sel ? BIT(12) : 0; + r[17] |= pr->ivid_sel ? BIT(11) : 0; + r[17] |= pr->flt_sel ? BIT(10) : 0; + r[17] |= pr->log_sel ? BIT(9) : 0; + r[17] |= pr->rmk_sel ? BIT(8) : 0; + r[17] |= pr->meter_sel ? BIT(7) : 0; + r[17] |= pr->tagst_sel ? BIT(6) : 0; + r[17] |= pr->mir_sel ? BIT(5) : 0; + r[17] |= pr->nopri_sel ? BIT(4) : 0; + r[17] |= pr->cpupri_sel ? BIT(3) : 0; + r[17] |= pr->otpid_sel ? BIT(2) : 0; + r[17] |= pr->itpid_sel ? BIT(1) : 0; + r[17] |= pr->shaper_sel ? BIT(0) : 0; +} + +static int rtl838x_write_pie_action(u32 r[], struct pie_rule *pr) +{ + u16 *aif = (u16 *)&r[17]; + u16 data; + int fields_used = 0; + + aif--; + + pr_debug("%s, at %08x\n", __func__, (u32)aif); + /* Multiple actions can be linked to a match of a PIE rule, + * they have different precedence depending on their type and this precedence + * defines which Action Information Field (0-4) in the IACL table stores + * the additional data of the action (like e.g. the port number a packet is + * forwarded to) + */ + /* TODO: count bits in selectors to limit to a maximum number of actions */ + if (pr->fwd_sel) { /* Forwarding action */ + data = pr->fwd_act << 13; + data |= pr->fwd_data; + data |= pr->bypass_all ? BIT(12) : 0; + data |= pr->bypass_ibc_sc ? BIT(11) : 0; + data |= pr->bypass_igr_stp ? BIT(10) : 0; + *aif-- = data; + fields_used++; + } + + if (pr->ovid_sel) { /* Outer VID action */ + data = (pr->ovid_act & 0x3) << 12; + data |= pr->ovid_data; + *aif-- = data; + fields_used++; + } + + if (pr->ivid_sel) { /* Inner VID action */ + data = (pr->ivid_act & 0x3) << 12; + data |= pr->ivid_data; + *aif-- = data; + fields_used++; + } + + if (pr->flt_sel) { /* Filter action */ + *aif-- = pr->flt_data; + fields_used++; + } + + if (pr->log_sel) { /* Log action */ + if (fields_used >= 4) + return -1; + *aif-- = pr->log_data; + fields_used++; + } + + if (pr->rmk_sel) { /* Remark action */ + if (fields_used >= 4) + return -1; + *aif-- = pr->rmk_data; + fields_used++; + } + + if (pr->meter_sel) { /* Meter action */ + if (fields_used >= 4) + return -1; + *aif-- = pr->meter_data; + fields_used++; + } + + if (pr->tagst_sel) { /* Egress Tag Status action */ + if (fields_used >= 4) + return -1; + *aif-- = pr->tagst_data; + fields_used++; + } + + if (pr->mir_sel) { /* Mirror action */ + if (fields_used >= 4) + return -1; + *aif-- = pr->mir_data; + fields_used++; + } + + if (pr->nopri_sel) { /* Normal Priority action */ + if (fields_used >= 4) + return -1; + *aif-- = pr->nopri_data; + fields_used++; + } + + if (pr->cpupri_sel) { /* CPU Priority action */ + if (fields_used >= 4) + return -1; + *aif-- = pr->nopri_data; + fields_used++; + } + + if (pr->otpid_sel) { /* OTPID action */ + if (fields_used >= 4) + return -1; + *aif-- = pr->otpid_data; + fields_used++; + } + + if (pr->itpid_sel) { /* ITPID action */ + if (fields_used >= 4) + return -1; + *aif-- = pr->itpid_data; + fields_used++; + } + + if (pr->shaper_sel) { /* Traffic shaper action */ + if (fields_used >= 4) + return -1; + *aif-- = pr->shaper_data; + fields_used++; + } + + return 0; +} + +static void rtl838x_read_pie_action(u32 r[], struct pie_rule *pr) +{ + u16 *aif = (u16 *)&r[17]; + + aif--; + + pr_debug("%s, at %08x\n", __func__, (u32)aif); + if (pr->drop) + pr_debug("%s: Action Drop: %d", __func__, pr->drop); + + if (pr->fwd_sel) { /* Forwarding action */ + pr->fwd_act = *aif >> 13; + pr->fwd_data = *aif--; + pr->bypass_all = pr->fwd_data & BIT(12); + pr->bypass_ibc_sc = pr->fwd_data & BIT(11); + pr->bypass_igr_stp = pr->fwd_data & BIT(10); + if (pr->bypass_all || pr->bypass_ibc_sc || pr->bypass_igr_stp) + pr->bypass_sel = true; + } + if (pr->ovid_sel) /* Outer VID action */ + pr->ovid_data = *aif--; + if (pr->ivid_sel) /* Inner VID action */ + pr->ivid_data = *aif--; + if (pr->flt_sel) /* Filter action */ + pr->flt_data = *aif--; + if (pr->log_sel) /* Log action */ + pr->log_data = *aif--; + if (pr->rmk_sel) /* Remark action */ + pr->rmk_data = *aif--; + if (pr->meter_sel) /* Meter action */ + pr->meter_data = *aif--; + if (pr->tagst_sel) /* Egress Tag Status action */ + pr->tagst_data = *aif--; + if (pr->mir_sel) /* Mirror action */ + pr->mir_data = *aif--; + if (pr->nopri_sel) /* Normal Priority action */ + pr->nopri_data = *aif--; + if (pr->cpupri_sel) /* CPU Priority action */ + pr->nopri_data = *aif--; + if (pr->otpid_sel) /* OTPID action */ + pr->otpid_data = *aif--; + if (pr->itpid_sel) /* ITPID action */ + pr->itpid_data = *aif--; + if (pr->shaper_sel) /* Traffic shaper action */ + pr->shaper_data = *aif--; +} + +static void rtl838x_pie_rule_dump_raw(u32 r[]) +{ + pr_debug("Raw IACL table entry:\n"); + pr_debug("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]); + pr_debug("Fixed : %08x\n", r[6]); + pr_debug("Match M: %08x %08x %08x %08x %08x %08x\n", r[7], r[8], r[9], r[10], r[11], r[12]); + pr_debug("Fixed M: %08x\n", r[13]); + pr_debug("AIF : %08x %08x %08x\n", r[14], r[15], r[16]); + pr_debug("Sel : %08x\n", r[17]); +} + +// Currently not used +// static void rtl838x_pie_rule_dump(struct pie_rule *pr) +// { +// pr_debug("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n", +// pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel, +// pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel); +// if (pr->fwd_sel) +// pr_debug("FWD: %08x\n", pr->fwd_data); +// pr_debug("TID: %x, %x\n", pr->tid, pr->tid_m); +// } + +static int rtl838x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) +{ + /* Read IACL table (1) via register 0 */ + struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1); + u32 r[18]; + int block = idx / PIE_BLOCK_SIZE; + u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)); + + memset(pr, 0, sizeof(*pr)); + rtl_table_read(q, idx); + for (int i = 0; i < 18; i++) + r[i] = sw_r32(rtl_table_data(q, i)); + + rtl_table_release(q); + + rtl838x_read_pie_fixed_fields(r, pr); + if (!pr->valid) + return 0; + + pr_debug("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid); + rtl838x_pie_rule_dump_raw(r); + + rtl838x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]); + + rtl838x_read_pie_action(r, pr); + + return 0; +} + +static int rtl838x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) +{ + /* Access IACL table (1) via register 0 */ + struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1); + u32 r[18]; + int err; + int block = idx / PIE_BLOCK_SIZE; + u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)); + + pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select); + + for (int i = 0; i < 18; i++) + r[i] = 0; + + if (!pr->valid) { + err = -EINVAL; + pr_err("Rule invalid\n"); + goto errout; + } + + rtl838x_write_pie_fixed_fields(r, pr); + + pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 3)) & 0x7); + rtl838x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]); + + err = rtl838x_write_pie_action(r, pr); + if (err) { + pr_err("Rule actions too complex\n"); + goto errout; + } + +/* rtl838x_pie_rule_dump_raw(r); */ + + for (int i = 0; i < 18; i++) + sw_w32(r[i], rtl_table_data(q, i)); + +errout: + rtl_table_write(q, idx); + rtl_table_release(q); + + return err; +} + +static bool rtl838x_pie_templ_has(int t, enum template_field_id field_type) +{ + enum template_field_id ft; + + for (int i = 0; i < N_FIXED_FIELDS; i++) { + ft = fixed_templates[t][i]; + if (field_type == ft) + return true; + } + + return false; +} + +static int rtl838x_pie_verify_template(struct rtl838x_switch_priv *priv, + struct pie_rule *pr, int t, int block) +{ + int i; + + if (!pr->is_ipv6 && pr->sip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP0)) + return -1; + + if (!pr->is_ipv6 && pr->dip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP0)) + return -1; + + if (pr->is_ipv6) { + if ((pr->sip6_m.s6_addr32[0] || + pr->sip6_m.s6_addr32[1] || + pr->sip6_m.s6_addr32[2] || + pr->sip6_m.s6_addr32[3]) && + !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) + return -1; + if ((pr->dip6_m.s6_addr32[0] || + pr->dip6_m.s6_addr32[1] || + pr->dip6_m.s6_addr32[2] || + pr->dip6_m.s6_addr32[3]) && + !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) + return -1; + } + + if (ether_addr_to_u64(pr->smac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0)) + return -1; + + if (ether_addr_to_u64(pr->dmac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0)) + return -1; + + /* TODO: Check more */ + + i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE); + + if (i >= PIE_BLOCK_SIZE) + return -1; + + return i + PIE_BLOCK_SIZE * block; +} + +static int rtl838x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr) +{ + int idx, block, j; + + pr_debug("In %s\n", __func__); + + mutex_lock(&priv->pie_mutex); + + for (block = 0; block < priv->r->n_pie_blocks; block++) { + for (j = 0; j < 3; j++) { + int t = (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7; + + pr_debug("Testing block %d, template %d, template id %d\n", block, j, t); + idx = rtl838x_pie_verify_template(priv, pr, t, block); + if (idx >= 0) + break; + } + if (j < 3) + break; + } + + if (block >= priv->r->n_pie_blocks) { + mutex_unlock(&priv->pie_mutex); + return -EOPNOTSUPP; + } + + pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j); + set_bit(idx, priv->pie_use_bm); + + pr->valid = true; + pr->tid = j; /* Mapped to template number */ + pr->tid_m = 0x3; + pr->id = idx; + + rtl838x_pie_lookup_enable(priv, idx); + rtl838x_pie_rule_write(priv, idx, pr); + + mutex_unlock(&priv->pie_mutex); + + return 0; +} + +static void rtl838x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr) +{ + int idx = pr->id; + + rtl838x_pie_rule_del(priv, idx, idx); + clear_bit(idx, priv->pie_use_bm); +} + +/* Initializes the Packet Inspection Engine: + * powers it up, enables default matching templates for all blocks + * and clears all rules possibly installed by u-boot + */ +static void rtl838x_pie_init(struct rtl838x_switch_priv *priv) +{ + u32 template_selectors; + + mutex_init(&priv->pie_mutex); + + /* Enable ACL lookup on all ports, including CPU_PORT */ + for (int i = 0; i <= priv->cpu_port; i++) + sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i)); + + /* Power on all PIE blocks */ + for (int i = 0; i < priv->r->n_pie_blocks; i++) + sw_w32_mask(0, BIT(i), RTL838X_ACL_BLK_PWR_CTRL); + + /* Include IPG in metering */ + sw_w32(1, RTL838X_METER_GLB_CTRL); + + /* Delete all present rules */ + rtl838x_pie_rule_del(priv, 0, priv->r->n_pie_blocks * PIE_BLOCK_SIZE - 1); + + /* Routing bypasses source port filter */ + sw_w32_mask(0, 1, RTL838X_DMY_REG27); + + /* Enable predefined templates 0, 1 and 2 for even blocks */ + template_selectors = 0 | (1 << 3) | (2 << 6); + for (int i = 0; i < 6; i += 2) + sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i)); + + /* Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks */ + template_selectors = 0 | (3 << 3) | (4 << 6); + for (int i = 1; i < priv->r->n_pie_blocks; i += 2) + sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i)); + + /* Group each pair of physical blocks together to a logical block */ + sw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL); +} + +static u32 rtl838x_packet_cntr_read(int counter) +{ + u32 v; + + /* Read LOG table (3) via register RTL8380_TBL_0 */ + struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3); + + pr_debug("In %s, id %d\n", __func__, counter); + rtl_table_read(r, counter / 2); + + pr_debug("Registers: %08x %08x\n", + sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1))); + /* The table has a size of 2 registers */ + if (counter % 2) + v = sw_r32(rtl_table_data(r, 0)); + else + v = sw_r32(rtl_table_data(r, 1)); + + rtl_table_release(r); + + return v; +} + +static void rtl838x_packet_cntr_clear(int counter) +{ + /* Access LOG table (3) via register RTL8380_TBL_0 */ + struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3); + + pr_debug("In %s, id %d\n", __func__, counter); + /* The table has a size of 2 registers */ + if (counter % 2) + sw_w32(0, rtl_table_data(r, 0)); + else + sw_w32(0, rtl_table_data(r, 1)); + + rtl_table_write(r, counter / 2); + + rtl_table_release(r); +} + +static void rtl838x_route_read(int idx, struct rtl83xx_route *rt) +{ + /* Read ROUTING table (2) via register RTL8380_TBL_1 */ + struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2); + + pr_debug("In %s, id %d\n", __func__, idx); + rtl_table_read(r, idx); + + /* The table has a size of 2 registers */ + rt->nh.gw = sw_r32(rtl_table_data(r, 0)); + rt->nh.gw <<= 32; + rt->nh.gw |= sw_r32(rtl_table_data(r, 1)); + + rtl_table_release(r); +} + +static void rtl838x_route_write(int idx, struct rtl83xx_route *rt) +{ + /* Access ROUTING table (2) via register RTL8380_TBL_1 */ + struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2); + + pr_debug("In %s, id %d, gw: %016llx\n", __func__, idx, rt->nh.gw); + sw_w32(rt->nh.gw >> 32, rtl_table_data(r, 0)); + sw_w32(rt->nh.gw, rtl_table_data(r, 1)); + rtl_table_write(r, idx); + + rtl_table_release(r); +} + +static int rtl838x_l3_setup(struct rtl838x_switch_priv *priv) +{ + /* Nothing to be done */ + return 0; +} + +static void rtl838x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) +{ + sw_w32(FIELD_PREP(RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK, + keep_outer ? RTL838X_VLAN_PORT_TAG_STS_TAGGED : RTL838X_VLAN_PORT_TAG_STS_UNTAG) | + FIELD_PREP(RTL838X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK, + keep_inner ? RTL838X_VLAN_PORT_TAG_STS_TAGGED : RTL838X_VLAN_PORT_TAG_STS_UNTAG), + RTL838X_VLAN_PORT_TAG_STS_CTRL(port)); +} + +static void rtl838x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0x3, mode, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); + else + sw_w32_mask(0x3 << 14, mode << 14, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); +} + +static void rtl838x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0xfff << 2, pvid << 2, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); + else + sw_w32_mask(0xfff << 16, pvid << 16, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); +} + +static int rtldsa_838x_fast_age(struct rtl838x_switch_priv *priv, int port, int vid) +{ + u32 val; + + val = BIT(26) | BIT(23) | (port << 5); + if (vid >= 0) + val |= BIT(24) | (vid << 10); + + sw_w32(val, priv->r->l2_tbl_flush_ctrl); + do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26)); + + return 0; +} + +static int rtl838x_set_ageing_time(unsigned long msec) +{ + int t = sw_r32(RTL838X_L2_CTRL_1); + + t &= 0x7FFFFF; + t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */ + pr_debug("L2 AGING time: %d sec\n", t); + + t = (msec * 625 + 127000) / 128000; + t = t > 0x7FFFFF ? 0x7FFFFF : t; + sw_w32_mask(0x7FFFFF, t, RTL838X_L2_CTRL_1); + pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL838X_L2_PORT_AGING_OUT)); + + return 0; +} + +static void rtl838x_set_igr_filter(int port, enum igr_filter state) +{ + sw_w32_mask(0x3 << ((port & 0xf) << 1), state << ((port & 0xf) << 1), + RTL838X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2))); +} + +static void rtl838x_set_egr_filter(int port, enum egr_filter state) +{ + sw_w32_mask(0x1 << (port % 0x1d), state << (port % 0x1d), + RTL838X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2))); +} + +static int rtldsa_838x_set_distribution_algorithm(struct rtl838x_switch_priv *priv, + int group, int algoidx, u32 algomsk) +{ + algoidx &= 1; /* RTL838X only supports 2 concurrent algorithms */ + sw_w32_mask(1 << (group % 8), algoidx << (group % 8), + RTL838X_TRK_HASH_IDX_CTRL + ((group >> 3) << 2)); + sw_w32(algomsk, RTL838X_TRK_HASH_CTRL + (algoidx << 2)); + return 0; +} + +static void rtl838x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action) +{ + switch (type) { + case BPDU: + sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), + RTL838X_RMA_BPDU_CTRL + ((port >> 4) << 2)); + break; + case PTP: + sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), + RTL838X_RMA_PTP_CTRL + ((port >> 4) << 2)); + break; + case LLDP: + sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), + RTL838X_RMA_LLDP_CTRL + ((port >> 4) << 2)); + break; + default: + break; + } +} + +static void +rtldsa_838x_vlan_profile_dump(struct rtl838x_switch_priv *priv, int idx) +{ + struct rtldsa_vlan_profile p; + + if (rtldsa_838x_vlan_profile_get(idx, &p) < 0) + return; + + dev_dbg(priv->dev, + "VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d\n", idx, + p.l2_learn, p.unkn_mc_fld.pmsks_idx.l2, + p.unkn_mc_fld.pmsks_idx.ip, p.unkn_mc_fld.pmsks_idx.ip6); +} + +static int rtldsa_838x_lag_set_port_members(struct rtl838x_switch_priv *priv, int group, + u64 members, struct netdev_lag_upper_info *info) +{ + priv->lags_port_members[group] = members; + + priv->r->set_port_reg_be(priv->lags_port_members[group], + priv->r->trk_mbr_ctr(group)); + + return 0; +} + +int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group, + struct netdev_lag_upper_info *info); + +const struct rtldsa_config rtldsa_838x_cfg = { + .mask_port_reg_be = rtl838x_mask_port_reg, + .set_port_reg_be = rtl838x_set_port_reg, + .get_port_reg_be = rtl838x_get_port_reg, + .mask_port_reg_le = rtl838x_mask_port_reg, + .set_port_reg_le = rtl838x_set_port_reg, + .get_port_reg_le = rtl838x_get_port_reg, + .stat_port_rst = RTL838X_STAT_PORT_RST, + .stat_rst = RTL838X_STAT_RST, + .stat_port_std_mib = RTL838X_STAT_PORT_STD_MIB, + .mib_desc = &rtldsa_838x_mib_desc, + .stat_counters_lock = rtldsa_counters_lock_register, + .stat_counters_unlock = rtldsa_counters_unlock_register, + .stat_update_counters_atomically = rtldsa_update_counters_atomically, + .stat_counter_poll_interval = RTLDSA_COUNTERS_POLL_INTERVAL, + .port_iso_ctrl = rtl838x_port_iso_ctrl, + .traffic_enable = rtl838x_traffic_enable, + .traffic_disable = rtl838x_traffic_disable, + .traffic_set = rtl838x_traffic_set, + .l2_ctrl_0 = RTL838X_L2_CTRL_0, + .l2_ctrl_1 = RTL838X_L2_CTRL_1, + .l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT, + .set_ageing_time = rtl838x_set_ageing_time, + .smi_poll_ctrl = RTL838X_SMI_POLL_CTRL, + .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL, + .exec_tbl0_cmd = rtl838x_exec_tbl0_cmd, + .exec_tbl1_cmd = rtl838x_exec_tbl1_cmd, + .tbl_access_data_0 = rtl838x_tbl_access_data_0, + .isr_glb_src = RTL838X_ISR_GLB_SRC, + .isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG, + .imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG, + .imr_glb = RTL838X_IMR_GLB, + .n_counters = 128, + .n_pie_blocks = 12, + .port_ignore = 0x1f, + .vlan_tables_read = rtl838x_vlan_tables_read, + .vlan_set_tagged = rtl838x_vlan_set_tagged, + .vlan_set_untagged = rtl838x_vlan_set_untagged, + .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl, + .mac_link_sts = RTL838X_MAC_LINK_STS, + .vlan_profile_get = rtldsa_838x_vlan_profile_get, + .vlan_profile_dump = rtldsa_838x_vlan_profile_dump, + .vlan_profile_setup = rtl838x_vlan_profile_setup, + .vlan_fwd_on_inner = rtl838x_vlan_fwd_on_inner, + .set_vlan_igr_filter = rtl838x_set_igr_filter, + .set_vlan_egr_filter = rtl838x_set_egr_filter, + .enable_learning = rtl838x_enable_learning, + .enable_flood = rtl838x_enable_flood, + .enable_mcast_flood = rtl838x_enable_mcast_flood, + .enable_bcast_flood = rtl838x_enable_bcast_flood, + .set_static_move_action = rtl838x_set_static_move_action, + .stp_get = rtldsa_838x_stp_get, + .stp_set = rtl838x_stp_set, + .mac_port_ctrl = rtl838x_mac_port_ctrl, + .l2_port_new_salrn = rtl838x_l2_port_new_salrn, + .l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd, + .get_mirror_config = rtldsa_838x_get_mirror_config, + .print_matrix = rtldsa_838x_print_matrix, + .read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash, + .write_l2_entry_using_hash = rtl838x_write_l2_entry_using_hash, + .read_cam = rtl838x_read_cam, + .write_cam = rtl838x_write_cam, + .vlan_port_keep_tag_set = rtl838x_vlan_port_keep_tag_set, + .vlan_port_pvidmode_set = rtl838x_vlan_port_pvidmode_set, + .vlan_port_pvid_set = rtl838x_vlan_port_pvid_set, + .fast_age = rtldsa_838x_fast_age, + .trk_mbr_ctr = rtl838x_trk_mbr_ctr, + .rma_bpdu_fld_pmask = RTL838X_RMA_BPDU_FLD_PMSK, + .spcl_trap_eapol_ctrl = RTL838X_SPCL_TRAP_EAPOL_CTRL, + .init_eee = rtl838x_init_eee, + .set_mac_eee = rtldsa_838x_set_mac_eee, + .l2_hash_seed = rtl838x_l2_hash_seed, + .l2_hash_key = rtl838x_l2_hash_key, + .read_mcast_pmask = rtl838x_read_mcast_pmask, + .write_mcast_pmask = rtl838x_write_mcast_pmask, + .pie_init = rtl838x_pie_init, + .pie_rule_read = rtl838x_pie_rule_read, + .pie_rule_write = rtl838x_pie_rule_write, + .pie_rule_add = rtl838x_pie_rule_add, + .pie_rule_rm = rtl838x_pie_rule_rm, + .l2_learning_setup = rtl838x_l2_learning_setup, + .packet_cntr_read = rtl838x_packet_cntr_read, + .packet_cntr_clear = rtl838x_packet_cntr_clear, + .route_read = rtl838x_route_read, + .route_write = rtl838x_route_write, + .l3_setup = rtl838x_l3_setup, + .set_receive_management_action = rtl838x_set_receive_management_action, + .qos_init = rtldsa_838x_qos_init, + .lag_set_distribution_algorithm = rtldsa_838x_set_distribution_algorithm, + .lag_set_port_members = rtldsa_838x_lag_set_port_members, + .lag_setup_algomask = rtldsa_83xx_lag_setup_algomask, +}; diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h new file mode 100644 index 0000000000..acdc40f048 --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h @@ -0,0 +1,1608 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _RTL838X_H +#define _RTL838X_H + +#include +#include + +/* Register definition */ +#define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7))) +#define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7))) +#define RTL930X_MAC_PORT_CTRL(port) (0x3260 + (((port) << 6))) +#define RTL931X_MAC_PORT_CTRL (0x6004) + +#define RTL930X_MAC_L2_PORT_CTRL(port) (0x3268 + (((port) << 6))) +#define RTL931X_MAC_L2_PORT_CTRL (0x6000) + +#define RTL838X_RST_GLB_CTRL_0 (0x003c) + +#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104) +#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc) +#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C) +#define RTL931X_MAC_FORCE_MODE_CTRL (0x0DCC) + +#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2)) +#define RTL839X_PORT_ISO_CTRL(port) (0x1400 + ((port) << 3)) + +/* Packet statistics */ +#define RTL838X_STAT_PORT_STD_MIB (0x1200) +#define RTL839X_STAT_PORT_STD_MIB (0xC000) +#define RTL930X_STAT_PORT_MIB_CNTR (0x0664) +#define RTL930X_STAT_PORT_PRVTE_CNTR (0x2364) +#define RTL838X_STAT_RST (0x3100) +#define RTL839X_STAT_RST (0xF504) +#define RTL930X_STAT_RST (0x3240) +#define RTL931X_STAT_RST (0x7ef4) +#define RTL838X_STAT_PORT_RST (0x3104) +#define RTL839X_STAT_PORT_RST (0xF508) +#define RTL930X_STAT_PORT_RST (0x3244) +#define RTL931X_STAT_PORT_RST (0x7ef8) +#define RTL838X_STAT_CTRL (0x3108) +#define RTL839X_STAT_CTRL (0x04cc) +#define RTL930X_STAT_CTRL (0x3248) +#define RTL931X_STAT_CTRL (0x5720) + +/* VLAN registers */ +#define RTL838X_VLAN_CTRL (0x3A74) +#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2)) +#define RTL838X_VLAN_PROFILE_MAX 7 +#define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84) +#define RTL838X_VLAN_PORT_PB_VLAN (0x3C00) +#define RTL838X_VLAN_PORT_IGR_FLTR (0x3A7C) + +#define RTL838X_VLAN_L2_LEARN_EN(i) (i) +#define RTL838X_VLAN_L2_UNKN_MC_FLD(pmsk) (pmsk << 1) +#define RTL838X_VLAN_IP4_UNKN_MC_FLD(pmsk) (pmsk << 10) +#define RTL838X_VLAN_IP6_UNKN_MC_FLD(pmsk) (pmsk << 19) + +#define RTL838X_VLAN_L2_LEARN_EN_R(p) (p & RTL838X_VLAN_L2_LEARN_EN(1)) +#define RTL838X_VLAN_L2_UNKN_MC_FLD_PMSK(p) ((p >> 1) & (MAX_MC_PMASKS - 1)) +#define RTL838X_VLAN_IP4_UNKN_MC_FLD_PMSK(p) ((p >> 10) & (MAX_MC_PMASKS - 1)) +#define RTL838X_VLAN_IP6_UNKN_MC_FLD_PMSK(p) ((p >> 19) & (MAX_MC_PMASKS - 1)) + +#define RTL839X_VLAN_PROFILE(idx) (0x25C0 + (((idx) << 3))) +#define RTL839X_VLAN_PROFILE_MAX 7 +#define RTL839X_VLAN_CTRL (0x26D4) +#define RTL839X_VLAN_PORT_PB_VLAN (0x26D8) +#define RTL839X_VLAN_PORT_IGR_FLTR (0x27B4) +#define RTL839X_VLAN_PORT_EGR_FLTR (0x27C4) + +#define RTL839X_VLAN_L2_LEARN_EN(i) (i) +#define RTL839X_VLAN_L2_UNKN_MC_FLD(pmsk) (pmsk << 1) +#define RTL839X_VLAN_IP4_UNKN_MC_FLD(pmsk) (pmsk << 13) +#define RTL839X_VLAN_IP6_UNKN_MC_FLD(pmsk) (pmsk) + +#define RTL839X_VLAN_L2_LEARN_EN_R(p) (p[1] & RTL839X_VLAN_L2_LEARN_EN(1)) +#define RTL839X_VLAN_L2_UNKN_MC_FLD_PMSK(p) ((p[1] >> 1) & (MAX_MC_PMASKS - 1)) +#define RTL839X_VLAN_IP4_UNKN_MC_FLD_PMSK(p) ((p[1] >> 13) & (MAX_MC_PMASKS - 1)) +#define RTL839X_VLAN_IP6_UNKN_MC_FLD_PMSK(p) ((p[0]) & (MAX_MC_PMASKS - 1)) + +#define RTL930X_VLAN_PROFILE_SET(idx) (0x9c60 + (((idx) * 20))) +#define RTL930X_VLAN_PROFILE_MAX 7 +#define RTL930X_VLAN_CTRL (0x82D4) +#define RTL930X_VLAN_PORT_PB_VLAN (0x82D8) +#define RTL930X_VLAN_PORT_IGR_FLTR (0x83C0) +#define RTL930X_VLAN_PORT_EGR_FLTR (0x83C8) + +#define RTL930X_VLAN_L2_UNKN_MC_FLD(pmsk) (pmsk) +#define RTL930X_VLAN_IP4_UNKN_MC_FLD(pmsk) (pmsk) +#define RTL930X_VLAN_IP6_UNKN_MC_FLD(pmsk) (pmsk) + +#define RTL930X_VLAN_L2_LEARN_EN_R(p) (p[0] & (3 << 21)) +#define RTL930X_VLAN_L2_UNKN_MC_FLD_PMSK(p) (p[2] & RTL930X_MC_PMASK_ALL_PORTS) +#define RTL930X_VLAN_IP4_UNKN_MC_FLD_PMSK(p) (p[3] & RTL930X_MC_PMASK_ALL_PORTS) +#define RTL930X_VLAN_IP6_UNKN_MC_FLD_PMSK(p) (p[4] & RTL930X_MC_PMASK_ALL_PORTS) + +#define RTL931X_VLAN_PROFILE_SET(idx) (0x9800 + (((idx) * 28))) +#define RTL931X_VLAN_PROFILE_MAX 15 +#define RTL931X_VLAN_CTRL (0x94E4) +#define RTL931X_VLAN_PORT_IGR_CTRL (0x94E8) +#define RTL931X_VLAN_PORT_IGR_FLTR (0x96B4) +#define RTL931X_VLAN_PORT_EGR_FLTR (0x96C4) + +#define RTL931X_VLAN_L2_UNKN_MC_FLD_H(pmsk) (((u64)pmsk) >> 32) +#define RTL931X_VLAN_L2_UNKN_MC_FLD_L(pmsk) (pmsk & GENMASK_ULL(31, 0)) +#define RTL931X_VLAN_IP4_UNKN_MC_FLD_H(pmsk) (((u64)pmsk) >> 32) +#define RTL931X_VLAN_IP4_UNKN_MC_FLD_L(pmsk) (pmsk & GENMASK_ULL(31, 0)) +#define RTL931X_VLAN_IP6_UNKN_MC_FLD_H(pmsk) (((u64)pmsk) >> 32) +#define RTL931X_VLAN_IP6_UNKN_MC_FLD_L(pmsk) (pmsk & GENMASK_ULL(31, 0)) + +#define RTL931X_VLAN_L2_LEARN_EN_R(p) (p[0] & (3 << 14)) +#define RTL931X_VLAN_L2_UNKN_MC_FLD_PMSK(p) ((((u64)p[1]) << 32 | p[2]) & RTL931X_MC_PMASK_ALL_PORTS) +#define RTL931X_VLAN_IP4_UNKN_MC_FLD_PMSK(p) ((((u64)p[3]) << 32 | p[4]) & RTL931X_MC_PMASK_ALL_PORTS) +#define RTL931X_VLAN_IP6_UNKN_MC_FLD_PMSK(p) ((((u64)p[5]) << 32 | p[6]) & RTL931X_MC_PMASK_ALL_PORTS) + +/* Table access registers */ +#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) +#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) +#define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8) +#define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2)) + +#define RTL839X_TBL_ACCESS_CTRL_0 (0x1190) +#define RTL839X_TBL_ACCESS_DATA_0(idx) (0x1194 + ((idx) << 2)) +#define RTL839X_TBL_ACCESS_CTRL_1 (0x6b80) +#define RTL839X_TBL_ACCESS_DATA_1(idx) (0x6b84 + ((idx) << 2)) +#define RTL839X_TBL_ACCESS_CTRL_2 (0x611C) +#define RTL839X_TBL_ACCESS_DATA_2(i) (0x6120 + (((i) << 2))) + +#define RTL930X_TBL_ACCESS_CTRL_0 (0xB340) +#define RTL930X_TBL_ACCESS_DATA_0(idx) (0xB344 + ((idx) << 2)) +#define RTL930X_TBL_ACCESS_CTRL_1 (0xB3A0) +#define RTL930X_TBL_ACCESS_DATA_1(idx) (0xB3A4 + ((idx) << 2)) +#define RTL930X_TBL_ACCESS_CTRL_2 (0xCE04) +#define RTL930X_TBL_ACCESS_DATA_2(i) (0xCE08 + (((i) << 2))) + +#define RTL931X_TBL_ACCESS_CTRL_0 (0x8500) +#define RTL931X_TBL_ACCESS_DATA_0(idx) (0x8508 + ((idx) << 2)) +#define RTL931X_TBL_ACCESS_CTRL_1 (0x40C0) +#define RTL931X_TBL_ACCESS_DATA_1(idx) (0x40C4 + ((idx) << 2)) +#define RTL931X_TBL_ACCESS_CTRL_2 (0x8528) +#define RTL931X_TBL_ACCESS_DATA_2(i) (0x852C + (((i) << 2))) +#define RTL931X_TBL_ACCESS_CTRL_3 (0x0200) +#define RTL931X_TBL_ACCESS_DATA_3(i) (0x0204 + (((i) << 2))) +#define RTL931X_TBL_ACCESS_CTRL_4 (0x20DC) +#define RTL931X_TBL_ACCESS_DATA_4(i) (0x20E0 + (((i) << 2))) +#define RTL931X_TBL_ACCESS_CTRL_5 (0x7E1C) +#define RTL931X_TBL_ACCESS_DATA_5(i) (0x7E20 + (((i) << 2))) + +/* MAC handling */ +#define RTL838X_MAC_LINK_STS (0xa188) +#define RTL839X_MAC_LINK_STS (0x0390) +#define RTL930X_MAC_LINK_STS (0xCB10) +#define RTL931X_MAC_LINK_STS (0x0EC0) + +/* MAC link state bits */ +#define RTL_SPEED_10 0 +#define RTL_SPEED_100 1 +#define RTL_SPEED_1000 2 +#define RTL_SPEED_2500 5 +#define RTL_SPEED_5000 6 +#define RTL_SPEED_10000 4 + +#define RTL83XX_FORCE_EN BIT(0) +#define RTL83XX_FORCE_LINK_EN BIT(1) + +#define RTL838X_NWAY_EN BIT(2) +#define RTL838X_DUPLEX_MODE BIT(3) +#define RTL838X_SPEED_SHIFT (4) +#define RTL838X_SPEED_MASK (3 << RTL838X_SPEED_SHIFT) +#define RTL838X_TX_PAUSE_EN BIT(6) +#define RTL838X_RX_PAUSE_EN BIT(7) +#define RTL838X_MAC_FORCE_FC_EN BIT(8) + +#define RTL839X_DUPLEX_MODE BIT(2) +#define RTL839X_SPEED_SHIFT (3) +#define RTL839X_SPEED_MASK (3 << RTL839X_SPEED_SHIFT) +#define RTL839X_TX_PAUSE_EN BIT(5) +#define RTL839X_RX_PAUSE_EN BIT(6) +#define RTL839X_MAC_FORCE_FC_EN BIT(7) + +#define RTL930X_FORCE_EN BIT(0) +#define RTL930X_FORCE_LINK_EN BIT(1) +#define RTL930X_DUPLEX_MODE BIT(2) +#define RTL930X_SPEED_SHIFT (3) +#define RTL930X_SPEED_MASK (15 << RTL930X_SPEED_SHIFT) +#define RTL930X_TX_PAUSE_EN BIT(7) +#define RTL930X_RX_PAUSE_EN BIT(8) +#define RTL930X_MAC_FORCE_FC_EN BIT(9) + +#define RTL931X_FORCE_EN BIT(9) +#define RTL931X_FORCE_LINK_EN BIT(0) +#define RTL931X_DUPLEX_MODE BIT(2) +#define RTL931X_MAC_FORCE_FC_EN BIT(4) +#define RTL931X_TX_PAUSE_EN BIT(16) +#define RTL931X_RX_PAUSE_EN BIT(17) + +/* EEE */ +#define RTL838X_MAC_EEE_ABLTY (0xa1a8) +#define RTL838X_EEE_PORT_TX_EN (0x014c) +#define RTL838X_EEE_PORT_RX_EN (0x0150) +#define RTL838X_EEE_CLK_STOP_CTRL (0x0148) +#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04) +#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08) + +#define RTL839X_EEE_TX_TIMER_GELITE_CTRL (0x042C) +#define RTL839X_EEE_TX_TIMER_GIGA_CTRL (0x0430) +#define RTL839X_EEE_TX_TIMER_10G_CTRL (0x0434) +#define RTL839X_EEE_CTRL(p) (0x8008 + ((p) << 7)) +#define RTL839X_MAC_EEE_ABLTY (0x03C8) + +#define RTL930X_MAC_EEE_ABLTY (0xCB34) +#define RTL930X_EEE_CTRL(p) (0x3274 + ((p) << 6)) +#define RTL930X_EEEP_PORT_CTRL(p) (0x3278 + ((p) << 6)) + +#define RTL931X_MAC_EEE_ABLTY (0x0f08) + +/* L2 functionality */ +#define RTL838X_L2_CTRL_0 (0x3200) +#define RTL839X_L2_CTRL_0 (0x3800) +#define RTL930X_L2_CTRL (0x8FD8) +#define RTL931X_L2_CTRL (0xC800) +#define RTL838X_L2_CTRL_1 (0x3204) +#define RTL839X_L2_CTRL_1 (0x3804) +#define RTL930X_L2_AGE_CTRL (0x8FDC) +#define RTL931X_L2_AGE_CTRL (0xC804) +#define RTL838X_L2_PORT_AGING_OUT (0x3358) +#define RTL839X_L2_PORT_AGING_OUT (0x3b74) +#define RTL930X_L2_PORT_AGE_CTRL (0x8FE0) +#define RTL931X_L2_PORT_AGE_CTRL (0xc808) +#define RTL838X_TBL_ACCESS_L2_CTRL (0x6900) +#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180) +#define RTL930X_TBL_ACCESS_L2_CTRL (0xB320) +#define RTL930X_TBL_ACCESS_L2_METHOD_CTRL (0xB324) +#define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2)) +#define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2)) +#define RTL930X_TBL_ACCESS_L2_DATA(idx) (0xab08 + ((idx) << 2)) + +#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370) +#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0) +#define RTL930X_L2_TBL_FLUSH_CTRL (0x9404) +#define RTL931X_L2_TBL_FLUSH_CTRL (0xCD9C) + +#define RTL838X_L2_LRN_CONSTRT (0x329C) +#define RTL839X_L2_LRN_CONSTRT (0x3910) +#define RTL930X_L2_LRN_CONSTRT_CTRL (0x909c) +#define RTL931X_L2_LRN_CONSTRT_CTRL (0xC964) + +#define RTL838X_L2_FLD_PMSK (0x3288) +#define RTL839X_L2_FLD_PMSK (0x38EC) +#define RTL930X_L2_BC_FLD_PMSK (0x9068) +#define RTL931X_L2_BC_FLD_PMSK (0xC8FC) + +#define RTL930X_L2_UNKN_UC_FLD_PMSK (0x9064) +#define RTL931X_L2_UNKN_UC_FLD_PMSK (0xC8F4) + +#define RTL838X_L2_BC_FLD(pmsk) (pmsk << 9) +#define RTL838X_L2_UNKN_UC_FLD(pmsk) (pmsk) +#define RTL839X_L2_BC_FLD(pmsk) (pmsk << 12) +#define RTL839X_L2_UNKN_UC_FLD(pmsk) (pmsk) + +#define RTL838X_L2_LRN_CONSTRT_EN (0x3368) +#define RTL838X_L2_PORT_LRN_CONSTRT (0x32A0) +#define RTL839X_L2_PORT_LRN_CONSTRT (0x3914) +#define RTL930X_L2_LRN_PORT_CONSTRT_CTRL (0x90A4) +#define RTL931X_L2_LRN_PORT_CONSTRT_CTRL (0xC96C) + +#define RTL838X_L2_PORT_NEW_SALRN(p) (0x328c + (((p >> 4) << 2))) +#define RTL839X_L2_PORT_NEW_SALRN(p) (0x38F0 + (((p >> 4) << 2))) +#define RTL930X_L2_PORT_SALRN(p) (0x8FEC + (((p >> 4) << 2))) +#define RTL931X_L2_PORT_NEW_SALRN(p) (0xC820 + (((p >> 4) << 2))) + +#define SALRN_PORT_SHIFT(p) ((p % 16) * 2) +#define SALRN_MODE_MASK 0x3 +#define SALRN_MODE_HARDWARE 0 +#define SALRN_MODE_DISABLED 2 + +#define RTL838X_L2_PORT_NEW_SA_FWD(p) (0x3294 + (((p >> 4) << 2))) +#define RTL839X_L2_PORT_NEW_SA_FWD(p) (0x3900 + (((p >> 4) << 2))) +#define RTL930X_L2_PORT_NEW_SA_FWD(p) (0x8FF4 + (((p / 10) << 2))) +#define RTL931X_L2_PORT_NEW_SA_FWD(p) (0xC830 + (((p / 10) << 2))) + +#define RTL838X_L2_PORT_MV_ACT(p) (0x335c + (((p >> 4) << 2))) +#define RTL839X_L2_PORT_MV_ACT(p) (0x3b80 + (((p >> 4) << 2))) + +#define RTL838X_L2_PORT_STATIC_MV_ACT(p) (0x327c + (((p >> 4) << 2))) +#define RTL839X_L2_PORT_STATIC_MV_ACT(p) (0x38dc + (((p >> 4) << 2))) + +#define MV_ACT_PORT_SHIFT(p) ((p % 16) * 2) +#define MV_ACT_MASK 0x3 +#define MV_ACT_FORWARD 0 +#define MV_ACT_DROP 1 +#define MV_ACT_TRAP2CPU 2 +#define MV_ACT_COPY2CPU 3 + +#define RTL930X_ST_CTRL (0x8798) +#define RTL931x_ST_CTRL (0x8000) + +#define RTL930X_L2_PORT_SABLK_CTRL (0x905c) +#define RTL930X_L2_PORT_DABLK_CTRL (0x9060) + +#define RTL838X_L2_PORT_LM_ACT(p) (0x3208 + ((p) << 2)) +#define RTL838X_VLAN_PORT_FWD (0x3A78) +#define RTL839X_VLAN_PORT_FWD (0x27AC) +#define RTL930X_VLAN_PORT_FWD (0x834C) +#define RTL931X_VLAN_PORT_FWD (0x95CC) +#define RTL838X_VLAN_FID_CTRL (0x3aa8) + +/* Port Mirroring */ +#define RTL838X_MIR_CTRL (0x5D00) +#define RTL838X_MIR_DPM_CTRL (0x5D20) +#define RTL838X_MIR_SPM_CTRL (0x5D10) + +#define RTL839X_MIR_CTRL (0x2500) +#define RTL839X_MIR_DPM_CTRL (0x2530) +#define RTL839X_MIR_SPM_CTRL (0x2510) + +#define RTL930X_MIR_CTRL (0xA2A0) +#define RTL930X_MIR_DPM_CTRL (0xA2C0) +#define RTL930X_MIR_SPM_CTRL (0xA2B0) + +#define RTL931X_MIR_CTRL (0xAF00) +#define RTL931X_MIR_DPM_CTRL (0xAF30) +#define RTL931X_MIR_SPM_CTRL (0xAF10) + +/* Storm/rate control and scheduling */ +#define RTL838X_STORM_CTRL (0x4700) +#define RTL839X_STORM_CTRL (0x1800) +#define RTL838X_STORM_CTRL_LB_CTRL(p) (0x4884 + (((p) << 2))) +#define RTL838X_STORM_CTRL_BURST_PPS_0 (0x4874) +#define RTL838X_STORM_CTRL_BURST_PPS_1 (0x4878) +#define RTL838X_STORM_CTRL_BURST_0 (0x487c) +#define RTL838X_STORM_CTRL_BURST_1 (0x4880) +#define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_0 (0x1804) +#define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_1 (0x1808) +#define RTL838X_SCHED_CTRL (0xB980) +#define RTL839X_SCHED_CTRL (0x60F4) +#define RTL838X_SCHED_LB_TICK_TKN_CTRL_0 (0xAD58) +#define RTL838X_SCHED_LB_TICK_TKN_CTRL_1 (0xAD5C) +#define RTL839X_SCHED_LB_TICK_TKN_CTRL_0 (0x1804) +#define RTL839X_SCHED_LB_TICK_TKN_CTRL_1 (0x1808) +#define RTL839X_STORM_CTRL_SPCL_LB_TICK_TKN_CTRL (0x2000) +#define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_0 (0x1604) +#define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_1 (0x1608) +#define RTL839X_SCHED_LB_TICK_TKN_CTRL (0x60F8) +#define RTL839X_SCHED_LB_TICK_TKN_PPS_CTRL (0x6200) +#define RTL838X_SCHED_LB_THR (0xB984) +#define RTL839X_SCHED_LB_THR (0x60FC) +#define RTL838X_SCHED_P_EGR_RATE_CTRL(p) (0xC008 + (((p) << 7))) +#define RTL838X_SCHED_Q_EGR_RATE_CTRL(p, q) (0xC00C + (p << 7) + (((q) << 2))) +#define RTL838X_STORM_CTRL_PORT_BC_EXCEED (0x470C) +#define RTL838X_STORM_CTRL_PORT_MC_EXCEED (0x4710) +#define RTL838X_STORM_CTRL_PORT_UC_EXCEED (0x4714) +#define RTL839X_STORM_CTRL_PORT_BC_EXCEED(p) (0x180c + (((p >> 5) << 2))) +#define RTL839X_STORM_CTRL_PORT_MC_EXCEED(p) (0x1814 + (((p >> 5) << 2))) +#define RTL839X_STORM_CTRL_PORT_UC_EXCEED(p) (0x181c + (((p >> 5) << 2))) +#define RTL838X_STORM_CTRL_PORT_UC(p) (0x4718 + (((p) << 2))) +#define RTL838X_STORM_CTRL_PORT_MC(p) (0x478c + (((p) << 2))) +#define RTL838X_STORM_CTRL_PORT_BC(p) (0x4800 + (((p) << 2))) +#define RTL839X_STORM_CTRL_PORT_UC_0(p) (0x185C + (((p) << 3))) +#define RTL839X_STORM_CTRL_PORT_UC_1(p) (0x1860 + (((p) << 3))) +#define RTL839X_STORM_CTRL_PORT_MC_0(p) (0x19FC + (((p) << 3))) +#define RTL839X_STORM_CTRL_PORT_MC_1(p) (0x1a00 + (((p) << 3))) +#define RTL839X_STORM_CTRL_PORT_BC_0(p) (0x1B9C + (((p) << 3))) +#define RTL839X_STORM_CTRL_PORT_BC_1(p) (0x1BA0 + (((p) << 3))) +#define RTL839X_TBL_ACCESS_CTRL_2 (0x611C) +#define RTL839X_TBL_ACCESS_DATA_2(i) (0x6120 + (((i) << 2))) +#define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_0(p) (0x1618 + (((p) << 3))) +#define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_1(p) (0x161C + (((p) << 3))) +#define RTL839X_IGR_BWCTRL_PORT_CTRL_0(p) (0x1640 + (((p) << 3))) +#define RTL839X_IGR_BWCTRL_PORT_CTRL_1(p) (0x1644 + (((p) << 3))) +#define RTL839X_IGR_BWCTRL_CTRL_LB_THR (0x1614) + +/* Link aggregation (Trunking) */ +#define TRUNK_DISTRIBUTION_ALGO_SPA_BIT BIT(0) +#define TRUNK_DISTRIBUTION_ALGO_SMAC_BIT BIT(1) +#define TRUNK_DISTRIBUTION_ALGO_DMAC_BIT BIT(2) + +#define TRUNK_DISTRIBUTION_ALGO_SIP_BIT BIT(3) +#define TRUNK_DISTRIBUTION_ALGO_DIP_BIT BIT(4) +#define TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT BIT(5) +#define TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT BIT(6) +#define TRUNK_DISTRIBUTION_ALGO_VLAN_BIT BIT(7) +#define TRUNK_DISTRIBUTION_ALGO_MASKALL GENMASK(6, 0) + +#define TRUNK_DISTRIBUTION_ALGO_L2_SPA_BIT BIT(0) +#define TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT BIT(1) +#define TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT BIT(2) +#define TRUNK_DISTRIBUTION_ALGO_L2_VLAN_BIT BIT(3) + +#define TRUNK_DISTRIBUTION_ALGO_L3_SPA_BIT BIT(4 + 0) +#define TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT BIT(4 + 1) +#define TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT BIT(4 + 2) +#define TRUNK_DISTRIBUTION_ALGO_L3_VLAN_BIT BIT(4 + 3) +#define TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT BIT(4 + 4) +#define TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT BIT(4 + 5) +#define TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT BIT(4 + 6) +#define TRUNK_DISTRIBUTION_ALGO_L3_DST_L4PORT_BIT BIT(4 + 7) +#define TRUNK_DISTRIBUTION_ALGO_L3_PROTO_BIT BIT(4 + 8) +#define TRUNK_DISTRIBUTION_ALGO_L3_FLOW_LABEL_BIT BIT(4 + 9) + +#define RTL838X_TRK_MBR_CTR (0x3E00) +#define RTL838X_TRK_HASH_IDX_CTRL (0x3E20) +#define RTL838X_TRK_HASH_CTRL (0x3E24) + +#define RTL839X_TRK_MBR_CTR (0x2200) +#define RTL839X_TRK_HASH_IDX_CTRL (0x2280) +#define RTL839X_TRK_HASH_CTRL (0x2284) + +#define RTL930X_LOCAL_PORT_TRK_MAP (0xD0C8) +#define RTL930X_TRK_ID_CTRL (0xA3A8) +#define RTL930X_TRK_MBR_CTRL (0xA41C) +#define RTL930X_TRK_HASH_CTRL (0x9F80) +#define RTL930X_TRK_CTRL (0x9F88) +#define RTL930X_TRK_SHIFT_CTRL (0x9F8C) +#define RTL930X_TRK_LOCAL_TBL_REFRESH (0x9F90) +#define RTL930X_TRK_LOCAL_TBL (0x9F94) +#define RTL930X_TRK_STK_CTRL (0xA07C) + +#define RTL930X_TRK_ID_CTRL_TRK_VALID BIT(6) +#define RTL930X_TRK_ID_CTRL_TRK_ID GENMASK(5, 0) + +#define RTL930X_LOCAL_PORT_TRK_MAP_IS_TRK_MBR BIT(6) +#define RTL930X_LOCAL_PORT_TRK_MAP_TRK_ID GENMASK(5, 0) + +#define RTL930X_SRC_TRK_MAP_TRK_VALID BIT(31) +#define RTL930X_SRC_TRK_MAP_TRK_ID GENMASK(30, 25) + +#define RTL931X_LOCAL_PORT_TRK_MAP (0x4CAC) +#define RTL931X_TRK_ID_CTRL (0xB800) +#define RTL931X_TRK_MBR_CTRL (0xB8D0) +#define RTL931X_TRK_HASH_CTRL (0xBA70) +#define RTL931X_TRK_CTRL (0xBA78) +#define RTL931X_TRK_SHIFT_CTRL (0xBA7C) +#define RTL931X_TRK_LOCAL_TBL_REFRESH (0xBA80) +#define RTL931X_TRK_LOCAL_TBL (0xBA84) +#define RTL931X_TRK_STK_CTRL (0xBE94) + +#define RLT931X_TRK_ID_CTRL_TRK_ID GENMASK(6, 0) +#define RTL931X_TRK_ID_CTRL_TRK_VALID BIT(7) + +#define RTL931X_LOCAL_PORT_TRK_MAP_IS_TRK_MBR BIT(7) +#define RTL931X_LOCAL_PORT_TRK_MAP_TRK_ID GENMASK(6, 0) + +#define RTL931X_SRC_TRK_MAP_TRK_ID GENMASK(30, 24) +#define RTL931X_SRC_TRK_MAP_TRK_ID_VALID BIT(31) + +#define GENMASK_MOD(high, low) GENMASK((high) % 32, (low) % 32) +#define BIT_MOD(bit) BIT((bit) % 32) + +/* RTL930X LAG Table offsets */ +#define RTL930X_LAG_NUM_TX_CANDI GENMASK_MOD(92, 89) +#define RTL930X_LAG_L2_HASH_MSK_IDX BIT_MOD(88) +#define RTL930X_LAG_IP4_HASH_MSK_IDX BIT_MOD(87) +#define RTL930X_LAG_IP6_HASH_MSK_IDX BIT_MOD(86) +#define RTL930X_LAG_SEP_DLF_BCAST_EN BIT_MOD(85) +#define RTL930X_LAG_SEP_KWN_MC_EN BIT_MOD(84) +#define RTL930X_LAG_TRK_DEV7 GENMASK_MOD(83, 80) +#define RTL930X_LAG_TRK_PORT7 GENMASK_MOD(79, 74) +#define RTL930X_LAG_TRK_DEV6 GENMASK_MOD(73, 70) +#define RTL930X_LAG_TRK_PORT6 GENMASK_MOD(69, 64) + +#define RTL930X_LAG_TRK_DEV5 GENMASK_MOD(61, 58) +#define RTL930X_LAG_TRK_PORT5 GENMASK_MOD(57, 52) +#define RTL930X_LAG_TRK_DEV4 GENMASK_MOD(51, 48) +#define RTL930X_LAG_TRK_PORT4 GENMASK_MOD(47, 42) +#define RTL930X_LAG_TRK_DEV3 GENMASK_MOD(41, 38) +#define RTL930X_LAG_TRK_PORT3 GENMASK_MOD(37, 32) + +#define RTL930X_LAG_TRK_DEV2 GENMASK_MOD(29, 26) +#define RTL930X_LAG_TRK_PORT2 GENMASK_MOD(25, 20) +#define RTL930X_LAG_TRK_DEV1 GENMASK_MOD(19, 16) +#define RTL930X_LAG_TRK_PORT1 GENMASK_MOD(15, 10) +#define RTL930X_LAG_TRK_DEV0 GENMASK_MOD(9, 6) +#define RTL930X_LAG_TRK_PORT0 GENMASK_MOD(5, 0) + +/* RTL931X LAG Table offsets */ +#define RTL931X_LAG_NUM_TX_CANDI GENMASK_MOD(92, 89) +#define RTL931X_LAG_L2_HASH_MSK_IDX BIT_MOD(88) +#define RTL931X_LAG_IP4_HASH_MSK_IDX BIT_MOD(87) +#define RTL931X_LAG_IP6_HASH_MSK_IDX BIT_MOD(86) +#define RTL931X_LAG_SEP_FLOOD_EN BIT_MOD(85) +#define RTL931X_LAG_SEP_KWN_MC_EN BIT_MOD(84) +#define RTL931X_LAG_TRK_DEV7 GENMASK_MOD(83, 80) +#define RTL931X_LAG_TRK_PORT7 GENMASK_MOD(79, 74) +#define RTL931X_LAG_TRK_DEV6 GENMASK_MOD(73, 70) +#define RTL931X_LAG_TRK_PORT6 GENMASK_MOD(69, 64) + +#define RTL931X_LAG_TRK_DEV5 GENMASK_MOD(61, 58) +#define RTL931X_LAG_TRK_PORT5 GENMASK_MOD(57, 52) +#define RTL931X_LAG_TRK_DEV4 GENMASK_MOD(51, 48) +#define RTL931X_LAG_TRK_PORT4 GENMASK_MOD(47, 42) +#define RTL931X_LAG_TRK_DEV3 GENMASK_MOD(41, 38) +#define RTL931X_LAG_TRK_PORT3 GENMASK_MOD(37, 32) + +#define RTL931X_LAG_TRK_DEV2 GENMASK_MOD(29, 26) +#define RTL931X_LAG_TRK_PORT2 GENMASK_MOD(25, 20) +#define RTL931X_LAG_TRK_DEV1 GENMASK_MOD(19, 16) +#define RTL931X_LAG_TRK_PORT1 GENMASK_MOD(15, 10) +#define RTL931X_LAG_TRK_DEV0 GENMASK_MOD(9, 6) +#define RTL931X_LAG_TRK_PORT0 GENMASK_MOD(5, 0) + +/* Attack prevention */ +#define RTL838X_ATK_PRVNT_PORT_EN (0x5B00) +#define RTL838X_ATK_PRVNT_CTRL (0x5B04) +#define RTL838X_ATK_PRVNT_ACT (0x5B08) +#define RTL838X_ATK_PRVNT_STS (0x5B1C) + +/* 802.1X */ +#define RTL838X_RMA_BPDU_FLD_PMSK (0x4348) +#define RTL930X_RMA_BPDU_FLD_PMSK (0x9F18) +#define RTL931X_RMA_BPDU_FLD_PMSK (0x8950) +#define RTL839X_RMA_BPDU_FLD_PMSK (0x125C) + +#define RTL838X_SPCL_TRAP_CTRL (0x6980) +#define RTL838X_SPCL_TRAP_EAPOL_CTRL (0x6988) +#define RTL838X_SPCL_TRAP_ARP_CTRL (0x698C) +#define RTL838X_SPCL_TRAP_IGMP_CTRL (0x6984) +#define RTL838X_SPCL_TRAP_IPV6_CTRL (0x6994) +#define RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL (0x6998) + +#define RTL839X_SPCL_TRAP_CTRL (0x1054) +#define RTL839X_SPCL_TRAP_EAPOL_CTRL (0x105C) +#define RTL839X_SPCL_TRAP_ARP_CTRL (0x1060) +#define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058) +#define RTL839X_SPCL_TRAP_IPV6_CTRL (0x1064) +#define RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL (0x1068) +#define RTL839X_SPCL_TRAP_SWITCH_IPV4_ADDR_CTRL (0x106C) +#define RTL839X_SPCL_TRAP_CRC_CTRL (0x1070) + +#define RTL930X_BANDWIDTH_CTRL_EGRESS(port) (0x7660 + (port * 16)) +#define RTL930X_BANDWIDTH_CTRL_INGRESS(port) (0x8068 + (port * 4)) +#define RTL930X_BANDWIDTH_CTRL_MAX_BURST (64 * 1000) +#define RTL930X_BANDWIDTH_CTRL_INGRESS_BURST_HIGH_ON(port) \ + (0x80DC + (port * 8)) +#define RTL930X_BANDWIDTH_CTRL_INGRESS_BURST_HIGH_OFF(port) \ + (0x80E0 + (port * 8)) +#define RTL930X_BANDWIDTH_CTRL_INGRESS_BURST_MAX \ + GENMASK(30, 0) + +#define RTL931X_BANDWIDTH_CTRL_EGRESS(port) (0x2164 + (port * 8)) +#define RTL931X_BANDWIDTH_CTRL_INGRESS(port) (0xe008 + (port * 8)) + +#define RTL93XX_BANDWIDTH_CTRL_RATE_MAX GENMASK(19, 0) +#define RTL93XX_BANDWIDTH_CTRL_ENABLE BIT(20) +#define RTL931X_BANDWIDTH_CTRL_MAX_BURST GENMASK(15, 0) + +#define RTL930X_INGRESS_FC_CTRL(port) (0x81CC + ((port / 29) * 4)) +#define RTL930X_INGRESS_FC_CTRL_EN(port) BIT(port % 29) + +/* Switch interrupts */ +#define RTL838X_IMR_GLB (0x1100) +#define RTL838X_IMR_PORT_LINK_STS_CHG (0x1104) +#define RTL838X_ISR_GLB_SRC (0x1148) +#define RTL838X_ISR_PORT_LINK_STS_CHG (0x114C) + +#define RTL839X_IMR_GLB (0x0064) +#define RTL839X_IMR_PORT_LINK_STS_CHG (0x0068) +#define RTL839X_ISR_GLB_SRC (0x009c) +#define RTL839X_ISR_PORT_LINK_STS_CHG (0x00a0) + +#define RTL930X_IMR_GLB (0xC628) +#define RTL930X_IMR_PORT_LINK_STS_CHG (0xC62C) +#define RTL930X_ISR_GLB (0xC658) +#define RTL930X_ISR_PORT_LINK_STS_CHG (0xC660) + +/* IMR_GLB does not exit on RTL931X */ +#define RTL931X_IMR_PORT_LINK_STS_CHG (0x126C) +#define RTL931X_ISR_GLB_SRC (0x12B4) +#define RTL931X_ISR_PORT_LINK_STS_CHG (0x12B8) + +/* + * MDIO via Realtek's SMI interface + */ +#define RTL838X_SMI_GLB_CTRL (0xa100) +#define RTL838X_SMI_POLL_CTRL (0xa17c) + +#define RTL839X_SMI_GLB_CTRL (0x03f8) +#define RTL839X_SMI_PORT_POLLING_CTRL (0x03fc) + +#define RTL930X_SMI_POLL_CTRL (0xca90) +#define RTL931X_SMI_PORT_POLLING_CTRL (0x0CCC) + +#define RTL838X_LED_GLB_CTRL (0xA000) +#define RTL839X_LED_GLB_CTRL (0x00E4) +#define RTL930X_LED_GLB_CTRL (0xCC00) +#define RTL931X_LED_GLB_CTRL (0x0600) + +/* LED control by switch */ +#define RTL838X_LED_MODE_SEL (0x1004) +#define RTL838X_LED_MODE_CTRL (0xA004) +#define RTL838X_LED_P_EN_CTRL (0xA008) + +/* LED control by software */ +#define RTL838X_LED_SW_CTRL (0xA00C) +#define RTL838X_LED0_SW_P_EN_CTRL (0xA010) +#define RTL838X_LED1_SW_P_EN_CTRL (0xA014) +#define RTL838X_LED2_SW_P_EN_CTRL (0xA018) +#define RTL838X_LED_SW_P_CTRL (0xA01C) +#define RTL838X_LED_SW_P_CTRL_PORT(p) (RTL838X_LED_SW_P_CTRL + (((p) << 2))) + +#define RTL93XX_HASH_MASK_INDEX_L2 (0) +#define RTL93XX_HASH_MASK_INDEX_L23 (1) + +#define RTL93XX_TRK_CTRL_NON_TMN_TUNNEL_HASH_SEL BIT(0) +#define RTL93XX_TRK_CTRL_SEP_PORT_SEL BIT(1) +#define RTL93XX_TRK_CTRL_TRK_STAND_ALONE_MODE BIT(2) +#define RTL93XX_TRK_CTRL_STK_HASH_CAL BIT(3) +#define RTL93XX_TRK_CTRL_LOCAL_FIRST BIT(4) +#define RTL93XX_TRK_CTRL_CONGST_AVOID BIT(5) +#define RTL93XX_TRK_CTRL_LINK_DOWN_AVOID BIT(6) + +/* special port action controls */ +/* values: + * 0 = FORWARD (default) + * 1 = DROP + * 2 = TRAP2CPU + * 3 = FLOOD IN ALL PORT + * + * Register encoding. + * offset = CTRL + (port >> 4) << 2 + * value/mask = 3 << ((port & 0xF) << 1) + */ + +typedef enum { + BPDU = 0, + PTP, + PTP_UDP, + PTP_ETH2, + LLDP, + EAPOL, + GRATARP, +} rma_ctrl_t; + +typedef enum { + FORWARD = 0, + DROP, + TRAP2CPU, + FLOODALL, + TRAP2MASTERCPU, + COPY2CPU, +} action_type_t; + +#define RTL838X_RMA_BPDU_CTRL (0x4330) +#define RTL839X_RMA_BPDU_CTRL (0x122C) +#define RTL930X_RMA_BPDU_CTRL (0x9E7C) +#define RTL931X_RMA_BPDU_CTRL (0x881C) + +#define RTL838X_RMA_PTP_CTRL (0x4338) +#define RTL839X_RMA_PTP_CTRL (0x123C) +#define RTL930X_RMA_PTP_CTRL (0x9E88) +#define RTL931X_RMA_PTP_CTRL (0x8834) + +#define RTL838X_RMA_LLDP_CTRL (0x4340) +#define RTL839X_RMA_LLDP_CTRL (0x124C) +#define RTL930X_RMA_LLDP_CTRL (0x9EFC) +#define RTL931X_RMA_LLDP_CTRL (0x8918) + +#define RTL930X_RMA_EAPOL_CTRL (0x9F08) +#define RTL930X_SPCL_TRAP_PORT_CTRL (0xA1A0) +#define RTL931X_RMA_EAPOL_CTRL (0x8930) +#define RTL931X_TRAP_ARP_GRAT_PORT_ACT (0x8C04) + +/* QoS */ +#define RTL838X_QM_INTPRI2QID_CTRL (0x5F00) +#define RTL839X_QM_INTPRI2QID_CTRL(q) (0x1110 + (q << 2)) +#define RTL839X_QM_PORT_QNUM(p) (0x1130 + (((p / 10) << 2))) +#define RTL838X_PRI_SEL_PORT_PRI(p) (0x5FB8 + (((p / 10) << 2))) +#define RTL839X_PRI_SEL_PORT_PRI(p) (0x10A8 + (((p / 10) << 2))) +#define RTL838X_QM_PKT2CPU_INTPRI_MAP (0x5F10) +#define RTL839X_QM_PKT2CPU_INTPRI_MAP (0x1154) +#define RTL838X_PRI_SEL_CTRL (0x10E0) +#define RTL839X_PRI_SEL_CTRL (0x10E0) +#define RTL838X_PRI_SEL_TBL_CTRL(i) (0x5FD8 + (((i) << 2))) +#define RTL839X_PRI_SEL_TBL_CTRL(i) (0x10D0 + (((i) << 2))) +#define RTL838X_QM_PKT2CPU_INTPRI_0 (0x5F04) +#define RTL838X_QM_PKT2CPU_INTPRI_1 (0x5F08) +#define RTL838X_QM_PKT2CPU_INTPRI_2 (0x5F0C) +#define RTL839X_OAM_CTRL (0x2100) +#define RTL839X_OAM_PORT_ACT_CTRL(p) (0x2104 + (((p) << 2))) +#define RTL839X_RMK_PORT_DEI_TAG_CTRL(p) (0x6A9C + (((p >> 5) << 2))) +#define RTL839X_PRI_SEL_IPRI_REMAP (0x1080) +#define RTL838X_PRI_SEL_IPRI_REMAP (0x5F8C) +#define RTL839X_PRI_SEL_DEI2DP_REMAP (0x10EC) +#define RTL839X_PRI_SEL_DSCP2DP_REMAP_ADDR(i) (0x10F0 + (((i >> 4) << 2))) +#define RTL839X_RMK_DEI_CTRL (0x6AA4) +#define RTL839X_WRED_PORT_THR_CTRL(i) (0x6084 + ((i) << 2)) +#define RTL839X_WRED_QUEUE_THR_CTRL(q, i) (0x6090 + ((q) * 12) + ((i) << 2)) +#define RTL838X_PRI_DSCP_INVLD_CTRL0 (0x5FE8) +#define RTL838X_RMK_IPRI_CTRL (0xA460) +#define RTL838X_RMK_OPRI_CTRL (0xA464) +#define RTL838X_SCHED_P_TYPE_CTRL(p) (0xC04C + (((p) << 7))) +#define RTL838X_SCHED_LB_CTRL(p) (0xC004 + (((p) << 7))) +#define RTL838X_FC_P_EGR_DROP_CTRL(p) (0x6B1C + (((p) << 2))) + +#define RTL930X_REMAP_DSCP(p) (0x9B04 + (((p) / 10) * 4)) +#define RTL931X_REMAP_DSCP(p) (0x9034 + (((p) / 10) * 4)) +#define RTL93XX_REMAP_DSCP_INTPRI_DSCP_OFFSET(p) \ + (((p) % 10) * 3) +#define RTL93XX_REMAP_DSCP_INTPRI_DSCP_MASK(index) \ + (0x7 << RTL93XX_REMAP_DSCP_INTPRI_DSCP_OFFSET(index)) + +#define RTL930X_PORT_TBL_IDX_CTRL(port) (0x9B20 + (((port) / 16) * 4)) +#define RTL931X_PORT_TBL_IDX_CTRL(port) (0x9064 + (((port) / 16) * 4)) +#define RTL93XX_PORT_TBL_IDX_CTRL_IDX_OFFSET(port) \ + (((port) & 0xF) << 1) +#define RTL93XX_PORT_TBL_IDX_CTRL_IDX_MASK(port) \ + (0x3 << RTL93XX_PORT_TBL_IDX_CTRL_IDX_OFFSET(port)) + +#define RTL93XX_PRI_SEL_GROUP_0 (0) +#define RTL93XX_PRI_SEL_GROUP_1 (1) + +#define RTL930X_PRI_SEL_TBL_CTRL(group) (0x9B28 + ((group) * 4)) +#define RTL931X_PRI_SEL_TBL_CTRL(group) (0x9074 + ((group) * 8)) +#define RTL931X_PRI_SEL_TBL_CTRL_1BR_MASK GENMASK(15, 12) +#define RTL931X_PRI_SEL_TBL_CTRL_MPLS_MASK GENMASK(11, 8) +#define RTL931X_PRI_SEL_TBL_CTRL_11E_MASK GENMASK(7, 4) +#define RTL931X_PRI_SEL_TBL_CTRL_TUNNEL_MASK GENMASK(3, 0) + +#define RTL93XX_PRI_SEL_TBL_CTRL_ROUT_MASK GENMASK(31, 28) +#define RTL93XX_PRI_SEL_TBL_CTRL_PROT_VLAN_MASK GENMASK(27, 24) +#define RTL93XX_PRI_SEL_TBL_CTRL_MAC_VLAN_MASK GENMASK(23, 20) +#define RTL93XX_PRI_SEL_TBL_CTRL_OTAG_MASK GENMASK(19, 16) +#define RTL93XX_PRI_SEL_TBL_CTRL_ITAG_MASK GENMASK(15, 12) +#define RTL93XX_PRI_SEL_TBL_CTRL_DSCP_MASK GENMASK(11, 8) +#define RTL93XX_PRI_SEL_TBL_CTRL_VACL_MASK GENMASK(7, 4) +#define RTL93XX_PRI_SEL_TBL_CTRL_PORT_MASK GENMASK(3, 0) + +/* port: 0-23, index: 0-7 */ +#define RTL930X_SCHED_PORT_Q_CTRL_SET0(port, index) \ + (0x3D48 + ((port) * 384) + ((index) * 4)) +/* port: 24-27, index: 0-11 */ +#define RTL930X_SCHED_PORT_Q_CTRL_SET1(port, index) \ + ((0xE860 + ((port) - 24) * 48) + ((index) * 4)) +/* port: 0-51, index: 0-7 */ +#define RTL931X_SCHED_PORT_Q_CTRL_SET0(port, index) \ + (0x2888 + ((port) << 5) + ((index) * 4)) +/* port: 52-55, index: 0-11 */ +#define RTL931X_SCHED_PORT_Q_CTRL_SET1(port, index) \ + ((0x2F08 + ((port) - 52) * 48) + ((index) * 4)) + +#define RTL930X_QM_INTPRI2QID_CTRL (0xA320) +#define RTL931X_QM_INTPRI2QID_CTRL (0xA9D0) + +/* Debug features */ +#define RTL930X_STAT_PRVTE_DROP_COUNTER0 (0xB5B8) + +/* Packet Inspection Engine */ +#define RTL838X_METER_GLB_CTRL (0x4B08) +#define RTL839X_METER_GLB_CTRL (0x1300) +#define RTL930X_METER_GLB_CTRL (0xa0a0) +#define RTL931X_METER_GLB_CTRL (0x411C) + +#define RTL839X_ACL_CTRL (0x1288) + +#define RTL838X_ACL_BLK_LOOKUP_CTRL (0x6100) +#define RTL839X_ACL_BLK_LOOKUP_CTRL (0x1280) +#define RTL930X_PIE_BLK_LOOKUP_CTRL (0xa5a0) +#define RTL931X_PIE_BLK_LOOKUP_CTRL (0x4180) + +#define RTL838X_ACL_BLK_PWR_CTRL (0x6104) +#define RTL839X_PS_ACL_PWR_CTRL (0x049c) + +#define RTL838X_ACL_BLK_TMPLTE_CTRL(block) (0x6108 + ((block) << 2)) +#define RTL839X_ACL_BLK_TMPLTE_CTRL(block) (0x128c + ((block) << 2)) +#define RTL930X_PIE_BLK_TMPLTE_CTRL(block) (0xa624 + ((block) << 2)) +#define RTL931X_PIE_BLK_TMPLTE_CTRL(block) (0x4214 + ((block) << 2)) + +#define RTL838X_ACL_BLK_GROUP_CTRL (0x615C) +#define RTL839X_ACL_BLK_GROUP_CTRL (0x12ec) + +#define RTL838X_ACL_CLR_CTRL (0x6168) +#define RTL839X_ACL_CLR_CTRL (0x12fc) +#define RTL930X_PIE_CLR_CTRL (0xa66c) +#define RTL931X_PIE_CLR_CTRL (0x42D8) + +#define RTL838X_DMY_REG27 (0x3378) + +#define RTL838X_ACL_PORT_LOOKUP_CTRL(p) (0x616C + (((p) << 2))) +#define RTL930X_ACL_PORT_LOOKUP_CTRL(p) (0xA784 + (((p) << 2))) +#define RTL931X_ACL_PORT_LOOKUP_CTRL(p) (0x44F8 + (((p) << 2))) + +#define RTL930X_PIE_BLK_PHASE_CTRL (0xA5A4) +#define RTL931X_PIE_BLK_PHASE_CTRL (0x4184) + +/* PIE actions */ +#define PIE_ACT_COPY_TO_PORT 2 +#define PIE_ACT_REDIRECT_TO_PORT 4 +#define PIE_ACT_ROUTE_UC 6 +#define PIE_ACT_VID_ASSIGN 0 + +/* L3 actions */ +#define L3_FORWARD 0 +#define L3_DROP 1 +#define L3_TRAP2CPU 2 +#define L3_COPY2CPU 3 +#define L3_TRAP2MASTERCPU 4 +#define L3_COPY2MASTERCPU 5 +#define L3_HARDDROP 6 + +/* Route actions */ +#define ROUTE_ACT_FORWARD 0 +#define ROUTE_ACT_TRAP2CPU 1 +#define ROUTE_ACT_COPY2CPU 2 +#define ROUTE_ACT_DROP 3 + +/* L3 Routing */ +#define RTL839X_ROUTING_SA_CTRL 0x6afc +#define RTL930X_L3_HOST_TBL_CTRL (0xAB48) +#define RTL930X_L3_IPUC_ROUTE_CTRL (0xAB4C) +#define RTL930X_L3_IP6UC_ROUTE_CTRL (0xAB50) +#define RTL930X_L3_IPMC_ROUTE_CTRL (0xAB54) +#define RTL930X_L3_IP6MC_ROUTE_CTRL (0xAB58) +#define RTL930X_L3_IP_MTU_CTRL(i) (0xAB5C + ((i >> 1) << 2)) +#define RTL930X_L3_IP6_MTU_CTRL(i) (0xAB6C + ((i >> 1) << 2)) +#define RTL930X_L3_HW_LU_KEY_CTRL (0xAC9C) +#define RTL930X_L3_HW_LU_KEY_IP_CTRL (0xACA0) +#define RTL930X_L3_HW_LU_CTRL (0xACC0) +#define RTL930X_L3_IP_ROUTE_CTRL 0xab44 + +/* Port LED Control */ +#define RTL930X_LED_PORT_NUM_CTRL(p) (0xCC04 + (((p >> 4) << 2))) +#define RTL930X_LED_SET0_0_CTRL (0xCC28) +#define RTL930X_LED_PORT_COPR_SET_SEL_CTRL(p) (0xCC2C + (((p >> 4) << 2))) +#define RTL930X_LED_PORT_FIB_SET_SEL_CTRL(p) (0xCC34 + (((p >> 4) << 2))) +#define RTL930X_LED_PORT_COPR_MASK_CTRL (0xCC3C) +#define RTL930X_LED_PORT_FIB_MASK_CTRL (0xCC40) +#define RTL930X_LED_PORT_COMBO_MASK_CTRL (0xCC44) + +#define RTL931X_LED_PORT_NUM_CTRL(p) (0x0604 + (((p >> 4) << 2))) +#define RTL931X_LED_SET0_0_CTRL (0x0630) +#define RTL931X_LED_PORT_COPR_SET_SEL_CTRL(p) (0x0634 + (((p >> 4) << 2))) +#define RTL931X_LED_PORT_FIB_SET_SEL_CTRL(p) (0x0644 + (((p >> 4) << 2))) +#define RTL931X_LED_PORT_COPR_MASK_CTRL (0x0654) +#define RTL931X_LED_PORT_FIB_MASK_CTRL (0x065c) +#define RTL931X_LED_PORT_COMBO_MASK_CTRL (0x0664) + +#define RTL931X_LED_GLB_ACTIVE_LOW BIT(21) + +#define RTL931X_LED_SETX_0_CTRL(x) (RTL931X_LED_SET0_0_CTRL - (x * 8)) +#define RTL931X_LED_SETX_1_CTRL(x) (RTL931X_LED_SETX_0_CTRL(x) - 4) + +/* get register for given set and led in the set */ +#define RTL931X_LED_SETX_LEDY(x, y) (RTL931X_LED_SETX_0_CTRL(x) - 4 * (y / 2)) + +/* get shift for given led in any set */ +#define RTL931X_LED_SET_LEDX_SHIFT(x) (16 * (x % 2)) + +#define MAX_VLANS 4096 +#define MAX_LAGS 16 +#define MAX_PRIOS 8 +#define RTL930X_PORT_IGNORE 0x3f +/* ToDo: MAX_MC_GROUPS could be increased + * 838x/839x/930x/931x -> 8192/16384/16384/32768 entries (priv->fib_entries) + * They are shared with unicast entries + */ +#define MAX_MC_GROUPS 512 +/* ToDo: MAX_MC_PMASKS could be increased + * 838x/839x/930x/931x -> 512/4096/1024/4096 entries + */ +#define MAX_MC_PMASKS 512 +#define RTL838X_MC_PMASK_ALL_PORTS (GENMASK(RTL838X_CPU_PORT, 0)) +#define RTL839X_MC_PMASK_ALL_PORTS (GENMASK_ULL(RTL839X_CPU_PORT, 0)) +#define RTL930X_MC_PMASK_ALL_PORTS (GENMASK(RTL930X_CPU_PORT, 0)) +#define RTL931X_MC_PMASK_ALL_PORTS (GENMASK_ULL(RTL931X_CPU_PORT, 0)) +#define MC_PMASK_ALL_PORTS_IDX ((MAX_MC_PMASKS - 1)) +#define PIE_BLOCK_SIZE 128 +#define MAX_PIE_ENTRIES (18 * PIE_BLOCK_SIZE) +#define N_FIXED_FIELDS 12 +#define N_FIXED_FIELDS_RTL931X 14 +#define MAX_COUNTERS 2048 +#define MAX_ROUTES 512 +#define MAX_HOST_ROUTES 1536 +#define MAX_INTF_MTUS 8 +#define DEFAULT_MTU 1536 +#define MAX_INTERFACES 100 +#define MAX_ROUTER_MACS 64 +#define L3_EGRESS_DMACS 2048 +#define MAX_SMACS 64 +#define DSCP_MAP_MAX 64 + +/* This interval needs to be short enough to prevent an undetected counter + * overflow. The octet counters don't need to be considered for this, because + * they are 64 bits on all platforms. Based on the possible packets per second + * at the highest supported speeds, an interval of a minute is probably a safe + * choice for the other counters. + */ +#define RTLDSA_COUNTERS_POLL_INTERVAL (60 * HZ) + +/* Some SoC families require table access to get the HW counters. A mutex is + * required for this access - which will potentially cause a sleep in the + * current context. This is not always possible with .get_stats64 because it + * is also called in atomic contexts. + * + * For these SoCs, the retrieval of the current counters in .get_stats64 is + * skipped and the counters are simply retrieved a lot more often from the HW. + */ +#define RTLDSA_COUNTERS_FAST_POLL_INTERVAL (3 * HZ) + +enum phy_type { + PHY_NONE = 0, + PHY_RTL838X_SDS = 1, + PHY_RTL8218B_INT = 2, + PHY_RTL8218B_EXT = 3, + PHY_RTL8214FC = 4, + PHY_RTL839X_SDS = 5, +}; + +enum pbvlan_type { + PBVLAN_TYPE_INNER = 0, + PBVLAN_TYPE_OUTER, +}; + +enum pbvlan_mode { + PBVLAN_MODE_UNTAG_AND_PRITAG = 0, + PBVLAN_MODE_UNTAG_ONLY, + PBVLAN_MODE_ALL_PKT, +}; + +struct rtldsa_counter { + u64 val; + u32 last; +}; + +struct rtldsa_counter_state { + /** + * @lock: protect updates to members of the structure when the + * priv->counters_lock is not used. (see rtl931x_reg->stat_update_counters_atomically) + */ + spinlock_t lock; + ktime_t last_update; + + struct rtldsa_counter symbol_errors; + + struct rtldsa_counter if_in_octets; + struct rtldsa_counter if_out_octets; + struct rtldsa_counter if_in_ucast_pkts; + struct rtldsa_counter if_in_mcast_pkts; + struct rtldsa_counter if_in_bcast_pkts; + struct rtldsa_counter if_out_ucast_pkts; + struct rtldsa_counter if_out_mcast_pkts; + struct rtldsa_counter if_out_bcast_pkts; + struct rtldsa_counter if_out_discards; + struct rtldsa_counter single_collisions; + struct rtldsa_counter multiple_collisions; + struct rtldsa_counter deferred_transmissions; + struct rtldsa_counter late_collisions; + struct rtldsa_counter excessive_collisions; + struct rtldsa_counter crc_align_errors; + struct rtldsa_counter rx_pkts_over_max_octets; + + struct rtldsa_counter unsupported_opcodes; + + struct rtldsa_counter rx_undersize_pkts; + struct rtldsa_counter rx_oversize_pkts; + struct rtldsa_counter rx_fragments; + struct rtldsa_counter rx_jabbers; + + struct rtldsa_counter tx_pkts[ETHTOOL_RMON_HIST_MAX]; + struct rtldsa_counter rx_pkts[ETHTOOL_RMON_HIST_MAX]; + + struct rtldsa_counter drop_events; + struct rtldsa_counter collisions; + + struct rtldsa_counter rx_pause_frames; + struct rtldsa_counter tx_pause_frames; + + /** @link_stat_lock: Protect link_stat */ + spinlock_t link_stat_lock; + + /** @link_stat: Prepared return data for .get_stats64 which can be accessed without mutex */ + struct rtnl_link_stats64 link_stat; +}; + +struct rtldsa_93xx_lag_entry { + u32 trk_port0:6; + u32 trk_dev0:4; + u32 trk_port1:6; + u32 trk_dev1:4; + u32 trk_port2:6; + u32 trk_dev2:4; + u32 trk_port3:6; + u32 trk_dev3:4; + u32 trk_port4:6; + u32 trk_dev4:4; + u32 trk_port5:6; + u32 trk_dev5:4; + u32 trk_port6:6; + u32 trk_dev6:4; + u32 trk_port7:6; + u32 trk_dev7:4; + u32 sep_kwn_mc_en:1; + union { + // for rtl930x + u32 sep_dlf_bcast_en:1; + // for rtl931x + u32 sep_flood_en:1; + } flood_dlf_bcast; + u32 ip6_hash_mask_idx:1; + u32 ip4_hash_mask_idx:1; + u32 l2_hash_mask_idx:1; + u32 num_tx_candi:4; +}; + +struct rtldsa_port { + bool enable:1; + bool phy_is_integrated:1; + bool isolated:1; + bool rate_police_egress:1; + bool rate_police_ingress:1; + u64 pm; + u16 pvid; + bool eee_enabled; + enum phy_type phy; + struct phylink_pcs *pcs; + int led_set; + int leds_on_this_port; + struct rtldsa_counter_state counters; + const struct dsa_port *dp; +}; + +struct rtl838x_vlan_info { + u64 untagged_ports; + u64 member_ports; + u8 profile_id; + bool hash_mc_fid; + bool hash_uc_fid; + u8 fid; /* AKA MSTI */ + + /* The following fields are used only by the RTL931X */ + int if_id; /* Interface (index in L3_EGR_INTF_IDX) */ + u16 multicast_grp_mask; + int l2_tunnel_list_id; +}; + +struct rtldsa_mst { + /** @msti: MSTI mapped to this slot. 0 == unused */ + u16 msti; + + /** @refcount: number of vlans currently using this msti, undefined when unused */ + struct kref refcount; +}; + +struct rtldsa_vlan_profile { + union { + struct { + u64 l2; + u64 ip; + u64 ip6; + } pmsks; + struct { + u16 l2; + u16 ip; + u16 ip6; + } pmsks_idx; + } unkn_mc_fld; + + int l2_learn; + + u8 pmsk_is_idx:1, routing_ipuc:1, routing_ip6uc:1, + routing_ipmc:1, routing_ip6mc:1, bridge_ipmc:1, bridge_ip6mc:1; +}; + +enum l2_entry_type { + L2_INVALID = 0, + L2_UNICAST = 1, + L2_MULTICAST = 2, + IP4_MULTICAST = 3, + IP6_MULTICAST = 4, +}; + +struct rtl838x_l2_entry { + u8 mac[6]; + u16 vid; + u16 rvid; + u8 port; + enum l2_entry_type type; + bool valid:1; + bool is_static:1; + bool is_ip_mc:1; + bool is_ipv6_mc:1; + bool block_da:1; + bool block_sa:1; + bool suspended:1; + bool next_hop:1; + bool is_trunk:1; + bool nh_vlan_target:1; /* Only RTL83xx: VLAN used for next hop */ + int age; + u8 trunk; + u8 stack_dev; + u16 mc_portmask_index; + u32 mc_gip; + u32 mc_sip; + u16 mc_mac_index; + u16 nh_route_id; + + /* The following is only valid on RTL931x */ + bool is_open_flow:1; + bool is_pe_forward:1; + bool is_local_forward:1; + bool is_remote_forward:1; + bool is_l2_tunnel:1; + bool hash_msb:1; + int l2_tunnel_id; + int l2_tunnel_list_id; +}; + +enum fwd_rule_action { + FWD_RULE_ACTION_NONE = 0, + FWD_RULE_ACTION_FWD = 1, +}; + +enum pie_phase { + PHASE_VACL = 0, + PHASE_IACL = 1, +}; + +enum igr_filter { + IGR_FORWARD = 0, + IGR_DROP = 1, + IGR_TRAP = 2, +}; + +enum egr_filter { + EGR_DISABLE = 0, + EGR_ENABLE = 1, +}; + +/* Intermediate representation of a Packet Inspection Engine Rule + * as suggested by the Kernel's tc flower offload subsystem + * Field meaning is universal across SoC families, but data content is specific + * to SoC family (e.g. because of different port ranges) + */ +struct pie_rule { + int id; + enum pie_phase phase; /* Phase in which this template is applied */ + int packet_cntr; /* ID of a packet counter assigned to this rule */ + int octet_cntr; /* ID of a byte counter assigned to this rule */ + u32 last_packet_cnt; + u64 last_octet_cnt; + + /* The following are requirements for the pie template */ + bool is_egress; + bool is_ipv6; /* This is a rule with IPv6 fields */ + + /* Fixed fields that are always matched against on RTL8380 */ + u8 spmmask_fix; + u8 spn; /* Source port number */ + bool stacking_port; /* Source port is stacking port */ + bool mgnt_vlan; /* Packet arrived on management VLAN */ + bool dmac_hit_sw; /* The packet's destination MAC matches one of the device's */ + bool content_too_deep; /* The content of the packet cannot be parsed: too many layers */ + bool not_first_frag; /* Not the first IP fragment */ + u8 frame_type_l4; /* 0: UDP, 1: TCP, 2: ICMP/ICMPv6, 3: IGMP */ + u8 frame_type; /* 0: ARP, 1: L2 only, 2: IPv4, 3: IPv6 */ + bool otag_fmt; /* 0: outer tag packet, 1: outer priority tag or untagged */ + bool itag_fmt; /* 0: inner tag packet, 1: inner priority tag or untagged */ + bool otag_exist; /* packet with outer tag */ + bool itag_exist; /* packet with inner tag */ + bool frame_type_l2; /* 0: Ethernet, 1: LLC_SNAP, 2: LLC_Other, 3: Reserved */ + bool igr_normal_port; /* Ingress port is not cpu or stacking port */ + u8 tid; /* The template ID defining the what the templated fields mean */ + + /* Masks for the fields that are always matched against on RTL8380 */ + u8 spmmask_fix_m; + u8 spn_m; + bool stacking_port_m; + bool mgnt_vlan_m; + bool dmac_hit_sw_m; + bool content_too_deep_m; + bool not_first_frag_m; + u8 frame_type_l4_m; + u8 frame_type_m; + bool otag_fmt_m; + bool itag_fmt_m; + bool otag_exist_m; + bool itag_exist_m; + bool frame_type_l2_m; + bool igr_normal_port_m; + u8 tid_m; + + /* Logical operations between rules, special rules for rule numbers apply */ + bool valid; + bool cond_not; /* Matches when conditions not match */ + bool cond_and1; /* And this rule 2n with the next rule 2n+1 in same block */ + bool cond_and2; /* And this rule m in block 2n with rule m in block 2n+1 */ + bool ivalid; + + /* Actions to be performed */ + bool drop; /* Drop the packet */ + bool fwd_sel; /* Forward packet: to port, portmask, dest route, next rule, drop */ + bool ovid_sel; /* So something to outer vlan-id: shift, re-assign */ + bool ivid_sel; /* Do something to inner vlan-id: shift, re-assign */ + bool flt_sel; /* Filter the packet when sending to certain ports */ + bool log_sel; /* Log the packet in one of the LOG-table counters */ + bool rmk_sel; /* Re-mark the packet, i.e. change the priority-tag */ + bool meter_sel; /* Meter the packet, i.e. limit rate of this type of packet */ + bool tagst_sel; /* Change the ergress tag */ + bool mir_sel; /* Mirror the packet to a Link Aggregation Group */ + bool nopri_sel; /* Change the normal priority */ + bool cpupri_sel; /* Change the CPU priority */ + bool otpid_sel; /* Change Outer Tag Protocol Identifier (802.1q) */ + bool itpid_sel; /* Change Inner Tag Protocol Identifier (802.1q) */ + bool shaper_sel; /* Apply traffic shaper */ + bool mpls_sel; /* MPLS actions */ + bool bypass_sel; /* Bypass actions */ + bool fwd_sa_lrn; /* Learn the source address when forwarding */ + bool fwd_mod_to_cpu; /* Forward the modified VLAN tag format to CPU-port */ + + /* Fields used in predefined templates 0-2 on RTL8380 / 90 / 9300 */ + u64 spm; /* Source Port Matrix */ + u16 otag; /* Outer VLAN-ID */ + u8 smac[ETH_ALEN]; /* Source MAC address */ + u8 dmac[ETH_ALEN]; /* Destination MAC address */ + u16 ethertype; /* Ethernet frame type field in ethernet header */ + u16 itag; /* Inner VLAN-ID */ + u16 field_range_check; + u32 sip; /* Source IP */ + struct in6_addr sip6; /* IPv6 Source IP */ + u32 dip; /* Destination IP */ + struct in6_addr dip6; /* IPv6 Destination IP */ + u16 tos_proto; /* IPv4: TOS + Protocol fields, IPv6: Traffic class + next header */ + u16 sport; /* TCP/UDP source port */ + u16 dport; /* TCP/UDP destination port */ + u16 icmp_igmp; + u16 tcp_info; + u16 dsap_ssap; /* Destination / Source Service Access Point bytes (802.3) */ + + u64 spm_m; + u16 otag_m; + u8 smac_m[ETH_ALEN]; + u8 dmac_m[ETH_ALEN]; + u8 ethertype_m; + u16 itag_m; + u16 field_range_check_m; + u32 sip_m; + struct in6_addr sip6_m; /* IPv6 Source IP mask */ + u32 dip_m; + struct in6_addr dip6_m; /* IPv6 Destination IP mask */ + u16 tos_proto_m; + u16 sport_m; + u16 dport_m; + u16 icmp_igmp_m; + u16 tcp_info_m; + u16 dsap_ssap_m; + + /* Data associated with actions */ + u8 fwd_act; /* Type of forwarding action */ + /* 0: permit, 1: drop, 2: copy to port id, 4: copy to portmask */ + /* 4: redirect to portid, 5: redirect to portmask */ + /* 6: route, 7: vlan leaky (only 8380) */ + u16 fwd_data; /* Additional data for forwarding action, e.g. destination port */ + u8 ovid_act; + u16 ovid_data; /* Outer VLAN ID */ + u8 ivid_act; + u16 ivid_data; /* Inner VLAN ID */ + u16 flt_data; /* Filtering data */ + u16 log_data; /* ID of packet or octet counter in LOG table, on RTL93xx */ + /* unnecessary since PIE-Rule-ID == LOG-counter-ID */ + bool log_octets; + u8 mpls_act; /* MPLS action type */ + u16 mpls_lib_idx; /* MPLS action data */ + + u16 rmk_data; /* Data for remarking */ + u16 meter_data; /* ID of meter for bandwidth control */ + u16 tagst_data; + u16 mir_data; + u16 nopri_data; + u16 cpupri_data; + u16 otpid_data; + u16 itpid_data; + u16 shaper_data; + + /* Bypass actions, ignored on RTL8380 */ + bool bypass_all; /* Not clear */ + bool bypass_igr_stp; /* Bypass Ingress STP state */ + bool bypass_ibc_sc; /* Bypass Ingress Bandwidth Control and Storm Control */ +}; + +struct rtl838x_l3_intf { + u16 vid; + u8 smac_idx; + u8 ip4_mtu_id; + u8 ip6_mtu_id; + u16 ip4_mtu; + u16 ip6_mtu; + u8 ttl_scope; + u8 hl_scope; + u8 ip4_icmp_redirect; + u8 ip6_icmp_redirect; + u8 ip4_pbr_icmp_redirect; + u8 ip6_pbr_icmp_redirect; +}; + +/* An entry in the RTL93XX SoC's ROUTER_MAC tables setting up a termination point + * for the L3 routing system. Packets arriving and matching an entry in this table + * will be considered for routing. + * Mask fields state whether the corresponding data fields matter for matching + */ +struct rtl93xx_rt_mac { + bool valid; /* Valid or not */ + bool p_type; /* Individual (0) or trunk (1) port */ + bool p_mask; /* Whether the port type is used */ + u8 p_id; + u8 p_id_mask; /* Mask for the port */ + u8 action; /* Routing action performed: 0: FORWARD, 1: DROP, 2: TRAP2CPU */ + /* 3: COPY2CPU, 4: TRAP2MASTERCPU, 5: COPY2MASTERCPU, 6: HARDDROP */ + u16 vid; + u16 vid_mask; + u64 mac; /* MAC address used as source MAC in the routed packet */ + u64 mac_mask; +}; + +struct rtl83xx_nexthop { + u16 id; /* ID: L3_NEXT_HOP table-index or route-index set in L2_NEXT_HOP */ + u32 dev_id; + u16 port; + u16 vid; /* VLAN-ID for L2 table entry (saved from L2-UC entry) */ + u16 rvid; /* Relay VID/FID for the L2 table entry */ + u64 mac; /* The MAC address of the entry in the L2_NEXT_HOP table */ + u16 mac_id; + u16 l2_id; /* Index of this next hop forwarding entry in L2 FIB table */ + u64 gw; /* The gateway MAC address packets are forwarded to */ + int if_id; /* Interface (into L3_EGR_INTF_IDX) */ +}; + +struct rtl838x_switch_priv; + +struct rtl83xx_flow { + unsigned long cookie; + struct rhash_head node; + struct rcu_head rcu_head; + struct rtl838x_switch_priv *priv; + struct pie_rule rule; + u32 flags; +}; + +struct rtl93xx_route_attr { + bool valid; + bool hit; + bool ttl_dec; + bool ttl_check; + bool dst_null; + bool qos_as; + u8 qos_prio; + u8 type; + u8 action; +}; + +struct rtl83xx_route { + u32 gw_ip; /* IP of the route's gateway */ + u32 dst_ip; /* IP of the destination net */ + struct in6_addr dst_ip6; + int prefix_len; /* Network prefix len of the destination net */ + bool is_host_route; + int id; /* ID number of this route */ + struct rhlist_head linkage; + u16 switch_mac_id; /* Index into switch's own MACs, RTL839X only */ + struct rtl83xx_nexthop nh; + struct pie_rule pr; + struct rtl93xx_route_attr attr; +}; + +/** + * struct rtldsa_mirror_config - Mirror configuration for specific group and port + */ +struct rtldsa_mirror_config { + /** @ctrl: control register for mirroring group */ + int ctrl; + + /** @spm: register for the destination port members */ + int spm; + + /** @dpm: register for the source port members */ + int dpm; + + /** @val: @ctrl register settings to enable mirroring */ + u32 val; +}; + +struct rtldsa_config { + void (*mask_port_reg_be)(u64 clear, u64 set, int reg); + void (*set_port_reg_be)(u64 set, int reg); + u64 (*get_port_reg_be)(int reg); + void (*mask_port_reg_le)(u64 clear, u64 set, int reg); + void (*set_port_reg_le)(u64 set, int reg); + u64 (*get_port_reg_le)(int reg); + int stat_port_rst; + int stat_rst; + int stat_port_std_mib; + int stat_port_prv_mib; + const struct rtldsa_mib_desc *mib_desc; + u64 (*stat_port_table_read)(int port, unsigned int mib_size, unsigned int offset, bool is_pvt); + void (*stat_counters_lock)(struct rtl838x_switch_priv *priv, int port); + void (*stat_counters_unlock)(struct rtl838x_switch_priv *priv, int port); + + /** + * @stat_update_counters_atomically: When set, the SoC family allows atomically retrieving + * of statistic counters using this function. This function must not require "might_sleep" + * code. + * + * Any SoC family which requires stat_port_table_read must use the table + * rtldsa_counters_(un)lock_table helpers. They are using a mutex for locking. The counters + * update is therefore not atomic. + */ + void (*stat_update_counters_atomically)(struct rtl838x_switch_priv *priv, int port); + unsigned long stat_counter_poll_interval; + int (*port_iso_ctrl)(int p); + void (*traffic_enable)(int source, int dest); + void (*traffic_disable)(int source, int dest); + void (*traffic_set)(int source, u64 dest_matrix); + int l2_ctrl_0; + int l2_ctrl_1; + int smi_poll_ctrl; + u32 l2_port_aging_out; + int l2_tbl_flush_ctrl; + void (*exec_tbl0_cmd)(u32 cmd); + void (*exec_tbl1_cmd)(u32 cmd); + int (*tbl_access_data_0)(int i); + int isr_glb_src; + int isr_port_link_sts_chg; + int imr_port_link_sts_chg; + int imr_glb; + int n_counters; + int n_pie_blocks; + u8 port_ignore; + int trk_ctrl; + int trk_hash_ctrl; + void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info); + void (*vlan_set_tagged)(u32 vlan, struct rtl838x_vlan_info *info); + void (*vlan_set_untagged)(u32 vlan, u64 portmask); + int (*vlan_profile_get)(int index, struct rtldsa_vlan_profile *profile); + void (*vlan_profile_dump)(struct rtl838x_switch_priv *priv, int index); + void (*vlan_profile_setup)(int profile); + void (*vlan_port_pvidmode_set)(int port, enum pbvlan_type type, enum pbvlan_mode mode); + void (*vlan_port_pvid_set)(int port, enum pbvlan_type type, int pvid); + void (*vlan_port_keep_tag_set)(int port, bool keep_outer, bool keep_inner); + int (*fast_age)(struct rtl838x_switch_priv *priv, int port, int vid); + void (*set_vlan_igr_filter)(int port, enum igr_filter state); + void (*set_vlan_egr_filter)(int port, enum egr_filter state); + void (*enable_learning)(int port, bool enable); + void (*enable_flood)(int port, bool enable); + void (*enable_mcast_flood)(int port, bool enable); + void (*enable_bcast_flood)(int port, bool enable); + void (*set_static_move_action)(int port, bool forward); + int (*stp_get)(struct rtl838x_switch_priv *priv, u16 msti, int port, u32 port_state[]); + void (*stp_set)(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]); + int mac_link_sts; + int (*mac_force_mode_ctrl)(int port); + int (*mac_port_ctrl)(int port); + int (*l2_port_new_salrn)(int port); + int (*l2_port_new_sa_fwd)(int port); + int (*set_ageing_time)(unsigned long msec); + int (*get_mirror_config)(struct rtldsa_mirror_config *config, int group, int port); + int (*port_rate_police_add)(struct dsa_switch *ds, int port, + const struct flow_action_entry *act, bool ingress); + int (*port_rate_police_del)(struct dsa_switch *ds, int port, struct flow_cls_offload *cls, + bool ingress); + void (*print_matrix)(void); + u64 (*read_l2_entry_using_hash)(u32 hash, u32 position, struct rtl838x_l2_entry *e); + void (*write_l2_entry_using_hash)(u32 hash, u32 pos, struct rtl838x_l2_entry *e); + u64 (*read_cam)(int idx, struct rtl838x_l2_entry *e); + void (*write_cam)(int idx, struct rtl838x_l2_entry *e); + int rma_bpdu_fld_pmask; + int spcl_trap_eapol_ctrl; + void (*init_eee)(struct rtl838x_switch_priv *priv, bool enable); + void (*set_mac_eee)(struct rtl838x_switch_priv *priv, int port, bool enable); + u64 (*l2_hash_seed)(u64 mac, u32 vid); + u32 (*l2_hash_key)(struct rtl838x_switch_priv *priv, u64 seed); + u64 (*read_mcast_pmask)(int idx); + void (*write_mcast_pmask)(int idx, u64 portmask); + void (*vlan_fwd_on_inner)(int port, bool is_set); + void (*pie_init)(struct rtl838x_switch_priv *priv); + int (*pie_rule_read)(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr); + int (*pie_rule_write)(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr); + int (*pie_rule_add)(struct rtl838x_switch_priv *priv, struct pie_rule *rule); + void (*pie_rule_rm)(struct rtl838x_switch_priv *priv, struct pie_rule *rule); + void (*l2_learning_setup)(void); + u32 (*packet_cntr_read)(int counter); + void (*packet_cntr_clear)(int counter); + void (*route_read)(int idx, struct rtl83xx_route *rt); + void (*route_write)(int idx, struct rtl83xx_route *rt); + void (*host_route_write)(int idx, struct rtl83xx_route *rt); + int (*l3_setup)(struct rtl838x_switch_priv *priv); + void (*set_l3_nexthop)(int idx, u16 dmac_id, u16 interface); + void (*get_l3_nexthop)(int idx, u16 *dmac_id, u16 *interface); + u64 (*get_l3_egress_mac)(u32 idx); + void (*set_l3_egress_mac)(u32 idx, u64 mac); + int (*find_l3_slot)(struct rtl83xx_route *rt, bool must_exist); + int (*route_lookup_hw)(struct rtl83xx_route *rt); + void (*get_l3_router_mac)(u32 idx, struct rtl93xx_rt_mac *m); + void (*set_l3_router_mac)(u32 idx, struct rtl93xx_rt_mac *m); + void (*set_l3_egress_intf)(int idx, struct rtl838x_l3_intf *intf); + void (*set_receive_management_action)(int port, rma_ctrl_t type, action_type_t action); + void (*led_init)(struct rtl838x_switch_priv *priv); + void (*qos_init)(struct rtl838x_switch_priv *priv); + int (*trk_mbr_ctr)(int group); + void (*lag_switch_init)(struct rtl838x_switch_priv *priv); + void (*prepare_lag_fdb)(struct rtl838x_l2_entry *e, int lag_group); + int (*lag_set_port_members)(struct rtl838x_switch_priv *priv, int group, u64 members, + struct netdev_lag_upper_info *info); + int (*lag_setup_algomask)(struct rtl838x_switch_priv *priv, int group, + struct netdev_lag_upper_info *info); + int (*lag_set_distribution_algorithm)(struct rtl838x_switch_priv *priv, + int group, int algoidx, + u32 algomask); + void (*lag_set_local_group_id)(int local_group, int global_group, bool valid); + void (*lag_write_data)(u32 data[], struct rtldsa_93xx_lag_entry *e); + void (*lag_fill_data)(u32 data[], struct rtldsa_93xx_lag_entry *e); + void (*lag_set_local_port2group)(int group, int port, bool valid); + void (*lag_set_port2group)(int group, int port, bool valid); + struct table_reg* (*lag_table)(void); + void (*lag_sync_tables)(void); +}; + +struct rtl838x_switch_priv { + /* Switch operation */ + struct dsa_switch *ds; + struct device *dev; + u16 id; + u16 family_id; + struct rtldsa_port ports[57]; + struct mutex reg_mutex; /* Mutex for individual register manipulations */ + struct mutex pie_mutex; /* Mutex for Packet Inspection Engine */ + int link_state_irq; + int mirror_group_ports[4]; + struct mii_bus *parent_bus; + const struct rtldsa_config *r; + u8 cpu_port; + u8 port_mask; + u8 port_width; + u64 irq_mask; + u32 fib_entries; + int l2_bucket_size; + u16 n_mst; + struct dentry *dbgfs_dir; + + /** @lags_port_members: Port (bit) is part of a specific LAG */ + u64 lags_port_members[MAX_LAGS]; + + /** @lag_primary: port of a LAG is primary (repesenting) and is added to + * the port matrix + */ + u32 lag_primary[MAX_LAGS]; + + /** + * @lag_non_primary: Port (bit) is part of any LAG but not the + * first/primary port which needs to be added in the port matrix + */ + u64 lag_non_primary; + + /** @lagmembers: Port (bit) is part of any LAG */ + u64 lagmembers; + struct workqueue_struct *wq; + struct notifier_block ne_nb; + struct notifier_block fib_nb; + bool eee_enabled; + unsigned long mc_group_bm[MAX_MC_GROUPS >> 5]; + struct rhashtable tc_ht; + unsigned long pie_use_bm[MAX_PIE_ENTRIES >> 5]; + unsigned long octet_cntr_use_bm[MAX_COUNTERS >> 5]; + unsigned long packet_cntr_use_bm[MAX_COUNTERS >> 4]; + struct rhltable routes; + unsigned long route_use_bm[MAX_ROUTES >> 5]; + unsigned long host_route_use_bm[MAX_HOST_ROUTES >> 5]; + struct rtl838x_l3_intf *interfaces[MAX_INTERFACES]; + u16 intf_mtus[MAX_INTF_MTUS]; + int intf_mtu_count[MAX_INTF_MTUS]; + + /** + * @msts: MSTI to HW MST slot allocations. index 0 is for HW slot 1 because CIST is + * not stored in @msts + */ + struct rtldsa_mst *msts; + struct delayed_work counters_work; + + /** + * @counters_lock: Protects the hardware reads happening from MIB + * callbacks and the workqueue which reads the data + * periodically. + */ + struct mutex counters_lock; +}; + +void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv); +void rtl930x_dbgfs_init(struct rtl838x_switch_priv *priv); +void rtldsa_93xx_lag_switch_init(struct rtl838x_switch_priv *priv); +int rtldsa_93xx_lag_set_distribution_algorithm(struct rtl838x_switch_priv *priv, + int group, int algoidx, u32 algomsk); +int rtldsa_93xx_lag_set_port_members(struct rtl838x_switch_priv *priv, int group, + u64 members, struct netdev_lag_upper_info *info); + +void rtldsa_93xx_prepare_lag_fdb(struct rtl838x_l2_entry *e, int lag_group); + +void rtldsa_counters_lock_register(struct rtl838x_switch_priv *priv, int port) + __acquires(&priv->ports[port].counters.lock); +void rtldsa_counters_unlock_register(struct rtl838x_switch_priv *priv, int port) + __releases(&priv->ports[port].counters.lock); +void rtldsa_counters_lock_table(struct rtl838x_switch_priv *priv, int port) + __acquires(&priv->counters_lock); +void rtldsa_counters_unlock_table(struct rtl838x_switch_priv *priv, int port) + __releases(&priv->ports[port].counters.lock); + +void rtldsa_update_counters_atomically(struct rtl838x_switch_priv *priv, int port); + +extern int rtldsa_max_available_queue[]; +extern int rtldsa_default_queue_weights[]; + +#endif /* _RTL838X_H */ diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c new file mode 100644 index 0000000000..3fab93ac69 --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c @@ -0,0 +1,1815 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include + +#include "rtl83xx.h" + +#define RTL839X_VLAN_PORT_TAG_STS_UNTAG 0x0 +#define RTL839X_VLAN_PORT_TAG_STS_TAGGED 0x1 +#define RTL839X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x2 + +#define RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE 0x6828 +/* port 0-52 */ +#define RTL839X_VLAN_PORT_TAG_STS_CTRL(port) \ + (RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)) +#define RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK GENMASK(7, 6) +#define RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK GENMASK(5, 4) +#define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(3, 3) +#define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(2, 2) +#define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(1, 1) +#define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(0, 0) + +/* Definition of the RTL839X-specific template field IDs as used in the PIE */ +enum template_field_id { + TEMPLATE_FIELD_SPMMASK = 0, + TEMPLATE_FIELD_SPM0 = 1, /* Source portmask ports 0-15 */ + TEMPLATE_FIELD_SPM1 = 2, /* Source portmask ports 16-31 */ + TEMPLATE_FIELD_SPM2 = 3, /* Source portmask ports 32-47 */ + TEMPLATE_FIELD_SPM3 = 4, /* Source portmask ports 48-56 */ + TEMPLATE_FIELD_DMAC0 = 5, /* Destination MAC [15:0] */ + TEMPLATE_FIELD_DMAC1 = 6, /* Destination MAC [31:16] */ + TEMPLATE_FIELD_DMAC2 = 7, /* Destination MAC [47:32] */ + TEMPLATE_FIELD_SMAC0 = 8, /* Source MAC [15:0] */ + TEMPLATE_FIELD_SMAC1 = 9, /* Source MAC [31:16] */ + TEMPLATE_FIELD_SMAC2 = 10, /* Source MAC [47:32] */ + TEMPLATE_FIELD_ETHERTYPE = 11, /* Ethernet frame type field */ + /* Field-ID 12 is not used */ + TEMPLATE_FIELD_OTAG = 13, + TEMPLATE_FIELD_ITAG = 14, + TEMPLATE_FIELD_SIP0 = 15, + TEMPLATE_FIELD_SIP1 = 16, + TEMPLATE_FIELD_DIP0 = 17, + TEMPLATE_FIELD_DIP1 = 18, + TEMPLATE_FIELD_IP_TOS_PROTO = 19, + TEMPLATE_FIELD_IP_FLAG = 20, + TEMPLATE_FIELD_L4_SPORT = 21, + TEMPLATE_FIELD_L4_DPORT = 22, + TEMPLATE_FIELD_L34_HEADER = 23, + TEMPLATE_FIELD_ICMP_IGMP = 24, + TEMPLATE_FIELD_VID_RANG0 = 25, + TEMPLATE_FIELD_VID_RANG1 = 26, + TEMPLATE_FIELD_L4_PORT_RANG = 27, + TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 28, + TEMPLATE_FIELD_FIELD_SELECTOR_0 = 29, + TEMPLATE_FIELD_FIELD_SELECTOR_1 = 30, + TEMPLATE_FIELD_FIELD_SELECTOR_2 = 31, + TEMPLATE_FIELD_FIELD_SELECTOR_3 = 32, + TEMPLATE_FIELD_FIELD_SELECTOR_4 = 33, + TEMPLATE_FIELD_FIELD_SELECTOR_5 = 34, + TEMPLATE_FIELD_SIP2 = 35, + TEMPLATE_FIELD_SIP3 = 36, + TEMPLATE_FIELD_SIP4 = 37, + TEMPLATE_FIELD_SIP5 = 38, + TEMPLATE_FIELD_SIP6 = 39, + TEMPLATE_FIELD_SIP7 = 40, + TEMPLATE_FIELD_OLABEL = 41, + TEMPLATE_FIELD_ILABEL = 42, + TEMPLATE_FIELD_OILABEL = 43, + TEMPLATE_FIELD_DPMMASK = 44, + TEMPLATE_FIELD_DPM0 = 45, + TEMPLATE_FIELD_DPM1 = 46, + TEMPLATE_FIELD_DPM2 = 47, + TEMPLATE_FIELD_DPM3 = 48, + TEMPLATE_FIELD_L2DPM0 = 49, + TEMPLATE_FIELD_L2DPM1 = 50, + TEMPLATE_FIELD_L2DPM2 = 51, + TEMPLATE_FIELD_L2DPM3 = 52, + TEMPLATE_FIELD_IVLAN = 53, + TEMPLATE_FIELD_OVLAN = 54, + TEMPLATE_FIELD_FWD_VID = 55, + TEMPLATE_FIELD_DIP2 = 56, + TEMPLATE_FIELD_DIP3 = 57, + TEMPLATE_FIELD_DIP4 = 58, + TEMPLATE_FIELD_DIP5 = 59, + TEMPLATE_FIELD_DIP6 = 60, + TEMPLATE_FIELD_DIP7 = 61, +}; + +/* Number of fixed templates predefined in the SoC */ +#define N_FIXED_TEMPLATES 5 +static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = { + { + TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_ITAG, + TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2, + TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, + TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3 + }, { + TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, + TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT, + TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_SPM0, + TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3 + }, { + TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, + TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO, + TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0, + TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1 + }, { + TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2, + TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5, + TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT, + TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO + }, { + TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2, + TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5, + TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_SPM0, + TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3 + }, +}; + +const struct rtldsa_mib_list_item rtldsa_839x_mib_list[] = { + MIB_LIST_ITEM("ifOutDiscards", MIB_ITEM(MIB_REG_STD, 0xd4, 1)), + MIB_LIST_ITEM("dot1dTpPortInDiscards", MIB_ITEM(MIB_REG_STD, 0xd0, 1)), + MIB_LIST_ITEM("DropEvents", MIB_ITEM(MIB_REG_STD, 0xa8, 1)), + MIB_LIST_ITEM("tx_BroadcastPkts", MIB_ITEM(MIB_REG_STD, 0xa4, 1)), + MIB_LIST_ITEM("tx_MulticastPkts", MIB_ITEM(MIB_REG_STD, 0xa0, 1)), + MIB_LIST_ITEM("tx_UndersizePkts", MIB_ITEM(MIB_REG_STD, 0x98, 1)), + MIB_LIST_ITEM("rx_UndersizeDropPkts", MIB_ITEM(MIB_REG_STD, 0x90, 1)), + MIB_LIST_ITEM("tx_OversizePkts", MIB_ITEM(MIB_REG_STD, 0x8c, 1)), + MIB_LIST_ITEM("Collisions", MIB_ITEM(MIB_REG_STD, 0x7c, 1)), + MIB_LIST_ITEM("rx_LengthFieldError", MIB_ITEM(MIB_REG_STD, 0x40, 1)), + MIB_LIST_ITEM("rx_FalseCarrierTimes", MIB_ITEM(MIB_REG_STD, 0x3c, 1)), + MIB_LIST_ITEM("rx_UnderSizeOctets", MIB_ITEM(MIB_REG_STD, 0x38, 1)), + MIB_LIST_ITEM("tx_Fragments", MIB_ITEM(MIB_REG_STD, 0x34, 1)), + MIB_LIST_ITEM("tx_Jabbers", MIB_ITEM(MIB_REG_STD, 0x30, 1)), + MIB_LIST_ITEM("tx_CRCAlignErrors", MIB_ITEM(MIB_REG_STD, 0x2c, 1)), + MIB_LIST_ITEM("rx_FramingErrors", MIB_ITEM(MIB_REG_STD, 0x28, 1)), + MIB_LIST_ITEM("rx_MacDiscards", MIB_ITEM(MIB_REG_STD, 0x24, 1)) +}; + +const struct rtldsa_mib_desc rtldsa_839x_mib_desc = { + .symbol_errors = MIB_ITEM(MIB_REG_STD, 0xb8, 1), + + .if_in_octets = MIB_ITEM(MIB_REG_STD, 0xf8, 2), + .if_out_octets = MIB_ITEM(MIB_REG_STD, 0xf0, 2), + .if_in_ucast_pkts = MIB_ITEM(MIB_REG_STD, 0xec, 1), + .if_in_mcast_pkts = MIB_ITEM(MIB_REG_STD, 0xe8, 1), + .if_in_bcast_pkts = MIB_ITEM(MIB_REG_STD, 0xe4, 1), + .if_out_ucast_pkts = MIB_ITEM(MIB_REG_STD, 0xe0, 1), + .if_out_mcast_pkts = MIB_ITEM(MIB_REG_STD, 0xdc, 1), + .if_out_bcast_pkts = MIB_ITEM(MIB_REG_STD, 0xd8, 1), + .if_out_discards = MIB_ITEM(MIB_REG_STD, 0xd4, 1), + .single_collisions = MIB_ITEM(MIB_REG_STD, 0xcc, 1), + .multiple_collisions = MIB_ITEM(MIB_REG_STD, 0xc8, 1), + .deferred_transmissions = MIB_ITEM(MIB_REG_STD, 0xc4, 1), + .late_collisions = MIB_ITEM(MIB_REG_STD, 0xc0, 1), + .excessive_collisions = MIB_ITEM(MIB_REG_STD, 0xbc, 1), + .crc_align_errors = MIB_ITEM(MIB_REG_STD, 0x9c, 1), + + .unsupported_opcodes = MIB_ITEM(MIB_REG_STD, 0xb4, 1), + + .rx_undersize_pkts = MIB_ITEM(MIB_REG_STD, 0x94, 1), + .rx_oversize_pkts = MIB_ITEM(MIB_REG_STD, 0x88, 1), + .rx_fragments = MIB_ITEM(MIB_REG_STD, 0x84, 1), + .rx_jabbers = MIB_ITEM(MIB_REG_STD, 0x80, 1), + + .tx_pkts = { + MIB_ITEM(MIB_REG_STD, 0x78, 1), + MIB_ITEM(MIB_REG_STD, 0x70, 1), + MIB_ITEM(MIB_REG_STD, 0x68, 1), + MIB_ITEM(MIB_REG_STD, 0x60, 1), + MIB_ITEM(MIB_REG_STD, 0x58, 1), + MIB_ITEM(MIB_REG_STD, 0x50, 1), + MIB_ITEM(MIB_REG_STD, 0x48, 1) + }, + .rx_pkts = { + MIB_ITEM(MIB_REG_STD, 0x74, 1), + MIB_ITEM(MIB_REG_STD, 0x6c, 1), + MIB_ITEM(MIB_REG_STD, 0x64, 1), + MIB_ITEM(MIB_REG_STD, 0x5c, 1), + MIB_ITEM(MIB_REG_STD, 0x54, 1), + MIB_ITEM(MIB_REG_STD, 0x4c, 1), + MIB_ITEM(MIB_REG_STD, 0x44, 1) + }, + .rmon_ranges = { + { 0, 64 }, + { 65, 127 }, + { 128, 255 }, + { 256, 511 }, + { 512, 1023 }, + { 1024, 1518 }, + { 1519, 12288 } + }, + + .drop_events = MIB_ITEM(MIB_REG_STD, 0xa8, 1), + .collisions = MIB_ITEM(MIB_REG_STD, 0x7c, 1), + + .rx_pause_frames = MIB_ITEM(MIB_REG_STD, 0xb0, 1), + .tx_pause_frames = MIB_ITEM(MIB_REG_STD, 0xac, 1), + + .list_count = ARRAY_SIZE(rtldsa_839x_mib_list), + .list = rtldsa_839x_mib_list +}; + +void rtldsa_839x_print_matrix(void) +{ + volatile u64 *ptr9; + + ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0); + for (int i = 0; i < 52; i += 4) + pr_debug("> %16llx %16llx %16llx %16llx\n", + ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]); + pr_debug("CPU_PORT> %16llx\n", ptr9[52]); +} + +static inline int rtl839x_port_iso_ctrl(int p) +{ + return RTL839X_PORT_ISO_CTRL(p); +} + +static inline void rtl839x_exec_tbl0_cmd(u32 cmd) +{ + sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0); + do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16)); +} + +static inline void rtl839x_exec_tbl1_cmd(u32 cmd) +{ + sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1); + do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16)); +} + +inline void rtl839x_exec_tbl2_cmd(u32 cmd) +{ + sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_2); + do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2) & (1 << 9)); +} + +static inline int rtl839x_tbl_access_data_0(int i) +{ + return RTL839X_TBL_ACCESS_DATA_0(i); +} + +static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 u, v, w; + /* Read VLAN table (0) via register 0 */ + struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0); + + rtl_table_read(r, vlan); + u = sw_r32(rtl_table_data(r, 0)); + v = sw_r32(rtl_table_data(r, 1)); + w = sw_r32(rtl_table_data(r, 2)); + rtl_table_release(r); + + info->member_ports = u; + info->member_ports = (info->member_ports << 21) | ((v >> 11) & 0x1fffff); + info->profile_id = w >> 30 | ((v & 1) << 2); + info->hash_mc_fid = !!(w & BIT(2)); + info->hash_uc_fid = !!(w & BIT(3)); + info->fid = (v >> 3) & 0xff; + + /* Read UNTAG table (0) via table register 1 */ + r = rtl_table_get(RTL8390_TBL_1, 0); + rtl_table_read(r, vlan); + u = sw_r32(rtl_table_data(r, 0)); + v = sw_r32(rtl_table_data(r, 1)); + rtl_table_release(r); + + info->untagged_ports = u; + info->untagged_ports = (info->untagged_ports << 21) | ((v >> 11) & 0x1fffff); +} + +static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 u, v, w; + /* Access VLAN table (0) via register 0 */ + struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0); + + u = info->member_ports >> 21; + v = info->member_ports << 11; + v |= ((u32)info->fid) << 3; + v |= info->hash_uc_fid ? BIT(2) : 0; + v |= info->hash_mc_fid ? BIT(1) : 0; + v |= (info->profile_id & 0x4) ? 1 : 0; + w = ((u32)(info->profile_id & 3)) << 30; + + sw_w32(u, rtl_table_data(r, 0)); + sw_w32(v, rtl_table_data(r, 1)); + sw_w32(w, rtl_table_data(r, 2)); + + rtl_table_write(r, vlan); + rtl_table_release(r); +} + +static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask) +{ + u32 u, v; + + /* Access UNTAG table (0) via table register 1 */ + struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 0); + + u = portmask >> 21; + v = portmask << 11; + + sw_w32(u, rtl_table_data(r, 0)); + sw_w32(v, rtl_table_data(r, 1)); + rtl_table_write(r, vlan); + + rtl_table_release(r); +} + +/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer */ +static void rtl839x_vlan_fwd_on_inner(int port, bool is_set) +{ + if (is_set) + rtl839x_mask_port_reg_be(BIT_ULL(port), 0ULL, RTL839X_VLAN_PORT_FWD); + else + rtl839x_mask_port_reg_be(0ULL, BIT_ULL(port), RTL839X_VLAN_PORT_FWD); +} + +/* Hash seed is vid (actually rvid) concatenated with the MAC address */ +static u64 rtl839x_l2_hash_seed(u64 mac, u32 vid) +{ + u64 v = vid; + + v <<= 48; + v |= mac; + + return v; +} + +/* Applies the same hash algorithm as the one used currently by the ASIC to the seed + * and returns a key into the L2 hash table + */ +static u32 rtl839x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) +{ + u32 h1, h2, h; + + if (sw_r32(priv->r->l2_ctrl_0) & 1) { + h1 = (u32)(((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f) ^ + ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f) ^ + ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f)); + h2 = (u32)(((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f) ^ + ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f) ^ + (seed & 0x3f)); + h = (h1 << 6) | h2; + } else { + h = (seed >> 60) ^ + ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f)) ^ + ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff) ^ + ((seed >> 12) & 0xfff) ^ (seed & 0xfff); + } + + return h; +} + +static inline int rtl839x_mac_force_mode_ctrl(int p) +{ + return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +static inline int rtl839x_mac_port_ctrl(int p) +{ + return RTL839X_MAC_PORT_CTRL(p); +} + +static inline int rtl839x_l2_port_new_salrn(int p) +{ + return RTL839X_L2_PORT_NEW_SALRN(p); +} + +static inline int rtl839x_l2_port_new_sa_fwd(int p) +{ + return RTL839X_L2_PORT_NEW_SA_FWD(p); +} + +static int rtldsa_839x_get_mirror_config(struct rtldsa_mirror_config *config, + int group, int port) +{ + config->ctrl = RTL839X_MIR_CTRL + group * 4; + config->spm = RTL839X_MIR_SPM_CTRL + group * 8; + config->dpm = RTL839X_MIR_DPM_CTRL + group * 8; + + /* Enable mirroring to destination port */ + config->val = BIT(0); + config->val |= port << 4; + + return 0; +} + +static inline int rtl839x_trk_mbr_ctr(int group) +{ + return RTL839X_TRK_MBR_CTR + (group << 3); +} + +static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) +{ + /* Table contains different entry types, we need to identify the right one: + * Check for MC entries, first + */ + e->is_ip_mc = !!(r[2] & BIT(31)); + e->is_ipv6_mc = !!(r[2] & BIT(30)); + e->type = L2_INVALID; + if (!e->is_ip_mc && !e->is_ipv6_mc) { + e->mac[0] = (r[0] >> 12); + e->mac[1] = (r[0] >> 4); + e->mac[2] = ((r[1] >> 28) | (r[0] << 4)); + e->mac[3] = (r[1] >> 20); + e->mac[4] = (r[1] >> 12); + e->mac[5] = (r[1] >> 4); + + e->vid = (r[2] >> 4) & 0xfff; + e->rvid = (r[0] >> 20) & 0xfff; + + /* Is it a unicast entry? check multicast bit */ + if (!(e->mac[0] & 1)) { + e->is_static = !!((r[2] >> 18) & 1); + e->port = (r[2] >> 24) & 0x3f; + e->block_da = !!(r[2] & (1 << 19)); + e->block_sa = !!(r[2] & (1 << 20)); + e->suspended = !!(r[2] & (1 << 17)); + e->next_hop = !!(r[2] & (1 << 16)); + if (e->next_hop) { + pr_debug("Found next hop entry, need to read data\n"); + e->nh_vlan_target = !!(r[2] & BIT(15)); + e->nh_route_id = (r[2] >> 4) & 0x1ff; + e->vid = e->rvid; + } + e->age = (r[2] >> 21) & 3; + e->valid = true; + if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */ + e->valid = false; + else + e->type = L2_UNICAST; + } else { + e->valid = true; + e->type = L2_MULTICAST; + e->mc_portmask_index = (r[2] >> 6) & 0xfff; + e->vid = e->rvid; + } + } else { /* IPv4 and IPv6 multicast */ + e->vid = e->rvid = (r[0] << 20) & 0xfff; + e->mc_gip = r[1]; + e->mc_portmask_index = (r[2] >> 6) & 0xfff; + } + if (e->is_ip_mc) { + e->valid = true; + e->type = IP4_MULTICAST; + } + if (e->is_ipv6_mc) { + e->valid = true; + e->type = IP6_MULTICAST; + } + /* pr_debug("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid); */ +} + +/* Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry */ +static void rtl839x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) +{ + if (!e->valid) { + r[0] = r[1] = r[2] = 0; + return; + } + + r[2] = e->is_ip_mc ? BIT(31) : 0; + r[2] |= e->is_ipv6_mc ? BIT(30) : 0; + + if (!e->is_ip_mc && !e->is_ipv6_mc) { + r[0] = ((u32)e->mac[0]) << 12; + r[0] |= ((u32)e->mac[1]) << 4; + r[0] |= ((u32)e->mac[2]) >> 4; + r[1] = ((u32)e->mac[2]) << 28; + r[1] |= ((u32)e->mac[3]) << 20; + r[1] |= ((u32)e->mac[4]) << 12; + r[1] |= ((u32)e->mac[5]) << 4; + + if (!(e->mac[0] & 1)) { /* Not multicast */ + r[2] |= e->is_static ? BIT(18) : 0; + r[0] |= ((u32)e->rvid) << 20; + r[2] |= e->port << 24; + r[2] |= e->block_da ? BIT(19) : 0; + r[2] |= e->block_sa ? BIT(20) : 0; + r[2] |= e->suspended ? BIT(17) : 0; + r[2] |= ((u32)e->age) << 21; + if (e->next_hop) { + r[2] |= BIT(16); + r[2] |= e->nh_vlan_target ? BIT(15) : 0; + r[2] |= (e->nh_route_id & 0x7ff) << 4; + } else { + r[2] |= e->vid << 4; + } + pr_debug("Write L2 NH: %08x %08x %08x\n", r[0], r[1], r[2]); + } else { /* L2 Multicast */ + r[0] |= ((u32)e->rvid) << 20; + r[2] |= ((u32)e->mc_portmask_index) << 6; + } + } else { /* IPv4 or IPv6 MC entry */ + r[0] = ((u32)e->rvid) << 20; + r[1] = e->mc_gip; + r[2] |= ((u32)e->mc_portmask_index) << 6; + } +} + +/* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table + * hash is the id of the bucket and pos is the position of the entry in that bucket + * The data read from the SoC is filled into rtl838x_l2_entry + */ +static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) +{ + u32 r[3]; + struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0); + u32 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */ + + rtl_table_read(q, idx); + for (int i = 0; i < 3; i++) + r[i] = sw_r32(rtl_table_data(q, i)); + + rtl_table_release(q); + + rtl839x_fill_l2_entry(r, e); + if (!e->valid) + return 0; + + return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid); +} + +static void rtl839x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) +{ + u32 r[3]; + struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0); + + u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */ + + rtl839x_fill_l2_row(r, e); + + for (int i = 0; i < 3; i++) + sw_w32(r[i], rtl_table_data(q, i)); + + rtl_table_write(q, idx); + rtl_table_release(q); +} + +static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e) +{ + u32 r[3]; + struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); /* Access L2 Table 1 */ + + rtl_table_read(q, idx); + for (int i = 0; i < 3; i++) + r[i] = sw_r32(rtl_table_data(q, i)); + + rtl_table_release(q); + + rtl839x_fill_l2_entry(r, e); + if (!e->valid) + return 0; + + pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]); + + /* Return MAC with concatenated VID ac concatenated ID */ + return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid); +} + +static void rtl839x_write_cam(int idx, struct rtl838x_l2_entry *e) +{ + u32 r[3]; + struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); /* Access L2 Table 1 */ + + rtl839x_fill_l2_row(r, e); + + for (int i = 0; i < 3; i++) + sw_w32(r[i], rtl_table_data(q, i)); + + rtl_table_write(q, idx); + rtl_table_release(q); +} + +static u64 rtl839x_read_mcast_pmask(int idx) +{ + u64 portmask; + /* Read MC_PMSK (2) via register RTL8390_TBL_L2 */ + struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2); + + rtl_table_read(q, idx); + portmask = sw_r32(rtl_table_data(q, 0)); + portmask <<= 32; + portmask |= sw_r32(rtl_table_data(q, 1)); + portmask >>= 11; /* LSB is bit 11 in data registers */ + rtl_table_release(q); + + return portmask; +} + +static void rtl839x_write_mcast_pmask(int idx, u64 portmask) +{ + /* Access MC_PMSK (2) via register RTL8380_TBL_L2 */ + struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2); + + portmask <<= 11; /* LSB is bit 11 in data registers */ + sw_w32((u32)(portmask >> 32), rtl_table_data(q, 0)); + sw_w32((u32)((portmask & 0xfffff800)), rtl_table_data(q, 1)); + rtl_table_write(q, idx); + rtl_table_release(q); +} + +static int +rtldsa_839x_vlan_profile_get(int idx, struct rtldsa_vlan_profile *profile) +{ + u32 p[2]; + + if (idx < 0 || idx > RTL839X_VLAN_PROFILE_MAX) + return -EINVAL; + + p[0] = sw_r32(RTL839X_VLAN_PROFILE(idx)); + p[1] = sw_r32(RTL839X_VLAN_PROFILE(idx) + 4); + + *profile = (struct rtldsa_vlan_profile) { + .l2_learn = RTL839X_VLAN_L2_LEARN_EN_R(p), + .unkn_mc_fld.pmsks_idx = { + .l2 = RTL839X_VLAN_L2_UNKN_MC_FLD_PMSK(p), + .ip = RTL839X_VLAN_IP4_UNKN_MC_FLD_PMSK(p), + .ip6 = RTL839X_VLAN_IP6_UNKN_MC_FLD_PMSK(p), + }, + .pmsk_is_idx = 1, + }; + + return 0; +} + +static void rtl839x_vlan_profile_setup(int profile) +{ + u32 p[2] = { 0, 0 }; + + p[1] = RTL839X_VLAN_L2_LEARN_EN(1); + p[1] |= RTL839X_VLAN_L2_UNKN_MC_FLD(MC_PMASK_ALL_PORTS_IDX) | + RTL839X_VLAN_IP4_UNKN_MC_FLD(MC_PMASK_ALL_PORTS_IDX); + p[0] |= RTL839X_VLAN_IP6_UNKN_MC_FLD(MC_PMASK_ALL_PORTS_IDX); + + sw_w32(p[0], RTL839X_VLAN_PROFILE(profile)); + sw_w32(p[1], RTL839X_VLAN_PROFILE(profile) + 4); +} + +static void rtl839x_traffic_set(int source, u64 dest_matrix) +{ + rtl839x_set_port_reg_be(dest_matrix, rtl839x_port_iso_ctrl(source)); +} + +static void rtl839x_traffic_enable(int source, int dest) +{ + rtl839x_mask_port_reg_be(0, BIT_ULL(dest), rtl839x_port_iso_ctrl(source)); +} + +static void rtl839x_traffic_disable(int source, int dest) +{ + rtl839x_mask_port_reg_be(BIT_ULL(dest), 0, rtl839x_port_iso_ctrl(source)); +} + +static void rtl839x_l2_learning_setup(void) +{ + /* Set portmask for broadcast (offset bit 12) and unknown unicast (offset 0) + * address flooding to the reserved entry in the portmask table used + * also for multicast flooding + */ + sw_w32(RTL839X_L2_BC_FLD(MC_PMASK_ALL_PORTS_IDX) | + RTL839X_L2_UNKN_UC_FLD(MC_PMASK_ALL_PORTS_IDX), + RTL839X_L2_FLD_PMSK); + + /* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */ + sw_w32((0x7fff << 2) | 0, RTL839X_L2_LRN_CONSTRT); + + /* Do not trap ARP packets to CPU_PORT */ + sw_w32(0, RTL839X_SPCL_TRAP_ARP_CTRL); +} + +static void rtl839x_enable_learning(int port, bool enable) +{ + /* Limit learning to maximum: 32k entries */ + + sw_w32_mask(0x7fff << 2, enable ? (0x7fff << 2) : 0, + RTL839X_L2_PORT_LRN_CONSTRT + (port << 2)); +} + +static void rtl839x_enable_flood(int port, bool enable) +{ + /* 0: Forward + * 1: Disable + * 2: to CPU + * 3: Copy to CPU + */ + sw_w32_mask(0x3, enable ? 0 : 1, + RTL839X_L2_PORT_LRN_CONSTRT + (port << 2)); +} + +static void rtl839x_enable_mcast_flood(int port, bool enable) +{ +} + +static void rtl839x_enable_bcast_flood(int port, bool enable) +{ +} + +static void rtl839x_set_static_move_action(int port, bool forward) +{ + int shift = MV_ACT_PORT_SHIFT(port); + u32 val = forward ? MV_ACT_FORWARD : MV_ACT_DROP; + + sw_w32_mask(MV_ACT_MASK << shift, val << shift, + RTL839X_L2_PORT_STATIC_MV_ACT(port)); +} + +static void +rtldsa_839x_vlan_profile_dump(struct rtl838x_switch_priv *priv, int idx) +{ + struct rtldsa_vlan_profile p; + + if (rtldsa_839x_vlan_profile_get(idx, &p) < 0) + return; + + dev_dbg(priv->dev, + "VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d\n" + "VLAN profile %d: raw %08x, %08x\n", idx, + p.l2_learn, p.unkn_mc_fld.pmsks_idx.l2, + p.unkn_mc_fld.pmsks_idx.ip, p.unkn_mc_fld.pmsks_idx.ip6, idx, + sw_r32(RTL839X_VLAN_PROFILE(idx)), + sw_r32(RTL839X_VLAN_PROFILE(idx) + 4)); +} + +static int rtldsa_839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, int port, u32 port_state[]) +{ + int idx = 3 - ((port + 12) / 16); + int bit = 2 * ((port + 12) % 16); + u32 cmd = 1 << 16 | /* Execute cmd */ + 0 << 15 | /* Read */ + 5 << 12 | /* Table type 0b101 */ + (msti & 0xfff); + + priv->r->exec_tbl0_cmd(cmd); + for (int i = 0; i < 4; i++) + port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); + + return (port_state[idx] >> bit) & 3; +} + +static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) +{ + u32 cmd = 1 << 16 | /* Execute cmd */ + 1 << 15 | /* Write */ + 5 << 12 | /* Table type 0b101 */ + (msti & 0xfff); + for (int i = 0; i < 4; i++) + sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); + priv->r->exec_tbl0_cmd(cmd); +} + +/* Enables or disables the EEE/EEEP capability of a port */ +static void rtldsa_839x_set_mac_eee(struct rtl838x_switch_priv *priv, int port, bool enable) +{ + u32 v; + + /* This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP */ + if (port >= 48) + return; + + enable = true; + pr_debug("In %s: setting port %d to %d\n", __func__, port, enable); + v = enable ? 0xf : 0x0; + + /* Set EEE for 100, 500, 1000MBit and 10GBit */ + sw_w32_mask(0xf << 8, v << 8, rtl839x_mac_force_mode_ctrl(port)); + + /* Set TX/RX EEE state */ + v = enable ? 0x3 : 0x0; + sw_w32(v, RTL839X_EEE_CTRL(port)); + + priv->ports[port].eee_enabled = enable; +} + +static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable) +{ + pr_debug("Setting up EEE, state: %d\n", enable); + + /* Set wake timer for TX and pause timer both to 0x21 */ + sw_w32_mask(0xff << 20 | 0xff, 0x21 << 20 | 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL); + /* Set pause wake timer for GIGA-EEE to 0x11 */ + sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL); + /* Set pause wake timer for 10GBit ports to 0x11 */ + sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL); + + /* Setup EEE on all ports */ + for (int i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy) + priv->r->set_mac_eee(priv, i, enable); + } + priv->eee_enabled = enable; +} + +static void rtl839x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index) +{ + int block = index / PIE_BLOCK_SIZE; + + sw_w32_mask(0, BIT(block), RTL839X_ACL_BLK_LOOKUP_CTRL); +} + +/* Delete a range of Packet Inspection Engine rules */ +static int rtl839x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to) +{ + u32 v = (index_from << 1) | (index_to << 13) | BIT(0); + + pr_debug("%s: from %d to %d\n", __func__, index_from, index_to); + mutex_lock(&priv->reg_mutex); + + /* Write from-to and execute bit into control register */ + sw_w32(v, RTL839X_ACL_CLR_CTRL); + + /* Wait until command has completed */ + do { + } while (sw_r32(RTL839X_ACL_CLR_CTRL) & BIT(0)); + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +/* Reads the intermediate representation of the templated match-fields of the + * PIE rule in the pie_rule structure and fills in the raw data fields in the + * raw register space r[]. + * The register space configuration size is identical for the RTL8380/90 and RTL9300, + * however the RTL9310 has 2 more registers / fields and the physical field-ids are different + * on all SoCs + * On the RTL8390 the template mask registers are not word-aligned! + */ +static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) +{ + for (int i = 0; i < N_FIXED_FIELDS; i++) { + enum template_field_id field_type = t[i]; + u16 data = 0, data_m = 0; + + switch (field_type) { + case TEMPLATE_FIELD_SPM0: + data = pr->spm; + data_m = pr->spm_m; + break; + case TEMPLATE_FIELD_SPM1: + data = pr->spm >> 16; + data_m = pr->spm_m >> 16; + break; + case TEMPLATE_FIELD_SPM2: + data = pr->spm >> 32; + data_m = pr->spm_m >> 32; + break; + case TEMPLATE_FIELD_SPM3: + data = pr->spm >> 48; + data_m = pr->spm_m >> 48; + break; + case TEMPLATE_FIELD_OTAG: + data = pr->otag; + data_m = pr->otag_m; + break; + case TEMPLATE_FIELD_SMAC0: + data = pr->smac[4]; + data = (data << 8) | pr->smac[5]; + data_m = pr->smac_m[4]; + data_m = (data_m << 8) | pr->smac_m[5]; + break; + case TEMPLATE_FIELD_SMAC1: + data = pr->smac[2]; + data = (data << 8) | pr->smac[3]; + data_m = pr->smac_m[2]; + data_m = (data_m << 8) | pr->smac_m[3]; + break; + case TEMPLATE_FIELD_SMAC2: + data = pr->smac[0]; + data = (data << 8) | pr->smac[1]; + data_m = pr->smac_m[0]; + data_m = (data_m << 8) | pr->smac_m[1]; + break; + case TEMPLATE_FIELD_DMAC0: + data = pr->dmac[4]; + data = (data << 8) | pr->dmac[5]; + data_m = pr->dmac_m[4]; + data_m = (data_m << 8) | pr->dmac_m[5]; + break; + case TEMPLATE_FIELD_DMAC1: + data = pr->dmac[2]; + data = (data << 8) | pr->dmac[3]; + data_m = pr->dmac_m[2]; + data_m = (data_m << 8) | pr->dmac_m[3]; + break; + case TEMPLATE_FIELD_DMAC2: + data = pr->dmac[0]; + data = (data << 8) | pr->dmac[1]; + data_m = pr->dmac_m[0]; + data_m = (data_m << 8) | pr->dmac_m[1]; + break; + case TEMPLATE_FIELD_ETHERTYPE: + data = pr->ethertype; + data_m = pr->ethertype_m; + break; + case TEMPLATE_FIELD_ITAG: + data = pr->itag; + data_m = pr->itag_m; + break; + case TEMPLATE_FIELD_SIP0: + if (pr->is_ipv6) { + data = pr->sip6.s6_addr16[7]; + data_m = pr->sip6_m.s6_addr16[7]; + } else { + data = pr->sip; + data_m = pr->sip_m; + } + break; + case TEMPLATE_FIELD_SIP1: + if (pr->is_ipv6) { + data = pr->sip6.s6_addr16[6]; + data_m = pr->sip6_m.s6_addr16[6]; + } else { + data = pr->sip >> 16; + data_m = pr->sip_m >> 16; + } + break; + case TEMPLATE_FIELD_SIP2: + case TEMPLATE_FIELD_SIP3: + case TEMPLATE_FIELD_SIP4: + case TEMPLATE_FIELD_SIP5: + case TEMPLATE_FIELD_SIP6: + case TEMPLATE_FIELD_SIP7: + data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; + data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; + break; + case TEMPLATE_FIELD_DIP0: + if (pr->is_ipv6) { + data = pr->dip6.s6_addr16[7]; + data_m = pr->dip6_m.s6_addr16[7]; + } else { + data = pr->dip; + data_m = pr->dip_m; + } + break; + case TEMPLATE_FIELD_DIP1: + if (pr->is_ipv6) { + data = pr->dip6.s6_addr16[6]; + data_m = pr->dip6_m.s6_addr16[6]; + } else { + data = pr->dip >> 16; + data_m = pr->dip_m >> 16; + } + break; + case TEMPLATE_FIELD_DIP2: + case TEMPLATE_FIELD_DIP3: + case TEMPLATE_FIELD_DIP4: + case TEMPLATE_FIELD_DIP5: + case TEMPLATE_FIELD_DIP6: + case TEMPLATE_FIELD_DIP7: + data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; + data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; + break; + case TEMPLATE_FIELD_IP_TOS_PROTO: + data = pr->tos_proto; + data_m = pr->tos_proto_m; + break; + case TEMPLATE_FIELD_L4_SPORT: + data = pr->sport; + data_m = pr->sport_m; + break; + case TEMPLATE_FIELD_L4_DPORT: + data = pr->dport; + data_m = pr->dport_m; + break; + case TEMPLATE_FIELD_ICMP_IGMP: + data = pr->icmp_igmp; + data_m = pr->icmp_igmp_m; + break; + default: + pr_debug("%s: unknown field %d\n", __func__, field_type); + } + + /* On the RTL8390, the mask fields are not word aligned! */ + if (!(i % 2)) { + r[5 - i / 2] = data; + r[12 - i / 2] |= ((u32)data_m << 8); + } else { + r[5 - i / 2] |= ((u32)data) << 16; + r[12 - i / 2] |= ((u32)data_m) << 24; + r[11 - i / 2] |= ((u32)data_m) >> 8; + } + } +} + +/* Creates the intermediate representation of the templated match-fields of the + * PIE rule in the pie_rule structure by reading the raw data fields in the + * raw register space r[]. + * The register space configuration size is identical for the RTL8380/90 and RTL9300, + * however the RTL9310 has 2 more registers / fields and the physical field-ids + * On the RTL8390 the template mask registers are not word-aligned! + */ +static void rtl839x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) +{ + for (int i = 0; i < N_FIXED_FIELDS; i++) { + enum template_field_id field_type = t[i]; + u16 data, data_m; + + if (!(i % 2)) { + data = r[5 - i / 2]; + data_m = r[12 - i / 2]; + } else { + data = r[5 - i / 2] >> 16; + data_m = r[12 - i / 2] >> 16; + } + + switch (field_type) { + case TEMPLATE_FIELD_SPM0: + pr->spm = (pr->spn << 16) | data; + pr->spm_m = (pr->spn << 16) | data_m; + break; + case TEMPLATE_FIELD_SPM1: + pr->spm = data; + pr->spm_m = data_m; + break; + case TEMPLATE_FIELD_OTAG: + pr->otag = data; + pr->otag_m = data_m; + break; + case TEMPLATE_FIELD_SMAC0: + pr->smac[4] = data >> 8; + pr->smac[5] = data; + pr->smac_m[4] = data >> 8; + pr->smac_m[5] = data; + break; + case TEMPLATE_FIELD_SMAC1: + pr->smac[2] = data >> 8; + pr->smac[3] = data; + pr->smac_m[2] = data >> 8; + pr->smac_m[3] = data; + break; + case TEMPLATE_FIELD_SMAC2: + pr->smac[0] = data >> 8; + pr->smac[1] = data; + pr->smac_m[0] = data >> 8; + pr->smac_m[1] = data; + break; + case TEMPLATE_FIELD_DMAC0: + pr->dmac[4] = data >> 8; + pr->dmac[5] = data; + pr->dmac_m[4] = data >> 8; + pr->dmac_m[5] = data; + break; + case TEMPLATE_FIELD_DMAC1: + pr->dmac[2] = data >> 8; + pr->dmac[3] = data; + pr->dmac_m[2] = data >> 8; + pr->dmac_m[3] = data; + break; + case TEMPLATE_FIELD_DMAC2: + pr->dmac[0] = data >> 8; + pr->dmac[1] = data; + pr->dmac_m[0] = data >> 8; + pr->dmac_m[1] = data; + break; + case TEMPLATE_FIELD_ETHERTYPE: + pr->ethertype = data; + pr->ethertype_m = data_m; + break; + case TEMPLATE_FIELD_ITAG: + pr->itag = data; + pr->itag_m = data_m; + break; + case TEMPLATE_FIELD_SIP0: + pr->sip = data; + pr->sip_m = data_m; + break; + case TEMPLATE_FIELD_SIP1: + pr->sip = (pr->sip << 16) | data; + pr->sip_m = (pr->sip << 16) | data_m; + break; + case TEMPLATE_FIELD_SIP2: + pr->is_ipv6 = true; + /* Make use of limitiations on the position of the match values */ + ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2], + r[4 - i / 2], r[3 - i / 2]); + ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2], + r[4 - i / 2], r[3 - i / 2]); + case TEMPLATE_FIELD_SIP3: + case TEMPLATE_FIELD_SIP4: + case TEMPLATE_FIELD_SIP5: + case TEMPLATE_FIELD_SIP6: + case TEMPLATE_FIELD_SIP7: + break; + + case TEMPLATE_FIELD_DIP0: + pr->dip = data; + pr->dip_m = data_m; + break; + + case TEMPLATE_FIELD_DIP1: + pr->dip = (pr->dip << 16) | data; + pr->dip_m = (pr->dip << 16) | data_m; + break; + + case TEMPLATE_FIELD_DIP2: + pr->is_ipv6 = true; + ipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2], + r[4 - i / 2], r[3 - i / 2]); + ipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2], + r[4 - i / 2], r[3 - i / 2]); + case TEMPLATE_FIELD_DIP3: + case TEMPLATE_FIELD_DIP4: + case TEMPLATE_FIELD_DIP5: + case TEMPLATE_FIELD_DIP6: + case TEMPLATE_FIELD_DIP7: + break; + case TEMPLATE_FIELD_IP_TOS_PROTO: + pr->tos_proto = data; + pr->tos_proto_m = data_m; + break; + case TEMPLATE_FIELD_L4_SPORT: + pr->sport = data; + pr->sport_m = data_m; + break; + case TEMPLATE_FIELD_L4_DPORT: + pr->dport = data; + pr->dport_m = data_m; + break; + case TEMPLATE_FIELD_ICMP_IGMP: + pr->icmp_igmp = data; + pr->icmp_igmp_m = data_m; + break; + default: + pr_debug("%s: unknown field %d\n", __func__, field_type); + } + } +} + +static void rtl839x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr) +{ + pr->spmmask_fix = (r[6] >> 30) & 0x3; + pr->spn = (r[6] >> 24) & 0x3f; + pr->mgnt_vlan = (r[6] >> 23) & 1; + pr->dmac_hit_sw = (r[6] >> 22) & 1; + pr->not_first_frag = (r[6] >> 21) & 1; + pr->frame_type_l4 = (r[6] >> 18) & 7; + pr->frame_type = (r[6] >> 16) & 3; + pr->otag_fmt = (r[6] >> 15) & 1; + pr->itag_fmt = (r[6] >> 14) & 1; + pr->otag_exist = (r[6] >> 13) & 1; + pr->itag_exist = (r[6] >> 12) & 1; + pr->frame_type_l2 = (r[6] >> 10) & 3; + pr->tid = (r[6] >> 8) & 3; + + pr->spmmask_fix_m = (r[12] >> 6) & 0x3; + pr->spn_m = r[12] & 0x3f; + pr->mgnt_vlan_m = (r[13] >> 31) & 1; + pr->dmac_hit_sw_m = (r[13] >> 30) & 1; + pr->not_first_frag_m = (r[13] >> 29) & 1; + pr->frame_type_l4_m = (r[13] >> 26) & 7; + pr->frame_type_m = (r[13] >> 24) & 3; + pr->otag_fmt_m = (r[13] >> 23) & 1; + pr->itag_fmt_m = (r[13] >> 22) & 1; + pr->otag_exist_m = (r[13] >> 21) & 1; + pr->itag_exist_m = (r[13] >> 20) & 1; + pr->frame_type_l2_m = (r[13] >> 18) & 3; + pr->tid_m = (r[13] >> 16) & 3; + + pr->valid = r[13] & BIT(15); + pr->cond_not = r[13] & BIT(14); + pr->cond_and1 = r[13] & BIT(13); + pr->cond_and2 = r[13] & BIT(12); +} + +static void rtl839x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr) +{ + r[6] = ((u32)(pr->spmmask_fix & 0x3)) << 30; + r[6] |= ((u32)(pr->spn & 0x3f)) << 24; + r[6] |= pr->mgnt_vlan ? BIT(23) : 0; + r[6] |= pr->dmac_hit_sw ? BIT(22) : 0; + r[6] |= pr->not_first_frag ? BIT(21) : 0; + r[6] |= ((u32)(pr->frame_type_l4 & 0x7)) << 18; + r[6] |= ((u32)(pr->frame_type & 0x3)) << 16; + r[6] |= pr->otag_fmt ? BIT(15) : 0; + r[6] |= pr->itag_fmt ? BIT(14) : 0; + r[6] |= pr->otag_exist ? BIT(13) : 0; + r[6] |= pr->itag_exist ? BIT(12) : 0; + r[6] |= ((u32)(pr->frame_type_l2 & 0x3)) << 10; + r[6] |= ((u32)(pr->tid & 0x3)) << 8; + + r[12] |= ((u32)(pr->spmmask_fix_m & 0x3)) << 6; + r[12] |= (u32)(pr->spn_m & 0x3f); + r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0; + r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0; + r[13] |= pr->not_first_frag_m ? BIT(29) : 0; + r[13] |= ((u32)(pr->frame_type_l4_m & 0x7)) << 26; + r[13] |= ((u32)(pr->frame_type_m & 0x3)) << 24; + r[13] |= pr->otag_fmt_m ? BIT(23) : 0; + r[13] |= pr->itag_fmt_m ? BIT(22) : 0; + r[13] |= pr->otag_exist_m ? BIT(21) : 0; + r[13] |= pr->itag_exist_m ? BIT(20) : 0; + r[13] |= ((u32)(pr->frame_type_l2_m & 0x3)) << 18; + r[13] |= ((u32)(pr->tid_m & 0x3)) << 16; + + r[13] |= pr->valid ? BIT(15) : 0; + r[13] |= pr->cond_not ? BIT(14) : 0; + r[13] |= pr->cond_and1 ? BIT(13) : 0; + r[13] |= pr->cond_and2 ? BIT(12) : 0; +} + +static void rtl839x_write_pie_action(u32 r[], struct pie_rule *pr) +{ + if (pr->drop) { + r[13] |= 0x9; /* Set ACT_MASK_FWD & FWD_ACT = DROP */ + r[13] |= BIT(3); + } else { + r[13] |= pr->fwd_sel ? BIT(3) : 0; + r[13] |= pr->fwd_act; + } + r[13] |= pr->bypass_sel ? BIT(11) : 0; + r[13] |= pr->mpls_sel ? BIT(10) : 0; + r[13] |= pr->nopri_sel ? BIT(9) : 0; + r[13] |= pr->ovid_sel ? BIT(8) : 0; + r[13] |= pr->ivid_sel ? BIT(7) : 0; + r[13] |= pr->meter_sel ? BIT(6) : 0; + r[13] |= pr->mir_sel ? BIT(5) : 0; + r[13] |= pr->log_sel ? BIT(4) : 0; + + r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 18; + r[14] |= pr->log_octets ? BIT(17) : 0; + r[14] |= ((u32)(pr->log_data & 0x7ff)) << 4; + r[14] |= (pr->mir_data & 0x3) << 3; + r[14] |= ((u32)(pr->meter_data >> 7)) & 0x7; + r[15] |= (u32)(pr->meter_data) << 26; + r[15] |= ((u32)(pr->ivid_act) << 23) & 0x3; + r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff; + r[15] |= ((u32)(pr->ovid_act) << 6) & 0x3; + r[15] |= ((u32)(pr->ovid_data) >> 4) & 0xff; + r[16] |= ((u32)(pr->ovid_data) & 0xf) << 28; + r[16] |= ((u32)(pr->nopri_data) & 0x7) << 20; + r[16] |= ((u32)(pr->mpls_act) & 0x7) << 20; + r[16] |= ((u32)(pr->mpls_lib_idx) & 0x7) << 20; + r[16] |= pr->bypass_all ? BIT(9) : 0; + r[16] |= pr->bypass_igr_stp ? BIT(8) : 0; + r[16] |= pr->bypass_ibc_sc ? BIT(7) : 0; +} + +static void rtl839x_read_pie_action(u32 r[], struct pie_rule *pr) +{ + if (r[13] & BIT(3)) { /* ACT_MASK_FWD set, is it a drop? */ + if ((r[14] & 0x7) == 1) { + pr->drop = true; + } else { + pr->fwd_sel = true; + pr->fwd_act = r[14] & 0x7; + } + } + + pr->bypass_sel = r[13] & BIT(11); + pr->mpls_sel = r[13] & BIT(10); + pr->nopri_sel = r[13] & BIT(9); + pr->ovid_sel = r[13] & BIT(8); + pr->ivid_sel = r[13] & BIT(7); + pr->meter_sel = r[13] & BIT(6); + pr->mir_sel = r[13] & BIT(5); + pr->log_sel = r[13] & BIT(4); + + /* TODO: Read in data fields */ + + pr->bypass_all = r[16] & BIT(9); + pr->bypass_igr_stp = r[16] & BIT(8); + pr->bypass_ibc_sc = r[16] & BIT(7); +} + +static void rtl839x_pie_rule_dump_raw(u32 r[]) +{ + pr_debug("Raw IACL table entry:\n"); + pr_debug("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]); + pr_debug("Fixed : %06x\n", r[6] >> 8); + pr_debug("Match M: %08x %08x %08x %08x %08x %08x\n", + (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8), + (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8), + (r[11] << 24) | (r[12] >> 8)); + pr_debug("R[13]: %08x\n", r[13]); + pr_debug("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff); + pr_debug("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf); + pr_debug("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]); +} + +void rtl839x_pie_rule_dump(struct pie_rule *pr) +{ + pr_debug("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n", + pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel, + pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel); + if (pr->fwd_sel) + pr_debug("FWD: %08x\n", pr->fwd_data); + pr_debug("TID: %x, %x\n", pr->tid, pr->tid_m); +} + +static int rtl839x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) +{ + /* Read IACL table (2) via register 0 */ + struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 2); + u32 r[17]; + int block = idx / PIE_BLOCK_SIZE; + u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block)); + + memset(pr, 0, sizeof(*pr)); + rtl_table_read(q, idx); + for (int i = 0; i < 17; i++) + r[i] = sw_r32(rtl_table_data(q, i)); + + rtl_table_release(q); + + rtl839x_read_pie_fixed_fields(r, pr); + if (!pr->valid) + return 0; + + pr_debug("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid); + rtl839x_pie_rule_dump_raw(r); + + rtl839x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]); + + rtl839x_read_pie_action(r, pr); + + return 0; +} + +static int rtl839x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) +{ + /* Access IACL table (2) via register 0 */ + struct table_reg *q = rtl_table_get(RTL8390_TBL_0, 2); + u32 r[17]; + int block = idx / PIE_BLOCK_SIZE; + u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block)); + + pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select); + + for (int i = 0; i < 17; i++) + r[i] = 0; + + if (!pr->valid) { + rtl_table_write(q, idx); + rtl_table_release(q); + return 0; + } + rtl839x_write_pie_fixed_fields(r, pr); + + pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 3)) & 0x7); + rtl839x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]); + + rtl839x_write_pie_action(r, pr); + +/* rtl839x_pie_rule_dump_raw(r); */ + + for (int i = 0; i < 17; i++) + sw_w32(r[i], rtl_table_data(q, i)); + + rtl_table_write(q, idx); + rtl_table_release(q); + + return 0; +} + +static bool rtl839x_pie_templ_has(int t, enum template_field_id field_type) +{ + for (int i = 0; i < N_FIXED_FIELDS; i++) { + enum template_field_id ft = fixed_templates[t][i]; + + if (field_type == ft) + return true; + } + + return false; +} + +static int rtl839x_pie_verify_template(struct rtl838x_switch_priv *priv, + struct pie_rule *pr, int t, int block) +{ + int i; + + if (!pr->is_ipv6 && pr->sip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP0)) + return -1; + + if (!pr->is_ipv6 && pr->dip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP0)) + return -1; + + if (pr->is_ipv6) { + if ((pr->sip6_m.s6_addr32[0] || + pr->sip6_m.s6_addr32[1] || + pr->sip6_m.s6_addr32[2] || + pr->sip6_m.s6_addr32[3]) && + !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) + return -1; + if ((pr->dip6_m.s6_addr32[0] || + pr->dip6_m.s6_addr32[1] || + pr->dip6_m.s6_addr32[2] || + pr->dip6_m.s6_addr32[3]) && + !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) + return -1; + } + + if (ether_addr_to_u64(pr->smac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0)) + return -1; + + if (ether_addr_to_u64(pr->dmac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0)) + return -1; + + /* TODO: Check more */ + + i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE); + + if (i >= PIE_BLOCK_SIZE) + return -1; + + return i + PIE_BLOCK_SIZE * block; +} + +static int rtl839x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr) +{ + int idx, block, j, t; + int min_block = 0; + int max_block = priv->r->n_pie_blocks / 2; + + if (pr->is_egress) { + min_block = max_block; + max_block = priv->r->n_pie_blocks; + } + + mutex_lock(&priv->pie_mutex); + + for (block = min_block; block < max_block; block++) { + for (j = 0; j < 2; j++) { + t = (sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7; + idx = rtl839x_pie_verify_template(priv, pr, t, block); + if (idx >= 0) + break; + } + if (j < 2) + break; + } + + if (block >= priv->r->n_pie_blocks) { + mutex_unlock(&priv->pie_mutex); + return -EOPNOTSUPP; + } + + set_bit(idx, priv->pie_use_bm); + + pr->valid = true; + pr->tid = j; /* Mapped to template number */ + pr->tid_m = 0x3; + pr->id = idx; + + rtl839x_pie_lookup_enable(priv, idx); + rtl839x_pie_rule_write(priv, idx, pr); + + mutex_unlock(&priv->pie_mutex); + + return 0; +} + +static void rtl839x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr) +{ + int idx = pr->id; + + rtl839x_pie_rule_del(priv, idx, idx); + clear_bit(idx, priv->pie_use_bm); +} + +static void rtl839x_pie_init(struct rtl838x_switch_priv *priv) +{ + u32 template_selectors; + + mutex_init(&priv->pie_mutex); + + /* Power on all PIE blocks */ + for (int i = 0; i < priv->r->n_pie_blocks; i++) + sw_w32_mask(0, BIT(i), RTL839X_PS_ACL_PWR_CTRL); + + /* Set ingress and egress ACL blocks to 50/50: first Egress block is 9 */ + sw_w32_mask(0x1f, 9, RTL839X_ACL_CTRL); /* Writes 9 to cutline field */ + + /* Include IPG in metering */ + sw_w32(1, RTL839X_METER_GLB_CTRL); + + /* Delete all present rules */ + rtl839x_pie_rule_del(priv, 0, priv->r->n_pie_blocks * PIE_BLOCK_SIZE - 1); + + /* Enable predefined templates 0, 1 for blocks 0-2 */ + template_selectors = 0 | (1 << 3); + for (int i = 0; i < 3; i++) + sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); + + /* Enable predefined templates 2, 3 for blocks 3-5 */ + template_selectors = 2 | (3 << 3); + for (int i = 3; i < 6; i++) + sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); + + /* Enable predefined templates 1, 4 for blocks 6-8 */ + template_selectors = 2 | (3 << 3); + for (int i = 6; i < 9; i++) + sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); + + /* Enable predefined templates 0, 1 for blocks 9-11 */ + template_selectors = 0 | (1 << 3); + for (int i = 9; i < 12; i++) + sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); + + /* Enable predefined templates 2, 3 for blocks 12-14 */ + template_selectors = 2 | (3 << 3); + for (int i = 12; i < 15; i++) + sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); + + /* Enable predefined templates 1, 4 for blocks 15-17 */ + template_selectors = 2 | (3 << 3); + for (int i = 15; i < 18; i++) + sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); +} + +static u32 rtl839x_packet_cntr_read(int counter) +{ + u32 v; + + /* Read LOG table (4) via register RTL8390_TBL_0 */ + struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4); + + pr_debug("In %s, id %d\n", __func__, counter); + rtl_table_read(r, counter / 2); + + /* The table has a size of 2 registers */ + if (counter % 2) + v = sw_r32(rtl_table_data(r, 0)); + else + v = sw_r32(rtl_table_data(r, 1)); + + rtl_table_release(r); + + return v; +} + +static void rtl839x_packet_cntr_clear(int counter) +{ + /* Access LOG table (4) via register RTL8390_TBL_0 */ + struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4); + + pr_debug("In %s, id %d\n", __func__, counter); + /* The table has a size of 2 registers */ + if (counter % 2) + sw_w32(0, rtl_table_data(r, 0)); + else + sw_w32(0, rtl_table_data(r, 1)); + + rtl_table_write(r, counter / 2); + + rtl_table_release(r); +} + +static void rtl839x_route_read(int idx, struct rtl83xx_route *rt) +{ + u64 v; + /* Read ROUTING table (2) via register RTL8390_TBL_1 */ + struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2); + + pr_debug("In %s\n", __func__); + rtl_table_read(r, idx); + + /* The table has a size of 2 registers */ + v = sw_r32(rtl_table_data(r, 0)); + v <<= 32; + v |= sw_r32(rtl_table_data(r, 1)); + rt->switch_mac_id = (v >> 12) & 0xf; + rt->nh.gw = v >> 16; + + rtl_table_release(r); +} + +static void rtl839x_route_write(int idx, struct rtl83xx_route *rt) +{ + u32 v; + + /* Read ROUTING table (2) via register RTL8390_TBL_1 */ + struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2); + + pr_debug("In %s\n", __func__); + sw_w32(rt->nh.gw >> 16, rtl_table_data(r, 0)); + v = rt->nh.gw << 16; + v |= rt->switch_mac_id << 12; + sw_w32(v, rtl_table_data(r, 1)); + rtl_table_write(r, idx); + + rtl_table_release(r); +} + +/* Configure the switch's own MAC addresses used when routing packets */ +static void rtl839x_setup_port_macs(struct rtl838x_switch_priv *priv) +{ + struct net_device *dev; + u64 mac; + + pr_debug("%s: got port %08x\n", __func__, (u32)priv->ports[priv->cpu_port].dp); + dev = priv->ports[priv->cpu_port].dp->user; + mac = ether_addr_to_u64(dev->dev_addr); + + for (int i = 0; i < 15; i++) { + mac++; /* BUG: VRRP for testing */ + sw_w32(mac >> 32, RTL839X_ROUTING_SA_CTRL + i * 8); + sw_w32(mac, RTL839X_ROUTING_SA_CTRL + i * 8 + 4); + } +} + +static int rtl839x_l3_setup(struct rtl838x_switch_priv *priv) +{ + rtl839x_setup_port_macs(priv); + + return 0; +} + +static void rtl839x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) +{ + sw_w32(FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK, + keep_outer ? RTL839X_VLAN_PORT_TAG_STS_TAGGED : RTL839X_VLAN_PORT_TAG_STS_UNTAG) | + FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK, + keep_inner ? RTL839X_VLAN_PORT_TAG_STS_TAGGED : RTL839X_VLAN_PORT_TAG_STS_UNTAG), + RTL839X_VLAN_PORT_TAG_STS_CTRL(port)); +} + +static void rtl839x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0x3, mode, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); + else + sw_w32_mask(0x3 << 14, mode << 14, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); +} + +static void rtl839x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0xfff << 2, pvid << 2, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); + else + sw_w32_mask(0xfff << 16, pvid << 16, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); +} + +static int rtldsa_839x_fast_age(struct rtl838x_switch_priv *priv, int port, int vid) +{ + u32 val; + + val = BIT(28) | BIT(25) | (port << 6); + if (vid >= 0) + val |= BIT(26) | (vid << 12); + + sw_w32(val, priv->r->l2_tbl_flush_ctrl); + do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(28)); + + return 0; +} + +static int rtl839x_set_ageing_time(unsigned long msec) +{ + int t = sw_r32(RTL839X_L2_CTRL_1); + + t &= 0x1FFFFF; + t = t * 3 / 5; /* Aging time in seconds. 0: L2 aging disabled */ + pr_debug("L2 AGING time: %d sec\n", t); + + t = (msec * 5 + 2000) / 3000; + t = t > 0x1FFFFF ? 0x1FFFFF : t; + sw_w32_mask(0x1FFFFF, t, RTL839X_L2_CTRL_1); + pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL839X_L2_PORT_AGING_OUT)); + + return 0; +} + +static void rtl839x_set_igr_filter(int port, enum igr_filter state) +{ + sw_w32_mask(0x3 << ((port & 0xf) << 1), state << ((port & 0xf) << 1), + RTL839X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2))); +} + +static void rtl839x_set_egr_filter(int port, enum egr_filter state) +{ + sw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20), + RTL839X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2))); +} + +static int rtldsa_839x_set_distribution_algorithm(struct rtl838x_switch_priv *priv, + int group, int algoidx, u32 algomsk) +{ + sw_w32_mask(3 << ((group & 0xf) << 1), algoidx << ((group & 0xf) << 1), + RTL839X_TRK_HASH_IDX_CTRL + ((group >> 4) << 2)); + sw_w32(algomsk, RTL839X_TRK_HASH_CTRL + (algoidx << 2)); + + return 0; +} + +static void rtl839x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action) +{ + switch (type) { + case BPDU: + sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), + RTL839X_RMA_BPDU_CTRL + ((port >> 4) << 2)); + break; + case PTP: + sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), + RTL839X_RMA_PTP_CTRL + ((port >> 4) << 2)); + break; + case LLDP: + sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), + RTL839X_RMA_LLDP_CTRL + ((port >> 4) << 2)); + break; + default: + break; + } +} + +static int rtldsa_839x_lag_set_port_members(struct rtl838x_switch_priv *priv, int group, + u64 members, struct netdev_lag_upper_info *info) +{ + priv->lags_port_members[group] = members; + + priv->r->set_port_reg_be(priv->lags_port_members[group], + priv->r->trk_mbr_ctr(group)); + + return 0; +} + +int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group, + struct netdev_lag_upper_info *info); + +const struct rtldsa_config rtldsa_839x_cfg = { + .mask_port_reg_be = rtl839x_mask_port_reg_be, + .set_port_reg_be = rtl839x_set_port_reg_be, + .get_port_reg_be = rtl839x_get_port_reg_be, + .mask_port_reg_le = rtl839x_mask_port_reg_le, + .set_port_reg_le = rtl839x_set_port_reg_le, + .get_port_reg_le = rtl839x_get_port_reg_le, + .stat_port_rst = RTL839X_STAT_PORT_RST, + .stat_rst = RTL839X_STAT_RST, + .stat_port_std_mib = RTL839X_STAT_PORT_STD_MIB, + .mib_desc = &rtldsa_839x_mib_desc, + .stat_counters_lock = rtldsa_counters_lock_register, + .stat_counters_unlock = rtldsa_counters_unlock_register, + .stat_update_counters_atomically = rtldsa_update_counters_atomically, + .stat_counter_poll_interval = RTLDSA_COUNTERS_POLL_INTERVAL, + .traffic_enable = rtl839x_traffic_enable, + .traffic_disable = rtl839x_traffic_disable, + .traffic_set = rtl839x_traffic_set, + .port_iso_ctrl = rtl839x_port_iso_ctrl, + .l2_ctrl_0 = RTL839X_L2_CTRL_0, + .l2_ctrl_1 = RTL839X_L2_CTRL_1, + .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT, + .set_ageing_time = rtl839x_set_ageing_time, + .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL, + .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL, + .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd, + .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd, + .tbl_access_data_0 = rtl839x_tbl_access_data_0, + .isr_glb_src = RTL839X_ISR_GLB_SRC, + .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG, + .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG, + .imr_glb = RTL839X_IMR_GLB, + .n_counters = 1024, + .n_pie_blocks = 18, + .port_ignore = 0x3f, + .vlan_tables_read = rtl839x_vlan_tables_read, + .vlan_set_tagged = rtl839x_vlan_set_tagged, + .vlan_set_untagged = rtl839x_vlan_set_untagged, + .vlan_profile_get = rtldsa_839x_vlan_profile_get, + .vlan_profile_dump = rtldsa_839x_vlan_profile_dump, + .vlan_profile_setup = rtl839x_vlan_profile_setup, + .vlan_fwd_on_inner = rtl839x_vlan_fwd_on_inner, + .vlan_port_keep_tag_set = rtl839x_vlan_port_keep_tag_set, + .vlan_port_pvidmode_set = rtl839x_vlan_port_pvidmode_set, + .vlan_port_pvid_set = rtl839x_vlan_port_pvid_set, + .set_vlan_igr_filter = rtl839x_set_igr_filter, + .set_vlan_egr_filter = rtl839x_set_egr_filter, + .enable_learning = rtl839x_enable_learning, + .enable_flood = rtl839x_enable_flood, + .enable_mcast_flood = rtl839x_enable_mcast_flood, + .enable_bcast_flood = rtl839x_enable_bcast_flood, + .set_static_move_action = rtl839x_set_static_move_action, + .stp_get = rtldsa_839x_stp_get, + .stp_set = rtl839x_stp_set, + .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl, + .mac_link_sts = RTL839X_MAC_LINK_STS, + .mac_port_ctrl = rtl839x_mac_port_ctrl, + .l2_port_new_salrn = rtl839x_l2_port_new_salrn, + .l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd, + .get_mirror_config = rtldsa_839x_get_mirror_config, + .print_matrix = rtldsa_839x_print_matrix, + .read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash, + .write_l2_entry_using_hash = rtl839x_write_l2_entry_using_hash, + .read_cam = rtl839x_read_cam, + .write_cam = rtl839x_write_cam, + .fast_age = rtldsa_839x_fast_age, + .trk_mbr_ctr = rtl839x_trk_mbr_ctr, + .rma_bpdu_fld_pmask = RTL839X_RMA_BPDU_FLD_PMSK, + .spcl_trap_eapol_ctrl = RTL839X_SPCL_TRAP_EAPOL_CTRL, + .init_eee = rtl839x_init_eee, + .set_mac_eee = rtldsa_839x_set_mac_eee, + .l2_hash_seed = rtl839x_l2_hash_seed, + .l2_hash_key = rtl839x_l2_hash_key, + .read_mcast_pmask = rtl839x_read_mcast_pmask, + .write_mcast_pmask = rtl839x_write_mcast_pmask, + .pie_init = rtl839x_pie_init, + .pie_rule_read = rtl839x_pie_rule_read, + .pie_rule_write = rtl839x_pie_rule_write, + .pie_rule_add = rtl839x_pie_rule_add, + .pie_rule_rm = rtl839x_pie_rule_rm, + .l2_learning_setup = rtl839x_l2_learning_setup, + .packet_cntr_read = rtl839x_packet_cntr_read, + .packet_cntr_clear = rtl839x_packet_cntr_clear, + .route_read = rtl839x_route_read, + .route_write = rtl839x_route_write, + .l3_setup = rtl839x_l3_setup, + .set_receive_management_action = rtl839x_set_receive_management_action, + .qos_init = rtldsa_839x_qos_init, + .lag_set_distribution_algorithm = rtldsa_839x_set_distribution_algorithm, + .lag_set_port_members = rtldsa_839x_lag_set_port_members, + .lag_setup_algomask = rtldsa_83xx_lag_setup_algomask, +}; diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl83xx.h b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl83xx.h new file mode 100644 index 0000000000..cf24ecc1be --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl83xx.h @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _NET_DSA_RTL83XX_H +#define _NET_DSA_RTL83XX_H + +#include +#include "rtl838x.h" + +struct fdb_update_work { + struct work_struct work; + struct net_device *ndev; + u64 macs[]; +}; + +enum mib_reg { + MIB_REG_INVALID = 0, + MIB_REG_STD, + MIB_REG_PRV, + MIB_TBL_STD, + MIB_TBL_PRV, +}; + +#define MIB_ITEM(_reg, _offset, _size) \ + {.reg = _reg, .offset = _offset, .size = _size} + +#define MIB_LIST_ITEM(_name, _item) \ + {.name = _name, .item = _item} + +struct rtldsa_mib_item { + enum mib_reg reg; + unsigned int offset; + unsigned int size; +}; + +struct rtldsa_mib_list_item { + const char *name; + struct rtldsa_mib_item item; +}; + +struct rtldsa_mib_desc { + struct rtldsa_mib_item symbol_errors; + + struct rtldsa_mib_item if_in_octets; + struct rtldsa_mib_item if_out_octets; + struct rtldsa_mib_item if_in_ucast_pkts; + struct rtldsa_mib_item if_in_mcast_pkts; + struct rtldsa_mib_item if_in_bcast_pkts; + struct rtldsa_mib_item if_out_ucast_pkts; + struct rtldsa_mib_item if_out_mcast_pkts; + struct rtldsa_mib_item if_out_bcast_pkts; + struct rtldsa_mib_item if_out_discards; + struct rtldsa_mib_item single_collisions; + struct rtldsa_mib_item multiple_collisions; + struct rtldsa_mib_item deferred_transmissions; + struct rtldsa_mib_item late_collisions; + struct rtldsa_mib_item excessive_collisions; + struct rtldsa_mib_item crc_align_errors; + struct rtldsa_mib_item rx_pkts_over_max_octets; + + struct rtldsa_mib_item unsupported_opcodes; + + struct rtldsa_mib_item rx_undersize_pkts; + struct rtldsa_mib_item rx_oversize_pkts; + struct rtldsa_mib_item rx_fragments; + struct rtldsa_mib_item rx_jabbers; + + struct rtldsa_mib_item tx_pkts[ETHTOOL_RMON_HIST_MAX]; + struct rtldsa_mib_item rx_pkts[ETHTOOL_RMON_HIST_MAX]; + struct ethtool_rmon_hist_range rmon_ranges[ETHTOOL_RMON_HIST_MAX]; + + struct rtldsa_mib_item drop_events; + struct rtldsa_mib_item collisions; + + struct rtldsa_mib_item rx_pause_frames; + struct rtldsa_mib_item tx_pause_frames; + + size_t list_count; + const struct rtldsa_mib_list_item *list; +}; + +/* API for switch table access */ +struct table_reg { + u16 addr; + u16 data; + u8 max_data; + u8 c_bit; + u8 t_bit; + u8 rmode; + u8 tbl; + struct mutex lock; +}; + +#define TBL_DESC(_addr, _data, _max_data, _c_bit, _t_bit, _rmode) \ + { .addr = _addr, .data = _data, .max_data = _max_data, .c_bit = _c_bit, \ + .t_bit = _t_bit, .rmode = _rmode \ + } + +typedef enum { + RTL8380_TBL_L2 = 0, + RTL8380_TBL_0, + RTL8380_TBL_1, + RTL8390_TBL_L2, + RTL8390_TBL_0, + RTL8390_TBL_1, + RTL8390_TBL_2, + RTL9300_TBL_L2, + RTL9300_TBL_0, + RTL9300_TBL_1, + RTL9300_TBL_2, + RTL9300_TBL_HSB, + RTL9300_TBL_HSA, + RTL9310_TBL_0, + RTL9310_TBL_1, + RTL9310_TBL_2, + RTL9310_TBL_3, + RTL9310_TBL_4, + RTL9310_TBL_5, + RTL_TBL_END +} rtl838x_tbl_reg_t; + +void rtl_table_init(void); +struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t); +void rtl_table_release(struct table_reg *r); +int rtl_table_read(struct table_reg *r, int idx); +int rtl_table_write(struct table_reg *r, int idx); +inline u16 rtl_table_data(struct table_reg *r, int i); +inline u32 rtl_table_data_r(struct table_reg *r, int i); +inline void rtl_table_data_w(struct table_reg *r, u32 v, int i); + +int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group, + struct netdev_lag_upper_info *info); + +void rtldsa_838x_qos_init(struct rtl838x_switch_priv *priv); +void rtldsa_839x_qos_init(struct rtl838x_switch_priv *priv); + +void rtldsa_port_fast_age(struct dsa_switch *ds, int port); +int rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv *priv); +int rtldsa_port_get_stp_state(struct rtl838x_switch_priv *priv, int port); +int rtl83xx_port_is_under(const struct net_device *dev, struct rtl838x_switch_priv *priv); +void rtldsa_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); +int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data); + +/* Port register accessor functions for the RTL839x and RTL931X SoCs */ +void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg); +u32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port); +u64 rtl839x_get_port_reg_be(int reg); +void rtl839x_set_port_reg_be(u64 set, int reg); +void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg); +int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate); +void rtl839x_set_port_reg_le(u64 set, int reg); +u64 rtl839x_get_port_reg_le(int reg); + +/* Port register accessor functions for the RTL838x and RTL930X SoCs */ +void rtl838x_mask_port_reg(u64 clear, u64 set, int reg); +void rtl838x_set_port_reg(u64 set, int reg); +u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port); +u64 rtl838x_get_port_reg(int reg); +int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate); + +/* RTL838x-specific */ +u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed); +void rtldsa_838x_print_matrix(void); + +/* RTL839x-specific */ +u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed); +void rtl839x_exec_tbl2_cmd(u32 cmd); +void rtldsa_839x_print_matrix(void); + +/* RTL930x-specific */ +u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed); +void rtldsa_930x_print_matrix(void); + +/* RTL931x-specific */ +void rtldsa_931x_print_matrix(void); + +int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_lag_upper_info *info); +int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port); + +/* + * TODO: The following functions are currently not in use. So compiler will complain if + * they are static and not made available externally. To preserve them for future use + * collect them in this section. + */ + +void rtl839x_pie_rule_dump(struct pie_rule *pr); +void rtl839x_set_egress_queue(int port, int queue); + +void rtl9300_dump_debug(void); +void rtl930x_pie_rule_dump_raw(u32 r[]); + +extern const struct dsa_switch_ops rtldsa_83xx_switch_ops; +extern const struct dsa_switch_ops rtldsa_93xx_switch_ops; + +extern const struct rtldsa_config rtldsa_838x_cfg; +extern const struct rtldsa_config rtldsa_839x_cfg; +extern const struct rtldsa_config rtldsa_930x_cfg; +extern const struct rtldsa_config rtldsa_931x_cfg; + +/* TODO actually from arch/mips/rtl838x/prom.c */ +extern struct rtl83xx_soc_info soc_info; + +#endif /* _NET_DSA_RTL83XX_H */ diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c new file mode 100644 index 0000000000..1c428814bb --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c @@ -0,0 +1,2906 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include "rtl83xx.h" + +#define RTL930X_VLAN_PORT_TAG_STS_INTERNAL 0x0 +#define RTL930X_VLAN_PORT_TAG_STS_UNTAG 0x1 +#define RTL930X_VLAN_PORT_TAG_STS_TAGGED 0x2 +#define RTL930X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x3 + +#define RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE 0xCE24 +/* port 0-28 */ +#define RTL930X_VLAN_PORT_TAG_STS_CTRL(port) \ + (RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)) +#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK GENMASK(7, 6) +#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK GENMASK(5, 4) +#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(3, 3) +#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(2, 2) +#define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(1, 1) +#define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(0, 0) + +#define RTL930X_LED_GLB_ACTIVE_LOW BIT(22) + +#define RTL930X_LED_SETX_0_CTRL(x) (RTL930X_LED_SET0_0_CTRL - (x * 8)) +#define RTL930X_LED_SETX_1_CTRL(x) (RTL930X_LED_SETX_0_CTRL(x) - 4) + +/* get register for given set and led in the set */ +#define RTL930X_LED_SETX_LEDY(x, y) (RTL930X_LED_SETX_0_CTRL(x) - 4 * (y / 2)) + +/* get shift for given led in any set */ +#define RTL930X_LED_SET_LEDX_SHIFT(x) (16 * (x % 2)) + +/* Definition of the RTL930X-specific template field IDs as used in the PIE */ +enum template_field_id { + TEMPLATE_FIELD_SPM0 = 0, /* Source portmask ports 0-15 */ + TEMPLATE_FIELD_SPM1 = 1, /* Source portmask ports 16-31 */ + TEMPLATE_FIELD_DMAC0 = 2, /* Destination MAC [15:0] */ + TEMPLATE_FIELD_DMAC1 = 3, /* Destination MAC [31:16] */ + TEMPLATE_FIELD_DMAC2 = 4, /* Destination MAC [47:32] */ + TEMPLATE_FIELD_SMAC0 = 5, /* Source MAC [15:0] */ + TEMPLATE_FIELD_SMAC1 = 6, /* Source MAC [31:16] */ + TEMPLATE_FIELD_SMAC2 = 7, /* Source MAC [47:32] */ + TEMPLATE_FIELD_ETHERTYPE = 8, /* Ethernet frame type field */ + TEMPLATE_FIELD_OTAG = 9, + TEMPLATE_FIELD_ITAG = 10, + TEMPLATE_FIELD_SIP0 = 11, + TEMPLATE_FIELD_SIP1 = 12, + TEMPLATE_FIELD_DIP0 = 13, + TEMPLATE_FIELD_DIP1 = 14, + TEMPLATE_FIELD_IP_TOS_PROTO = 15, + TEMPLATE_FIELD_L4_SPORT = 16, + TEMPLATE_FIELD_L4_DPORT = 17, + TEMPLATE_FIELD_L34_HEADER = 18, + TEMPLATE_FIELD_TCP_INFO = 19, + TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 20, + TEMPLATE_FIELD_FIELD_SELECTOR_0 = 21, + TEMPLATE_FIELD_FIELD_SELECTOR_1 = 22, + TEMPLATE_FIELD_FIELD_SELECTOR_2 = 23, + TEMPLATE_FIELD_FIELD_SELECTOR_3 = 24, + TEMPLATE_FIELD_FIELD_SELECTOR_4 = 25, + TEMPLATE_FIELD_FIELD_SELECTOR_5 = 26, + TEMPLATE_FIELD_SIP2 = 27, + TEMPLATE_FIELD_SIP3 = 28, + TEMPLATE_FIELD_SIP4 = 29, + TEMPLATE_FIELD_SIP5 = 30, + TEMPLATE_FIELD_SIP6 = 31, + TEMPLATE_FIELD_SIP7 = 32, + TEMPLATE_FIELD_DIP2 = 33, + TEMPLATE_FIELD_DIP3 = 34, + TEMPLATE_FIELD_DIP4 = 35, + TEMPLATE_FIELD_DIP5 = 36, + TEMPLATE_FIELD_DIP6 = 37, + TEMPLATE_FIELD_DIP7 = 38, + TEMPLATE_FIELD_PKT_INFO = 39, + TEMPLATE_FIELD_FLOW_LABEL = 40, + TEMPLATE_FIELD_DSAP_SSAP = 41, + TEMPLATE_FIELD_SNAP_OUI = 42, + TEMPLATE_FIELD_FWD_VID = 43, + TEMPLATE_FIELD_RANGE_CHK = 44, + TEMPLATE_FIELD_VLAN_GMSK = 45, /* VLAN Group Mask/IP range check */ + TEMPLATE_FIELD_DLP = 46, + TEMPLATE_FIELD_META_DATA = 47, + TEMPLATE_FIELD_SRC_FWD_VID = 48, + TEMPLATE_FIELD_SLP = 49, +}; + +/* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in + * RTL930X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag: + */ +#define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG + +/* Number of fixed templates predefined in the RTL9300 SoC */ +#define N_FIXED_TEMPLATES 5 +/* RTL9300 specific predefined templates */ +static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = { + { + TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, + TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2, + TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP, + TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1 + }, { + TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, + TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO, + TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN, + TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1 + }, { + TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, + TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO, + TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, + TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT + }, { + TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2, + TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5, + TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO, + TEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT + }, { + TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2, + TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5, + TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_VLAN, + TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM1 + }, +}; + +const struct rtldsa_mib_list_item rtldsa_930x_mib_list[] = { + MIB_LIST_ITEM("ifOutDiscards", MIB_ITEM(MIB_REG_STD, 0xbc, 1)), + MIB_LIST_ITEM("dot1dTpPortInDiscards", MIB_ITEM(MIB_REG_STD, 0xb8, 1)), + MIB_LIST_ITEM("DropEvents", MIB_ITEM(MIB_REG_STD, 0x90, 1)), + MIB_LIST_ITEM("tx_BroadcastPkts", MIB_ITEM(MIB_REG_STD, 0x8c, 1)), + MIB_LIST_ITEM("tx_MulticastPkts", MIB_ITEM(MIB_REG_STD, 0x88, 1)), + MIB_LIST_ITEM("tx_CRCAlignErrors", MIB_ITEM(MIB_REG_STD, 0x84, 1)), + MIB_LIST_ITEM("tx_UndersizePkts", MIB_ITEM(MIB_REG_STD, 0x7c, 1)), + MIB_LIST_ITEM("tx_OversizePkts", MIB_ITEM(MIB_REG_STD, 0x74, 1)), + MIB_LIST_ITEM("tx_Fragments", MIB_ITEM(MIB_REG_STD, 0x6c, 1)), + MIB_LIST_ITEM("tx_Jabbers", MIB_ITEM(MIB_REG_STD, 0x64, 1)), + MIB_LIST_ITEM("tx_Collisions", MIB_ITEM(MIB_REG_STD, 0x5c, 1)), + MIB_LIST_ITEM("rx_UndersizeDropPkts", MIB_ITEM(MIB_REG_PRV, 0x7c, 1)), + MIB_LIST_ITEM("tx_PktsFlexibleOctetsSet1", MIB_ITEM(MIB_REG_PRV, 0x68, 1)), + MIB_LIST_ITEM("rx_PktsFlexibleOctetsSet1", MIB_ITEM(MIB_REG_PRV, 0x64, 1)), + MIB_LIST_ITEM("tx_PktsFlexibleOctetsCRCSet1", MIB_ITEM(MIB_REG_PRV, 0x60, 1)), + MIB_LIST_ITEM("rx_PktsFlexibleOctetsCRCSet1", MIB_ITEM(MIB_REG_PRV, 0x5c, 1)), + MIB_LIST_ITEM("tx_PktsFlexibleOctetsSet0", MIB_ITEM(MIB_REG_PRV, 0x58, 1)), + MIB_LIST_ITEM("rx_PktsFlexibleOctetsSet0", MIB_ITEM(MIB_REG_PRV, 0x54, 1)), + MIB_LIST_ITEM("tx_PktsFlexibleOctetsCRCSet0", MIB_ITEM(MIB_REG_PRV, 0x50, 1)), + MIB_LIST_ITEM("rx_PktsFlexibleOctetsCRCSet0", MIB_ITEM(MIB_REG_PRV, 0x4c, 1)), + MIB_LIST_ITEM("LengthFieldError", MIB_ITEM(MIB_REG_PRV, 0x48, 1)), + MIB_LIST_ITEM("FalseCarrierTimes", MIB_ITEM(MIB_REG_PRV, 0x44, 1)), + MIB_LIST_ITEM("UndersizeOctets", MIB_ITEM(MIB_REG_PRV, 0x40, 1)), + MIB_LIST_ITEM("FramingErrors", MIB_ITEM(MIB_REG_PRV, 0x3c, 1)), + MIB_LIST_ITEM("ParserErrors", MIB_ITEM(MIB_REG_PRV, 0x38, 1)), + MIB_LIST_ITEM("rx_MacDiscards", MIB_ITEM(MIB_REG_PRV, 0x34, 1)), + MIB_LIST_ITEM("rx_MacIPGShortDrop", MIB_ITEM(MIB_REG_PRV, 0x30, 1)) +}; + +const struct rtldsa_mib_desc rtldsa_930x_mib_desc = { + .symbol_errors = MIB_ITEM(MIB_REG_STD, 0xa0, 1), + + .if_in_octets = MIB_ITEM(MIB_REG_STD, 0xf8, 2), + .if_out_octets = MIB_ITEM(MIB_REG_STD, 0xf0, 2), + .if_in_ucast_pkts = MIB_ITEM(MIB_REG_STD, 0xe8, 2), + .if_in_mcast_pkts = MIB_ITEM(MIB_REG_STD, 0xe0, 2), + .if_in_bcast_pkts = MIB_ITEM(MIB_REG_STD, 0xd8, 2), + .if_out_ucast_pkts = MIB_ITEM(MIB_REG_STD, 0xd0, 2), + .if_out_mcast_pkts = MIB_ITEM(MIB_REG_STD, 0xc8, 2), + .if_out_bcast_pkts = MIB_ITEM(MIB_REG_STD, 0xc0, 2), + .if_out_discards = MIB_ITEM(MIB_REG_STD, 0xbc, 1), + .single_collisions = MIB_ITEM(MIB_REG_STD, 0xb4, 1), + .multiple_collisions = MIB_ITEM(MIB_REG_STD, 0xb0, 1), + .deferred_transmissions = MIB_ITEM(MIB_REG_STD, 0xac, 1), + .late_collisions = MIB_ITEM(MIB_REG_STD, 0xa8, 1), + .excessive_collisions = MIB_ITEM(MIB_REG_STD, 0xa4, 1), + .crc_align_errors = MIB_ITEM(MIB_REG_STD, 0x80, 1), + .rx_pkts_over_max_octets = MIB_ITEM(MIB_REG_PRV, 0x6c, 1), + + .unsupported_opcodes = MIB_ITEM(MIB_REG_STD, 0x9c, 1), + + .rx_undersize_pkts = MIB_ITEM(MIB_REG_STD, 0x78, 1), + .rx_oversize_pkts = MIB_ITEM(MIB_REG_STD, 0x70, 1), + .rx_fragments = MIB_ITEM(MIB_REG_STD, 0x68, 1), + .rx_jabbers = MIB_ITEM(MIB_REG_STD, 0x60, 1), + + .tx_pkts = { + MIB_ITEM(MIB_REG_STD, 0x58, 1), + MIB_ITEM(MIB_REG_STD, 0x50, 1), + MIB_ITEM(MIB_REG_STD, 0x48, 1), + MIB_ITEM(MIB_REG_STD, 0x40, 1), + MIB_ITEM(MIB_REG_STD, 0x38, 1), + MIB_ITEM(MIB_REG_STD, 0x30, 1), + MIB_ITEM(MIB_REG_PRV, 0x78, 1), + MIB_ITEM(MIB_REG_PRV, 0x70, 1) + }, + .rx_pkts = { + MIB_ITEM(MIB_REG_STD, 0x54, 1), + MIB_ITEM(MIB_REG_STD, 0x4c, 1), + MIB_ITEM(MIB_REG_STD, 0x44, 1), + MIB_ITEM(MIB_REG_STD, 0x3c, 1), + MIB_ITEM(MIB_REG_STD, 0x34, 1), + MIB_ITEM(MIB_REG_STD, 0x2c, 1), + MIB_ITEM(MIB_REG_PRV, 0x74, 1), + MIB_ITEM(MIB_REG_PRV, 0x6c, 1), + }, + .rmon_ranges = { + { 0, 64 }, + { 65, 127 }, + { 128, 255 }, + { 256, 511 }, + { 512, 1023 }, + { 1024, 1518 }, + { 1519, 12288 }, + { 12289, 65535 } + }, + + .drop_events = MIB_ITEM(MIB_REG_STD, 0x90, 1), + .collisions = MIB_ITEM(MIB_REG_STD, 0x5c, 1), + + .rx_pause_frames = MIB_ITEM(MIB_REG_STD, 0x98, 1), + .tx_pause_frames = MIB_ITEM(MIB_REG_STD, 0x94, 1), + + .list_count = ARRAY_SIZE(rtldsa_930x_mib_list), + .list = rtldsa_930x_mib_list +}; + +void rtldsa_930x_print_matrix(void) +{ + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); + + for (int i = 0; i < 29; i++) { + rtl_table_read(r, i); + pr_debug("> %08x\n", sw_r32(rtl_table_data(r, 0))); + } + rtl_table_release(r); +} + +inline void rtl930x_exec_tbl0_cmd(u32 cmd) +{ + sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_0); + do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_0) & (1 << 17)); +} + +inline void rtl930x_exec_tbl1_cmd(u32 cmd) +{ + sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_1); + do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_1) & (1 << 17)); +} + +inline int rtl930x_tbl_access_data_0(int i) +{ + return RTL930X_TBL_ACCESS_DATA_0(i); +} + +static inline int rtl930x_l2_port_new_salrn(int p) +{ + return RTL930X_L2_PORT_SALRN(p); +} + +static inline int rtl930x_l2_port_new_sa_fwd(int p) +{ + /* TODO: The definition of the fields changed, because of the master-cpu in a stack */ + return RTL930X_L2_PORT_NEW_SA_FWD(p); +} + +static int rtldsa_930x_get_mirror_config(struct rtldsa_mirror_config *config, + int group, int port) +{ + config->ctrl = RTL930X_MIR_CTRL + group * 4; + config->spm = RTL930X_MIR_SPM_CTRL + group * 4; + config->dpm = RTL930X_MIR_DPM_CTRL + group * 4; + + /* Enable mirroring to destination port */ + config->val = BIT(0); + config->val |= port << 9; + + /* mirror mode: let mirrored packets follow TX settings of + * mirroring port + */ + config->val |= BIT(5); + + /* direction of traffic to be mirrored when a packet + * hits both SPM and DPM ports: prefer egress + */ + config->val |= BIT(4); + + return 0; +} + +static int rtldsa_930x_port_rate_police_add(struct dsa_switch *ds, int port, + const struct flow_action_entry *act, + bool ingress) +{ + u32 burst; + u64 rate; + u32 addr; + + /* rate has unit 16000 bit */ + rate = div_u64(act->police.rate_bytes_ps, 2000); + rate = min_t(u64, rate, RTL93XX_BANDWIDTH_CTRL_RATE_MAX); + rate |= RTL93XX_BANDWIDTH_CTRL_ENABLE; + + if (ingress) + addr = RTL930X_BANDWIDTH_CTRL_INGRESS(port); + else + addr = RTL930X_BANDWIDTH_CTRL_EGRESS(port); + + if (ingress) { + burst = min_t(u32, act->police.burst, RTL930X_BANDWIDTH_CTRL_INGRESS_BURST_MAX); + + /* the linux kernel only provides a single burst value. But the + * realtek HW needs two. And to get flow control correctly + * working, the realtek default ratio of 1:2 seems to work + * reasonable well + */ + sw_w32(burst, RTL930X_BANDWIDTH_CTRL_INGRESS_BURST_HIGH_ON(port)); + sw_w32(burst / 2, RTL930X_BANDWIDTH_CTRL_INGRESS_BURST_HIGH_OFF(port)); + + /* Enable ingress bandwidth flow control to improve TCP throughput and avoid + * the drops behavior of the RTL930x ingress rate limiter which seem to not + * play well with any congestion control algorithm + */ + sw_w32_mask(0, RTL930X_INGRESS_FC_CTRL_EN(port), + RTL930X_INGRESS_FC_CTRL(port)); + } else { + burst = min_t(u32, act->police.burst, RTL930X_BANDWIDTH_CTRL_MAX_BURST); + + sw_w32(burst, addr + 4); + } + + sw_w32(rate, addr); + + return 0; +} + +static int rtldsa_930x_port_rate_police_del(struct dsa_switch *ds, int port, + struct flow_cls_offload *cls, + bool ingress) +{ + u32 addr; + + if (ingress) + addr = RTL930X_BANDWIDTH_CTRL_INGRESS(port); + else + addr = RTL930X_BANDWIDTH_CTRL_EGRESS(port); + + sw_w32_mask(RTL93XX_BANDWIDTH_CTRL_ENABLE, 0, addr); + + if (ingress) + sw_w32_mask(RTL930X_INGRESS_FC_CTRL_EN(port), 0, + RTL930X_INGRESS_FC_CTRL(port)); + + return 0; +} + +static inline int rtl930x_trk_mbr_ctr(int group) +{ + return RTL930X_TRK_MBR_CTRL + (group << 2); +} + +static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 v, w; + /* Read VLAN table (1) via register 0 */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1); + + rtl_table_read(r, vlan); + v = sw_r32(rtl_table_data(r, 0)); + w = sw_r32(rtl_table_data(r, 1)); + pr_debug("VLAN_READ %d: %08x %08x\n", vlan, v, w); + rtl_table_release(r); + + info->member_ports = v >> 3; + info->profile_id = (w >> 24) & 7; + info->hash_mc_fid = !!(w & BIT(27)); + info->hash_uc_fid = !!(w & BIT(28)); + info->fid = ((v & 0x7) << 3) | ((w >> 29) & 0x7); + + /* Read UNTAG table via table register 2 */ + r = rtl_table_get(RTL9300_TBL_2, 0); + rtl_table_read(r, vlan); + v = sw_r32(rtl_table_data(r, 0)); + rtl_table_release(r); + + info->untagged_ports = v >> 3; +} + +static void rtl930x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 v, w; + /* Access VLAN table (1) via register 0 */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1); + + v = info->member_ports << 3; + v |= ((u32)info->fid) >> 3; + + w = ((u32)info->fid) << 29; + w |= info->hash_mc_fid ? BIT(27) : 0; + w |= info->hash_uc_fid ? BIT(28) : 0; + w |= info->profile_id << 24; + + sw_w32(v, rtl_table_data(r, 0)); + sw_w32(w, rtl_table_data(r, 1)); + + rtl_table_write(r, vlan); + rtl_table_release(r); +} + +static int +rtldsa_930x_vlan_profile_get(int idx, struct rtldsa_vlan_profile *profile) +{ + u32 p[5]; + + if (idx < 0 || idx > RTL930X_VLAN_PROFILE_MAX) + return -EINVAL; + + for (int i = 0; i < 5; i++) + p[i] = sw_r32(RTL930X_VLAN_PROFILE_SET(idx) + i * 4); + + *profile = (struct rtldsa_vlan_profile) { + .l2_learn = RTL930X_VLAN_L2_LEARN_EN_R(p), + .unkn_mc_fld.pmsks = { + .l2 = RTL930X_VLAN_L2_UNKN_MC_FLD_PMSK(p), + .ip = RTL930X_VLAN_IP4_UNKN_MC_FLD_PMSK(p), + .ip6 = RTL930X_VLAN_IP6_UNKN_MC_FLD_PMSK(p), + }, + .pmsk_is_idx = 0, + .routing_ipuc = p[0] & BIT(17), + .routing_ip6uc = p[0] & BIT(16), + .routing_ipmc = p[0] & BIT(13), + .routing_ip6mc = p[0] & BIT(12), + .bridge_ipmc = p[0] & BIT(15), + .bridge_ip6mc = p[0] & BIT(14), + }; + + return 0; +} + +static void +rtldsa_930x_vlan_profile_dump(struct rtl838x_switch_priv *priv, int idx) +{ + struct rtldsa_vlan_profile p; + + if (rtldsa_930x_vlan_profile_get(idx, &p) < 0) + return; + + dev_dbg(priv->dev, + "VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %llx, IPv4 %llx, IPv6: %llx\n" + " Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\n" + " Bridge enabled: IPv4 MC %c, IPv6 MC %c\n" + "VLAN profile %d: raw %08x %08x %08x %08x %08x\n", + idx, p.l2_learn, p.unkn_mc_fld.pmsks.l2, + p.unkn_mc_fld.pmsks.ip, p.unkn_mc_fld.pmsks.ip6, + p.routing_ipuc ? 'y' : 'n', p.routing_ip6uc ? 'y' : 'n', + p.routing_ipmc ? 'y' : 'n', p.routing_ip6mc ? 'y' : 'n', + p.bridge_ipmc ? 'y' : 'n', p.bridge_ip6mc ? 'y' : 'n', idx, + sw_r32(RTL930X_VLAN_PROFILE_SET(idx)), + sw_r32(RTL930X_VLAN_PROFILE_SET(idx) + 4), + sw_r32(RTL930X_VLAN_PROFILE_SET(idx) + 8) & 0x1FFFFFFF, + sw_r32(RTL930X_VLAN_PROFILE_SET(idx) + 12) & 0x1FFFFFFF, + sw_r32(RTL930X_VLAN_PROFILE_SET(idx) + 16) & 0x1FFFFFFF); +} + +static void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask) +{ + struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 0); + + sw_w32(portmask << 3, rtl_table_data(r, 0)); + rtl_table_write(r, vlan); + rtl_table_release(r); +} + +/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer */ +static void rtl930x_vlan_fwd_on_inner(int port, bool is_set) +{ + /* Always set all tag modes to fwd based on either inner or outer tag */ + if (is_set) + sw_w32_mask(0xf, 0, RTL930X_VLAN_PORT_FWD + (port << 2)); + else + sw_w32_mask(0, 0xf, RTL930X_VLAN_PORT_FWD + (port << 2)); +} + +static void rtl930x_vlan_profile_setup(int profile) +{ + u32 p[5]; + + pr_debug("In %s\n", __func__); + p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile)); + p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4); + + /* Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic */ + p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12); + + p[2] = RTL930X_VLAN_L2_UNKN_MC_FLD(RTL930X_MC_PMASK_ALL_PORTS); + p[3] = RTL930X_VLAN_IP4_UNKN_MC_FLD(RTL930X_MC_PMASK_ALL_PORTS); + p[4] = RTL930X_VLAN_IP6_UNKN_MC_FLD(RTL930X_MC_PMASK_ALL_PORTS); + + sw_w32(p[0], RTL930X_VLAN_PROFILE_SET(profile)); + sw_w32(p[1], RTL930X_VLAN_PROFILE_SET(profile) + 4); + sw_w32(p[2], RTL930X_VLAN_PROFILE_SET(profile) + 8); + sw_w32(p[3], RTL930X_VLAN_PROFILE_SET(profile) + 12); + sw_w32(p[4], RTL930X_VLAN_PROFILE_SET(profile) + 16); +} + +static void rtl930x_l2_learning_setup(void) +{ + /* Portmask for flooding broadcast traffic */ + sw_w32(RTL930X_MC_PMASK_ALL_PORTS, RTL930X_L2_BC_FLD_PMSK); + + /* Portmask for flooding unicast traffic with unknown destination */ + sw_w32(RTL930X_MC_PMASK_ALL_PORTS, RTL930X_L2_UNKN_UC_FLD_PMSK); + + /* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */ + sw_w32((0x7fff << 2) | 0, RTL930X_L2_LRN_CONSTRT_CTRL); +} + +static void rtldsa_930x_enable_learning(int port, bool enable) +{ + /* Limit learning to maximum: 32k entries */ + sw_w32_mask(GENMASK(17, 3), enable ? (0x7ffe << 3) : 0, + RTL930X_L2_LRN_PORT_CONSTRT_CTRL + port * 4); +} + +static void rtldsa_930x_enable_flood(int port, bool enable) +{ + /* 0: forward + * 1: drop + * 2: trap to local CPU + * 3: copy to local CPU + * 4: trap to master CPU + * 5: copy to master CPU + */ + sw_w32_mask(GENMASK(2, 0), enable ? 0 : 1, + RTL930X_L2_LRN_PORT_CONSTRT_CTRL + port * 4); +} + +static void rtldsa_930x_lag_set_port2group(int group, int port, bool valid) +{ + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 8); + u32 mask = valid ? RTL930X_SRC_TRK_MAP_TRK_VALID : 0; + + rtl_table_read(r, port); + mask |= FIELD_PREP(RTL930X_SRC_TRK_MAP_TRK_ID, group); // Update TRK Field. + sw_w32(mask, rtl_table_data(r, 0)); + rtl_table_write(r, port); + rtl_table_release(r); +} + +/* Write data from the data buffer into the lag-entry strucure */ +static void rtldsa_930x_lag_fill_data(u32 data[], struct rtldsa_93xx_lag_entry *e) +{ + /* 95-64 */ + e->num_tx_candi = FIELD_GET(RTL930X_LAG_NUM_TX_CANDI, data[0]); + e->l2_hash_mask_idx = FIELD_GET(RTL930X_LAG_L2_HASH_MSK_IDX, data[0]); + e->ip4_hash_mask_idx = FIELD_GET(RTL930X_LAG_IP4_HASH_MSK_IDX, data[0]); + e->ip6_hash_mask_idx = FIELD_GET(RTL930X_LAG_IP6_HASH_MSK_IDX, data[0]); + e->flood_dlf_bcast.sep_dlf_bcast_en = FIELD_GET(RTL930X_LAG_SEP_DLF_BCAST_EN, data[0]); + e->sep_kwn_mc_en = FIELD_GET(RTL930X_LAG_SEP_KWN_MC_EN, data[0]); + e->trk_dev7 = FIELD_GET(RTL930X_LAG_TRK_DEV7, data[0]); + e->trk_port7 = FIELD_GET(RTL930X_LAG_TRK_PORT7, data[0]); + e->trk_dev6 = FIELD_GET(RTL930X_LAG_TRK_DEV6, data[0]); + e->trk_port6 = FIELD_GET(RTL930X_LAG_TRK_PORT6, data[0]); + + /* 63-32 */ + e->trk_dev5 = FIELD_GET(RTL930X_LAG_TRK_DEV5, data[1]); + e->trk_port5 = FIELD_GET(RTL930X_LAG_TRK_PORT5, data[1]); + e->trk_dev4 = FIELD_GET(RTL930X_LAG_TRK_DEV4, data[1]); + e->trk_port4 = FIELD_GET(RTL930X_LAG_TRK_PORT4, data[1]); + e->trk_dev3 = FIELD_GET(RTL930X_LAG_TRK_DEV3, data[1]); + e->trk_port3 = FIELD_GET(RTL930X_LAG_TRK_PORT3, data[1]); + + /* 31-0 */ + e->trk_dev2 = FIELD_GET(RTL930X_LAG_TRK_DEV2, data[2]); + e->trk_port2 = FIELD_GET(RTL930X_LAG_TRK_PORT2, data[2]); + e->trk_dev1 = FIELD_GET(RTL930X_LAG_TRK_DEV1, data[2]); + e->trk_port1 = FIELD_GET(RTL930X_LAG_TRK_PORT1, data[2]); + e->trk_dev0 = FIELD_GET(RTL930X_LAG_TRK_DEV0, data[2]); + e->trk_port0 = FIELD_GET(RTL930X_LAG_TRK_PORT0, data[2]); +} + +/* Write lag-entry data into buffer */ +static void rtldsa_930x_lag_write_data(u32 data[], struct rtldsa_93xx_lag_entry *e) +{ + /* 95-64 */ + data[0] = FIELD_PREP(RTL930X_LAG_NUM_TX_CANDI, e->num_tx_candi); + data[0] |= FIELD_PREP(RTL930X_LAG_L2_HASH_MSK_IDX, e->l2_hash_mask_idx); + data[0] |= FIELD_PREP(RTL930X_LAG_IP4_HASH_MSK_IDX, e->ip4_hash_mask_idx); + data[0] |= FIELD_PREP(RTL930X_LAG_IP6_HASH_MSK_IDX, e->ip6_hash_mask_idx); + data[0] |= FIELD_PREP(RTL930X_LAG_SEP_DLF_BCAST_EN, e->flood_dlf_bcast.sep_dlf_bcast_en); + data[0] |= FIELD_PREP(RTL930X_LAG_SEP_KWN_MC_EN, e->sep_kwn_mc_en); + data[0] |= FIELD_PREP(RTL930X_LAG_TRK_DEV7, e->trk_dev7); + data[0] |= FIELD_PREP(RTL930X_LAG_TRK_PORT7, e->trk_port7); + data[0] |= FIELD_PREP(RTL930X_LAG_TRK_DEV6, e->trk_dev6); + data[0] |= FIELD_PREP(RTL930X_LAG_TRK_PORT6, e->trk_port6); + + /* 63-32 */ + data[1] = FIELD_PREP(RTL930X_LAG_TRK_DEV5, e->trk_dev5); + data[1] |= FIELD_PREP(RTL930X_LAG_TRK_PORT5, e->trk_port5); + data[1] |= FIELD_PREP(RTL930X_LAG_TRK_DEV4, e->trk_dev4); + data[1] |= FIELD_PREP(RTL930X_LAG_TRK_PORT4, e->trk_port4); + data[1] |= FIELD_PREP(RTL930X_LAG_TRK_DEV3, e->trk_dev3); + data[1] |= FIELD_PREP(RTL930X_LAG_TRK_PORT3, e->trk_port3); + + /* 31-0 */ + data[2] = FIELD_PREP(RTL930X_LAG_TRK_DEV2, e->trk_dev2); + data[2] |= FIELD_PREP(RTL930X_LAG_TRK_PORT2, e->trk_port2); + data[2] |= FIELD_PREP(RTL930X_LAG_TRK_DEV1, e->trk_dev1); + data[2] |= FIELD_PREP(RTL930X_LAG_TRK_PORT1, e->trk_port1); + data[2] |= FIELD_PREP(RTL930X_LAG_TRK_DEV0, e->trk_dev0); + data[2] |= FIELD_PREP(RTL930X_LAG_TRK_PORT0, e->trk_port0); +} + +static void rtldsa_930x_lag_set_local_group_id(int local_group, int global_group, bool valid) +{ + u32 mask = 0; + + mask |= valid ? RTL930X_TRK_ID_CTRL_TRK_VALID : 0; + mask |= FIELD_PREP(RTL930X_TRK_ID_CTRL_TRK_ID, global_group); + sw_w32(mask, RTL930X_TRK_ID_CTRL + (4 * local_group)); +} + +static void rtldsa_930x_lag_set_local_port2group(int group, int port, bool valid) +{ + u32 mask = 0; + + mask |= valid ? RTL930X_LOCAL_PORT_TRK_MAP_IS_TRK_MBR : 0; + mask |= FIELD_PREP(RTL930X_LOCAL_PORT_TRK_MAP_TRK_ID, group); + sw_w32(mask, RTL930X_LOCAL_PORT_TRK_MAP + (4 * port)); +} + +static void rtldsa_930x_lag_sync_tables(void) +{ + u32 val; + int ret; + + sw_w32(BIT(0), RTL930X_TRK_LOCAL_TBL_REFRESH); + + ret = readx_poll_timeout(sw_r32, RTL930X_TRK_LOCAL_TBL_REFRESH, val, + !(val & BIT(0)), 20, 10000); + if (ret) + pr_err("%s: timeout\n", __func__); +} + +static struct table_reg *rtldsa_930x_lag_table(void) +{ + return rtl_table_get(RTL9300_TBL_0, 7); +} + +static int rtldsa_930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, int port, u32 port_state[]) +{ + int idx = 1 - ((port + 3) / 16); + int bit = 2 * ((port + 3) % 16); + u32 cmd = 1 << 17 | /* Execute cmd */ + 0 << 16 | /* Read */ + 4 << 12 | /* Table type 0b10 */ + (msti & 0xfff); + + priv->r->exec_tbl0_cmd(cmd); + for (int i = 0; i < 2; i++) + port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); + + return (port_state[idx] >> bit) & 3; +} + +static void rtl930x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) +{ + u32 cmd = 1 << 17 | /* Execute cmd */ + 1 << 16 | /* Write */ + 4 << 12 | /* Table type 4 */ + (msti & 0xfff); + + for (int i = 0; i < 2; i++) + sw_w32(port_state[i], RTL930X_TBL_ACCESS_DATA_0(i)); + priv->r->exec_tbl0_cmd(cmd); +} + +static inline int rtl930x_mac_force_mode_ctrl(int p) +{ + return RTL930X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +static inline int rtl930x_mac_port_ctrl(int p) +{ + return RTL930X_MAC_L2_PORT_CTRL(p); +} + +static u64 rtl930x_l2_hash_seed(u64 mac, u32 vid) +{ + u64 v = vid; + + v <<= 48; + v |= mac; + + return v; +} + +/* Calculate both the block 0 and the block 1 hash by applyingthe same hash + * algorithm as the one used currently by the ASIC to the seed, and return + * both hashes in the lower and higher word of the return value since only 12 bit of + * the hash are significant + */ +static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) +{ + u32 k0, k1, h1, h2, h; + + k0 = (u32)(((seed >> 55) & 0x1f) ^ + ((seed >> 44) & 0x7ff) ^ + ((seed >> 33) & 0x7ff) ^ + ((seed >> 22) & 0x7ff) ^ + ((seed >> 11) & 0x7ff) ^ + (seed & 0x7ff)); + + h1 = (seed >> 11) & 0x7ff; + h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f); + + h2 = (seed >> 33) & 0x7ff; + h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x3f); + + k1 = (u32)(((seed << 55) & 0x1f) ^ + ((seed >> 44) & 0x7ff) ^ + h2 ^ + ((seed >> 22) & 0x7ff) ^ + h1 ^ + (seed & 0x7ff)); + + /* Algorithm choice for block 0 */ + if (sw_r32(RTL930X_L2_CTRL) & BIT(0)) + h = k1; + else + h = k0; + + /* Algorithm choice for block 1 + * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second + * half of hash-space + * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket + * divided by 2 to divide the hash space in 2 + */ + if (sw_r32(RTL930X_L2_CTRL) & BIT(1)) + h |= (k1 + 2048) << 16; + else + h |= (k0 + 2048) << 16; + + return h; +} + +/* Fills an L2 entry structure from the SoC registers */ +static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) +{ + pr_debug("In %s valid?\n", __func__); + e->valid = !!(r[2] & BIT(31)); + if (!e->valid) + return; + + pr_debug("In %s is valid\n", __func__); + e->is_ip_mc = false; + e->is_ipv6_mc = false; + + /* TODO: Is there not a function to copy directly MAC memory? */ + e->mac[0] = (r[0] >> 24); + e->mac[1] = (r[0] >> 16); + e->mac[2] = (r[0] >> 8); + e->mac[3] = r[0]; + e->mac[4] = (r[1] >> 24); + e->mac[5] = (r[1] >> 16); + + e->next_hop = !!(r[2] & BIT(12)); + e->rvid = r[1] & 0xfff; + + /* Is it a unicast entry? check multicast bit */ + if (!(e->mac[0] & 1)) { + e->type = L2_UNICAST; + e->is_static = !!(r[2] & BIT(14)); + e->port = (r[2] >> 20) & 0x3ff; + /* Check for trunk port */ + if (r[2] & BIT(30)) { + e->is_trunk = true; + e->stack_dev = (e->port >> 9) & 1; + e->trunk = e->port & 0x3f; + } else { + e->is_trunk = false; + e->stack_dev = (e->port >> 6) & 0xf; + e->port = e->port & 0x3f; + } + + e->block_da = !!(r[2] & BIT(15)); + e->block_sa = !!(r[2] & BIT(16)); + e->suspended = !!(r[2] & BIT(13)); + e->age = (r[2] >> 17) & 3; + e->valid = true; + /* the UC_VID field in hardware is used for the VID or for the route id */ + if (e->next_hop) { + e->nh_route_id = r[2] & 0x7ff; + e->vid = 0; + } else { + e->vid = r[2] & 0xfff; + e->nh_route_id = 0; + } + } else { + e->valid = true; + e->type = L2_MULTICAST; + e->mc_portmask_index = (r[2] >> 16) & 0x3ff; + } +} + +/* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */ +static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) +{ + u32 port; + + if (!e->valid) { + r[0] = r[1] = r[2] = 0; + return; + } + + r[2] = BIT(31); /* Set valid bit */ + + r[0] = ((u32)e->mac[0]) << 24 | + ((u32)e->mac[1]) << 16 | + ((u32)e->mac[2]) << 8 | + ((u32)e->mac[3]); + r[1] = ((u32)e->mac[4]) << 24 | + ((u32)e->mac[5]) << 16; + + r[2] |= e->next_hop ? BIT(12) : 0; + + if (e->type == L2_UNICAST) { + r[2] |= e->is_static ? BIT(14) : 0; + r[1] |= e->rvid & 0xfff; + r[2] |= (e->port & 0x3ff) << 20; + if (e->is_trunk) { + r[2] |= BIT(30); + port = e->stack_dev << 9 | (e->port & 0x3f); + } else { + port = (e->stack_dev & 0xf) << 6; + port |= e->port & 0x3f; + } + r[2] |= port << 20; + r[2] |= e->block_da ? BIT(15) : 0; + r[2] |= e->block_sa ? BIT(17) : 0; + r[2] |= e->suspended ? BIT(13) : 0; + r[2] |= (e->age & 0x3) << 17; + /* the UC_VID field in hardware is used for the VID or for the route id */ + if (e->next_hop) + r[2] |= e->nh_route_id & 0x7ff; + else + r[2] |= e->vid & 0xfff; + } else { /* L2_MULTICAST */ + r[2] |= (e->mc_portmask_index & 0x3ff) << 16; + r[2] |= e->mc_mac_index & 0x7ff; + } +} + +/* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table + * hash is the id of the bucket and pos is the position of the entry in that bucket + * The data read from the SoC is filled into rtl838x_l2_entry + */ +static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) +{ + u32 r[3]; + struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0); + u32 idx; + u64 mac; + u64 seed; + + pr_debug("%s: hash %08x, pos: %d\n", __func__, hash, pos); + + /* On the RTL93xx, 2 different hash algorithms are used making it a + * total of 8 buckets that need to be searched, 4 for each hash-half + * Use second hash space when bucket is between 4 and 8 + */ + if (pos >= 4) { + pos -= 4; + hash >>= 16; + } else { + hash &= 0xffff; + } + + idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */ + pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos); + + rtl_table_read(q, idx); + for (int i = 0; i < 3; i++) + r[i] = sw_r32(rtl_table_data(q, i)); + + rtl_table_release(q); + + rtl930x_fill_l2_entry(r, e); + + pr_debug("%s: valid: %d, nh: %d\n", __func__, e->valid, e->next_hop); + if (!e->valid) + return 0; + + mac = ((u64)e->mac[0]) << 40 | + ((u64)e->mac[1]) << 32 | + ((u64)e->mac[2]) << 24 | + ((u64)e->mac[3]) << 16 | + ((u64)e->mac[4]) << 8 | + ((u64)e->mac[5]); + + seed = rtl930x_l2_hash_seed(mac, e->rvid); + pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed); + + /* return vid with concatenated mac as unique id */ + return seed; +} + +static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) +{ + u32 r[3]; + struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0); + u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */ + + pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos); + pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx, + e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5]); + + rtl930x_fill_l2_row(r, e); + + for (int i = 0; i < 3; i++) + sw_w32(r[i], rtl_table_data(q, i)); + + rtl_table_write(q, idx); + rtl_table_release(q); +} + +static u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e) +{ + u32 r[3]; + struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); + + rtl_table_read(q, idx); + for (int i = 0; i < 3; i++) + r[i] = sw_r32(rtl_table_data(q, i)); + + rtl_table_release(q); + + rtl930x_fill_l2_entry(r, e); + if (!e->valid) + return 0; + + /* return mac with concatenated vid as unique id */ + return ((u64)r[0] << 28) | ((r[1] & 0xffff0000) >> 4) | e->vid; +} + +static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e) +{ + u32 r[3]; + struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); /* Access L2 Table 1 */ + + rtl930x_fill_l2_row(r, e); + + for (int i = 0; i < 3; i++) + sw_w32(r[i], rtl_table_data(q, i)); + + rtl_table_write(q, idx); + rtl_table_release(q); +} + +static u64 rtl930x_read_mcast_pmask(int idx) +{ + u32 portmask; + /* Read MC_PORTMASK (2) via register RTL9300_TBL_L2 */ + struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2); + + rtl_table_read(q, idx); + portmask = sw_r32(rtl_table_data(q, 0)); + portmask >>= 3; + rtl_table_release(q); + + pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, portmask); + + return portmask; +} + +static void rtl930x_write_mcast_pmask(int idx, u64 portmask) +{ + u32 pm = portmask; + + /* Access MC_PORTMASK (2) via register RTL9300_TBL_L2 */ + struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2); + + pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, pm); + pm <<= 3; + sw_w32(pm, rtl_table_data(q, 0)); + rtl_table_write(q, idx); + rtl_table_release(q); +} + +static void rtldsa_930x_set_receive_management_action(int port, rma_ctrl_t type, + action_type_t action) +{ + u32 shift; + u32 value; + u32 reg; + + /* hack for value mapping */ + if (type == GRATARP && action == COPY2CPU) + action = TRAP2MASTERCPU; + + /* PTP doesn't allow to flood to all ports */ + if (action == FLOODALL && + (type == PTP || type == PTP_UDP || type == PTP_ETH2)) { + pr_warn("%s: Port flooding not supported for PTP\n", __func__); + return; + } + + switch (action) { + case FORWARD: + value = 0; + break; + case DROP: + value = 1; + break; + case TRAP2CPU: + value = 2; + break; + case TRAP2MASTERCPU: + value = 3; + break; + case FLOODALL: + value = 4; + break; + default: + return; + } + + switch (type) { + case BPDU: + reg = RTL930X_RMA_BPDU_CTRL + (port / 10) * 4; + shift = (port % 10) * 3; + sw_w32_mask(GENMASK(shift + 2, shift), value << shift, reg); + break; + case PTP: + reg = RTL930X_RMA_PTP_CTRL + port * 4; + + /* udp */ + sw_w32_mask(GENMASK(3, 2), value << 2, reg); + + /* eth2 */ + sw_w32_mask(GENMASK(1, 0), value, reg); + break; + case PTP_UDP: + reg = RTL930X_RMA_PTP_CTRL + port * 4; + sw_w32_mask(GENMASK(3, 2), value << 2, reg); + break; + case PTP_ETH2: + reg = RTL930X_RMA_PTP_CTRL + port * 4; + sw_w32_mask(GENMASK(1, 0), value, reg); + break; + case LLDP: + reg = RTL930X_RMA_LLDP_CTRL + (port / 10) * 4; + shift = (port % 10) * 3; + sw_w32_mask(GENMASK(shift + 2, shift), value << shift, reg); + break; + case EAPOL: + reg = RTL930X_RMA_EAPOL_CTRL + (port / 10) * 4; + shift = (port % 10) * 3; + sw_w32_mask(GENMASK(shift + 2, shift), value << shift, reg); + break; + case GRATARP: + reg = RTL930X_SPCL_TRAP_PORT_CTRL + (port / 16) * 4; + shift = (port % 16) * 2; + sw_w32_mask(GENMASK(shift + 1, shift), value << shift, reg); + break; + } +} + +/* Enable traffic between a source port and a destination port matrix */ +static void rtl930x_traffic_set(int source, u64 dest_matrix) +{ + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); + + sw_w32((dest_matrix << 3), rtl_table_data(r, 0)); + rtl_table_write(r, source); + rtl_table_release(r); +} + +static void rtl930x_traffic_enable(int source, int dest) +{ + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); + + rtl_table_read(r, source); + sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0)); + rtl_table_write(r, source); + rtl_table_release(r); +} + +static void rtl930x_traffic_disable(int source, int dest) +{ + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); + + rtl_table_read(r, source); + sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0)); + rtl_table_write(r, source); + rtl_table_release(r); +} + +void rtl9300_dump_debug(void) +{ + u16 r = RTL930X_STAT_PRVTE_DROP_COUNTER0; + + for (int i = 0; i < 10; i++) { + pr_debug("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8, + sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), + sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28)); + r += 32; + } + pr_debug("# %08x %08x %08x %08x %08x\n", + sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16)); + rtldsa_930x_print_matrix(); + pr_debug("RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\n", + sw_r32(RTL930X_L2_PORT_SABLK_CTRL), sw_r32(RTL930X_L2_PORT_DABLK_CTRL) + + ); +} + +/* Calculate both the block 0 and the block 1 hash, and return in + * lower and higher word of the return value since only 12 bit of + * the hash are significant + */ +u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed) +{ + u32 k0, k1, h1, h2, h; + + k0 = (u32) (((seed >> 55) & 0x1f) ^ + ((seed >> 44) & 0x7ff) ^ + ((seed >> 33) & 0x7ff) ^ + ((seed >> 22) & 0x7ff) ^ + ((seed >> 11) & 0x7ff) ^ + (seed & 0x7ff)); + + h1 = (seed >> 11) & 0x7ff; + h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f); + + h2 = (seed >> 33) & 0x7ff; + h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x3f); + + k1 = (u32) (((seed << 55) & 0x1f) ^ + ((seed >> 44) & 0x7ff) ^ + h2 ^ + ((seed >> 22) & 0x7ff) ^ + h1 ^ + (seed & 0x7ff)); + + /* Algorithm choice for block 0 */ + if (sw_r32(RTL930X_L2_CTRL) & BIT(0)) + h = k1; + else + h = k0; + + /* Algorithm choice for block 1 + * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second + * half of hash-space + * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket + * divided by 2 to divide the hash space in 2 + */ + if (sw_r32(RTL930X_L2_CTRL) & BIT(1)) + h |= (k1 + 2048) << 16; + else + h |= (k0 + 2048) << 16; + + return h; +} + +/* Enables or disables the EEE/EEEP capability of a port */ +static void rtldsa_930x_set_mac_eee(struct rtl838x_switch_priv *priv, int port, bool enable) +{ + u32 v; + + /* This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP */ + if (port >= 26) + return; + + pr_debug("In %s: setting port %d to %d\n", __func__, port, enable); + v = enable ? 0x3f : 0x0; + + /* Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit */ + sw_w32_mask(0, v << 10, rtl930x_mac_force_mode_ctrl(port)); + + /* Set TX/RX EEE state */ + v = enable ? 0x3 : 0x0; + sw_w32(v, RTL930X_EEE_CTRL(port)); + + priv->ports[port].eee_enabled = enable; +} + +static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable) +{ + pr_debug("Setting up EEE, state: %d\n", enable); + + /* Setup EEE on all ports */ + for (int i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy) + priv->r->set_mac_eee(priv, i, enable); + } + + priv->eee_enabled = enable; +} + +#ifdef CONFIG_NET_DSA_RTL83XX_RTL930X_L3_OFFLOAD + +#define HASH_PICK(val, lsb, len) ((val & (((1 << len) - 1) << lsb)) >> lsb) + +static u32 rtl930x_l3_hash4(u32 ip, int algorithm, bool move_dip) +{ + u32 rows[4]; + u32 hash; + u32 s0, s1, pH; + + memset(rows, 0, sizeof(rows)); + + rows[0] = HASH_PICK(ip, 27, 5); + rows[1] = HASH_PICK(ip, 18, 9); + rows[2] = HASH_PICK(ip, 9, 9); + + if (!move_dip) + rows[3] = HASH_PICK(ip, 0, 9); + + if (!algorithm) { + hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3]; + } else { + s0 = rows[0] + rows[1] + rows[2]; + s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9); + pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9); + hash = pH ^ rows[3]; + } + return hash; +} + +// Currently not used +// static u32 rtl930x_l3_hash6(struct in6_addr *ip6, int algorithm, bool move_dip) +// { +// u32 rows[16]; +// u32 hash; +// u32 s0, s1, pH; + +// rows[0] = (HASH_PICK(ip6->s6_addr[0], 6, 2) << 0); +// rows[1] = (HASH_PICK(ip6->s6_addr[0], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[1], 5, 3); +// rows[2] = (HASH_PICK(ip6->s6_addr[1], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[2], 4, 4); +// rows[3] = (HASH_PICK(ip6->s6_addr[2], 0, 4) << 5) | HASH_PICK(ip6->s6_addr[3], 3, 5); +// rows[4] = (HASH_PICK(ip6->s6_addr[3], 0, 3) << 6) | HASH_PICK(ip6->s6_addr[4], 2, 6); +// rows[5] = (HASH_PICK(ip6->s6_addr[4], 0, 2) << 7) | HASH_PICK(ip6->s6_addr[5], 1, 7); +// rows[6] = (HASH_PICK(ip6->s6_addr[5], 0, 1) << 8) | HASH_PICK(ip6->s6_addr[6], 0, 8); +// rows[7] = (HASH_PICK(ip6->s6_addr[7], 0, 8) << 1) | HASH_PICK(ip6->s6_addr[8], 7, 1); +// rows[8] = (HASH_PICK(ip6->s6_addr[8], 0, 7) << 2) | HASH_PICK(ip6->s6_addr[9], 6, 2); +// rows[9] = (HASH_PICK(ip6->s6_addr[9], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[10], 5, 3); +// rows[10] = (HASH_PICK(ip6->s6_addr[10], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[11], 4, 4); +// if (!algorithm) { +// rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5) | +// (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0); +// rows[12] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) | +// (HASH_PICK(ip6->s6_addr[13], 2, 6) << 0); +// rows[13] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) | +// (HASH_PICK(ip6->s6_addr[14], 1, 7) << 0); +// if (!move_dip) { +// rows[14] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) | +// (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0); +// } +// hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^ +// rows[5] ^ rows[6] ^ rows[7] ^ rows[8] ^ rows[9] ^ +// rows[10] ^ rows[11] ^ rows[12] ^ rows[13] ^ rows[14]; +// } else { +// rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5); +// rows[12] = (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0); +// rows[13] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) | +// HASH_PICK(ip6->s6_addr[13], 2, 6); +// rows[14] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) | +// HASH_PICK(ip6->s6_addr[14], 1, 7); +// if (!move_dip) { +// rows[15] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) | +// (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0); +// } +// s0 = rows[12] + rows[13] + rows[14]; +// s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9); +// pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9); +// hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^ +// rows[5] ^ rows[6] ^ rows[7] ^ rows[8] ^ rows[9] ^ +// rows[10] ^ rows[11] ^ pH ^ rows[15]; +// } +// return hash; +// } + +/* Read a prefix route entry from the L3_PREFIX_ROUTE_IPUC table + * We currently only support IPv4 and IPv6 unicast route + */ +static void rtl930x_route_read(int idx, struct rtl83xx_route *rt) +{ + u32 v, ip4_m; + bool host_route, default_route; + struct in6_addr ip6_m; + + /* Read L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2); + + rtl_table_read(r, idx); + /* The table has a size of 11 registers */ + rt->attr.valid = !!(sw_r32(rtl_table_data(r, 0)) & BIT(31)); + if (!rt->attr.valid) + goto out; + + rt->attr.type = (sw_r32(rtl_table_data(r, 0)) >> 29) & 0x3; + + v = sw_r32(rtl_table_data(r, 10)); + host_route = !!(v & BIT(21)); + default_route = !!(v & BIT(20)); + rt->prefix_len = -1; + pr_debug("%s: host route %d, default_route %d\n", __func__, host_route, default_route); + + switch (rt->attr.type) { + case 0: /* IPv4 Unicast route */ + rt->dst_ip = sw_r32(rtl_table_data(r, 4)); + ip4_m = sw_r32(rtl_table_data(r, 9)); + pr_debug("%s: Read ip4 mask: %08x\n", __func__, ip4_m); + rt->prefix_len = host_route ? 32 : -1; + rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1; + if (rt->prefix_len < 0) + rt->prefix_len = inet_mask_len(ip4_m); + break; + case 2: /* IPv6 Unicast route */ + ipv6_addr_set(&rt->dst_ip6, + sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)), + sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4))); + ipv6_addr_set(&ip6_m, + sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)), + sw_r32(rtl_table_data(r, 8)), sw_r32(rtl_table_data(r, 9))); + rt->prefix_len = host_route ? 128 : 0; + rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1; + if (rt->prefix_len < 0) + rt->prefix_len = find_last_bit((unsigned long *)&ip6_m.s6_addr32, + 128); + break; + case 1: /* IPv4 Multicast route */ + case 3: /* IPv6 Multicast route */ + pr_warn("%s: route type not supported\n", __func__); + goto out; + } + + rt->attr.hit = !!(v & BIT(22)); + rt->attr.action = (v >> 18) & 3; + rt->nh.id = (v >> 7) & 0x7ff; + rt->attr.ttl_dec = !!(v & BIT(6)); + rt->attr.ttl_check = !!(v & BIT(5)); + rt->attr.dst_null = !!(v & BIT(4)); + rt->attr.qos_as = !!(v & BIT(3)); + rt->attr.qos_prio = v & 0x7; + pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid); + pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n", + __func__, rt->nh.id, rt->attr.hit, rt->attr.action, + rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null); + pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len); +out: + rtl_table_release(r); +} + +static void rtl930x_net6_mask(int prefix_len, struct in6_addr *ip6_m) +{ + int o, b; + /* Define network mask */ + o = prefix_len >> 3; + b = prefix_len & 0x7; + memset(ip6_m->s6_addr, 0xff, o); + ip6_m->s6_addr[o] |= b ? 0xff00 >> b : 0x00; +} + +/* Read a host route entry from the table using its index + * We currently only support IPv4 and IPv6 unicast route + */ +static void rtl930x_host_route_read(int idx, struct rtl83xx_route *rt) +{ + u32 v; + /* Read L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1); + + idx = ((idx / 6) * 8) + (idx % 6); + + pr_debug("In %s, physical index %d\n", __func__, idx); + rtl_table_read(r, idx); + /* The table has a size of 5 (for UC, 11 for MC) registers */ + v = sw_r32(rtl_table_data(r, 0)); + rt->attr.valid = !!(v & BIT(31)); + if (!rt->attr.valid) + goto out; + rt->attr.type = (v >> 29) & 0x3; + switch (rt->attr.type) { + case 0: /* IPv4 Unicast route */ + rt->dst_ip = sw_r32(rtl_table_data(r, 4)); + break; + case 2: /* IPv6 Unicast route */ + ipv6_addr_set(&rt->dst_ip6, + sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 2)), + sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 0))); + break; + case 1: /* IPv4 Multicast route */ + case 3: /* IPv6 Multicast route */ + pr_warn("%s: route type not supported\n", __func__); + goto out; + } + + rt->attr.hit = !!(v & BIT(20)); + rt->attr.dst_null = !!(v & BIT(19)); + rt->attr.action = (v >> 17) & 3; + rt->nh.id = (v >> 6) & 0x7ff; + rt->attr.ttl_dec = !!(v & BIT(5)); + rt->attr.ttl_check = !!(v & BIT(4)); + rt->attr.qos_as = !!(v & BIT(3)); + rt->attr.qos_prio = v & 0x7; + pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid); + pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n", + __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check, + rt->attr.dst_null); + pr_debug("%s: Destination: %pI4\n", __func__, &rt->dst_ip); + +out: + rtl_table_release(r); +} + +/* Write a host route entry from the table using its index + * We currently only support IPv4 and IPv6 unicast route + */ +static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt) +{ + u32 v; + /* Access L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1); + /* The table has a size of 5 (for UC, 11 for MC) registers */ + + idx = ((idx / 6) * 8) + (idx % 6); + + pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid); + pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n", + __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check, + rt->attr.dst_null); + pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len); + + v = BIT(31); /* Entry is valid */ + v |= (rt->attr.type & 0x3) << 29; + v |= rt->attr.hit ? BIT(20) : 0; + v |= rt->attr.dst_null ? BIT(19) : 0; + v |= (rt->attr.action & 0x3) << 17; + v |= (rt->nh.id & 0x7ff) << 6; + v |= rt->attr.ttl_dec ? BIT(5) : 0; + v |= rt->attr.ttl_check ? BIT(4) : 0; + v |= rt->attr.qos_as ? BIT(3) : 0; + v |= rt->attr.qos_prio & 0x7; + + sw_w32(v, rtl_table_data(r, 0)); + switch (rt->attr.type) { + case 0: /* IPv4 Unicast route */ + sw_w32(0, rtl_table_data(r, 1)); + sw_w32(0, rtl_table_data(r, 2)); + sw_w32(0, rtl_table_data(r, 3)); + sw_w32(rt->dst_ip, rtl_table_data(r, 4)); + break; + case 2: /* IPv6 Unicast route */ + sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1)); + sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2)); + sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3)); + sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4)); + break; + case 1: /* IPv4 Multicast route */ + case 3: /* IPv6 Multicast route */ + pr_warn("%s: route type not supported\n", __func__); + goto out; + } + + rtl_table_write(r, idx); + +out: + rtl_table_release(r); +} + +/* Look up the index of a prefix route in the routing table CAM for unicast IPv4/6 routes + * using hardware offload. + */ +static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt) +{ + u32 ip4_m, v; + struct in6_addr ip6_m; + + if (rt->attr.type == 1 || rt->attr.type == 3) /* Hardware only supports UC routes */ + return -1; + + sw_w32_mask(0x3 << 19, rt->attr.type, RTL930X_L3_HW_LU_KEY_CTRL); + if (rt->attr.type) { /* IPv6 */ + rtl930x_net6_mask(rt->prefix_len, &ip6_m); + for (int i = 0; i < 4; i++) + sw_w32(rt->dst_ip6.s6_addr32[0] & ip6_m.s6_addr32[0], + RTL930X_L3_HW_LU_KEY_IP_CTRL + (i << 2)); + } else { /* IPv4 */ + ip4_m = inet_make_mask(rt->prefix_len); + sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL); + sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 4); + sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 8); + v = rt->dst_ip & ip4_m; + pr_debug("%s: searching for %pI4\n", __func__, &v); + sw_w32(v, RTL930X_L3_HW_LU_KEY_IP_CTRL + 12); + } + + /* Execute CAM lookup in SoC */ + sw_w32(BIT(15), RTL930X_L3_HW_LU_CTRL); + + /* Wait until execute bit clears and result is ready */ + do { + v = sw_r32(RTL930X_L3_HW_LU_CTRL); + } while (v & BIT(15)); + + pr_debug("%s: found: %d, index: %d\n", __func__, !!(v & BIT(14)), v & 0x1ff); + + /* Test if search successful (BIT 14 set) */ + if (v & BIT(14)) + return v & 0x1ff; + + return -1; +} + +static int rtl930x_find_l3_slot(struct rtl83xx_route *rt, bool must_exist) +{ + int slot_width, algorithm, addr, idx; + u32 hash; + struct rtl83xx_route route_entry; + + /* IPv6 entries take up 3 slots */ + slot_width = (rt->attr.type == 0) || (rt->attr.type == 2) ? 1 : 3; + + for (int t = 0; t < 2; t++) { + algorithm = (sw_r32(RTL930X_L3_HOST_TBL_CTRL) >> (2 + t)) & 0x1; + hash = rtl930x_l3_hash4(rt->dst_ip, algorithm, false); + + pr_debug("%s: table %d, algorithm %d, hash %04x\n", __func__, t, algorithm, hash); + + for (int s = 0; s < 6; s += slot_width) { + addr = (t << 12) | ((hash & 0x1ff) << 3) | s; + pr_debug("%s physical address %d\n", __func__, addr); + idx = ((addr / 8) * 6) + (addr % 8); + pr_debug("%s logical address %d\n", __func__, idx); + + rtl930x_host_route_read(idx, &route_entry); + pr_debug("%s route valid %d, route dest: %pI4, hit %d\n", __func__, + rt->attr.valid, &rt->dst_ip, rt->attr.hit); + if (!must_exist && rt->attr.valid) + return idx; + if (must_exist && route_entry.dst_ip == rt->dst_ip) + return idx; + } + } + + return -1; +} + +/* Write a prefix route into the routing table CAM at position idx + * Currently only IPv4 and IPv6 unicast routes are supported + */ +static void rtl930x_route_write(int idx, struct rtl83xx_route *rt) +{ + u32 v, ip4_m; + struct in6_addr ip6_m; + /* Access L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 */ + /* The table has a size of 11 registers (20 for MC) */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2); + + pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid); + pr_debug("%s: nexthop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n", + __func__, rt->nh.id, rt->attr.hit, rt->attr.action, + rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null); + pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len); + + v = rt->attr.valid ? BIT(31) : 0; + v |= (rt->attr.type & 0x3) << 29; + sw_w32(v, rtl_table_data(r, 0)); + + v = rt->attr.hit ? BIT(22) : 0; + v |= (rt->attr.action & 0x3) << 18; + v |= (rt->nh.id & 0x7ff) << 7; + v |= rt->attr.ttl_dec ? BIT(6) : 0; + v |= rt->attr.ttl_check ? BIT(5) : 0; + v |= rt->attr.dst_null ? BIT(6) : 0; + v |= rt->attr.qos_as ? BIT(6) : 0; + v |= rt->attr.qos_prio & 0x7; + v |= rt->prefix_len == 0 ? BIT(20) : 0; /* set default route bit */ + + /* set bit mask for entry type always to 0x3 */ + sw_w32(0x3 << 29, rtl_table_data(r, 5)); + + switch (rt->attr.type) { + case 0: /* IPv4 Unicast route */ + sw_w32(0, rtl_table_data(r, 1)); + sw_w32(0, rtl_table_data(r, 2)); + sw_w32(0, rtl_table_data(r, 3)); + sw_w32(rt->dst_ip, rtl_table_data(r, 4)); + + v |= rt->prefix_len == 32 ? BIT(21) : 0; /* set host-route bit */ + ip4_m = inet_make_mask(rt->prefix_len); + sw_w32(0, rtl_table_data(r, 6)); + sw_w32(0, rtl_table_data(r, 7)); + sw_w32(0, rtl_table_data(r, 8)); + sw_w32(ip4_m, rtl_table_data(r, 9)); + break; + case 2: /* IPv6 Unicast route */ + sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1)); + sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2)); + sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3)); + sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4)); + + v |= rt->prefix_len == 128 ? BIT(21) : 0; /* set host-route bit */ + + rtl930x_net6_mask(rt->prefix_len, &ip6_m); + + sw_w32(ip6_m.s6_addr32[0], rtl_table_data(r, 6)); + sw_w32(ip6_m.s6_addr32[1], rtl_table_data(r, 7)); + sw_w32(ip6_m.s6_addr32[2], rtl_table_data(r, 8)); + sw_w32(ip6_m.s6_addr32[3], rtl_table_data(r, 9)); + break; + case 1: /* IPv4 Multicast route */ + case 3: /* IPv6 Multicast route */ + pr_warn("%s: route type not supported\n", __func__); + rtl_table_release(r); + return; + } + sw_w32(v, rtl_table_data(r, 10)); + + pr_debug("%s: %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n", __func__, + sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)), + sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)), + sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)), sw_r32(rtl_table_data(r, 8)), + sw_r32(rtl_table_data(r, 9)), sw_r32(rtl_table_data(r, 10))); + + rtl_table_write(r, idx); + rtl_table_release(r); +} + +/* Get the destination MAC and L3 egress interface ID of a nexthop entry from + * the SoC's L3_NEXTHOP table + */ +static void rtl930x_get_l3_nexthop(int idx, u16 *dmac_id, u16 *interface) +{ + u32 v; + /* Read L3_NEXTHOP table (3) via register RTL9300_TBL_1 */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3); + + rtl_table_read(r, idx); + /* The table has a size of 1 register */ + v = sw_r32(rtl_table_data(r, 0)); + rtl_table_release(r); + + *dmac_id = (v >> 7) & 0x7fff; + *interface = v & 0x7f; +} + +// Currently not used +// static int rtl930x_l3_mtu_del(struct rtl838x_switch_priv *priv, int mtu) +// { +// int i; + +// for (i = 0; i < MAX_INTF_MTUS; i++) { +// if (mtu == priv->intf_mtus[i]) +// break; +// } +// if (i >= MAX_INTF_MTUS || !priv->intf_mtu_count[i]) { +// pr_err("%s: No MTU slot found for MTU: %d\n", __func__, mtu); +// return -EINVAL; +// } + +// priv->intf_mtu_count[i]--; +// } + +// Currently not used +// static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu) +// { +// int i, free_mtu; +// int mtu_id; + +// /* Try to find an existing mtu-value or a free slot */ +// free_mtu = MAX_INTF_MTUS; +// for (i = 0; i < MAX_INTF_MTUS && priv->intf_mtus[i] != mtu; i++) { +// if ((!priv->intf_mtu_count[i]) && (free_mtu == MAX_INTF_MTUS)) +// free_mtu = i; +// } +// i = (i < MAX_INTF_MTUS) ? i : free_mtu; +// if (i < MAX_INTF_MTUS) { +// mtu_id = i; +// } else { +// pr_err("%s: No free MTU slot available!\n", __func__); +// return -EINVAL; +// } + +// priv->intf_mtus[i] = mtu; +// pr_debug("Writing MTU %d to slot %d\n", priv->intf_mtus[i], i); +// /* Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots */ +// sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16), +// RTL930X_L3_IP_MTU_CTRL(i)); +// sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16), +// RTL930X_L3_IP6_MTU_CTRL(i)); + +// priv->intf_mtu_count[i]++; + +// return mtu_id; +// } + + +// Currently not used +// /* Creates an interface for a route by setting up the HW tables in the SoC */ +// static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf) +// { +// int i, intf_id, mtu_id; +// /* number of MTU-values < 16384 */ + +// /* Use the same IPv6 mtu as the ip4 mtu for this route if unset */ +// intf->ip6_mtu = intf->ip6_mtu ? intf->ip6_mtu : intf->ip4_mtu; + +// mtu_id = rtl930x_l3_mtu_add(priv, intf->ip4_mtu); +// pr_debug("%s: added mtu %d with mtu-id %d\n", __func__, intf->ip4_mtu, mtu_id); +// if (mtu_id < 0) +// return -ENOSPC; +// intf->ip4_mtu_id = mtu_id; +// intf->ip6_mtu_id = mtu_id; + +// for (i = 0; i < MAX_INTERFACES; i++) { +// if (!priv->interfaces[i]) +// break; +// } +// if (i >= MAX_INTERFACES) { +// pr_err("%s: cannot find free interface entry\n", __func__); +// return -EINVAL; +// } +// intf_id = i; +// priv->interfaces[i] = kzalloc(sizeof(struct rtl838x_l3_intf), GFP_KERNEL); +// if (!priv->interfaces[i]) { +// pr_err("%s: no memory to allocate new interface\n", __func__); +// return -ENOMEM; +// } +// } + +/* Set the destination MAC and L3 egress interface ID for a nexthop entry in the SoC's + * L3_NEXTHOP table. The nexthop entry is identified by idx. + * dmac_id is the reference to the L2 entry in the L2 forwarding table, special values are + * 0x7ffe: TRAP2CPU + * 0x7ffd: TRAP2MASTERCPU + * 0x7fff: DMAC_ID_DROP + */ +static void rtl930x_set_l3_nexthop(int idx, u16 dmac_id, u16 interface) +{ + /* Access L3_NEXTHOP table (3) via register RTL9300_TBL_1 */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3); + + pr_debug("%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\n", + __func__, idx, dmac_id, interface); + sw_w32(((dmac_id & 0x7fff) << 7) | (interface & 0x7f), rtl_table_data(r, 0)); + + pr_debug("%s: %08x\n", __func__, sw_r32(rtl_table_data(r, 0))); + rtl_table_write(r, idx); + rtl_table_release(r); +} + +#endif /* CONFIG_NET_DSA_RTL83XX_RTL930X_L3_OFFLOAD */ + +static void rtl930x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index) +{ + int block = index / PIE_BLOCK_SIZE; + + sw_w32_mask(0, BIT(block), RTL930X_PIE_BLK_LOOKUP_CTRL); +} + +/* Reads the intermediate representation of the templated match-fields of the + * PIE rule in the pie_rule structure and fills in the raw data fields in the + * raw register space r[]. + * The register space configuration size is identical for the RTL8380/90 and RTL9300, + * however the RTL9310 has 2 more registers / fields and the physical field-ids are different + * on all SoCs + * On the RTL9300 the mask fields are not word-aligend! + */ +static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) +{ + for (int i = 0; i < N_FIXED_FIELDS; i++) { + enum template_field_id field_type = t[i]; + u16 data = 0, data_m = 0; + + switch (field_type) { + case TEMPLATE_FIELD_SPM0: + data = pr->spm; + data_m = pr->spm_m; + break; + case TEMPLATE_FIELD_SPM1: + data = pr->spm >> 16; + data_m = pr->spm_m >> 16; + break; + case TEMPLATE_FIELD_OTAG: + data = pr->otag; + data_m = pr->otag_m; + break; + case TEMPLATE_FIELD_SMAC0: + data = pr->smac[4]; + data = (data << 8) | pr->smac[5]; + data_m = pr->smac_m[4]; + data_m = (data_m << 8) | pr->smac_m[5]; + break; + case TEMPLATE_FIELD_SMAC1: + data = pr->smac[2]; + data = (data << 8) | pr->smac[3]; + data_m = pr->smac_m[2]; + data_m = (data_m << 8) | pr->smac_m[3]; + break; + case TEMPLATE_FIELD_SMAC2: + data = pr->smac[0]; + data = (data << 8) | pr->smac[1]; + data_m = pr->smac_m[0]; + data_m = (data_m << 8) | pr->smac_m[1]; + break; + case TEMPLATE_FIELD_DMAC0: + data = pr->dmac[4]; + data = (data << 8) | pr->dmac[5]; + data_m = pr->dmac_m[4]; + data_m = (data_m << 8) | pr->dmac_m[5]; + break; + case TEMPLATE_FIELD_DMAC1: + data = pr->dmac[2]; + data = (data << 8) | pr->dmac[3]; + data_m = pr->dmac_m[2]; + data_m = (data_m << 8) | pr->dmac_m[3]; + break; + case TEMPLATE_FIELD_DMAC2: + data = pr->dmac[0]; + data = (data << 8) | pr->dmac[1]; + data_m = pr->dmac_m[0]; + data_m = (data_m << 8) | pr->dmac_m[1]; + break; + case TEMPLATE_FIELD_ETHERTYPE: + data = pr->ethertype; + data_m = pr->ethertype_m; + break; + case TEMPLATE_FIELD_ITAG: + data = pr->itag; + data_m = pr->itag_m; + break; + case TEMPLATE_FIELD_SIP0: + if (pr->is_ipv6) { + data = pr->sip6.s6_addr16[7]; + data_m = pr->sip6_m.s6_addr16[7]; + } else { + data = pr->sip; + data_m = pr->sip_m; + } + break; + case TEMPLATE_FIELD_SIP1: + if (pr->is_ipv6) { + data = pr->sip6.s6_addr16[6]; + data_m = pr->sip6_m.s6_addr16[6]; + } else { + data = pr->sip >> 16; + data_m = pr->sip_m >> 16; + } + break; + case TEMPLATE_FIELD_SIP2: + case TEMPLATE_FIELD_SIP3: + case TEMPLATE_FIELD_SIP4: + case TEMPLATE_FIELD_SIP5: + case TEMPLATE_FIELD_SIP6: + case TEMPLATE_FIELD_SIP7: + data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; + data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; + break; + case TEMPLATE_FIELD_DIP0: + if (pr->is_ipv6) { + data = pr->dip6.s6_addr16[7]; + data_m = pr->dip6_m.s6_addr16[7]; + } else { + data = pr->dip; + data_m = pr->dip_m; + } + break; + case TEMPLATE_FIELD_DIP1: + if (pr->is_ipv6) { + data = pr->dip6.s6_addr16[6]; + data_m = pr->dip6_m.s6_addr16[6]; + } else { + data = pr->dip >> 16; + data_m = pr->dip_m >> 16; + } + break; + case TEMPLATE_FIELD_DIP2: + case TEMPLATE_FIELD_DIP3: + case TEMPLATE_FIELD_DIP4: + case TEMPLATE_FIELD_DIP5: + case TEMPLATE_FIELD_DIP6: + case TEMPLATE_FIELD_DIP7: + data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; + data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; + break; + case TEMPLATE_FIELD_IP_TOS_PROTO: + data = pr->tos_proto; + data_m = pr->tos_proto_m; + break; + case TEMPLATE_FIELD_L4_SPORT: + data = pr->sport; + data_m = pr->sport_m; + break; + case TEMPLATE_FIELD_L4_DPORT: + data = pr->dport; + data_m = pr->dport_m; + break; + case TEMPLATE_FIELD_DSAP_SSAP: + data = pr->dsap_ssap; + data_m = pr->dsap_ssap_m; + break; + case TEMPLATE_FIELD_TCP_INFO: + data = pr->tcp_info; + data_m = pr->tcp_info_m; + break; + case TEMPLATE_FIELD_RANGE_CHK: + pr_debug("TEMPLATE_FIELD_RANGE_CHK: not configured\n"); + break; + default: + pr_debug("%s: unknown field %d\n", __func__, field_type); + } + + /* On the RTL9300, the mask fields are not word aligned! */ + if (!(i % 2)) { + r[5 - i / 2] = data; + r[12 - i / 2] |= ((u32)data_m << 8); + } else { + r[5 - i / 2] |= ((u32)data) << 16; + r[12 - i / 2] |= ((u32)data_m) << 24; + r[11 - i / 2] |= ((u32)data_m) >> 8; + } + } +} + +// Currently not used +// static void rtl930x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr) +// { +// pr->stacking_port = r[6] & BIT(31); +// pr->spn = (r[6] >> 24) & 0x7f; +// pr->mgnt_vlan = r[6] & BIT(23); +// if (pr->phase == PHASE_IACL) +// pr->dmac_hit_sw = r[6] & BIT(22); +// else +// pr->content_too_deep = r[6] & BIT(22); +// pr->not_first_frag = r[6] & BIT(21); +// pr->frame_type_l4 = (r[6] >> 18) & 7; +// pr->frame_type = (r[6] >> 16) & 3; +// pr->otag_fmt = (r[6] >> 15) & 1; +// pr->itag_fmt = (r[6] >> 14) & 1; +// pr->otag_exist = (r[6] >> 13) & 1; +// pr->itag_exist = (r[6] >> 12) & 1; +// pr->frame_type_l2 = (r[6] >> 10) & 3; +// pr->igr_normal_port = (r[6] >> 9) & 1; +// pr->tid = (r[6] >> 8) & 1; + +// pr->stacking_port_m = r[12] & BIT(7); +// pr->spn_m = r[12] & 0x7f; +// pr->mgnt_vlan_m = r[13] & BIT(31); +// if (pr->phase == PHASE_IACL) +// pr->dmac_hit_sw_m = r[13] & BIT(30); +// else +// pr->content_too_deep_m = r[13] & BIT(30); +// pr->not_first_frag_m = r[13] & BIT(29); +// pr->frame_type_l4_m = (r[13] >> 26) & 7; +// pr->frame_type_m = (r[13] >> 24) & 3; +// pr->otag_fmt_m = r[13] & BIT(23); +// pr->itag_fmt_m = r[13] & BIT(22); +// pr->otag_exist_m = r[13] & BIT(21); +// pr->itag_exist_m = r[13] & BIT (20); +// pr->frame_type_l2_m = (r[13] >> 18) & 3; +// pr->igr_normal_port_m = r[13] & BIT(17); +// pr->tid_m = (r[13] >> 16) & 1; + +// pr->valid = r[13] & BIT(15); +// pr->cond_not = r[13] & BIT(14); +// pr->cond_and1 = r[13] & BIT(13); +// pr->cond_and2 = r[13] & BIT(12); +// } + +static void rtl930x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr) +{ + r[6] = pr->stacking_port ? BIT(31) : 0; + r[6] |= ((u32)(pr->spn & 0x7f)) << 24; + r[6] |= pr->mgnt_vlan ? BIT(23) : 0; + if (pr->phase == PHASE_IACL) + r[6] |= pr->dmac_hit_sw ? BIT(22) : 0; + else + r[6] |= pr->content_too_deep ? BIT(22) : 0; + r[6] |= pr->not_first_frag ? BIT(21) : 0; + r[6] |= ((u32)(pr->frame_type_l4 & 0x7)) << 18; + r[6] |= ((u32)(pr->frame_type & 0x3)) << 16; + r[6] |= pr->otag_fmt ? BIT(15) : 0; + r[6] |= pr->itag_fmt ? BIT(14) : 0; + r[6] |= pr->otag_exist ? BIT(13) : 0; + r[6] |= pr->itag_exist ? BIT(12) : 0; + r[6] |= ((u32)(pr->frame_type_l2 & 0x3)) << 10; + r[6] |= pr->igr_normal_port ? BIT(9) : 0; + r[6] |= ((u32)(pr->tid & 0x1)) << 8; + + r[12] |= pr->stacking_port_m ? BIT(7) : 0; + r[12] |= (u32)(pr->spn_m & 0x7f); + r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0; + if (pr->phase == PHASE_IACL) + r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0; + else + r[13] |= pr->content_too_deep_m ? BIT(30) : 0; + r[13] |= pr->not_first_frag_m ? BIT(29) : 0; + r[13] |= ((u32)(pr->frame_type_l4_m & 0x7)) << 26; + r[13] |= ((u32)(pr->frame_type_m & 0x3)) << 24; + r[13] |= pr->otag_fmt_m ? BIT(23) : 0; + r[13] |= pr->itag_fmt_m ? BIT(22) : 0; + r[13] |= pr->otag_exist_m ? BIT(21) : 0; + r[13] |= pr->itag_exist_m ? BIT(20) : 0; + r[13] |= ((u32)(pr->frame_type_l2_m & 0x3)) << 18; + r[13] |= pr->igr_normal_port_m ? BIT(17) : 0; + r[13] |= ((u32)(pr->tid_m & 0x1)) << 16; + + r[13] |= pr->valid ? BIT(15) : 0; + r[13] |= pr->cond_not ? BIT(14) : 0; + r[13] |= pr->cond_and1 ? BIT(13) : 0; + r[13] |= pr->cond_and2 ? BIT(12) : 0; +} + +static void rtl930x_write_pie_action(u32 r[], struct pie_rule *pr) +{ + /* Either drop or forward */ + if (pr->drop) { + r[14] |= BIT(24) | BIT(25) | BIT(26); /* Do Green, Yellow and Red drops */ + /* Actually DROP, not PERMIT in Green / Yellow / Red */ + r[14] |= BIT(23) | BIT(22) | BIT(20); + } else { + r[14] |= pr->fwd_sel ? BIT(27) : 0; + r[14] |= pr->fwd_act << 18; + r[14] |= BIT(14); /* We overwrite any drop */ + } + if (pr->phase == PHASE_VACL) + r[14] |= pr->fwd_sa_lrn ? BIT(15) : 0; + r[13] |= pr->bypass_sel ? BIT(5) : 0; + r[13] |= pr->nopri_sel ? BIT(4) : 0; + r[13] |= pr->tagst_sel ? BIT(3) : 0; + r[13] |= pr->ovid_sel ? BIT(1) : 0; + r[14] |= pr->ivid_sel ? BIT(31) : 0; + r[14] |= pr->meter_sel ? BIT(30) : 0; + r[14] |= pr->mir_sel ? BIT(29) : 0; + r[14] |= pr->log_sel ? BIT(28) : 0; + + r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 3; + r[15] |= pr->log_octets ? BIT(31) : 0; + r[15] |= (u32)(pr->meter_data) << 23; + + r[15] |= ((u32)(pr->ivid_act) << 21) & 0x3; + r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff; + r[16] |= ((u32)(pr->ovid_act) << 30) & 0x3; + r[16] |= ((u32)(pr->ovid_data) & 0xfff) << 16; + r[16] |= (pr->mir_data & 0x3) << 6; + r[17] |= ((u32)(pr->tagst_data) & 0xf) << 28; + r[17] |= ((u32)(pr->nopri_data) & 0x7) << 25; + r[17] |= pr->bypass_ibc_sc ? BIT(16) : 0; +} + +void rtl930x_pie_rule_dump_raw(u32 r[]) +{ + pr_debug("Raw IACL table entry:\n"); + pr_debug("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n", + r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]); + pr_debug("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n", + r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]); + pr_debug("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]); + pr_debug("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]); + pr_debug("Fixed : %06x\n", r[6] >> 8); + pr_debug("Match M: %08x %08x %08x %08x %08x %08x\n", + (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8), + (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8), + (r[11] << 24) | (r[12] >> 8)); + pr_debug("R[13]: %08x\n", r[13]); + pr_debug("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff); + pr_debug("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf); + pr_debug("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]); +} + +static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) +{ + /* Access IACL table (2) via register 0 */ + struct table_reg *q = rtl_table_get(RTL9300_TBL_0, 2); + u32 r[19]; + int block = idx / PIE_BLOCK_SIZE; + u32 t_select = sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)); + + pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select); + + for (int i = 0; i < 19; i++) + r[i] = 0; + + if (!pr->valid) { + rtl_table_write(q, idx); + rtl_table_release(q); + return 0; + } + rtl930x_write_pie_fixed_fields(r, pr); + + pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf); + rtl930x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]); + + rtl930x_write_pie_action(r, pr); + +/* rtl930x_pie_rule_dump_raw(r); */ + + for (int i = 0; i < 19; i++) + sw_w32(r[i], rtl_table_data(q, i)); + + rtl_table_write(q, idx); + rtl_table_release(q); + + return 0; +} + +static bool rtl930x_pie_templ_has(int t, enum template_field_id field_type) +{ + for (int i = 0; i < N_FIXED_FIELDS; i++) { + enum template_field_id ft = fixed_templates[t][i]; + + if (field_type == ft) + return true; + } + + return false; +} + +/* Verify that the rule pr is compatible with a given template t in block + * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0 + * depend on the SoC + */ +static int rtl930x_pie_verify_template(struct rtl838x_switch_priv *priv, + struct pie_rule *pr, int t, int block) +{ + int i; + + if (!pr->is_ipv6 && pr->sip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP0)) + return -1; + + if (!pr->is_ipv6 && pr->dip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP0)) + return -1; + + if (pr->is_ipv6) { + if ((pr->sip6_m.s6_addr32[0] || + pr->sip6_m.s6_addr32[1] || + pr->sip6_m.s6_addr32[2] || + pr->sip6_m.s6_addr32[3]) && + !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) + return -1; + if ((pr->dip6_m.s6_addr32[0] || + pr->dip6_m.s6_addr32[1] || + pr->dip6_m.s6_addr32[2] || + pr->dip6_m.s6_addr32[3]) && + !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) + return -1; + } + + if (ether_addr_to_u64(pr->smac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0)) + return -1; + + if (ether_addr_to_u64(pr->dmac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0)) + return -1; + + /* TODO: Check more */ + + i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE); + + if (i >= PIE_BLOCK_SIZE) + return -1; + + return i + PIE_BLOCK_SIZE * block; +} + +static int rtl930x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr) +{ + int idx, block, j, t; + int min_block = 0; + int max_block = priv->r->n_pie_blocks / 2; + + if (pr->is_egress) { + min_block = max_block; + max_block = priv->r->n_pie_blocks; + } + pr_debug("In %s\n", __func__); + + mutex_lock(&priv->pie_mutex); + + for (block = min_block; block < max_block; block++) { + for (j = 0; j < 2; j++) { + t = (sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf; + pr_debug("Testing block %d, template %d, template id %d\n", block, j, t); + pr_debug("%s: %08x\n", + __func__, sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block))); + idx = rtl930x_pie_verify_template(priv, pr, t, block); + if (idx >= 0) + break; + } + if (j < 2) + break; + } + + if (block >= priv->r->n_pie_blocks) { + mutex_unlock(&priv->pie_mutex); + return -EOPNOTSUPP; + } + + pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j); + set_bit(idx, priv->pie_use_bm); + + pr->valid = true; + pr->tid = j; /* Mapped to template number */ + pr->tid_m = 0x1; + pr->id = idx; + + rtl930x_pie_lookup_enable(priv, idx); + rtl930x_pie_rule_write(priv, idx, pr); + + mutex_unlock(&priv->pie_mutex); + return 0; +} + +/* Delete a range of Packet Inspection Engine rules */ +static int rtl930x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to) +{ + u32 v = (index_from << 1) | (index_to << 12) | BIT(0); + + pr_debug("%s: from %d to %d\n", __func__, index_from, index_to); + mutex_lock(&priv->reg_mutex); + + /* Write from-to and execute bit into control register */ + sw_w32(v, RTL930X_PIE_CLR_CTRL); + + /* Wait until command has completed */ + do { + } while (sw_r32(RTL930X_PIE_CLR_CTRL) & BIT(0)); + + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static void rtl930x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr) +{ + int idx = pr->id; + + rtl930x_pie_rule_del(priv, idx, idx); + clear_bit(idx, priv->pie_use_bm); +} + +static void rtl930x_pie_init(struct rtl838x_switch_priv *priv) +{ + u32 template_selectors; + + mutex_init(&priv->pie_mutex); + + pr_debug("%s\n", __func__); + /* Enable ACL lookup on all ports, including CPU_PORT */ + for (int i = 0; i <= priv->cpu_port; i++) + sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i)); + + /* Include IPG in metering */ + sw_w32_mask(0, 1, RTL930X_METER_GLB_CTRL); + + /* Delete all present rules, block size is 128 on all SoC families */ + rtl930x_pie_rule_del(priv, 0, priv->r->n_pie_blocks * 128 - 1); + + /* Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1) */ + sw_w32(0xff00, RTL930X_PIE_BLK_PHASE_CTRL); + + /* Enable predefined templates 0, 1 for first quarter of all blocks */ + template_selectors = 0 | (1 << 4); + for (int i = 0; i < priv->r->n_pie_blocks / 4; i++) + sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); + + /* Enable predefined templates 2, 3 for second quarter of all blocks */ + template_selectors = 2 | (3 << 4); + for (int i = priv->r->n_pie_blocks / 4; i < priv->r->n_pie_blocks / 2; i++) + sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); + + /* Enable predefined templates 0, 1 for third half of all blocks */ + template_selectors = 0 | (1 << 4); + for (int i = priv->r->n_pie_blocks / 2; i < priv->r->n_pie_blocks * 3 / 4; i++) + sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); + + /* Enable predefined templates 2, 3 for fourth quater of all blocks */ + template_selectors = 2 | (3 << 4); + for (int i = priv->r->n_pie_blocks * 3 / 4; i < priv->r->n_pie_blocks; i++) + sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); +} + +#ifdef CONFIG_NET_DSA_RTL83XX_RTL930X_L3_OFFLOAD + +/* Sets up an egress interface for L3 actions + * Actions for ip4/6_icmp_redirect, ip4/6_pbr_icmp_redirect are: + * 0: FORWARD, 1: DROP, 2: TRAP2CPU, 3: COPY2CPU, 4: TRAP2MASTERCPU 5: COPY2MASTERCPU + * 6: HARDDROP + * idx is the index in the HW interface table: idx < 0x80 + */ +static void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf) +{ + u32 u, v; + /* Read L3_EGR_INTF table (4) via register RTL9300_TBL_1 */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 4); + + /* The table has 2 registers */ + u = (intf->vid & 0xfff) << 9; + u |= (intf->smac_idx & 0x3f) << 3; + u |= (intf->ip4_mtu_id & 0x7); + + v = (intf->ip6_mtu_id & 0x7) << 28; + v |= (intf->ttl_scope & 0xff) << 20; + v |= (intf->hl_scope & 0xff) << 12; + v |= (intf->ip4_icmp_redirect & 0x7) << 9; + v |= (intf->ip6_icmp_redirect & 0x7) << 6; + v |= (intf->ip4_pbr_icmp_redirect & 0x7) << 3; + v |= (intf->ip6_pbr_icmp_redirect & 0x7); + + sw_w32(u, rtl_table_data(r, 0)); + sw_w32(v, rtl_table_data(r, 1)); + + pr_debug("%s writing to index %d: %08x %08x\n", __func__, idx, u, v); + rtl_table_write(r, idx & 0x7f); + rtl_table_release(r); +} + +/* Reads a MAC entry for L3 termination as entry point for routing + * from the hardware table + * idx is the index into the L3_ROUTER_MAC table + */ +static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) +{ + u32 v, w; + /* Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0); + + rtl_table_read(r, idx); + /* The table has a size of 7 registers, 64 entries */ + v = sw_r32(rtl_table_data(r, 0)); + w = sw_r32(rtl_table_data(r, 3)); + m->valid = !!(v & BIT(20)); + if (!m->valid) + goto out; + + m->p_type = !!(v & BIT(19)); + m->p_id = (v >> 13) & 0x3f; /* trunk id of port */ + m->vid = v & 0xfff; + m->vid_mask = w & 0xfff; + m->action = sw_r32(rtl_table_data(r, 6)) & 0x7; + m->mac_mask = ((((u64)sw_r32(rtl_table_data(r, 5))) << 32) & 0xffffffffffffULL) | + (sw_r32(rtl_table_data(r, 4))); + m->mac = ((((u64)sw_r32(rtl_table_data(r, 1))) << 32) & 0xffffffffffffULL) | + (sw_r32(rtl_table_data(r, 2))); + /* Bits L3_INTF and BMSK_L3_INTF are 0 */ + +out: + rtl_table_release(r); +} + +/* Writes a MAC entry for L3 termination as entry point for routing + * into the hardware table + * idx is the index into the L3_ROUTER_MAC table + */ +static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) +{ + u32 v, w; + /* Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0); + + /* The table has a size of 7 registers, 64 entries */ + v = BIT(20); /* mac entry valid, port type is 0: individual */ + v |= (m->p_id & 0x3f) << 13; + v |= (m->vid & 0xfff); /* Set the interface_id to the vlan id */ + + w = m->vid_mask; + w |= (m->p_id_mask & 0x3f) << 13; + + sw_w32(v, rtl_table_data(r, 0)); + sw_w32(w, rtl_table_data(r, 3)); + + /* Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0 */ + sw_w32((u32)(m->mac), rtl_table_data(r, 2)); + sw_w32(m->mac >> 32, rtl_table_data(r, 1)); + + /* Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0 */ + sw_w32((u32)(m->mac_mask >> 32), rtl_table_data(r, 4)); + sw_w32((u32)m->mac_mask, rtl_table_data(r, 5)); + + sw_w32(m->action & 0x7, rtl_table_data(r, 6)); + + pr_debug("%s writing index %d: %08x %08x %08x %08x %08x %08x %08x\n", __func__, idx, + sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)), + sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)), + sw_r32(rtl_table_data(r, 6)) + ); + rtl_table_write(r, idx); + rtl_table_release(r); +} + +/* Get the Destination-MAC of an L3 egress interface or the Source MAC for routed packets + * from the SoC's L3_EGR_INTF_MAC table + * Indexes 0-2047 are DMACs, 2048+ are SMACs + */ +static u64 rtl930x_get_l3_egress_mac(u32 idx) +{ + u64 mac; + /* Read L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2); + + rtl_table_read(r, idx); + /* The table has a size of 2 registers */ + mac = sw_r32(rtl_table_data(r, 0)); + mac <<= 32; + mac |= sw_r32(rtl_table_data(r, 1)); + rtl_table_release(r); + + return mac; +} + +/* Set the Destination-MAC of a route or the Source MAC of an L3 egress interface + * in the SoC's L3_EGR_INTF_MAC table + * Indexes 0-2047 are DMACs, 2048+ are SMACs + */ +static void rtl930x_set_l3_egress_mac(u32 idx, u64 mac) +{ + /* Access L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2); + + /* The table has a size of 2 registers */ + sw_w32(mac >> 32, rtl_table_data(r, 0)); + sw_w32(mac, rtl_table_data(r, 1)); + + pr_debug("%s: setting index %d to %016llx\n", __func__, idx, mac); + rtl_table_write(r, idx); + rtl_table_release(r); +} + +/* Configure L3 routing settings of the device: + * - MTUs + * - Egress interface + * - The router's MAC address on which routed packets are expected + * - MAC addresses used as source macs of routed packets + */ +static int rtl930x_l3_setup(struct rtl838x_switch_priv *priv) +{ + /* Setup MTU with id 0 for default interface */ + for (int i = 0; i < MAX_INTF_MTUS; i++) + priv->intf_mtu_count[i] = priv->intf_mtus[i] = 0; + + priv->intf_mtu_count[0] = 0; /* Needs to stay forever */ + priv->intf_mtus[0] = DEFAULT_MTU; + sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(0)); + sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(0)); + priv->intf_mtus[1] = DEFAULT_MTU; + sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(0)); + sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(0)); + + sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(1)); + sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(1)); + sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(1)); + sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(1)); + + /* Clear all source port MACs */ + for (int i = 0; i < MAX_SMACS; i++) + rtl930x_set_l3_egress_mac(L3_EGRESS_DMACS + i, 0ULL); + + /* Configure the default L3 hash algorithm */ + sw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 0 = 0 */ + sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 1 = 1 */ + + pr_debug("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n", + sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL), + sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL)); + sw_w32_mask(0, 1, RTL930X_L3_IPUC_ROUTE_CTRL); + sw_w32_mask(0, 1, RTL930X_L3_IP6UC_ROUTE_CTRL); + sw_w32_mask(0, 1, RTL930X_L3_IPMC_ROUTE_CTRL); + sw_w32_mask(0, 1, RTL930X_L3_IP6MC_ROUTE_CTRL); + + sw_w32(0x00002001, RTL930X_L3_IPUC_ROUTE_CTRL); + sw_w32(0x00014581, RTL930X_L3_IP6UC_ROUTE_CTRL); + sw_w32(0x00000501, RTL930X_L3_IPMC_ROUTE_CTRL); + sw_w32(0x00012881, RTL930X_L3_IP6MC_ROUTE_CTRL); + + pr_debug("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n", + sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL), + sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL)); + + /* Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable) */ + sw_w32_mask(0x3 << 8, 0x1 << 8, RTL930X_L3_IP_ROUTE_CTRL); + pr_debug("L3_IP_ROUTE_CTRL %08x\n", sw_r32(RTL930X_L3_IP_ROUTE_CTRL)); + + /* PORT_ISO_RESTRICT_ROUTE_CTRL? */ + + /* Do not use prefix route 0 because of HW limitations */ + set_bit(0, priv->route_use_bm); + + return 0; +} + +#endif /* CONFIG_NET_DSA_RTL83XX_RTL930X_L3_OFFLOAD */ + +static u32 rtl930x_packet_cntr_read(int counter) +{ + u32 v; + + /* Read LOG table (3) via register RTL9300_TBL_0 */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3); + + pr_debug("In %s, id %d\n", __func__, counter); + rtl_table_read(r, counter / 2); + + pr_debug("Registers: %08x %08x\n", + sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1))); + /* The table has a size of 2 registers */ + if (counter % 2) + v = sw_r32(rtl_table_data(r, 0)); + else + v = sw_r32(rtl_table_data(r, 1)); + + rtl_table_release(r); + + return v; +} + +static void rtl930x_packet_cntr_clear(int counter) +{ + /* Access LOG table (3) via register RTL9300_TBL_0 */ + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3); + + pr_debug("In %s, id %d\n", __func__, counter); + /* The table has a size of 2 registers */ + if (counter % 2) + sw_w32(0, rtl_table_data(r, 0)); + else + sw_w32(0, rtl_table_data(r, 1)); + + rtl_table_write(r, counter / 2); + + rtl_table_release(r); +} + +static void rtl930x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) +{ + sw_w32(FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK, + keep_outer ? RTL930X_VLAN_PORT_TAG_STS_TAGGED : RTL930X_VLAN_PORT_TAG_STS_UNTAG) | + FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK, + keep_inner ? RTL930X_VLAN_PORT_TAG_STS_TAGGED : RTL930X_VLAN_PORT_TAG_STS_UNTAG), + RTL930X_VLAN_PORT_TAG_STS_CTRL(port)); +} + +static void rtl930x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0x3, mode, RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); + else + sw_w32_mask(0x3 << 14, mode << 14, RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); +} + +static void rtl930x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0xfff << 2, pvid << 2, RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); + else + sw_w32_mask(0xfff << 16, pvid << 16, RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); +} + +static int rtldsa_930x_fast_age(struct rtl838x_switch_priv *priv, int port, int vid) +{ + u32 val; + + sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4); + + val = 0; + val |= BIT(26); /* compare port id */ + val |= BIT(30); /* status - trigger flush */ + if (vid >= 0) { + val |= BIT(28); /* compare VID */ + val |= vid << 12; + } + + sw_w32(val, RTL930X_L2_TBL_FLUSH_CTRL); + + do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30)); + + return 0; +} + +static int rtl930x_set_ageing_time(unsigned long msec) +{ + int t = sw_r32(RTL930X_L2_AGE_CTRL); + + t &= 0x1FFFFF; + t = (t * 7) / 10; + pr_debug("L2 AGING time: %d sec\n", t); + + t = (msec / 100 + 6) / 7; + t = t > 0x1FFFFF ? 0x1FFFFF : t; + sw_w32_mask(0x1FFFFF, t, RTL930X_L2_AGE_CTRL); + pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL930X_L2_PORT_AGE_CTRL)); + + return 0; +} + +static void rtl930x_set_igr_filter(int port, enum igr_filter state) +{ + sw_w32_mask(0x3 << ((port & 0xf) << 1), state << ((port & 0xf) << 1), + RTL930X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2))); +} + +static void rtl930x_set_egr_filter(int port, enum egr_filter state) +{ + sw_w32_mask(0x1 << (port % 0x1D), state << (port % 0x1D), + RTL930X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2))); +} + +static void rtldsa_930x_led_get_forced(const struct device_node *node, + const u8 leds_in_set[4], + u8 forced_leds_per_port[RTL930X_CPU_PORT]) +{ + DECLARE_BITMAP(mask, RTL930X_CPU_PORT); + unsigned int port; + char set_str[36]; + u32 pm; + + for (u8 set = 0; set < 4; set++) { + snprintf(set_str, sizeof(set_str), "realtek,led-set%d-force-port-mask", set); + if (of_property_read_u32(node, set_str, &pm)) + continue; + + bitmap_from_arr32(mask, &pm, RTL930X_CPU_PORT); + + for_each_set_bit(port, mask, RTL930X_CPU_PORT) + forced_leds_per_port[port] = leds_in_set[set]; + } +} + +static void rtl930x_led_init(struct rtl838x_switch_priv *priv) +{ + u8 forced_leds_per_port[RTL930X_CPU_PORT] = {}; + struct device_node *node; + struct device *dev = priv->dev; + u8 leds_in_set[4] = {}; + u32 pm = 0; + + node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds"); + if (!node) { + dev_dbg(dev, "No compatible LED node found\n"); + return; + } + + for (int set = 0; set < 4; set++) { + char set_name[16] = {0}; + u32 set_config[4]; + int leds_in_this_set = 0; + + /* Reset LED set configuration */ + sw_w32(0, RTL930X_LED_SETX_0_CTRL(set)); + sw_w32(0, RTL930X_LED_SETX_1_CTRL(set)); + + /* Each LED set has (up to) 4 LEDs, and each LED is configured + * with 16 bits. So each 32 bit register holds configuration for + * 2 LEDs. Therefore, each set requires 2 registers for + * configuring all 4 LEDs. + */ + snprintf(set_name, sizeof(set_name), "led_set%d", set); + leds_in_this_set = of_property_count_u32_elems(node, set_name); + + if (leds_in_this_set <= 0 || leds_in_this_set > ARRAY_SIZE(set_config)) { + if (leds_in_this_set != -EINVAL) { + dev_err(dev, "%s invalid, skipping this set, leds_in_this_set=%d, should be (0, %d]\n", + set_name, leds_in_this_set, ARRAY_SIZE(set_config)); + } + + continue; + } + + dev_info(dev, "%s has %d LEDs configured\n", set_name, leds_in_this_set); + leds_in_set[set] = leds_in_this_set; + + if (of_property_read_u32_array(node, set_name, set_config, leds_in_this_set)) + break; + + /* Write configuration for selected LEDs */ + for (int i = 0, led = leds_in_this_set - 1; led >= 0; led--, i++) { + sw_w32_mask(0xffff << RTL930X_LED_SET_LEDX_SHIFT(led), + (0xffff & set_config[i]) << RTL930X_LED_SET_LEDX_SHIFT(led), + RTL930X_LED_SETX_LEDY(set, led)); + } + } + + rtldsa_930x_led_get_forced(node, leds_in_set, forced_leds_per_port); + + for (int i = 0; i < priv->cpu_port; i++) { + int pos = (i << 1) % 32; + u32 set; + + sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i)); + sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i)); + + if (!priv->ports[i].phy && !priv->ports[i].pcs && !(forced_leds_per_port[i])) + continue; + + if (forced_leds_per_port[i] > 0) + priv->ports[i].leds_on_this_port = forced_leds_per_port[i]; + + /* 0x0 = 1 led, 0x1 = 2 leds, 0x2 = 3 leds, 0x3 = 4 leds per port */ + sw_w32_mask(0x3 << pos, (priv->ports[i].leds_on_this_port - 1) << pos, RTL930X_LED_PORT_NUM_CTRL(i)); + + pm |= BIT(i); + + set = priv->ports[i].led_set; + sw_w32_mask(0, set << pos, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i)); + sw_w32_mask(0, set << pos, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i)); + } + + /* Set LED mode to serial (0x1) */ + sw_w32_mask(0x3, 0x1, RTL930X_LED_GLB_CTRL); + + /* Set LED active state */ + if (of_property_read_bool(node, "active-low")) + sw_w32_mask(RTL930X_LED_GLB_ACTIVE_LOW, 0, RTL930X_LED_GLB_CTRL); + else + sw_w32_mask(0, RTL930X_LED_GLB_ACTIVE_LOW, RTL930X_LED_GLB_CTRL); + + /* Set port type masks */ + sw_w32(pm, RTL930X_LED_PORT_COPR_MASK_CTRL); + sw_w32(pm, RTL930X_LED_PORT_FIB_MASK_CTRL); + sw_w32(pm, RTL930X_LED_PORT_COMBO_MASK_CTRL); + + for (int i = 0; i < 24; i++) + dev_dbg(dev, "%08x: %08x\n", 0xbb00cc00 + i * 4, sw_r32(0xcc00 + i * 4)); +} + +static void rtldsa_930x_qos_set_group_selector(int port, int group) +{ + sw_w32_mask(RTL93XX_PORT_TBL_IDX_CTRL_IDX_MASK(port), + group << RTL93XX_PORT_TBL_IDX_CTRL_IDX_OFFSET(port), + RTL930X_PORT_TBL_IDX_CTRL(port)); +} + +static void rtldsa_930x_qos_setup_default_dscp2queue_map(void) +{ + u32 queue; + + /* The default mapping between dscp and queue is based on + * the first 3 bits indicate the precedence (prio = dscp >> 3). + */ + for (int i = 0; i < DSCP_MAP_MAX; i++) { + queue = (i >> 3) << RTL93XX_REMAP_DSCP_INTPRI_DSCP_OFFSET(i); + sw_w32_mask(RTL93XX_REMAP_DSCP_INTPRI_DSCP_MASK(i), + queue, RTL930X_REMAP_DSCP(i)); + } +} + +static void rtldsa_930x_qos_prio2queue_matrix(int *min_queues) +{ + u32 v = 0; + + for (int i = 0; i < MAX_PRIOS; i++) + v |= i << (min_queues[i] * 3); + + sw_w32(v, RTL930X_QM_INTPRI2QID_CTRL); +} + +static void rtldsa_930x_qos_set_scheduling_queue_weights(struct rtl838x_switch_priv *priv) +{ + struct dsa_port *dp; + u32 addr; + + dsa_switch_for_each_user_port(dp, priv->ds) { + for (int q = 0; q < 8; q++) { + if (dp->index < 24) + addr = RTL930X_SCHED_PORT_Q_CTRL_SET0(dp->index, q); + else + addr = RTL930X_SCHED_PORT_Q_CTRL_SET1(dp->index, q); + + sw_w32(rtldsa_default_queue_weights[q], addr); + } + } +} + +static void rtldsa_930x_qos_init(struct rtl838x_switch_priv *priv) +{ + struct dsa_port *dp; + u32 v; + + /* Assign all the ports to the Group-0 */ + dsa_switch_for_each_user_port(dp, priv->ds) + rtldsa_930x_qos_set_group_selector(dp->index, 0); + + rtldsa_930x_qos_prio2queue_matrix(rtldsa_max_available_queue); + + /* configure priority weights */ + v = 0; + v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_PORT_MASK, 3); + v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_DSCP_MASK, 5); + v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_ITAG_MASK, 6); + v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_OTAG_MASK, 7); + + sw_w32(v, RTL930X_PRI_SEL_TBL_CTRL(0)); + + rtldsa_930x_qos_setup_default_dscp2queue_map(); + rtldsa_930x_qos_set_scheduling_queue_weights(priv); +} + +const struct rtldsa_config rtldsa_930x_cfg = { + .mask_port_reg_be = rtl838x_mask_port_reg, + .set_port_reg_be = rtl838x_set_port_reg, + .get_port_reg_be = rtl838x_get_port_reg, + .mask_port_reg_le = rtl838x_mask_port_reg, + .set_port_reg_le = rtl838x_set_port_reg, + .get_port_reg_le = rtl838x_get_port_reg, + .stat_port_rst = RTL930X_STAT_PORT_RST, + .stat_rst = RTL930X_STAT_RST, + .stat_port_std_mib = RTL930X_STAT_PORT_MIB_CNTR, + .stat_port_prv_mib = RTL930X_STAT_PORT_PRVTE_CNTR, + .mib_desc = &rtldsa_930x_mib_desc, + .stat_counters_lock = rtldsa_counters_lock_register, + .stat_counters_unlock = rtldsa_counters_unlock_register, + .stat_update_counters_atomically = rtldsa_update_counters_atomically, + .stat_counter_poll_interval = RTLDSA_COUNTERS_POLL_INTERVAL, + .traffic_enable = rtl930x_traffic_enable, + .traffic_disable = rtl930x_traffic_disable, + .traffic_set = rtl930x_traffic_set, + .l2_ctrl_0 = RTL930X_L2_CTRL, + .l2_ctrl_1 = RTL930X_L2_AGE_CTRL, + .l2_port_aging_out = RTL930X_L2_PORT_AGE_CTRL, + .set_ageing_time = rtl930x_set_ageing_time, + .smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, /* TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL */ + .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL, + .exec_tbl0_cmd = rtl930x_exec_tbl0_cmd, + .exec_tbl1_cmd = rtl930x_exec_tbl1_cmd, + .tbl_access_data_0 = rtl930x_tbl_access_data_0, + .isr_glb_src = RTL930X_ISR_GLB, + .isr_port_link_sts_chg = RTL930X_ISR_PORT_LINK_STS_CHG, + .imr_port_link_sts_chg = RTL930X_IMR_PORT_LINK_STS_CHG, + .imr_glb = RTL930X_IMR_GLB, + .n_counters = 2048, + .n_pie_blocks = 16, + .port_ignore = 0x3f, + .vlan_tables_read = rtl930x_vlan_tables_read, + .vlan_set_tagged = rtl930x_vlan_set_tagged, + .vlan_set_untagged = rtl930x_vlan_set_untagged, + .vlan_profile_get = rtldsa_930x_vlan_profile_get, + .vlan_profile_dump = rtldsa_930x_vlan_profile_dump, + .vlan_profile_setup = rtl930x_vlan_profile_setup, + .vlan_fwd_on_inner = rtl930x_vlan_fwd_on_inner, + .set_vlan_igr_filter = rtl930x_set_igr_filter, + .set_vlan_egr_filter = rtl930x_set_egr_filter, + .stp_get = rtldsa_930x_stp_get, + .stp_set = rtl930x_stp_set, + .mac_link_sts = RTL930X_MAC_LINK_STS, + .mac_force_mode_ctrl = rtl930x_mac_force_mode_ctrl, + .mac_port_ctrl = rtl930x_mac_port_ctrl, + .l2_port_new_salrn = rtl930x_l2_port_new_salrn, + .l2_port_new_sa_fwd = rtl930x_l2_port_new_sa_fwd, + .get_mirror_config = rtldsa_930x_get_mirror_config, + .port_rate_police_add = rtldsa_930x_port_rate_police_add, + .port_rate_police_del = rtldsa_930x_port_rate_police_del, + .print_matrix = rtldsa_930x_print_matrix, + .read_l2_entry_using_hash = rtl930x_read_l2_entry_using_hash, + .write_l2_entry_using_hash = rtl930x_write_l2_entry_using_hash, + .read_cam = rtl930x_read_cam, + .write_cam = rtl930x_write_cam, + .vlan_port_keep_tag_set = rtl930x_vlan_port_keep_tag_set, + .vlan_port_pvidmode_set = rtl930x_vlan_port_pvidmode_set, + .vlan_port_pvid_set = rtl930x_vlan_port_pvid_set, + .fast_age = rtldsa_930x_fast_age, + .trk_mbr_ctr = rtl930x_trk_mbr_ctr, + .rma_bpdu_fld_pmask = RTL930X_RMA_BPDU_FLD_PMSK, + .init_eee = rtl930x_init_eee, + .set_mac_eee = rtldsa_930x_set_mac_eee, + .l2_hash_seed = rtl930x_l2_hash_seed, + .l2_hash_key = rtl930x_l2_hash_key, + .read_mcast_pmask = rtl930x_read_mcast_pmask, + .write_mcast_pmask = rtl930x_write_mcast_pmask, + .pie_init = rtl930x_pie_init, + .pie_rule_write = rtl930x_pie_rule_write, + .pie_rule_add = rtl930x_pie_rule_add, + .pie_rule_rm = rtl930x_pie_rule_rm, + .l2_learning_setup = rtl930x_l2_learning_setup, + .packet_cntr_read = rtl930x_packet_cntr_read, + .packet_cntr_clear = rtl930x_packet_cntr_clear, +#ifdef CONFIG_NET_DSA_RTL83XX_RTL930X_L3_OFFLOAD + .route_read = rtl930x_route_read, + .route_write = rtl930x_route_write, + .host_route_write = rtl930x_host_route_write, + .l3_setup = rtl930x_l3_setup, + .set_l3_nexthop = rtl930x_set_l3_nexthop, + .get_l3_nexthop = rtl930x_get_l3_nexthop, + .get_l3_egress_mac = rtl930x_get_l3_egress_mac, + .set_l3_egress_mac = rtl930x_set_l3_egress_mac, + .find_l3_slot = rtl930x_find_l3_slot, + .route_lookup_hw = rtl930x_route_lookup_hw, + .get_l3_router_mac = rtl930x_get_l3_router_mac, + .set_l3_router_mac = rtl930x_set_l3_router_mac, + .set_l3_egress_intf = rtl930x_set_l3_egress_intf, +#endif + .led_init = rtl930x_led_init, + .enable_learning = rtldsa_930x_enable_learning, + .enable_flood = rtldsa_930x_enable_flood, + .set_receive_management_action = rtldsa_930x_set_receive_management_action, + .qos_init = rtldsa_930x_qos_init, + .trk_ctrl = RTL930X_TRK_CTRL, + .trk_hash_ctrl = RTL930X_TRK_HASH_CTRL, + .prepare_lag_fdb = rtldsa_93xx_prepare_lag_fdb, + .lag_switch_init = rtldsa_93xx_lag_switch_init, + .lag_set_port_members = rtldsa_93xx_lag_set_port_members, + .lag_set_distribution_algorithm = rtldsa_93xx_lag_set_distribution_algorithm, + .lag_set_local_group_id = rtldsa_930x_lag_set_local_group_id, + .lag_write_data = rtldsa_930x_lag_write_data, + .lag_fill_data = rtldsa_930x_lag_fill_data, + .lag_set_local_port2group = rtldsa_930x_lag_set_local_port2group, + .lag_set_port2group = rtldsa_930x_lag_set_port2group, + .lag_sync_tables = rtldsa_930x_lag_sync_tables, + .lag_table = rtldsa_930x_lag_table, +}; diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c new file mode 100644 index 0000000000..2e31c10cdc --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c @@ -0,0 +1,2027 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include + +#include "rtl83xx.h" + +#define RTL931X_VLAN_PORT_TAG_STS_INTERNAL 0x0 +#define RTL931X_VLAN_PORT_TAG_STS_UNTAG 0x1 +#define RTL931X_VLAN_PORT_TAG_STS_TAGGED 0x2 +#define RTL931X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x3 + +#define RTL931X_VLAN_PORT_TAG_CTRL_BASE 0x4860 +/* port 0-56 */ +#define RTL931X_VLAN_PORT_TAG_CTRL(port) \ + (RTL931X_VLAN_PORT_TAG_CTRL_BASE + (port << 2)) +#define RTL931X_VLAN_PORT_TAG_EGR_OTAG_STS_MASK GENMASK(13, 12) +#define RTL931X_VLAN_PORT_TAG_EGR_ITAG_STS_MASK GENMASK(11, 10) +#define RTL931X_VLAN_PORT_TAG_EGR_OTAG_KEEP_MASK GENMASK(9, 9) +#define RTL931X_VLAN_PORT_TAG_EGR_ITAG_KEEP_MASK GENMASK(8, 8) +#define RTL931X_VLAN_PORT_TAG_IGR_OTAG_KEEP_MASK GENMASK(7, 7) +#define RTL931X_VLAN_PORT_TAG_IGR_ITAG_KEEP_MASK GENMASK(6, 6) +#define RTL931X_VLAN_PORT_TAG_OTPID_IDX_MASK GENMASK(5, 4) +#define RTL931X_VLAN_PORT_TAG_OTPID_KEEP_MASK GENMASK(3, 3) +#define RTL931X_VLAN_PORT_TAG_ITPID_IDX_MASK GENMASK(2, 1) +#define RTL931X_VLAN_PORT_TAG_ITPID_KEEP_MASK GENMASK(0, 0) + +/* Definition of the RTL931X-specific template field IDs as used in the PIE */ +enum template_field_id { + TEMPLATE_FIELD_SPM0 = 1, + TEMPLATE_FIELD_SPM1 = 2, + TEMPLATE_FIELD_SPM2 = 3, + TEMPLATE_FIELD_SPM3 = 4, + TEMPLATE_FIELD_DMAC0 = 9, + TEMPLATE_FIELD_DMAC1 = 10, + TEMPLATE_FIELD_DMAC2 = 11, + TEMPLATE_FIELD_SMAC0 = 12, + TEMPLATE_FIELD_SMAC1 = 13, + TEMPLATE_FIELD_SMAC2 = 14, + TEMPLATE_FIELD_ETHERTYPE = 15, + TEMPLATE_FIELD_OTAG = 16, + TEMPLATE_FIELD_ITAG = 17, + TEMPLATE_FIELD_SIP0 = 18, + TEMPLATE_FIELD_SIP1 = 19, + TEMPLATE_FIELD_DIP0 = 20, + TEMPLATE_FIELD_DIP1 = 21, + TEMPLATE_FIELD_IP_TOS_PROTO = 22, + TEMPLATE_FIELD_L4_SPORT = 23, + TEMPLATE_FIELD_L4_DPORT = 24, + TEMPLATE_FIELD_L34_HEADER = 25, + TEMPLATE_FIELD_TCP_INFO = 26, + TEMPLATE_FIELD_SIP2 = 34, + TEMPLATE_FIELD_SIP3 = 35, + TEMPLATE_FIELD_SIP4 = 36, + TEMPLATE_FIELD_SIP5 = 37, + TEMPLATE_FIELD_SIP6 = 38, + TEMPLATE_FIELD_SIP7 = 39, + TEMPLATE_FIELD_DIP2 = 42, + TEMPLATE_FIELD_DIP3 = 43, + TEMPLATE_FIELD_DIP4 = 44, + TEMPLATE_FIELD_DIP5 = 45, + TEMPLATE_FIELD_DIP6 = 46, + TEMPLATE_FIELD_DIP7 = 47, + TEMPLATE_FIELD_FLOW_LABEL = 49, + TEMPLATE_FIELD_DSAP_SSAP = 50, + TEMPLATE_FIELD_FWD_VID = 52, + TEMPLATE_FIELD_RANGE_CHK = 53, + TEMPLATE_FIELD_SLP = 55, + TEMPLATE_FIELD_DLP = 56, + TEMPLATE_FIELD_META_DATA = 57, + TEMPLATE_FIELD_FIRST_MPLS1 = 60, + TEMPLATE_FIELD_FIRST_MPLS2 = 61, + TEMPLATE_FIELD_DPM3 = 8, +}; + +/* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in + * RTL931X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag: + */ +#define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG + +/* Number of fixed templates predefined in the RTL9300 SoC */ +#define N_FIXED_TEMPLATES 5 +/* RTL931x specific predefined templates */ +static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS_RTL931X] = { + { + TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, + TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2, + TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP, + TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, + TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3 + }, { + TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, + TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO, + TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN, + TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, + TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3 + }, { + TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, + TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO, + TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, + TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, + TEMPLATE_FIELD_META_DATA, TEMPLATE_FIELD_SLP + }, { + TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2, + TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5, + TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO, + TEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, + TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SLP + }, { + TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2, + TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5, + TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_META_DATA, + TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, + TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3 + }, +}; + +const struct rtldsa_mib_list_item rtldsa_931x_mib_list[] = { + MIB_LIST_ITEM("ifOutDiscards", MIB_ITEM(MIB_TBL_STD, 36, 1)), + MIB_LIST_ITEM("dot1dTpPortInDiscards", MIB_ITEM(MIB_TBL_STD, 35, 1)), + MIB_LIST_ITEM("DropEvents", MIB_ITEM(MIB_TBL_STD, 25, 1)), + MIB_LIST_ITEM("tx_BroadcastPkts", MIB_ITEM(MIB_TBL_STD, 24, 1)), + MIB_LIST_ITEM("tx_MulticastPkts", MIB_ITEM(MIB_TBL_STD, 23, 1)), + MIB_LIST_ITEM("tx_CRCAlignErrors", MIB_ITEM(MIB_TBL_STD, 22, 1)), + MIB_LIST_ITEM("tx_UndersizePkts", MIB_ITEM(MIB_TBL_STD, 20, 1)), + MIB_LIST_ITEM("tx_OversizePkts", MIB_ITEM(MIB_TBL_STD, 18, 1)), + MIB_LIST_ITEM("tx_Fragments", MIB_ITEM(MIB_TBL_STD, 16, 1)), + MIB_LIST_ITEM("tx_Jabbers", MIB_ITEM(MIB_TBL_STD, 14, 1)), + MIB_LIST_ITEM("tx_Collisions", MIB_ITEM(MIB_TBL_STD, 12, 1)), + + MIB_LIST_ITEM("rx_UndersizeDropPkts", MIB_ITEM(MIB_TBL_PRV, 27, 1)), + MIB_LIST_ITEM("tx_PktsFlexibleOctetsSet1", MIB_ITEM(MIB_TBL_PRV, 22, 1)), + MIB_LIST_ITEM("rx_PktsFlexibleOctetsSet1", MIB_ITEM(MIB_TBL_PRV, 21, 1)), + MIB_LIST_ITEM("tx_PktsFlexibleOctetsCRCSet1", MIB_ITEM(MIB_TBL_PRV, 28, 1)), + MIB_LIST_ITEM("rx_PktsFlexibleOctetsCRCSet1", MIB_ITEM(MIB_TBL_PRV, 27, 1)), + MIB_LIST_ITEM("tx_PktsFlexibleOctetsSet0", MIB_ITEM(MIB_TBL_PRV, 18, 1)), + MIB_LIST_ITEM("rx_PktsFlexibleOctetsSet0", MIB_ITEM(MIB_TBL_PRV, 17, 1)), + MIB_LIST_ITEM("tx_PktsFlexibleOctetsCRCSet0", MIB_ITEM(MIB_TBL_PRV, 16, 1)), + MIB_LIST_ITEM("rx_PktsFlexibleOctetsCRCSet0", MIB_ITEM(MIB_TBL_PRV, 15, 1)), + MIB_LIST_ITEM("LengthFieldError", MIB_ITEM(MIB_TBL_PRV, 14, 1)), + MIB_LIST_ITEM("FalseCarrierTimes", MIB_ITEM(MIB_TBL_PRV, 13, 1)), + MIB_LIST_ITEM("UndersizeOctets", MIB_ITEM(MIB_TBL_PRV, 12, 1)), + MIB_LIST_ITEM("FramingErrors", MIB_ITEM(MIB_TBL_PRV, 11, 1)), + MIB_LIST_ITEM("rx_MacDiscards", MIB_ITEM(MIB_TBL_PRV, 9, 1)), + MIB_LIST_ITEM("rx_MacIPGShortDrop", MIB_ITEM(MIB_TBL_PRV, 8, 1)) +}; + +const struct rtldsa_mib_desc rtldsa_931x_mib_desc = { + .symbol_errors = MIB_ITEM(MIB_TBL_STD, 29, 1), + + .if_in_octets = MIB_ITEM(MIB_TBL_STD, 51, 2), + .if_out_octets = MIB_ITEM(MIB_TBL_STD, 49, 2), + .if_in_ucast_pkts = MIB_ITEM(MIB_TBL_STD, 47, 2), + .if_in_mcast_pkts = MIB_ITEM(MIB_TBL_STD, 45, 2), + .if_in_bcast_pkts = MIB_ITEM(MIB_TBL_STD, 43, 2), + .if_out_ucast_pkts = MIB_ITEM(MIB_TBL_STD, 41, 2), + .if_out_mcast_pkts = MIB_ITEM(MIB_TBL_STD, 39, 2), + .if_out_bcast_pkts = MIB_ITEM(MIB_TBL_STD, 37, 2), + .if_out_discards = MIB_ITEM(MIB_TBL_STD, 36, 1), + .single_collisions = MIB_ITEM(MIB_TBL_STD, 35, 1), + .multiple_collisions = MIB_ITEM(MIB_TBL_STD, 33, 1), + .deferred_transmissions = MIB_ITEM(MIB_TBL_STD, 32, 1), + .late_collisions = MIB_ITEM(MIB_TBL_STD, 31, 1), + .excessive_collisions = MIB_ITEM(MIB_TBL_STD, 30, 1), + .crc_align_errors = MIB_ITEM(MIB_TBL_STD, 21, 1), + .rx_pkts_over_max_octets = MIB_ITEM(MIB_TBL_PRV, 23, 1), + + .unsupported_opcodes = MIB_ITEM(MIB_TBL_STD, 28, 1), + + .rx_undersize_pkts = MIB_ITEM(MIB_TBL_STD, 19, 1), + .rx_oversize_pkts = MIB_ITEM(MIB_TBL_STD, 17, 1), + .rx_fragments = MIB_ITEM(MIB_TBL_STD, 15, 1), + .rx_jabbers = MIB_ITEM(MIB_TBL_STD, 13, 1), + + .tx_pkts = { + MIB_ITEM(MIB_TBL_STD, 11, 1), + MIB_ITEM(MIB_TBL_STD, 9, 1), + MIB_ITEM(MIB_TBL_STD, 7, 1), + MIB_ITEM(MIB_TBL_STD, 5, 1), + MIB_ITEM(MIB_TBL_STD, 3, 1), + MIB_ITEM(MIB_TBL_STD, 1, 1), + MIB_ITEM(MIB_TBL_PRV, 26, 1), + MIB_ITEM(MIB_TBL_PRV, 24, 1) + }, + .rx_pkts = { + MIB_ITEM(MIB_TBL_STD, 10, 1), + MIB_ITEM(MIB_TBL_STD, 8, 1), + MIB_ITEM(MIB_TBL_STD, 6, 1), + MIB_ITEM(MIB_TBL_STD, 4, 1), + MIB_ITEM(MIB_TBL_STD, 2, 1), + MIB_ITEM(MIB_TBL_STD, 0, 1), + MIB_ITEM(MIB_TBL_PRV, 25, 1), + MIB_ITEM(MIB_TBL_PRV, 23, 1), + }, + .rmon_ranges = { + { 0, 64 }, + { 65, 127 }, + { 128, 255 }, + { 256, 511 }, + { 512, 1023 }, + { 1024, 1518 }, + { 1519, 12288 }, + { 12289, 65535 } + }, + + .drop_events = MIB_ITEM(MIB_TBL_STD, 25, 1), + .collisions = MIB_ITEM(MIB_TBL_STD, 12, 1), + + .rx_pause_frames = MIB_ITEM(MIB_TBL_STD, 27, 1), + .tx_pause_frames = MIB_ITEM(MIB_TBL_STD, 26, 1), + + .list_count = ARRAY_SIZE(rtldsa_931x_mib_list), + .list = rtldsa_931x_mib_list +}; + +inline void rtl931x_exec_tbl0_cmd(u32 cmd) +{ + sw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_0); + do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_0) & (1 << 20)); +} + +inline void rtl931x_exec_tbl1_cmd(u32 cmd) +{ + sw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_1); + do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_1) & (1 << 17)); +} + +inline int rtl931x_tbl_access_data_0(int i) +{ + return RTL931X_TBL_ACCESS_DATA_0(i); +} + +static int +rtldsa_931x_vlan_profile_get(int idx, struct rtldsa_vlan_profile *profile) +{ + u32 p[7]; + + if (idx < 0 || idx > RTL931X_VLAN_PROFILE_MAX) + return -EINVAL; + + for (int i = 0; i < 7; i++) + p[i] = sw_r32(RTL931X_VLAN_PROFILE_SET(idx) + i * 4); + + *profile = (struct rtldsa_vlan_profile) { + .l2_learn = RTL931X_VLAN_L2_LEARN_EN_R(p), + .unkn_mc_fld.pmsks = { + .l2 = RTL931X_VLAN_L2_UNKN_MC_FLD_PMSK(p), + .ip = RTL931X_VLAN_IP4_UNKN_MC_FLD_PMSK(p), + .ip6 = RTL931X_VLAN_IP6_UNKN_MC_FLD_PMSK(p), + }, + }; + + return 0; +} + +static void +rtldsa_931x_vlan_profile_dump(struct rtl838x_switch_priv *priv, int idx) +{ + struct rtldsa_vlan_profile p; + + if (rtldsa_931x_vlan_profile_get(idx, &p) < 0) + return; + + dev_dbg(priv->dev, + "VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, IPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx\n", + idx, p.l2_learn, p.unkn_mc_fld.pmsks.l2, + p.unkn_mc_fld.pmsks.ip, p.unkn_mc_fld.pmsks.ip6); +} + +static int rtldsa_931x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, int port, u32 port_state[]) +{ + int idx = 3 - ((port + 8) / 16); + int bit = 2 * ((port + 8) % 16); + u32 cmd = 1 << 20 | /* Execute cmd */ + 0 << 19 | /* Read */ + 5 << 15 | /* Table type 0b101 */ + (msti & 0x3fff); + + priv->r->exec_tbl0_cmd(cmd); + for (int i = 0; i < 4; i++) + port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); + + return (port_state[idx] >> bit) & 3; +} + +static void rtl931x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) +{ + u32 cmd = 1 << 20 | /* Execute cmd */ + 1 << 19 | /* Write */ + 5 << 15 | /* Table type 0b101 */ + (msti & 0x3fff); + for (int i = 0; i < 4; i++) + sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); + priv->r->exec_tbl0_cmd(cmd); +} + +static inline int rtldsa_931x_trk_mbr_ctr(int group) +{ + return RTL931X_TRK_MBR_CTRL + (group << 3); +} + +static void rtl931x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 v, w, x, y; + /* Read VLAN table (3) via register 0 */ + struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3); + + rtl_table_read(r, vlan); + v = sw_r32(rtl_table_data(r, 0)); + w = sw_r32(rtl_table_data(r, 1)); + x = sw_r32(rtl_table_data(r, 2)); + y = sw_r32(rtl_table_data(r, 3)); + rtl_table_release(r); + + pr_debug("VLAN_READ %d: %08x %08x %08x %08x\n", vlan, v, w, x, y); + info->member_ports = ((u64)v) << 25 | (w >> 7); + info->profile_id = (x >> 16) & 0xf; + info->fid = w & 0x7f; /* AKA MSTI depending on context */ + info->hash_uc_fid = !!(x & BIT(31)); + info->hash_mc_fid = !!(x & BIT(30)); + info->if_id = (x >> 20) & 0x3ff; + info->multicast_grp_mask = x & 0xffff; + if (y & BIT(31)) + info->l2_tunnel_list_id = y >> 18; + else + info->l2_tunnel_list_id = -1; + pr_debug("%s read member %016llx, profile-id %d, uc %d, mc %d, intf-id %d\n", __func__, + info->member_ports, info->profile_id, info->hash_uc_fid, info->hash_mc_fid, + info->if_id); + + /* Read UNTAG table via table register 3 */ + r = rtl_table_get(RTL9310_TBL_3, 0); + rtl_table_read(r, vlan); + info->untagged_ports = ((u64)sw_r32(rtl_table_data(r, 0))) << 25; + info->untagged_ports |= sw_r32(rtl_table_data(r, 1)) >> 7; + + rtl_table_release(r); +} + +static void rtl931x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) +{ + struct table_reg *r; + u32 v, w, x, y; + + v = info->member_ports >> 25; + w = (info->member_ports & GENMASK(24, 0)) << 7; + w |= info->fid & 0x7f; + x = info->hash_uc_fid ? BIT(31) : 0; + x |= info->hash_mc_fid ? BIT(30) : 0; + x |= info->if_id & 0x3ff << 20; + x |= (info->profile_id & 0xf) << 16; + x |= info->multicast_grp_mask & 0xffff; + if (info->l2_tunnel_list_id >= 0) { + y = info->l2_tunnel_list_id << 18; + y |= BIT(31); + } else { + y = 0; + } + + r = rtl_table_get(RTL9310_TBL_0, 3); + sw_w32(v, rtl_table_data(r, 0)); + sw_w32(w, rtl_table_data(r, 1)); + sw_w32(x, rtl_table_data(r, 2)); + sw_w32(y, rtl_table_data(r, 3)); + + rtl_table_write(r, vlan); + rtl_table_release(r); +} + +static void rtl931x_vlan_set_untagged(u32 vlan, u64 portmask) +{ + struct table_reg *r = rtl_table_get(RTL9310_TBL_3, 0); + + rtl839x_set_port_reg_be(portmask << 7, rtl_table_data(r, 0)); + rtl_table_write(r, vlan); + rtl_table_release(r); +} + +static inline int rtl931x_mac_force_mode_ctrl(int p) +{ + return RTL931X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +static inline int rtl931x_mac_port_ctrl(int p) +{ + return RTL931X_MAC_L2_PORT_CTRL + (p << 7); +} + +static inline int rtl931x_l2_port_new_salrn(int p) +{ + return RTL931X_L2_PORT_NEW_SALRN(p); +} + +static inline int rtl931x_l2_port_new_sa_fwd(int p) +{ + return RTL931X_L2_PORT_NEW_SA_FWD(p); +} + +static int rtldsa_931x_get_mirror_config(struct rtldsa_mirror_config *config, + int group, int port) +{ + config->ctrl = RTL931X_MIR_CTRL + group * 4; + config->spm = RTL931X_MIR_SPM_CTRL + group * 8; + config->dpm = RTL931X_MIR_DPM_CTRL + group * 8; + + /* Enable mirroring to destination port */ + config->val = BIT(0); + config->val |= port << 9; + + /* mirror mode: let mirrored packets follow TX settings of + * mirroring port + */ + config->val |= BIT(5); + + /* direction of traffic to be mirrored when a packet + * hits both SPM and DPM ports: prefer egress + */ + config->val |= BIT(4); + + return 0; +} + +static int rtldsa_931x_port_rate_police_add(struct dsa_switch *ds, int port, + const struct flow_action_entry *act, + bool ingress) +{ + u32 burst; + u64 rate; + u32 addr; + + /* rate has unit 16000 bit */ + rate = div_u64(act->police.rate_bytes_ps, 2000); + rate = min_t(u64, rate, RTL93XX_BANDWIDTH_CTRL_RATE_MAX); + rate |= RTL93XX_BANDWIDTH_CTRL_ENABLE; + + burst = min_t(u32, act->police.burst, RTL931X_BANDWIDTH_CTRL_MAX_BURST); + + if (ingress) + addr = RTL931X_BANDWIDTH_CTRL_INGRESS(port); + else + addr = RTL931X_BANDWIDTH_CTRL_EGRESS(port); + + sw_w32(burst, addr + 4); + sw_w32(rate, addr); + + return 0; +} + +static int rtldsa_931x_port_rate_police_del(struct dsa_switch *ds, int port, + struct flow_cls_offload *cls, + bool ingress) +{ + u32 addr; + + if (ingress) + addr = RTL931X_BANDWIDTH_CTRL_INGRESS(port); + else + addr = RTL931X_BANDWIDTH_CTRL_EGRESS(port); + + sw_w32_mask(RTL93XX_BANDWIDTH_CTRL_ENABLE, 0, addr); + + return 0; +} + +void rtldsa_931x_print_matrix(void) +{ + struct table_reg *r = rtl_table_get(RTL9310_TBL_2, 1); + + for (int i = 0; i < 64; i++) { + rtl_table_read(r, i); + pr_info("> %08x %08x\n", sw_r32(rtl_table_data(r, 0)), + sw_r32(rtl_table_data(r, 1))); + } + rtl_table_release(r); +} + +static void rtldsa_931x_set_receive_management_action(int port, rma_ctrl_t type, + action_type_t action) +{ + u32 shift; + u32 value; + u32 reg; + + /* hack for value mapping */ + if (type == GRATARP && action == COPY2CPU) + action = TRAP2MASTERCPU; + + /* PTP doesn't allow to flood to all ports */ + if (action == FLOODALL && + (type == PTP || type == PTP_UDP || type == PTP_ETH2)) { + pr_warn("%s: Port flooding not supported for PTP\n", __func__); + return; + } + + switch (action) { + case FORWARD: + value = 0; + break; + case DROP: + value = 1; + break; + case TRAP2CPU: + value = 2; + break; + case TRAP2MASTERCPU: + value = 3; + break; + case FLOODALL: + value = 4; + break; + default: + return; + } + + switch (type) { + case BPDU: + reg = RTL931X_RMA_BPDU_CTRL + (port / 10) * 4; + shift = (port % 10) * 3; + sw_w32_mask(GENMASK(shift + 2, shift), value << shift, reg); + break; + case PTP: + reg = RTL931X_RMA_PTP_CTRL + port * 4; + + /* udp */ + sw_w32_mask(GENMASK(3, 2), value << 2, reg); + + /* eth2 */ + sw_w32_mask(GENMASK(1, 0), value, reg); + break; + case PTP_UDP: + reg = RTL931X_RMA_PTP_CTRL + port * 4; + sw_w32_mask(GENMASK(3, 2), value << 2, reg); + break; + case PTP_ETH2: + reg = RTL931X_RMA_PTP_CTRL + port * 4; + sw_w32_mask(GENMASK(1, 0), value, reg); + break; + case LLDP: + reg = RTL931X_RMA_LLDP_CTRL + (port / 10) * 4; + shift = (port % 10) * 3; + sw_w32_mask(GENMASK(shift + 2, shift), value << shift, reg); + break; + case EAPOL: + reg = RTL931X_RMA_EAPOL_CTRL + (port / 10) * 4; + shift = (port % 10) * 3; + sw_w32_mask(GENMASK(shift + 2, shift), value << shift, reg); + break; + case GRATARP: + reg = RTL931X_TRAP_ARP_GRAT_PORT_ACT + (port / 16) * 4; + shift = (port % 16) * 2; + sw_w32_mask(GENMASK(shift + 1, shift), value << shift, reg); + break; + } +} + +/* Enable traffic between a source port and a destination port matrix */ +static void rtl931x_traffic_set(int source, u64 dest_matrix) +{ + struct table_reg *r = rtl_table_get(RTL9310_TBL_2, 1); + + sw_w32(dest_matrix >> (32 - 7), rtl_table_data(r, 0)); + sw_w32(dest_matrix << 7, rtl_table_data(r, 1)); + rtl_table_write(r, source); + rtl_table_release(r); +} + +static void rtl931x_traffic_enable(int source, int dest) +{ + struct table_reg *r = rtl_table_get(RTL9310_TBL_2, 1); + + rtl_table_read(r, source); + sw_w32_mask(0, BIT((dest + 7) % 32), rtl_table_data(r, (dest + 7) / 32 ? 0 : 1)); + rtl_table_write(r, source); + rtl_table_release(r); +} + +static void rtl931x_traffic_disable(int source, int dest) +{ + struct table_reg *r = rtl_table_get(RTL9310_TBL_2, 1); + + rtl_table_read(r, source); + sw_w32_mask(BIT((dest + 7) % 32), 0, rtl_table_data(r, (dest + 7) / 32 ? 0 : 1)); + rtl_table_write(r, source); + rtl_table_release(r); +} + +static u64 rtldsa_931x_l2_hash_seed(u64 mac, u32 vid) +{ + return (u64)vid << 48 | mac; +} + +/* Calculate both the block 0 and the block 1 hash by applyingthe same hash + * algorithm as the one used currently by the ASIC to the seed, and return + * both hashes in the lower and higher word of the return value since only 12 bit of + * the hash are significant. + */ +static u32 rtl931x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) +{ + u32 h, h0, h1, h2, h3, h4, k0, k1; + + h0 = seed & 0xfff; + h1 = (seed >> 12) & 0xfff; + h2 = (seed >> 24) & 0xfff; + h3 = (seed >> 36) & 0xfff; + h4 = (seed >> 48) & 0xfff; + h4 = ((h4 & 0x7) << 9) | ((h4 >> 3) & 0x1ff); + k0 = h0 ^ h1 ^ h2 ^ h3 ^ h4; + + h0 = seed & 0xfff; + h0 = ((h0 & 0x1ff) << 3) | ((h0 >> 9) & 0x7); + h1 = (seed >> 12) & 0xfff; + h1 = ((h1 & 0x3f) << 6) | ((h1 >> 6) & 0x3f); + h2 = (seed >> 24) & 0xfff; + h3 = (seed >> 36) & 0xfff; + h3 = ((h3 & 0x3f) << 6) | ((h3 >> 6) & 0x3f); + h4 = (seed >> 48) & 0xfff; + k1 = h0 ^ h1 ^ h2 ^ h3 ^ h4; + + /* Algorithm choice for block 0 */ + if (sw_r32(RTL931X_L2_CTRL) & BIT(0)) + h = k1; + else + h = k0; + + /* Algorithm choice for block 1 + * Since k0 and k1 are < 4096, adding 4096 will offset the hash into the second + * half of hash-space + * 4096 is in fact the hash-table size 32768 divided by 4 hashes per bucket + * divided by 2 to divide the hash space in 2 + */ + if (sw_r32(RTL931X_L2_CTRL) & BIT(1)) + h |= (k1 + 4096) << 16; + else + h |= (k0 + 4096) << 16; + + return h; +} + +/* Fills an L2 entry structure from the SoC registers */ +static void rtl931x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) +{ + pr_debug("In %s valid?\n", __func__); + e->valid = !!(r[0] & BIT(31)); + if (!e->valid) + return; + + pr_debug("%s: entry valid, raw: %08x %08x %08x %08x\n", __func__, r[0], r[1], r[2], r[3]); + e->is_ip_mc = false; + e->is_ipv6_mc = false; + + e->mac[0] = r[0] >> 8; + e->mac[1] = r[0]; + e->mac[2] = r[1] >> 24; + e->mac[3] = r[1] >> 16; + e->mac[4] = r[1] >> 8; + e->mac[5] = r[1]; + + e->is_open_flow = !!(r[0] & BIT(30)); + e->is_pe_forward = !!(r[0] & BIT(29)); + e->next_hop = !!(r[2] & BIT(30)); + e->rvid = (r[0] >> 16) & 0xfff; + + /* Is it a unicast entry? check multicast bit */ + if (!(e->mac[0] & 1)) { + e->type = L2_UNICAST; + e->is_l2_tunnel = !!(r[2] & BIT(31)); + e->is_static = !!(r[2] & BIT(13)); + e->port = (r[2] >> 19) & 0x3ff; + /* Check for trunk port */ + if (r[2] & BIT(29)) { + e->is_trunk = true; + e->trunk = e->port & 0xff; + } else { + e->is_trunk = false; + e->stack_dev = (e->port >> 6) & 0xf; + e->port = e->port & 0x3f; + } + + e->block_da = !!(r[2] & BIT(14)); + e->block_sa = !!(r[2] & BIT(15)); + e->suspended = !!(r[2] & BIT(12)); + e->age = (r[2] >> 16) & 7; + + /* HW doesn't use VID but FID for as key */ + e->vid = (r[0] >> 16) & 0xfff; + + if (e->is_l2_tunnel) + e->l2_tunnel_id = ((r[2] & 0xff) << 4) | (r[3] >> 28); + /* TODO: Implement VLAN conversion */ + } else { + e->type = L2_MULTICAST; + e->is_local_forward = !!(r[2] & BIT(31)); + e->is_remote_forward = !!(r[2] & BIT(17)); + e->mc_portmask_index = (r[2] >> 18) & 0xfff; + e->l2_tunnel_list_id = (r[2] >> 4) & 0x1fff; + } +} + +/* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */ +static void rtl931x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) +{ + u32 port; + + if (!e->valid) { + r[0] = r[1] = r[2] = r[3] = 0; + return; + } + + r[3] = 0; + + r[0] = BIT(31); /* Set valid bit */ + + r[0] |= ((u32)e->mac[0]) << 8 | + ((u32)e->mac[1]); + r[1] = ((u32)e->mac[2]) << 24 | + ((u32)e->mac[3]) << 16 | + ((u32)e->mac[4]) << 8 | + ((u32)e->mac[5]); + + r[0] |= e->is_open_flow ? BIT(30) : 0; + r[0] |= e->is_pe_forward ? BIT(29) : 0; + r[0] |= e->hash_msb ? BIT(28) : 0; + r[2] = e->next_hop ? BIT(30) : 0; + r[0] |= (e->rvid & 0xfff) << 16; + + if (e->type == L2_UNICAST) { + r[2] |= e->is_l2_tunnel ? BIT(31) : 0; + r[2] |= e->is_static ? BIT(13) : 0; + + if (e->is_trunk) { + r[2] |= BIT(29); + port = e->trunk & 0xff; + } else { + port = e->port & 0x3f; + port |= (e->stack_dev & 0xf) << 6; + } + + r[2] |= (port & 0x3ff) << 19; + r[2] |= e->block_da ? BIT(14) : 0; + r[2] |= e->block_sa ? BIT(15) : 0; + r[2] |= e->suspended ? BIT(12) : 0; + r[2] |= (e->age & 0x7) << 16; + if (e->is_l2_tunnel) { + r[2] |= (e->l2_tunnel_id >> 4) & 0xff; + r[3] |= (e->l2_tunnel_id & 0xf) << 28; + } + } else { /* L2_MULTICAST */ + r[2] |= (e->mc_portmask_index & 0xfff) << 18; + } +} + +/* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table + * hash is the id of the bucket and pos is the position of the entry in that bucket + * The data read from the SoC is filled into rtl838x_l2_entry + */ +static u64 rtl931x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) +{ + u32 r[4]; + struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 0); + u32 idx; + u64 mac; + u64 seed; + + pr_debug("%s: hash %08x, pos: %d\n", __func__, hash, pos); + + /* On the RTL93xx, 2 different hash algorithms are used making it a total of + * 8 buckets that need to be searched, 4 for each hash-half + * Use second hash space when bucket is between 4 and 8 + */ + if (pos >= 4) { + pos -= 4; + hash >>= 16; + } else { + hash &= 0xffff; + } + + idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */ + pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos); + + rtl_table_read(q, idx); + for (int i = 0; i < 4; i++) + r[i] = sw_r32(rtl_table_data(q, i)); + + rtl_table_release(q); + + rtl931x_fill_l2_entry(r, e); + + pr_debug("%s: valid: %d, nh: %d\n", __func__, e->valid, e->next_hop); + if (!e->valid) + return 0; + + mac = ((u64)e->mac[0]) << 40 | + ((u64)e->mac[1]) << 32 | + ((u64)e->mac[2]) << 24 | + ((u64)e->mac[3]) << 16 | + ((u64)e->mac[4]) << 8 | + ((u64)e->mac[5]); + + seed = rtldsa_931x_l2_hash_seed(mac, e->rvid); + pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed); + + /* return vid with concatenated mac as unique id */ + return seed; +} + +static u64 rtl931x_read_cam(int idx, struct rtl838x_l2_entry *e) +{ + u32 r[4]; + struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 1); + + rtl_table_read(q, idx); + for (int i = 0; i < 4; i++) + r[i] = sw_r32(rtl_table_data(q, i)); + + rtl_table_release(q); + rtl931x_fill_l2_entry(r, e); + if (!e->valid) + return 0; + + /* return mac with concatenated fid as unique id */ + return ((((u64)(r[0] & 0xffff) << 32) | (u64)r[1]) << 12) | e->vid; +} + +static void rtl931x_write_cam(int idx, struct rtl838x_l2_entry *e) +{ + u32 r[4]; + struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 1); + + rtl931x_fill_l2_row(r, e); + + for (int i = 0; i < 4; i++) + sw_w32(r[i], rtl_table_data(q, i)); + rtl_table_write(q, idx); + rtl_table_release(q); +} + +static void rtl931x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) +{ + u32 r[4]; + struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 0); + u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */ + int hash_algo_id; + + pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos); + pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx, + e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5]); + + if (idx < 0x4000) + hash_algo_id = sw_r32(RTL931X_L2_CTRL) & BIT(0); + else + hash_algo_id = (sw_r32(RTL931X_L2_CTRL) & BIT(1)) >> 1; + + if (hash_algo_id == 0) + e->hash_msb = (e->rvid >> 2) & 0x1; + else + e->hash_msb = (e->rvid >> 11) & 0x1; + + rtl931x_fill_l2_row(r, e); + pr_debug("%s: %d: %08x %08x %08x\n", __func__, idx, r[0], r[1], r[2]); + + for (int i = 0; i < 4; i++) + sw_w32(r[i], rtl_table_data(q, i)); + + rtl_table_write(q, idx); + rtl_table_release(q); +} + +static void rtl931x_vlan_fwd_on_inner(int port, bool is_set) +{ + /* Always set all tag modes to fwd based on either inner or outer tag */ + if (is_set) + sw_w32_mask(0xf, 0, RTL931X_VLAN_PORT_FWD + (port << 2)); + else + sw_w32_mask(0, 0xf, RTL931X_VLAN_PORT_FWD + (port << 2)); +} + +static void rtl931x_vlan_profile_setup(int profile) +{ + u32 p[7]; + + pr_debug("In %s\n", __func__); + + if (profile > 15) + return; + + p[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(profile)); + + /* Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic */ + /* p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12); */ + p[0] |= 0x3 << 11; /* COPY2CPU */ + + p[1] = RTL931X_VLAN_L2_UNKN_MC_FLD_H(RTL931X_MC_PMASK_ALL_PORTS); + p[2] = RTL931X_VLAN_L2_UNKN_MC_FLD_L(RTL931X_MC_PMASK_ALL_PORTS); + p[3] = RTL931X_VLAN_IP4_UNKN_MC_FLD_H(RTL931X_MC_PMASK_ALL_PORTS); + p[4] = RTL931X_VLAN_IP4_UNKN_MC_FLD_L(RTL931X_MC_PMASK_ALL_PORTS); + p[5] = RTL931X_VLAN_IP6_UNKN_MC_FLD_H(RTL931X_MC_PMASK_ALL_PORTS); + p[6] = RTL931X_VLAN_IP6_UNKN_MC_FLD_L(RTL931X_MC_PMASK_ALL_PORTS); + + for (int i = 0; i < 7; i++) + sw_w32(p[i], RTL931X_VLAN_PROFILE_SET(profile) + i * 4); + pr_debug("Leaving %s\n", __func__); +} + +static void rtl931x_l2_learning_setup(void) +{ + /* Portmask for flooding broadcast traffic */ + rtl839x_set_port_reg_be(RTL931X_MC_PMASK_ALL_PORTS, RTL931X_L2_BC_FLD_PMSK); + + /* Portmask for flooding unicast traffic with unknown destination */ + rtl839x_set_port_reg_be(RTL931X_MC_PMASK_ALL_PORTS, RTL931X_L2_UNKN_UC_FLD_PMSK); + + /* Limit learning to maximum: 64k entries, after that just flood (bits 0-2) */ + sw_w32((0xffff << 3) | FORWARD, RTL931X_L2_LRN_CONSTRT_CTRL); +} + +static void rtldsa_931x_enable_learning(int port, bool enable) +{ + /* Limit learning to maximum: 64k entries */ + sw_w32_mask(GENMASK(18, 3), enable ? (0xfffe << 3) : 0, + RTL931X_L2_LRN_PORT_CONSTRT_CTRL + port * 4); +} + +static void rtldsa_931x_enable_flood(int port, bool enable) +{ + /* 0: forward + * 1: drop + * 2: trap to local CPU + * 3: copy to local CPU + * 4: trap to master CPU + * 5: copy to master CPU + */ + sw_w32_mask(GENMASK(2, 0), enable ? 0 : 1, + RTL931X_L2_LRN_PORT_CONSTRT_CTRL + port * 4); +} + +static u64 rtl931x_read_mcast_pmask(int idx) +{ + u64 portmask; + /* Read MC_PMSK (2) via register RTL9310_TBL_0 */ + struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 2); + + rtl_table_read(q, idx); + portmask = sw_r32(rtl_table_data(q, 0)); + portmask <<= 32; + portmask |= sw_r32(rtl_table_data(q, 1)); + portmask >>= 7; + rtl_table_release(q); + + pr_debug("%s: Index idx %d has portmask %016llx\n", __func__, idx, portmask); + + return portmask; +} + +static void rtl931x_write_mcast_pmask(int idx, u64 portmask) +{ + u64 pm = portmask; + + /* Access MC_PMSK (2) via register RTL9310_TBL_0 */ + struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 2); + + pr_debug("%s: Index idx %d has portmask %016llx\n", __func__, idx, pm); + pm <<= 7; + sw_w32((u32)(pm >> 32), rtl_table_data(q, 0)); + sw_w32((u32)pm, rtl_table_data(q, 1)); + rtl_table_write(q, idx); + rtl_table_release(q); +} + +static int rtl931x_set_ageing_time(unsigned long msec) +{ + int t = sw_r32(RTL931X_L2_AGE_CTRL); + + t &= 0x1FFFFF; + t = (t * 8) / 10; + pr_debug("L2 AGING time: %d sec\n", t); + + t = (msec / 100 + 7) / 8; + t = t > 0x1FFFFF ? 0x1FFFFF : t; + sw_w32_mask(0x1FFFFF, t, RTL931X_L2_AGE_CTRL); + pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL931X_L2_PORT_AGE_CTRL)); + + return 0; +} + +static void rtl931x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index) +{ + int block = index / PIE_BLOCK_SIZE; + + sw_w32_mask(0, BIT(block), RTL931X_PIE_BLK_LOOKUP_CTRL); +} + +/* Fills the data in the intermediate representation in the pie_rule structure + * into a data field for a given template field field_type + * TODO: This function looks very similar to the function of the rtl9300, but + * since it uses the physical template_field_id, which are different for each + * SoC and there are other field types, it is actually not. If we would also use + * an intermediate representation for a field type, we would could have one + * pie_data_fill function for all SoCs, provided we have also for each SoC a + * function to map between physical and intermediate field type + */ +static int rtl931x_pie_data_fill(enum template_field_id field_type, struct pie_rule *pr, u16 *data, u16 *data_m) +{ + *data = *data_m = 0; + + switch (field_type) { + case TEMPLATE_FIELD_SPM0: + *data = pr->spm; + *data_m = pr->spm_m; + break; + case TEMPLATE_FIELD_SPM1: + *data = pr->spm >> 16; + *data_m = pr->spm_m >> 16; + break; + case TEMPLATE_FIELD_OTAG: + *data = pr->otag; + *data_m = pr->otag_m; + break; + case TEMPLATE_FIELD_SMAC0: + *data = pr->smac[4]; + *data = (*data << 8) | pr->smac[5]; + *data_m = pr->smac_m[4]; + *data_m = (*data_m << 8) | pr->smac_m[5]; + break; + case TEMPLATE_FIELD_SMAC1: + *data = pr->smac[2]; + *data = (*data << 8) | pr->smac[3]; + *data_m = pr->smac_m[2]; + *data_m = (*data_m << 8) | pr->smac_m[3]; + break; + case TEMPLATE_FIELD_SMAC2: + *data = pr->smac[0]; + *data = (*data << 8) | pr->smac[1]; + *data_m = pr->smac_m[0]; + *data_m = (*data_m << 8) | pr->smac_m[1]; + break; + case TEMPLATE_FIELD_DMAC0: + *data = pr->dmac[4]; + *data = (*data << 8) | pr->dmac[5]; + *data_m = pr->dmac_m[4]; + *data_m = (*data_m << 8) | pr->dmac_m[5]; + break; + case TEMPLATE_FIELD_DMAC1: + *data = pr->dmac[2]; + *data = (*data << 8) | pr->dmac[3]; + *data_m = pr->dmac_m[2]; + *data_m = (*data_m << 8) | pr->dmac_m[3]; + break; + case TEMPLATE_FIELD_DMAC2: + *data = pr->dmac[0]; + *data = (*data << 8) | pr->dmac[1]; + *data_m = pr->dmac_m[0]; + *data_m = (*data_m << 8) | pr->dmac_m[1]; + break; + case TEMPLATE_FIELD_ETHERTYPE: + *data = pr->ethertype; + *data_m = pr->ethertype_m; + break; + case TEMPLATE_FIELD_ITAG: + *data = pr->itag; + *data_m = pr->itag_m; + break; + case TEMPLATE_FIELD_SIP0: + if (pr->is_ipv6) { + *data = pr->sip6.s6_addr16[7]; + *data_m = pr->sip6_m.s6_addr16[7]; + } else { + *data = pr->sip; + *data_m = pr->sip_m; + } + break; + case TEMPLATE_FIELD_SIP1: + if (pr->is_ipv6) { + *data = pr->sip6.s6_addr16[6]; + *data_m = pr->sip6_m.s6_addr16[6]; + } else { + *data = pr->sip >> 16; + *data_m = pr->sip_m >> 16; + } + break; + case TEMPLATE_FIELD_SIP2: + case TEMPLATE_FIELD_SIP3: + case TEMPLATE_FIELD_SIP4: + case TEMPLATE_FIELD_SIP5: + case TEMPLATE_FIELD_SIP6: + case TEMPLATE_FIELD_SIP7: + *data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; + *data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; + break; + case TEMPLATE_FIELD_DIP0: + if (pr->is_ipv6) { + *data = pr->dip6.s6_addr16[7]; + *data_m = pr->dip6_m.s6_addr16[7]; + } else { + *data = pr->dip; + *data_m = pr->dip_m; + } + break; + case TEMPLATE_FIELD_DIP1: + if (pr->is_ipv6) { + *data = pr->dip6.s6_addr16[6]; + *data_m = pr->dip6_m.s6_addr16[6]; + } else { + *data = pr->dip >> 16; + *data_m = pr->dip_m >> 16; + } + break; + case TEMPLATE_FIELD_DIP2: + case TEMPLATE_FIELD_DIP3: + case TEMPLATE_FIELD_DIP4: + case TEMPLATE_FIELD_DIP5: + case TEMPLATE_FIELD_DIP6: + case TEMPLATE_FIELD_DIP7: + *data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; + *data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; + break; + case TEMPLATE_FIELD_IP_TOS_PROTO: + *data = pr->tos_proto; + *data_m = pr->tos_proto_m; + break; + case TEMPLATE_FIELD_L4_SPORT: + *data = pr->sport; + *data_m = pr->sport_m; + break; + case TEMPLATE_FIELD_L4_DPORT: + *data = pr->dport; + *data_m = pr->dport_m; + break; + case TEMPLATE_FIELD_DSAP_SSAP: + *data = pr->dsap_ssap; + *data_m = pr->dsap_ssap_m; + break; + case TEMPLATE_FIELD_TCP_INFO: + *data = pr->tcp_info; + *data_m = pr->tcp_info_m; + break; + case TEMPLATE_FIELD_RANGE_CHK: + pr_debug("TEMPLATE_FIELD_RANGE_CHK: not configured\n"); + break; + default: + pr_debug("%s: unknown field %d\n", __func__, field_type); + return -1; + } + + return 0; +} + +/* Reads the intermediate representation of the templated match-fields of the + * PIE rule in the pie_rule structure and fills in the raw data fields in the + * raw register space r[]. + * The register space configuration size is identical for the RTL8380/90 and RTL9300, + * however the RTL931X has 2 more registers / fields and the physical field-ids are different + * on all SoCs + * On the RTL9300 the mask fields are not word-aligend! + */ +static void rtl931x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) +{ + for (int i = 0; i < N_FIXED_FIELDS; i++) { + u16 data, data_m; + + rtl931x_pie_data_fill(t[i], pr, &data, &data_m); + + /* On the RTL9300, the mask fields are not word aligned! */ + if (!(i % 2)) { + r[5 - i / 2] = data; + r[12 - i / 2] |= ((u32)data_m << 8); + } else { + r[5 - i / 2] |= ((u32)data) << 16; + r[12 - i / 2] |= ((u32)data_m) << 24; + r[11 - i / 2] |= ((u32)data_m) >> 8; + } + } +} + +// Currently unused +// static void rtl931x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr) +// { +// pr->mgnt_vlan = r[7] & BIT(31); +// if (pr->phase == PHASE_IACL) +// pr->dmac_hit_sw = r[7] & BIT(30); +// else /* TODO: EACL/VACL phase handling */ +// pr->content_too_deep = r[7] & BIT(30); +// pr->not_first_frag = r[7] & BIT(29); +// pr->frame_type_l4 = (r[7] >> 26) & 7; +// pr->frame_type = (r[7] >> 24) & 3; +// pr->otag_fmt = (r[7] >> 23) & 1; +// pr->itag_fmt = (r[7] >> 22) & 1; +// pr->otag_exist = (r[7] >> 21) & 1; +// pr->itag_exist = (r[7] >> 20) & 1; +// pr->frame_type_l2 = (r[7] >> 18) & 3; +// pr->igr_normal_port = (r[7] >> 17) & 1; +// pr->tid = (r[7] >> 16) & 1; + +// pr->mgnt_vlan_m = r[14] & BIT(15); +// if (pr->phase == PHASE_IACL) +// pr->dmac_hit_sw_m = r[14] & BIT(14); +// else +// pr->content_too_deep_m = r[14] & BIT(14); +// pr->not_first_frag_m = r[14] & BIT(13); +// pr->frame_type_l4_m = (r[14] >> 10) & 7; +// pr->frame_type_m = (r[14] >> 8) & 3; +// pr->otag_fmt_m = r[14] & BIT(7); +// pr->itag_fmt_m = r[14] & BIT(6); +// pr->otag_exist_m = r[14] & BIT(5); +// pr->itag_exist_m = r[14] & BIT (4); +// pr->frame_type_l2_m = (r[14] >> 2) & 3; +// pr->igr_normal_port_m = r[14] & BIT(1); +// pr->tid_m = r[14] & 1; + +// pr->valid = r[15] & BIT(31); +// pr->cond_not = r[15] & BIT(30); +// pr->cond_and1 = r[15] & BIT(29); +// pr->cond_and2 = r[15] & BIT(28); +// } + +static void rtl931x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr) +{ + r[7] |= pr->mgnt_vlan ? BIT(31) : 0; + if (pr->phase == PHASE_IACL) + r[7] |= pr->dmac_hit_sw ? BIT(30) : 0; + else + r[7] |= pr->content_too_deep ? BIT(30) : 0; + r[7] |= pr->not_first_frag ? BIT(29) : 0; + r[7] |= ((u32)(pr->frame_type_l4 & 0x7)) << 26; + r[7] |= ((u32)(pr->frame_type & 0x3)) << 24; + r[7] |= pr->otag_fmt ? BIT(23) : 0; + r[7] |= pr->itag_fmt ? BIT(22) : 0; + r[7] |= pr->otag_exist ? BIT(21) : 0; + r[7] |= pr->itag_exist ? BIT(20) : 0; + r[7] |= ((u32)(pr->frame_type_l2 & 0x3)) << 18; + r[7] |= pr->igr_normal_port ? BIT(17) : 0; + r[7] |= ((u32)(pr->tid & 0x1)) << 16; + + r[14] |= pr->mgnt_vlan_m ? BIT(15) : 0; + if (pr->phase == PHASE_IACL) + r[14] |= pr->dmac_hit_sw_m ? BIT(14) : 0; + else + r[14] |= pr->content_too_deep_m ? BIT(14) : 0; + r[14] |= pr->not_first_frag_m ? BIT(13) : 0; + r[14] |= ((u32)(pr->frame_type_l4_m & 0x7)) << 10; + r[14] |= ((u32)(pr->frame_type_m & 0x3)) << 8; + r[14] |= pr->otag_fmt_m ? BIT(7) : 0; + r[14] |= pr->itag_fmt_m ? BIT(6) : 0; + r[14] |= pr->otag_exist_m ? BIT(5) : 0; + r[14] |= pr->itag_exist_m ? BIT(4) : 0; + r[14] |= ((u32)(pr->frame_type_l2_m & 0x3)) << 2; + r[14] |= pr->igr_normal_port_m ? BIT(1) : 0; + r[14] |= (u32)(pr->tid_m & 0x1); + + r[15] |= pr->valid ? BIT(31) : 0; + r[15] |= pr->cond_not ? BIT(30) : 0; + r[15] |= pr->cond_and1 ? BIT(29) : 0; + r[15] |= pr->cond_and2 ? BIT(28) : 0; +} + +static void rtl931x_write_pie_action(u32 r[], struct pie_rule *pr) +{ + /* Either drop or forward */ + if (pr->drop) { + r[15] |= BIT(11) | BIT(12) | BIT(13); /* Do Green, Yellow and Red drops */ + /* Actually DROP, not PERMIT in Green / Yellow / Red */ + r[16] |= BIT(27) | BIT(28) | BIT(29); + } else { + r[15] |= pr->fwd_sel ? BIT(14) : 0; + r[16] |= pr->fwd_act << 24; + r[16] |= BIT(21); /* We overwrite any drop */ + } + if (pr->phase == PHASE_VACL) + r[16] |= pr->fwd_sa_lrn ? BIT(22) : 0; + r[15] |= pr->bypass_sel ? BIT(10) : 0; + r[15] |= pr->nopri_sel ? BIT(21) : 0; + r[15] |= pr->tagst_sel ? BIT(20) : 0; + r[15] |= pr->ovid_sel ? BIT(18) : 0; + r[15] |= pr->ivid_sel ? BIT(16) : 0; + r[15] |= pr->meter_sel ? BIT(27) : 0; + r[15] |= pr->mir_sel ? BIT(15) : 0; + r[15] |= pr->log_sel ? BIT(26) : 0; + + r[16] |= ((u32)(pr->fwd_data & 0xfff)) << 9; +/* r[15] |= pr->log_octets ? BIT(31) : 0; */ + r[15] |= (u32)(pr->meter_data) >> 2; + r[16] |= (((u32)(pr->meter_data) >> 7) & 0x3) << 29; + + r[16] |= ((u32)(pr->ivid_act & 0x3)) << 21; + r[15] |= ((u32)(pr->ivid_data & 0xfff)) << 9; + r[16] |= ((u32)(pr->ovid_act & 0x3)) << 30; + r[16] |= ((u32)(pr->ovid_data & 0xfff)) << 16; + r[16] |= ((u32)(pr->mir_data & 0x3)) << 6; + r[17] |= ((u32)(pr->tagst_data & 0xf)) << 28; + r[17] |= ((u32)(pr->nopri_data & 0x7)) << 25; + r[17] |= pr->bypass_ibc_sc ? BIT(16) : 0; +} + +static void rtl931x_pie_rule_dump_raw(u32 r[]) +{ + pr_debug("Raw IACL table entry:\n"); + pr_debug("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n", + r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]); + pr_debug("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n", + r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]); + pr_debug("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]); + pr_debug("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]); + pr_debug("Fixed : %06x\n", r[6] >> 8); + pr_debug("Match M: %08x %08x %08x %08x %08x %08x\n", + (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8), + (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8), + (r[11] << 24) | (r[12] >> 8)); + pr_debug("R[13]: %08x\n", r[13]); + pr_debug("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff); + pr_debug("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf); + pr_debug("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]); +} + +static int rtl931x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) +{ + /* Access IACL table (0) via register 1, the table size is 4096 */ + struct table_reg *q = rtl_table_get(RTL9310_TBL_1, 0); + u32 r[22]; + int block = idx / PIE_BLOCK_SIZE; + u32 t_select = sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)); + + pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select); + + for (int i = 0; i < 22; i++) + r[i] = 0; + + if (!pr->valid) { + rtl_table_write(q, idx); + rtl_table_release(q); + return 0; + } + rtl931x_write_pie_fixed_fields(r, pr); + + pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf); + rtl931x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]); + + rtl931x_write_pie_action(r, pr); + + rtl931x_pie_rule_dump_raw(r); + + for (int i = 0; i < 22; i++) + sw_w32(r[i], rtl_table_data(q, i)); + + rtl_table_write(q, idx); + rtl_table_release(q); + + return 0; +} + +static bool rtl931x_pie_templ_has(int t, enum template_field_id field_type) +{ + for (int i = 0; i < N_FIXED_FIELDS_RTL931X; i++) { + enum template_field_id ft = fixed_templates[t][i]; + + if (field_type == ft) + return true; + } + + return false; +} + +/* Verify that the rule pr is compatible with a given template t in block + * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0 + * depend on the SoC + */ +static int rtl931x_pie_verify_template(struct rtl838x_switch_priv *priv, + struct pie_rule *pr, int t, int block) +{ + int i; + + if (!pr->is_ipv6 && pr->sip_m && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SIP0)) + return -1; + + if (!pr->is_ipv6 && pr->dip_m && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DIP0)) + return -1; + + if (pr->is_ipv6) { + if ((pr->sip6_m.s6_addr32[0] || + pr->sip6_m.s6_addr32[1] || + pr->sip6_m.s6_addr32[2] || + pr->sip6_m.s6_addr32[3]) && + !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) + return -1; + if ((pr->dip6_m.s6_addr32[0] || + pr->dip6_m.s6_addr32[1] || + pr->dip6_m.s6_addr32[2] || + pr->dip6_m.s6_addr32[3]) && + !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) + return -1; + } + + if (ether_addr_to_u64(pr->smac) && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0)) + return -1; + + if (ether_addr_to_u64(pr->dmac) && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0)) + return -1; + + /* TODO: Check more */ + + i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE); + + if (i >= PIE_BLOCK_SIZE) + return -1; + + return i + PIE_BLOCK_SIZE * block; +} + +static int rtl931x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr) +{ + int idx, block, j; + int min_block = 0; + int max_block = priv->r->n_pie_blocks / 2; + + if (pr->is_egress) { + min_block = max_block; + max_block = priv->r->n_pie_blocks; + } + pr_debug("In %s\n", __func__); + + mutex_lock(&priv->pie_mutex); + + for (block = min_block; block < max_block; block++) { + for (j = 0; j < 2; j++) { + int t = (sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf; + + pr_debug("Testing block %d, template %d, template id %d\n", block, j, t); + pr_debug("%s: %08x\n", + __func__, sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block))); + idx = rtl931x_pie_verify_template(priv, pr, t, block); + if (idx >= 0) + break; + } + if (j < 2) + break; + } + + if (block >= priv->r->n_pie_blocks) { + mutex_unlock(&priv->pie_mutex); + return -EOPNOTSUPP; + } + + pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j); + set_bit(idx, priv->pie_use_bm); + + pr->valid = true; + pr->tid = j; /* Mapped to template number */ + pr->tid_m = 0x1; + pr->id = idx; + + rtl931x_pie_lookup_enable(priv, idx); + rtl931x_pie_rule_write(priv, idx, pr); + + mutex_unlock(&priv->pie_mutex); + + return 0; +} + +/* Delete a range of Packet Inspection Engine rules */ +static int rtl931x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to) +{ + u32 v = (index_from << 1) | (index_to << 13) | BIT(0); + + pr_debug("%s: from %d to %d\n", __func__, index_from, index_to); + mutex_lock(&priv->reg_mutex); + + /* Write from-to and execute bit into control register */ + sw_w32(v, RTL931X_PIE_CLR_CTRL); + + /* Wait until command has completed */ + do { + } while (sw_r32(RTL931X_PIE_CLR_CTRL) & BIT(0)); + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static void rtl931x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr) +{ + int idx = pr->id; + + rtl931x_pie_rule_del(priv, idx, idx); + clear_bit(idx, priv->pie_use_bm); +} + +static void rtl931x_pie_init(struct rtl838x_switch_priv *priv) +{ + u32 template_selectors; + + mutex_init(&priv->pie_mutex); + + pr_debug("%s\n", __func__); + /* Enable ACL lookup on all ports, including CPU_PORT */ + for (int i = 0; i <= priv->cpu_port; i++) + sw_w32(1, RTL931X_ACL_PORT_LOOKUP_CTRL(i)); + + /* Include IPG in metering */ + sw_w32_mask(0, 1, RTL931X_METER_GLB_CTRL); + + /* Delete all present rules, block size is 128 on all SoC families */ + rtl931x_pie_rule_del(priv, 0, priv->r->n_pie_blocks * 128 - 1); + + /* Assign first half blocks 0-7 to VACL phase, second half to IACL */ + /* 3 bits are used for each block, values for PIE blocks are */ + /* 6: Disabled, 0: VACL, 1: IACL, 2: EACL */ + /* And for OpenFlow Flow blocks: 3: Ingress Flow table 0, */ + /* 4: Ingress Flow Table 3, 5: Egress flow table 0 */ + for (int i = 0; i < priv->r->n_pie_blocks; i++) { + int pos = (i % 10) * 3; + u32 r = RTL931X_PIE_BLK_PHASE_CTRL + 4 * (i / 10); + + if (i < priv->r->n_pie_blocks / 2) + sw_w32_mask(0x7 << pos, 0, r); + else + sw_w32_mask(0x7 << pos, 1 << pos, r); + } + + /* Enable predefined templates 0, 1 for first quarter of all blocks */ + template_selectors = 0 | (1 << 4); + for (int i = 0; i < priv->r->n_pie_blocks / 4; i++) + sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); + + /* Enable predefined templates 2, 3 for second quarter of all blocks */ + template_selectors = 2 | (3 << 4); + for (int i = priv->r->n_pie_blocks / 4; i < priv->r->n_pie_blocks / 2; i++) + sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); + + /* Enable predefined templates 0, 1 for third quater of all blocks */ + template_selectors = 0 | (1 << 4); + for (int i = priv->r->n_pie_blocks / 2; i < priv->r->n_pie_blocks * 3 / 4; i++) + sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); + + /* Enable predefined templates 2, 3 for fourth quater of all blocks */ + template_selectors = 2 | (3 << 4); + for (int i = priv->r->n_pie_blocks * 3 / 4; i < priv->r->n_pie_blocks; i++) + sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); +} + +static void rtl931x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) +{ + sw_w32(FIELD_PREP(RTL931X_VLAN_PORT_TAG_EGR_OTAG_STS_MASK, + keep_outer ? RTL931X_VLAN_PORT_TAG_STS_TAGGED : RTL931X_VLAN_PORT_TAG_STS_UNTAG) | + FIELD_PREP(RTL931X_VLAN_PORT_TAG_EGR_ITAG_STS_MASK, + keep_inner ? RTL931X_VLAN_PORT_TAG_STS_TAGGED : RTL931X_VLAN_PORT_TAG_STS_UNTAG), + RTL931X_VLAN_PORT_TAG_CTRL(port)); +} + +static void rtl931x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0x3 << 12, mode << 12, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); + else + sw_w32_mask(0x3 << 26, mode << 26, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); +} + +static void rtl931x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0xfff, pvid, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); + else + sw_w32_mask(0xfff << 14, pvid << 14, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); +} + +static int rtldsa_931x_fast_age(struct rtl838x_switch_priv *priv, int port, int vid) +{ + u32 val; + + sw_w32(0, RTL931X_L2_TBL_FLUSH_CTRL + 4); + + val = 0; + val |= port << 11; + val |= BIT(24); /* compare port id */ + val |= BIT(28); /* status - trigger flush */ + if (vid >= 0) { + sw_w32(vid << 20, RTL931X_L2_TBL_FLUSH_CTRL + 4); + val |= BIT(26); /* compare VID */ + } + sw_w32(val, RTL931X_L2_TBL_FLUSH_CTRL); + + do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT(28)); + + return 0; +} + +static void rtl931x_set_igr_filter(int port, enum igr_filter state) +{ + sw_w32_mask(0x3 << ((port & 0xf) << 1), state << ((port & 0xf) << 1), + RTL931X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2))); +} + +static void rtl931x_set_egr_filter(int port, enum egr_filter state) +{ + sw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20), + RTL931X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2))); +} + +static void rtldsa_931x_led_get_forced(const struct device_node *node, + const u8 leds_in_set[4], + u8 forced_leds_per_port[RTL931X_CPU_PORT]) +{ + DECLARE_BITMAP(mask, RTL931X_CPU_PORT); + unsigned int port; + char set_str[36]; + u64 pm; + + for (u8 set = 0; set < 4; set++) { + snprintf(set_str, sizeof(set_str), "realtek,led-set%d-force-port-mask", set); + if (of_property_read_u64(node, set_str, &pm)) + continue; + + bitmap_from_arr64(mask, &pm, RTL931X_CPU_PORT); + + for_each_set_bit(port, mask, RTL931X_CPU_PORT) + forced_leds_per_port[port] = leds_in_set[set]; + } +} + +static void rtldsa_931x_led_init(struct rtl838x_switch_priv *priv) +{ + u8 forced_leds_per_port[RTL931X_CPU_PORT] = {}; + u64 pm_copper = 0, pm_fiber = 0; + struct device *dev = priv->dev; + struct device_node *node; + u8 leds_in_set[4] = {}; + + node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds"); + if (!node) { + dev_dbg(dev, "No compatible LED node found\n"); + return; + } + + for (int set = 0; set < 4; set++) { + char set_name[16] = {0}; + u32 set_config[4]; + int leds_in_this_set = 0; + + /* Reset LED set configuration */ + sw_w32(0, RTL931X_LED_SETX_0_CTRL(set)); + sw_w32(0, RTL931X_LED_SETX_1_CTRL(set)); + + /* Each LED set has (up to) 4 LEDs, and each LED is configured + * with 16 bits. So each 32 bit register holds configuration for + * 2 LEDs. Therefore, each set requires 2 registers for + * configuring all 4 LEDs. + */ + snprintf(set_name, sizeof(set_name), "led_set%d", set); + leds_in_this_set = of_property_count_u32_elems(node, set_name); + + if (leds_in_this_set <= 0 || leds_in_this_set > ARRAY_SIZE(set_config)) { + if (leds_in_this_set != -EINVAL) { + dev_err(dev, "%s invalid, skipping this set, leds_in_this_set=%d, should be (0, %d]\n", + set_name, leds_in_this_set, ARRAY_SIZE(set_config)); + } + + continue; + } + + dev_info(dev, "%s has %d LEDs configured\n", set_name, leds_in_this_set); + leds_in_set[set] = leds_in_this_set; + + if (of_property_read_u32_array(node, set_name, set_config, leds_in_this_set)) + break; + + /* Write configuration for selected LEDs */ + for (int i = 0, led = leds_in_this_set - 1; led >= 0; led--, i++) { + sw_w32_mask(0xffff << RTL931X_LED_SET_LEDX_SHIFT(led), + (0xffff & set_config[i]) << RTL931X_LED_SET_LEDX_SHIFT(led), + RTL931X_LED_SETX_LEDY(set, led)); + } + } + + rtldsa_931x_led_get_forced(node, leds_in_set, forced_leds_per_port); + + for (int i = 0; i < priv->cpu_port; i++) { + int pos = (i << 1) % 32; + u32 set; + + sw_w32_mask(0x3 << pos, 0, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i)); + sw_w32_mask(0x3 << pos, 0, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i)); + + /* Skip port if not present (auto-detect) or not in forced mask */ + if (!priv->ports[i].phy && !priv->ports[i].pcs && !(forced_leds_per_port[i])) + continue; + + if (forced_leds_per_port[i] > 0) + priv->ports[i].leds_on_this_port = forced_leds_per_port[i]; + + /* 0x0 = 1 led, 0x1 = 2 leds, 0x2 = 3 leds, 0x3 = 4 leds per port */ + sw_w32_mask(0x3 << pos, (priv->ports[i].leds_on_this_port - 1) << pos, + RTL931X_LED_PORT_NUM_CTRL(i)); + + if (priv->ports[i].phy_is_integrated) + pm_fiber |= BIT_ULL(i); + else + pm_copper |= BIT_ULL(i); + + set = priv->ports[i].led_set; + sw_w32_mask(0, set << pos, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i)); + sw_w32_mask(0, set << pos, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i)); + } + + /* Set LED mode to serial (0x1) */ + sw_w32_mask(0x3, 0x1, RTL931X_LED_GLB_CTRL); + + if (of_property_read_bool(node, "active-low")) + sw_w32_mask(RTL931X_LED_GLB_ACTIVE_LOW, 0, RTL931X_LED_GLB_CTRL); + else + sw_w32_mask(0, RTL931X_LED_GLB_ACTIVE_LOW, RTL931X_LED_GLB_CTRL); + + rtl839x_set_port_reg_le(pm_copper, RTL931X_LED_PORT_COPR_MASK_CTRL); + rtl839x_set_port_reg_le(pm_fiber, RTL931X_LED_PORT_FIB_MASK_CTRL); + rtl839x_set_port_reg_le(pm_copper | pm_fiber, RTL931X_LED_PORT_COMBO_MASK_CTRL); + + for (int i = 0; i < 32; i++) + dev_dbg(dev, "%08x: %08x\n", 0xbb000600 + i * 4, sw_r32(0x0600 + i * 4)); +} + +static void rtldsa_931x_lag_set_port2group(int group, int port, bool valid) +{ + u32 trk_id_valid = valid ? RTL931X_SRC_TRK_MAP_TRK_ID_VALID : 0; + struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 13); + u32 mask = 0; + + rtl_table_read(r, port); + + mask |= trk_id_valid; + /* Update TRK Field */ + mask |= FIELD_PREP(RTL931X_SRC_TRK_MAP_TRK_ID, group); + + sw_w32(mask, rtl_table_data(r, 0)); + rtl_table_write(r, port); + rtl_table_release(r); +} + +/* Write data from the data buffer into the lag-entry strucure */ +static void rtldsa_931x_lag_fill_data(u32 data[], struct rtldsa_93xx_lag_entry *e) +{ + /* 95-64 */ + e->num_tx_candi = FIELD_GET(RTL931X_LAG_NUM_TX_CANDI, data[0]); + e->l2_hash_mask_idx = FIELD_GET(RTL931X_LAG_L2_HASH_MSK_IDX, data[0]); + e->ip4_hash_mask_idx = FIELD_GET(RTL931X_LAG_IP4_HASH_MSK_IDX, data[0]); + e->ip6_hash_mask_idx = FIELD_GET(RTL931X_LAG_IP6_HASH_MSK_IDX, data[0]); + e->flood_dlf_bcast.sep_flood_en = FIELD_GET(RTL931X_LAG_SEP_FLOOD_EN, data[0]); + e->sep_kwn_mc_en = FIELD_GET(RTL931X_LAG_SEP_KWN_MC_EN, data[0]); + e->trk_dev7 = FIELD_GET(RTL931X_LAG_TRK_DEV7, data[0]); + e->trk_port7 = FIELD_GET(RTL931X_LAG_TRK_PORT7, data[0]); + e->trk_dev6 = FIELD_GET(RTL931X_LAG_TRK_DEV6, data[0]); + e->trk_port6 = FIELD_GET(RTL931X_LAG_TRK_PORT6, data[0]); + + /* 63-32 */ + e->trk_dev5 = FIELD_GET(RTL931X_LAG_TRK_DEV5, data[1]); + e->trk_port5 = FIELD_GET(RTL931X_LAG_TRK_PORT5, data[1]); + e->trk_dev4 = FIELD_GET(RTL931X_LAG_TRK_DEV4, data[1]); + e->trk_port4 = FIELD_GET(RTL931X_LAG_TRK_PORT4, data[1]); + e->trk_dev3 = FIELD_GET(RTL931X_LAG_TRK_DEV3, data[1]); + e->trk_port3 = FIELD_GET(RTL931X_LAG_TRK_PORT3, data[1]); + + /* 31-0 */ + e->trk_dev2 = FIELD_GET(RTL931X_LAG_TRK_DEV2, data[2]); + e->trk_port2 = FIELD_GET(RTL931X_LAG_TRK_PORT2, data[2]); + e->trk_dev1 = FIELD_GET(RTL931X_LAG_TRK_DEV1, data[2]); + e->trk_port1 = FIELD_GET(RTL931X_LAG_TRK_PORT1, data[2]); + e->trk_dev0 = FIELD_GET(RTL931X_LAG_TRK_DEV0, data[2]); + e->trk_port0 = FIELD_GET(RTL931X_LAG_TRK_PORT0, data[2]); +} + +/* Write lag-entry data into buffer */ +static void rtldsa_931x_lag_write_data(u32 data[], struct rtldsa_93xx_lag_entry *e) +{ + /* 95-64 */ + data[0] = FIELD_PREP(RTL931X_LAG_NUM_TX_CANDI, e->num_tx_candi); + data[0] |= FIELD_PREP(RTL931X_LAG_L2_HASH_MSK_IDX, e->l2_hash_mask_idx); + data[0] |= FIELD_PREP(RTL931X_LAG_IP4_HASH_MSK_IDX, e->ip4_hash_mask_idx); + data[0] |= FIELD_PREP(RTL931X_LAG_IP6_HASH_MSK_IDX, e->ip6_hash_mask_idx); + data[0] |= FIELD_PREP(RTL931X_LAG_SEP_FLOOD_EN, e->flood_dlf_bcast.sep_flood_en); + data[0] |= FIELD_PREP(RTL931X_LAG_SEP_KWN_MC_EN, e->sep_kwn_mc_en); + data[0] |= FIELD_PREP(RTL931X_LAG_TRK_DEV7, e->trk_dev7); + data[0] |= FIELD_PREP(RTL931X_LAG_TRK_PORT7, e->trk_port7); + data[0] |= FIELD_PREP(RTL931X_LAG_TRK_DEV6, e->trk_dev6); + data[0] |= FIELD_PREP(RTL931X_LAG_TRK_PORT6, e->trk_port6); + + /* 63-32 */ + data[1] = FIELD_PREP(RTL931X_LAG_TRK_DEV5, e->trk_dev5); + data[1] |= FIELD_PREP(RTL931X_LAG_TRK_PORT5, e->trk_port5); + data[1] |= FIELD_PREP(RTL931X_LAG_TRK_DEV4, e->trk_dev4); + data[1] |= FIELD_PREP(RTL931X_LAG_TRK_PORT4, e->trk_port4); + data[1] |= FIELD_PREP(RTL931X_LAG_TRK_DEV3, e->trk_dev3); + data[1] |= FIELD_PREP(RTL931X_LAG_TRK_PORT3, e->trk_port3); + + /* 31-0 */ + data[2] = FIELD_PREP(RTL931X_LAG_TRK_DEV2, e->trk_dev2); + data[2] |= FIELD_PREP(RTL931X_LAG_TRK_PORT2, e->trk_port2); + data[2] |= FIELD_PREP(RTL931X_LAG_TRK_DEV1, e->trk_dev1); + data[2] |= FIELD_PREP(RTL931X_LAG_TRK_PORT1, e->trk_port1); + data[2] |= FIELD_PREP(RTL931X_LAG_TRK_DEV0, e->trk_dev0); + data[2] |= FIELD_PREP(RTL931X_LAG_TRK_PORT0, e->trk_port0); +} + +static void rtldsa_931x_lag_set_local_group_id(int local_group, int global_group, bool valid) +{ + u32 mask = 0; + + mask |= valid ? RTL931X_TRK_ID_CTRL_TRK_VALID : 0; + mask |= FIELD_PREP(RLT931X_TRK_ID_CTRL_TRK_ID, global_group); + sw_w32(mask, RTL931X_TRK_ID_CTRL + (4 * local_group)); +} + +static void rtldsa_931x_lag_set_local_port2group(int group, int port, bool valid) +{ + u32 mask = 0; + + mask |= valid ? RTL931X_LOCAL_PORT_TRK_MAP_IS_TRK_MBR : 0; + mask |= FIELD_PREP(RTL931X_LOCAL_PORT_TRK_MAP_TRK_ID, group); + sw_w32(mask, RTL931X_LOCAL_PORT_TRK_MAP + (4 * port)); +} + +static void rtldsa_931x_lag_sync_tables(void) +{ + u32 val; + int ret; + + sw_w32(BIT(0), RTL931X_TRK_LOCAL_TBL_REFRESH); + + ret = readx_poll_timeout(sw_r32, RTL931X_TRK_LOCAL_TBL_REFRESH, val, + !(val & BIT(0)), 20, 10000); + if (ret) + pr_err("%s: timeout\n", __func__); +} + +static struct table_reg *rtldsa_931x_lag_table(void) +{ + return rtl_table_get(RTL9310_TBL_2, 0); +} + +static u64 rtldsa_931x_stat_port_table_read(int port, unsigned int mib_size, + unsigned int mib_offset, bool is_pvt) +{ + struct table_reg *r; + int field_offset; + u64 ret = 0; + + if (is_pvt) { + r = rtl_table_get(RTL9310_TBL_5, 1); + field_offset = 27; + } else { + r = rtl_table_get(RTL9310_TBL_5, 0); + field_offset = 52; + } + + rtl_table_read(r, port); + + if (mib_size == 2) { + ret = sw_r32(rtl_table_data(r, field_offset - (mib_offset + 1))); + ret <<= 32; + } + + ret |= sw_r32(rtl_table_data(r, field_offset - mib_offset)); + + rtl_table_release(r); + + return ret; +} + +static void rtldsa_931x_qos_set_group_selector(int port, int group) +{ + sw_w32_mask(RTL93XX_PORT_TBL_IDX_CTRL_IDX_MASK(port), + group << RTL93XX_PORT_TBL_IDX_CTRL_IDX_OFFSET(port), + RTL931X_PORT_TBL_IDX_CTRL(port)); +} + +static void rtldsa_931x_qos_setup_default_dscp2queue_map(void) +{ + u32 queue; + + /* The default mapping between dscp and queue is based on + * the first 3 bits indicate the precedence (prio = dscp >> 3). + */ + for (int i = 0; i < DSCP_MAP_MAX; i++) { + queue = (i >> 3) << RTL93XX_REMAP_DSCP_INTPRI_DSCP_OFFSET(i); + sw_w32_mask(RTL93XX_REMAP_DSCP_INTPRI_DSCP_MASK(i), + queue, RTL931X_REMAP_DSCP(i)); + } +} + +static void rtldsa_931x_qos_prio2queue_matrix(int *min_queues) +{ + u32 v = 0; + + for (int i = 0; i < MAX_PRIOS; i++) + v |= i << (min_queues[i] * 3); + + sw_w32(v, RTL931X_QM_INTPRI2QID_CTRL); +} + +static void rtldsa_931x_qos_set_scheduling_queue_weights(struct rtl838x_switch_priv *priv) +{ + struct dsa_port *dp; + u32 addr; + + dsa_switch_for_each_user_port(dp, priv->ds) { + for (int q = 0; q < 8; q++) { + if (dp->index < 51) + addr = RTL931X_SCHED_PORT_Q_CTRL_SET0(dp->index, q); + else + addr = RTL931X_SCHED_PORT_Q_CTRL_SET1(dp->index, q); + + sw_w32(rtldsa_default_queue_weights[q], addr); + } + } +} + +static void rtldsa_931x_qos_init(struct rtl838x_switch_priv *priv) +{ + struct dsa_port *dp; + u32 v; + + /* Assign all the ports to the Group-0 */ + dsa_switch_for_each_user_port(dp, priv->ds) + rtldsa_931x_qos_set_group_selector(dp->index, 0); + + rtldsa_931x_qos_prio2queue_matrix(rtldsa_max_available_queue); + + /* configure priority weights */ + v = 0; + v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_PORT_MASK, 3); + v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_DSCP_MASK, 5); + v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_ITAG_MASK, 6); + v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_OTAG_MASK, 7); + + sw_w32(v, RTL931X_PRI_SEL_TBL_CTRL(0) + 4); + sw_w32(0, RTL931X_PRI_SEL_TBL_CTRL(0)); + + rtldsa_931x_qos_setup_default_dscp2queue_map(); + rtldsa_931x_qos_set_scheduling_queue_weights(priv); +} + +const struct rtldsa_config rtldsa_931x_cfg = { + .mask_port_reg_be = rtl839x_mask_port_reg_be, + .set_port_reg_be = rtl839x_set_port_reg_be, + .get_port_reg_be = rtl839x_get_port_reg_be, + .mask_port_reg_le = rtl839x_mask_port_reg_le, + .set_port_reg_le = rtl839x_set_port_reg_le, + .get_port_reg_le = rtl839x_get_port_reg_le, + .stat_port_rst = RTL931X_STAT_PORT_RST, + .stat_rst = RTL931X_STAT_RST, + .stat_port_std_mib = 0, /* Not defined */ + .mib_desc = &rtldsa_931x_mib_desc, + .stat_port_table_read = rtldsa_931x_stat_port_table_read, + .stat_counters_lock = rtldsa_counters_lock_table, + .stat_counters_unlock = rtldsa_counters_unlock_table, + .stat_counter_poll_interval = RTLDSA_COUNTERS_FAST_POLL_INTERVAL, + .traffic_enable = rtl931x_traffic_enable, + .traffic_disable = rtl931x_traffic_disable, + .traffic_set = rtl931x_traffic_set, + .l2_ctrl_0 = RTL931X_L2_CTRL, + .l2_ctrl_1 = RTL931X_L2_AGE_CTRL, + .l2_port_aging_out = RTL931X_L2_PORT_AGE_CTRL, + .set_ageing_time = rtl931x_set_ageing_time, + .smi_poll_ctrl = RTL931X_SMI_PORT_POLLING_CTRL, + .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL, + .exec_tbl0_cmd = rtl931x_exec_tbl0_cmd, + .exec_tbl1_cmd = rtl931x_exec_tbl1_cmd, + .tbl_access_data_0 = rtl931x_tbl_access_data_0, + .isr_glb_src = RTL931X_ISR_GLB_SRC, + .isr_port_link_sts_chg = RTL931X_ISR_PORT_LINK_STS_CHG, + .imr_port_link_sts_chg = RTL931X_IMR_PORT_LINK_STS_CHG, + /* imr_glb does not exist on RTL931X */ + .n_counters = 2048, + .n_pie_blocks = 16, + .port_ignore = 0x3f, + .vlan_tables_read = rtl931x_vlan_tables_read, + .vlan_set_tagged = rtl931x_vlan_set_tagged, + .vlan_set_untagged = rtl931x_vlan_set_untagged, + .vlan_profile_get = rtldsa_931x_vlan_profile_get, + .vlan_profile_dump = rtldsa_931x_vlan_profile_dump, + .vlan_profile_setup = rtl931x_vlan_profile_setup, + .vlan_fwd_on_inner = rtl931x_vlan_fwd_on_inner, + .stp_get = rtldsa_931x_stp_get, + .stp_set = rtl931x_stp_set, + .mac_force_mode_ctrl = rtl931x_mac_force_mode_ctrl, + .mac_link_sts = RTL931X_MAC_LINK_STS, + .mac_port_ctrl = rtl931x_mac_port_ctrl, + .l2_port_new_salrn = rtl931x_l2_port_new_salrn, + .l2_port_new_sa_fwd = rtl931x_l2_port_new_sa_fwd, + .get_mirror_config = rtldsa_931x_get_mirror_config, + .port_rate_police_add = rtldsa_931x_port_rate_police_add, + .port_rate_police_del = rtldsa_931x_port_rate_police_del, + .print_matrix = rtldsa_931x_print_matrix, + .read_l2_entry_using_hash = rtl931x_read_l2_entry_using_hash, + .write_l2_entry_using_hash = rtl931x_write_l2_entry_using_hash, + .read_cam = rtl931x_read_cam, + .write_cam = rtl931x_write_cam, + .vlan_port_keep_tag_set = rtl931x_vlan_port_keep_tag_set, + .vlan_port_pvidmode_set = rtl931x_vlan_port_pvidmode_set, + .vlan_port_pvid_set = rtl931x_vlan_port_pvid_set, + .fast_age = rtldsa_931x_fast_age, + .trk_mbr_ctr = rtldsa_931x_trk_mbr_ctr, + .rma_bpdu_fld_pmask = RTL931X_RMA_BPDU_FLD_PMSK, + .set_vlan_igr_filter = rtl931x_set_igr_filter, + .set_vlan_egr_filter = rtl931x_set_egr_filter, + .l2_hash_key = rtl931x_l2_hash_key, + .l2_hash_seed = rtldsa_931x_l2_hash_seed, + .read_mcast_pmask = rtl931x_read_mcast_pmask, + .write_mcast_pmask = rtl931x_write_mcast_pmask, + .pie_init = rtl931x_pie_init, + .pie_rule_write = rtl931x_pie_rule_write, + .pie_rule_add = rtl931x_pie_rule_add, + .pie_rule_rm = rtl931x_pie_rule_rm, + .l2_learning_setup = rtl931x_l2_learning_setup, + .led_init = rtldsa_931x_led_init, + .enable_learning = rtldsa_931x_enable_learning, + .enable_flood = rtldsa_931x_enable_flood, + .set_receive_management_action = rtldsa_931x_set_receive_management_action, + .qos_init = rtldsa_931x_qos_init, + .trk_ctrl = RTL931X_TRK_CTRL, + .trk_hash_ctrl = RTL931X_TRK_HASH_CTRL, + .prepare_lag_fdb = rtldsa_93xx_prepare_lag_fdb, + .lag_switch_init = rtldsa_93xx_lag_switch_init, + .lag_set_port_members = rtldsa_93xx_lag_set_port_members, + .lag_set_distribution_algorithm = rtldsa_93xx_lag_set_distribution_algorithm, + .lag_set_local_group_id = rtldsa_931x_lag_set_local_group_id, + .lag_write_data = rtldsa_931x_lag_write_data, + .lag_fill_data = rtldsa_931x_lag_fill_data, + .lag_set_local_port2group = rtldsa_931x_lag_set_local_port2group, + .lag_set_port2group = rtldsa_931x_lag_set_port2group, + .lag_sync_tables = rtldsa_931x_lag_sync_tables, + .lag_table = rtldsa_931x_lag_table, +}; diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/tc.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/tc.c new file mode 100644 index 0000000000..4a9b6b8c9f --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/tc.c @@ -0,0 +1,409 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include + +#include "rtl83xx.h" +#include "rtl838x.h" + +/* Parse the flow rule for the matching conditions */ +static int rtl83xx_parse_flow_rule(struct rtl838x_switch_priv *priv, + struct flow_rule *rule, struct rtl83xx_flow *flow) +{ + struct flow_dissector *dissector = rule->match.dissector; + + pr_debug("In %s\n", __func__); + /* KEY_CONTROL and KEY_BASIC are needed for forming a meaningful key */ + if ((dissector->used_keys & BIT(FLOW_DISSECTOR_KEY_CONTROL)) == 0 || + (dissector->used_keys & BIT(FLOW_DISSECTOR_KEY_BASIC)) == 0) { + pr_err("Cannot form TC key: used_keys = 0x%llx\n", dissector->used_keys); + return -EOPNOTSUPP; + } + + if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { + struct flow_match_basic match; + + pr_debug("%s: BASIC\n", __func__); + flow_rule_match_basic(rule, &match); + if (match.key->n_proto == htons(ETH_P_ARP)) + flow->rule.frame_type = 0; + if (match.key->n_proto == htons(ETH_P_IP)) + flow->rule.frame_type = 2; + if (match.key->n_proto == htons(ETH_P_IPV6)) + flow->rule.frame_type = 3; + if ((match.key->n_proto == htons(ETH_P_ARP)) || flow->rule.frame_type) + flow->rule.frame_type_m = 3; + if (flow->rule.frame_type >= 2) { + if (match.key->ip_proto == IPPROTO_UDP) + flow->rule.frame_type_l4 = 0; + if (match.key->ip_proto == IPPROTO_TCP) + flow->rule.frame_type_l4 = 1; + if (match.key->ip_proto == IPPROTO_ICMP || match.key->ip_proto == IPPROTO_ICMPV6) + flow->rule.frame_type_l4 = 2; + if (match.key->ip_proto == IPPROTO_TCP) + flow->rule.frame_type_l4 = 3; + if ((match.key->ip_proto == IPPROTO_UDP) || flow->rule.frame_type_l4) + flow->rule.frame_type_l4_m = 7; + } + } + + if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { + struct flow_match_eth_addrs match; + + pr_debug("%s: ETH_ADDR\n", __func__); + flow_rule_match_eth_addrs(rule, &match); + ether_addr_copy(flow->rule.dmac, match.key->dst); + ether_addr_copy(flow->rule.dmac_m, match.mask->dst); + ether_addr_copy(flow->rule.smac, match.key->src); + ether_addr_copy(flow->rule.smac_m, match.mask->src); + } + + if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { + struct flow_match_vlan match; + + pr_debug("%s: VLAN\n", __func__); + flow_rule_match_vlan(rule, &match); + flow->rule.itag = match.key->vlan_id; + flow->rule.itag_m = match.mask->vlan_id; + /* TODO: What about match.key->vlan_priority? */ + } + + if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IPV4_ADDRS)) { + struct flow_match_ipv4_addrs match; + + pr_debug("%s: IPV4\n", __func__); + flow_rule_match_ipv4_addrs(rule, &match); + flow->rule.is_ipv6 = false; + flow->rule.dip = match.key->dst; + flow->rule.dip_m = match.mask->dst; + flow->rule.sip = match.key->src; + flow->rule.sip_m = match.mask->src; + } else if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IPV6_ADDRS)) { + struct flow_match_ipv6_addrs match; + + pr_debug("%s: IPV6\n", __func__); + flow->rule.is_ipv6 = true; + flow_rule_match_ipv6_addrs(rule, &match); + flow->rule.dip6 = match.key->dst; + flow->rule.dip6_m = match.mask->dst; + flow->rule.sip6 = match.key->src; + flow->rule.sip6_m = match.mask->src; + } + + if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) { + struct flow_match_ports match; + + pr_debug("%s: PORTS\n", __func__); + flow_rule_match_ports(rule, &match); + flow->rule.dport = match.key->dst; + flow->rule.dport_m = match.mask->dst; + flow->rule.sport = match.key->src; + flow->rule.sport_m = match.mask->src; + } + + /* TODO: ICMP */ + return 0; +} + +static void rtl83xx_flow_bypass_all(struct rtl83xx_flow *flow) +{ + flow->rule.bypass_sel = true; + flow->rule.bypass_all = true; + flow->rule.bypass_igr_stp = true; + flow->rule.bypass_ibc_sc = true; +} + +static int rtl83xx_parse_fwd(struct rtl838x_switch_priv *priv, + const struct flow_action_entry *act, struct rtl83xx_flow *flow) +{ + struct net_device *dev = act->dev; + int port; + + port = rtl83xx_port_is_under(dev, priv); + if (port < 0) { + netdev_info(dev, "%s: not a DSA device.\n", __func__); + return -EINVAL; + } + + flow->rule.fwd_sel = true; + flow->rule.fwd_data = port; + pr_debug("Using port index: %d\n", port); + rtl83xx_flow_bypass_all(flow); + + return 0; +} + +static int rtl83xx_add_flow(struct rtl838x_switch_priv *priv, struct flow_cls_offload *f, + struct rtl83xx_flow *flow) +{ + struct flow_rule *rule = flow_cls_offload_flow_rule(f); + const struct flow_action_entry *act; + int i, err; + + pr_debug("%s\n", __func__); + + rtl83xx_parse_flow_rule(priv, rule, flow); + + flow_action_for_each(i, act, &rule->action) { + switch (act->id) { + case FLOW_ACTION_DROP: + pr_debug("%s: DROP\n", __func__); + flow->rule.drop = true; + rtl83xx_flow_bypass_all(flow); + return 0; + + case FLOW_ACTION_TRAP: + pr_debug("%s: TRAP\n", __func__); + flow->rule.fwd_data = priv->cpu_port; + flow->rule.fwd_act = PIE_ACT_REDIRECT_TO_PORT; + rtl83xx_flow_bypass_all(flow); + break; + + case FLOW_ACTION_MANGLE: + pr_err("%s: FLOW_ACTION_MANGLE not supported\n", __func__); + return -EOPNOTSUPP; + + case FLOW_ACTION_ADD: + pr_err("%s: FLOW_ACTION_ADD not supported\n", __func__); + return -EOPNOTSUPP; + + case FLOW_ACTION_VLAN_PUSH: + pr_debug("%s: VLAN_PUSH\n", __func__); +/* TODO: act->vlan.proto */ + flow->rule.ivid_act = PIE_ACT_VID_ASSIGN; + flow->rule.ivid_sel = true; + flow->rule.ivid_data = htons(act->vlan.vid); + flow->rule.ovid_act = PIE_ACT_VID_ASSIGN; + flow->rule.ovid_sel = true; + flow->rule.ovid_data = htons(act->vlan.vid); + flow->rule.fwd_mod_to_cpu = true; + break; + + case FLOW_ACTION_VLAN_POP: + pr_debug("%s: VLAN_POP\n", __func__); + flow->rule.ivid_act = PIE_ACT_VID_ASSIGN; + flow->rule.ivid_data = 0; + flow->rule.ivid_sel = true; + flow->rule.ovid_act = PIE_ACT_VID_ASSIGN; + flow->rule.ovid_data = 0; + flow->rule.ovid_sel = true; + flow->rule.fwd_mod_to_cpu = true; + break; + + case FLOW_ACTION_CSUM: + pr_err("%s: FLOW_ACTION_CSUM not supported\n", __func__); + return -EOPNOTSUPP; + + case FLOW_ACTION_REDIRECT: + pr_debug("%s: REDIRECT\n", __func__); + err = rtl83xx_parse_fwd(priv, act, flow); + if (err) + return err; + flow->rule.fwd_act = PIE_ACT_REDIRECT_TO_PORT; + break; + + case FLOW_ACTION_MIRRED: + pr_debug("%s: MIRRED\n", __func__); + err = rtl83xx_parse_fwd(priv, act, flow); + if (err) + return err; + flow->rule.fwd_act = PIE_ACT_COPY_TO_PORT; + break; + + default: + pr_err("%s: Flow action not supported: %d\n", __func__, act->id); + return -EOPNOTSUPP; + } + } + + return 0; +} + +static const struct rhashtable_params tc_ht_params = { + .head_offset = offsetof(struct rtl83xx_flow, node), + .key_offset = offsetof(struct rtl83xx_flow, cookie), + .key_len = sizeof(((struct rtl83xx_flow *)0)->cookie), + .automatic_shrinking = true, +}; + +static int rtl83xx_configure_flower(struct rtl838x_switch_priv *priv, + struct flow_cls_offload *f) +{ + struct rtl83xx_flow *flow; + int err = 0; + + pr_debug("In %s\n", __func__); + + rcu_read_lock(); + pr_debug("Cookie %08lx\n", f->cookie); + flow = rhashtable_lookup(&priv->tc_ht, &f->cookie, tc_ht_params); + if (flow) { + pr_info("%s: Got flow\n", __func__); + err = -EEXIST; + goto rcu_unlock; + } + +rcu_unlock: + rcu_read_unlock(); + if (flow) + goto out; + pr_debug("%s: New flow\n", __func__); + + flow = kzalloc(sizeof(*flow), GFP_KERNEL); + if (!flow) { + err = -ENOMEM; + goto out; + } + + flow->cookie = f->cookie; + flow->priv = priv; + + err = rhashtable_insert_fast(&priv->tc_ht, &flow->node, tc_ht_params); + if (err) { + pr_err("Could not insert add new rule\n"); + goto out_free; + } + + rtl83xx_add_flow(priv, f, flow); /* TODO: check error */ + + /* Add log action to flow */ + flow->rule.packet_cntr = rtl83xx_packet_cntr_alloc(priv); + if (flow->rule.packet_cntr >= 0) { + pr_debug("Using packet counter %d\n", flow->rule.packet_cntr); + flow->rule.log_sel = true; + flow->rule.log_data = flow->rule.packet_cntr; + } + + err = priv->r->pie_rule_add(priv, &flow->rule); + return err; + +out_free: + kfree(flow); +out: + pr_err("%s: error %d\n", __func__, err); + + return err; +} + +static int rtl83xx_delete_flower(struct rtl838x_switch_priv *priv, + struct flow_cls_offload *cls_flower) +{ + struct rtl83xx_flow *flow; + + pr_debug("In %s\n", __func__); + rcu_read_lock(); + flow = rhashtable_lookup_fast(&priv->tc_ht, &cls_flower->cookie, tc_ht_params); + if (!flow) { + rcu_read_unlock(); + return -EINVAL; + } + + priv->r->pie_rule_rm(priv, &flow->rule); + + rhashtable_remove_fast(&priv->tc_ht, &flow->node, tc_ht_params); + + kfree_rcu(flow, rcu_head); + + rcu_read_unlock(); + + return 0; +} + +static int rtl83xx_stats_flower(struct rtl838x_switch_priv *priv, + struct flow_cls_offload *cls_flower) +{ + struct rtl83xx_flow *flow; + unsigned long lastused = 0; + int total_packets, new_packets; + + pr_debug("%s:\n", __func__); + flow = rhashtable_lookup_fast(&priv->tc_ht, &cls_flower->cookie, tc_ht_params); + if (!flow) + return -1; + + if (flow->rule.packet_cntr >= 0) { + total_packets = priv->r->packet_cntr_read(flow->rule.packet_cntr); + pr_debug("Total packets: %d\n", total_packets); + new_packets = total_packets - flow->rule.last_packet_cnt; + flow->rule.last_packet_cnt = total_packets; + } + + /* TODO: We need a second PIE rule to count the bytes */ + flow_stats_update(&cls_flower->stats, 100 * new_packets, new_packets, 0, lastused, + FLOW_ACTION_HW_STATS_IMMEDIATE); + + return 0; +} + +static int rtl83xx_setup_tc_cls_flower(struct rtl838x_switch_priv *priv, + struct flow_cls_offload *cls_flower) +{ + pr_debug("%s: %d\n", __func__, cls_flower->command); + switch (cls_flower->command) { + case FLOW_CLS_REPLACE: + return rtl83xx_configure_flower(priv, cls_flower); + case FLOW_CLS_DESTROY: + return rtl83xx_delete_flower(priv, cls_flower); + case FLOW_CLS_STATS: + return rtl83xx_stats_flower(priv, cls_flower); + default: + return -EOPNOTSUPP; + } +} + +static int rtl83xx_setup_tc_block_cb(enum tc_setup_type type, void *type_data, + void *cb_priv) +{ + struct rtl838x_switch_priv *priv = cb_priv; + + switch (type) { + case TC_SETUP_CLSFLOWER: + pr_debug("%s: TC_SETUP_CLSFLOWER\n", __func__); + return rtl83xx_setup_tc_cls_flower(priv, type_data); + default: + return -EOPNOTSUPP; + } +} + +static LIST_HEAD(rtl83xx_block_cb_list); + +int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data) +{ + struct rtl838x_switch_priv *priv; + struct flow_block_offload *f = type_data; + static bool first_time = true; + int err; + + pr_debug("%s: %d\n", __func__, type); + + if (!netdev_uses_dsa(dev)) { + pr_err("%s: no DSA\n", __func__); + return 0; + } + priv = dev->dsa_ptr->ds->priv; + + switch (type) { + case TC_SETUP_BLOCK: + if (first_time) { + first_time = false; + err = rhashtable_init(&priv->tc_ht, &tc_ht_params); + if (err) + pr_err("%s: Could not initialize hash table\n", __func__); + } + + f->unlocked_driver_cb = true; + return flow_block_cb_setup_simple(type_data, + &rtl83xx_block_cb_list, + rtl83xx_setup_tc_block_cb, + priv, priv, true); + default: + return -EOPNOTSUPP; + } + + return 0; +} diff --git a/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c new file mode 100644 index 0000000000..fc0e5ddc22 --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c @@ -0,0 +1,1663 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* linux/drivers/net/ethernet/rtl838x_eth.c + * Copyright (C) 2020 B. Koblitz + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "rtl838x_eth.h" + +#define RTETH_OWN_CPU 1 +#define RTETH_RX_RING_SIZE 128 +#define RTETH_RX_RINGS 2 +#define RTETH_TX_RING_SIZE 16 +#define RTETH_TX_RINGS 2 +#define RTETH_TX_TRIGGER(ctrl, ring) ((0x16 >> ring) & ctrl->r->tx_trigger_mask) + +#define NOTIFY_EVENTS 10 +#define NOTIFY_BLOCKS 10 +#define RX_TRUNCATE_EN_93XX BIT(6) +#define RX_TRUNCATE_EN_83XX BIT(4) +#define TX_PAD_EN_838X BIT(5) +#define WRAP 0x2 +#define RING_BUFFER 1600 + +struct rteth_packet { + /* hardware header part as required by SoC */ + dma_addr_t dma; + u16 reserved; + u16 size; + u16 offset; + u16 len; + u16 cpu_tag[10]; + /* software mangement and data part */ + union { + struct sk_buff *skb; + char *buf; + }; +} __packed __aligned(1); + +struct rteth_rx { + int slot; + dma_addr_t ring[RTETH_RX_RING_SIZE]; + struct rteth_packet packet[RTETH_RX_RING_SIZE]; +}; + +struct rteth_tx { + int slot; + dma_addr_t ring[RTETH_TX_RING_SIZE]; + struct rteth_packet packet[RTETH_TX_RING_SIZE]; +}; + +struct n_event { + u32 type:2; + u32 fidVid:12; + u64 mac:48; + u32 slp:6; + u32 valid:1; + u32 reserved:27; +} __packed __aligned(1); + +struct notify_block { + struct n_event events[NOTIFY_EVENTS]; +}; + +struct notify_b { + struct notify_block blocks[NOTIFY_BLOCKS]; + u32 reserved1[8]; + u32 ring[NOTIFY_BLOCKS]; + u32 reserved2[8]; +}; + +static void rteth_838x_create_tx_header(struct rteth_packet *h, unsigned int dest_port, int prio) +{ + /* cpu_tag[0] is reserved on the RTL83XX SoCs */ + h->cpu_tag[1] = 0x0400; /* BIT 10: RTL8380_CPU_TAG */ + h->cpu_tag[2] = 0x0200; /* Set only AS_DPM, to enable DPM settings below */ + h->cpu_tag[3] = 0x0000; + h->cpu_tag[4] = BIT(dest_port) >> 16; + h->cpu_tag[5] = BIT(dest_port) & 0xffff; + + /* Set internal priority (PRI) and enable (AS_PRI) */ + if (prio >= 0) + h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 12; +} + +static void rteth_839x_create_tx_header(struct rteth_packet *h, unsigned int dest_port, int prio) +{ + /* cpu_tag[0] is reserved on the RTL83XX SoCs */ + h->cpu_tag[1] = 0x0100; /* RTL8390_CPU_TAG marker */ + h->cpu_tag[2] = BIT(4); /* AS_DPM flag */ + h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0; + /* h->cpu_tag[1] |= BIT(1) | BIT(0); */ /* Bypass filter 1/2 */ + if (dest_port >= 32) { + dest_port -= 32; + h->cpu_tag[2] |= (BIT(dest_port) >> 16) & 0xf; + h->cpu_tag[3] = BIT(dest_port) & 0xffff; + } else { + h->cpu_tag[4] = BIT(dest_port) >> 16; + h->cpu_tag[5] = BIT(dest_port) & 0xffff; + } + + /* Set internal priority (PRI) and enable (AS_PRI) */ + if (prio >= 0) + h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 8; +} + +static void rteth_93xx_create_tx_header(struct rteth_packet *h, unsigned int dest_port, int prio) +{ + h->cpu_tag[0] = 0x8000; /* CPU tag marker */ + h->cpu_tag[1] = FIELD_PREP(RTL93XX_CPU_TAG1_FWD_MASK, RTL93XX_CPU_TAG1_FWD_PHYSICAL) | + FIELD_PREP(RTL93XX_CPU_TAG1_IGNORE_STP_MASK, 1); + + h->cpu_tag[2] = (prio >= 0) ? (BIT(5) | (prio & 0x1f)) << 8 : 0; + h->cpu_tag[3] = 0; + h->cpu_tag[4] = BIT_ULL(dest_port) >> 48; + h->cpu_tag[5] = BIT_ULL(dest_port) >> 32; + h->cpu_tag[6] = BIT_ULL(dest_port) >> 16; + h->cpu_tag[7] = BIT_ULL(dest_port) & 0xffff; +} + +struct rtl838x_rx_q { + int id; + struct rteth_ctrl *ctrl; + struct napi_struct napi; +}; + +struct rteth_ctrl { + struct net_device *netdev; + struct platform_device *pdev; + void *membase; + spinlock_t lock; + struct mii_bus *mii_bus; + struct rtl838x_rx_q rx_qs[RTETH_RX_RINGS]; + struct phylink *phylink; + struct phylink_config phylink_config; + const struct rteth_config *r; + u32 lastEvent; + /* receive handling */ + dma_addr_t rx_buf_dma; + char *rx_buf; + dma_addr_t rx_data_dma; + spinlock_t rx_lock; + struct rteth_rx *rx_data; + /* transmit handling */ + dma_addr_t tx_dma; + spinlock_t tx_lock; + struct rteth_tx *tx_data; +}; + +static inline void rteth_reenable_irq(struct rteth_ctrl *ctrl, int ring) +{ + u32 shift = ctrl->r->rx_rings % 32; + u32 reg = ctrl->r->rx_rings / 32; + unsigned long flags; + + spin_lock_irqsave(&ctrl->lock, flags); + sw_w32_mask(0, BIT(ring + shift), ctrl->r->dma_if_intr_msk + reg * 4); + spin_unlock_irqrestore(&ctrl->lock, flags); +} + +static inline void rteth_confirm_and_disable_irqs(struct rteth_ctrl *ctrl, + unsigned long *rings, bool *l2) +{ + u32 mask = GENMASK(ctrl->r->rx_rings - 1, 0); + u32 shift = ctrl->r->rx_rings % 32; + u32 reg = ctrl->r->rx_rings / 32; + unsigned long flags; + u32 active; + + /* get all irqs, disable only rx (on RTL839x this keeps L2), confirm all */ + spin_lock_irqsave(&ctrl->lock, flags); + active = sw_r32(ctrl->r->dma_if_intr_sts + reg * 4); + sw_w32_mask(active & (mask << shift), 0, ctrl->r->dma_if_intr_msk + reg * 4); + sw_w32(active, ctrl->r->dma_if_intr_sts + reg * 4); + spin_unlock_irqrestore(&ctrl->lock, flags); + + /* ~mask filters out RTL93xx devices */ + *l2 = !!(active & ~mask & RTL839X_DMA_IF_INTR_NOTIFY_MASK); + *rings = (active >> shift) & mask; +} + +static void rteth_disable_all_irqs(struct rteth_ctrl *ctrl) +{ + int registers = ((ctrl->r->rx_rings * 2 + 7) / 32) + 1; + + for (int reg = 0; reg < registers; reg++) { + sw_w32(0, ctrl->r->dma_if_intr_msk + reg * 4); + sw_w32(GENMASK(31, 0), ctrl->r->dma_if_intr_sts + reg * 4); + } +} + +static void rteth_enable_all_rx_irqs(struct rteth_ctrl *ctrl) +{ + int mask, shift, reg; + + /* + * The hardware has several types of interrupts. Basically for rx/tx completion and + * if hardware queues run out. For now the driver only needs notification about new + * incoming packets. Leave everything else disabled. + */ + mask = GENMASK(ctrl->r->rx_rings - 1, 0); + shift = ctrl->r->rx_rings % 32; + reg = ctrl->r->rx_rings / 32; + sw_w32_mask(0, mask << shift, ctrl->r->dma_if_intr_msk + reg * 4); + + /* + * RTL839x has additional L2 notification interrupts. Simply activate them. All other + * devices that do not have the feature have adequate reserved bit space and ignore it. + */ + mask = GENMASK(2, 0); + shift = (ctrl->r->rx_rings * 2 + 4) % 32; + reg = (ctrl->r->rx_rings * 2 + 4) / 32; + sw_w32_mask(0, mask << shift, ctrl->r->dma_if_intr_msk + reg * 4); +} + +static void rteth_83xx_update_counter(struct rteth_ctrl *ctrl, int ring, int released) +{ + /* Free floating rings without space tracking */ +} + +static void rteth_93xx_update_counter(struct rteth_ctrl *ctrl, int ring, int released) +{ + int pos = (ring % 3) * 10; + + /* writing x to the ring counter increases ring free space by x */ + sw_w32(released << pos, ctrl->r->dma_if_rx_ring_cntr(ring)); +} + +struct dsa_tag { + u8 reason; + u8 queue; + u16 port; + u8 l2_offloaded; + u8 prio; + bool crc_error; +}; + +static bool rteth_838x_decode_tag(struct rteth_packet *h, struct dsa_tag *t) +{ + /* cpu_tag[0] is reserved. Fields are off-by-one */ + t->reason = h->cpu_tag[4] & 0xf; + t->queue = (h->cpu_tag[1] & 0xe0) >> 5; + t->port = h->cpu_tag[1] & 0x1f; + t->crc_error = t->reason == 13; + + pr_debug("Reason: %d\n", t->reason); + if (t->reason != 6) /* NIC_RX_REASON_SPECIAL_TRAP */ + t->l2_offloaded = 1; + else + t->l2_offloaded = 0; + + return t->l2_offloaded; +} + +static bool rteth_839x_decode_tag(struct rteth_packet *h, struct dsa_tag *t) +{ + /* cpu_tag[0] is reserved. Fields are off-by-one */ + t->reason = h->cpu_tag[5] & 0x1f; + t->queue = (h->cpu_tag[4] & 0xe000) >> 13; + t->port = h->cpu_tag[1] & 0x3f; + t->crc_error = h->cpu_tag[4] & BIT(6); + + pr_debug("Reason: %d\n", t->reason); + if ((t->reason >= 7 && t->reason <= 13) || /* NIC_RX_REASON_RMA */ + (t->reason >= 23 && t->reason <= 25)) /* NIC_RX_REASON_SPECIAL_TRAP */ + t->l2_offloaded = 0; + else + t->l2_offloaded = 1; + + return t->l2_offloaded; +} + +static bool rteth_930x_decode_tag(struct rteth_packet *h, struct dsa_tag *t) +{ + t->reason = h->cpu_tag[7] & 0x3f; + t->queue = (h->cpu_tag[2] >> 11) & 0x1f; + t->port = (h->cpu_tag[0] >> 8) & 0x1f; + t->crc_error = h->cpu_tag[1] & BIT(6); + + pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue); + if (t->reason >= 19 && t->reason <= 27) + t->l2_offloaded = 0; + else + t->l2_offloaded = 1; + + return t->l2_offloaded; +} + +static bool rteth_931x_decode_tag(struct rteth_packet *h, struct dsa_tag *t) +{ + t->reason = h->cpu_tag[7] & 0x3f; + t->queue = (h->cpu_tag[2] >> 11) & 0x1f; + t->port = (h->cpu_tag[0] >> 8) & 0x3f; + t->crc_error = h->cpu_tag[1] & BIT(6); + + if (t->reason != 63) + pr_debug("%s: Reason %d, port %d, queue %d\n", __func__, t->reason, t->port, t->queue); + if (t->reason >= 19 && t->reason <= 27) /* NIC_RX_REASON_RMA */ + t->l2_offloaded = 0; + else + t->l2_offloaded = 1; + + return t->l2_offloaded; +} + +struct fdb_update_work { + struct work_struct work; + struct net_device *ndev; + u64 macs[NOTIFY_EVENTS + 1]; +}; + +static void rtl838x_fdb_sync(struct work_struct *work) +{ + const struct fdb_update_work *uw = container_of(work, struct fdb_update_work, work); + + for (int i = 0; uw->macs[i]; i++) { + struct switchdev_notifier_fdb_info info; + u8 addr[ETH_ALEN]; + int action; + + action = (uw->macs[i] & (1ULL << 63)) ? + SWITCHDEV_FDB_ADD_TO_BRIDGE : + SWITCHDEV_FDB_DEL_TO_BRIDGE; + u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr); + info.addr = &addr[0]; + info.vid = 0; + info.offloaded = 1; + pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action); + call_switchdev_notifiers(action, uw->ndev, &info.info, NULL); + } + kfree(work); +} + +static void rtl839x_l2_notification_handler(struct rteth_ctrl *ctrl) +{ + struct notify_b *nb = ctrl->membase; + u32 e = ctrl->lastEvent; + + while (!(nb->ring[e] & 1)) { + struct fdb_update_work *w; + struct n_event *event; + u64 mac; + int i; + + w = kzalloc(sizeof(*w), GFP_ATOMIC); + if (!w) + return; + + INIT_WORK(&w->work, rtl838x_fdb_sync); + + for (i = 0; i < NOTIFY_EVENTS; i++) { + event = &nb->blocks[e].events[i]; + if (!event->valid) + continue; + mac = event->mac; + if (event->type) + mac |= 1ULL << 63; + w->ndev = ctrl->netdev; + w->macs[i] = mac; + } + + /* Hand the ring entry back to the switch */ + nb->ring[e] = nb->ring[e] | 1; + e = (e + 1) % NOTIFY_BLOCKS; + + w->macs[i] = 0ULL; + schedule_work(&w->work); + } + ctrl->lastEvent = e; +} + +static irqreturn_t rteth_net_irq(int irq, void *dev_id) +{ + struct net_device *ndev = dev_id; + struct rteth_ctrl *ctrl = netdev_priv(ndev); + unsigned long ring, rings; + bool l2; + + rteth_confirm_and_disable_irqs(ctrl, &rings, &l2); + for_each_set_bit(ring, &rings, RTETH_RX_RINGS) { + netdev_dbg(ndev, "schedule rx ring %lu\n", ring); + napi_schedule(&ctrl->rx_qs[ring].napi); + } + + if (unlikely(l2)) + rtl839x_l2_notification_handler(ctrl); + + return IRQ_HANDLED; +} + +static void rteth_nic_reset(struct rteth_ctrl *ctrl, int reset_mask) +{ + pr_info("RESETTING CPU_PORT %d\n", ctrl->r->cpu_port); + sw_w32_mask(0x3, 0, ctrl->r->mac_l2_port_ctrl); + mdelay(100); + + /* Reset NIC (SW_NIC_RST) and queues (SW_Q_RST) */ + sw_w32_mask(0, reset_mask, ctrl->r->rst_glb_ctrl); + while (sw_r32(ctrl->r->rst_glb_ctrl) & reset_mask) + udelay(20); + + mdelay(100); +} + +static void rteth_838x_hw_reset(struct rteth_ctrl *ctrl) +{ + rteth_nic_reset(ctrl, 0xc); + + /* Free floating rings without space tracking */ + sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); +} + +static void rteth_839x_hw_reset(struct rteth_ctrl *ctrl) +{ + u32 int_saved, nbuf; + + /* Preserve L2 notification and NBUF settings */ + int_saved = sw_r32(ctrl->r->dma_if_intr_msk); + nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL); + + /* Disable link change interrupt on RTL839x */ + sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG); + sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4); + + rteth_nic_reset(ctrl, 0xc); + + /* Re-enable link change interrupt */ + sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG); + sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4); + sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG); + sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4); + + /* Restore notification settings: on RTL838x these bits are null */ + sw_w32_mask(7 << 20, int_saved & (7 << 20), ctrl->r->dma_if_intr_msk); + sw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL); + + /* Free floating rings without space tracking */ + sw_w32(0, RTL839X_DMA_IF_RX_RING_SIZE); +} + +static void rteth_93xx_hw_reset(struct rteth_ctrl *ctrl) +{ + rteth_nic_reset(ctrl, 0x6); + + /* Setup Head of Line */ + for (int r = 0; r < RTETH_RX_RINGS; r++) { + int cnt = min(RTETH_RX_RING_SIZE, 0x3ff); + int pos = (r % 3) * 10; + u32 v; + + /* set ring size */ + sw_w32_mask(0x3ff << pos, cnt << pos, ctrl->r->dma_if_rx_ring_size(r)); + /* clear counters */ + v = (sw_r32(ctrl->r->dma_if_rx_ring_cntr(r)) >> pos) & 0x3ff; + sw_w32_mask(0x3ff << pos, v, ctrl->r->dma_if_rx_ring_cntr(r)); + } +} + +static void rteth_setup_cpu_rx_rings(struct rteth_ctrl *ctrl) +{ + /* + * Realtek switches either have 8 (RTL83xx) or 32 (RTL93xx) receive queues. Whenever + * a packet is trapped/received for the CPU it is put into one of these queues. This + * is configured via mapping registers in two ways: + * + * - Switching queue/priority to CPU queue mapping (RTL83xx) + * - Reason (why it is sent to CPU) to CPU queue mapping (all devices) + * + * With only low performance CPUs there is not much benefit of using all of these + * queues in parallel. Especially because each queue needs buffer space. To keep + * the queue limit simple, just write the desired CPU queue in a round robin style + * to the registers. + */ + + if (ctrl->r->qm_pkt2cpu_intpri_map) { + for (int priority = 0; priority < 8; priority++) { + int ring = priority % RTETH_RX_RINGS; + int shift = priority * 3; + + sw_w32_mask(0x7 << shift, ring << shift, ctrl->r->qm_pkt2cpu_intpri_map); + } + } + + if (ctrl->r->qm_rsn2cpuqid_ctrl) { + int mask, bits_per_field, fields_per_reg, reason_cnt; + + mask = ctrl->r->rx_rings - 1; + bits_per_field = fls(mask); + fields_per_reg = 32 / bits_per_field; + reason_cnt = ctrl->r->qm_rsn2cpuqid_cnt * fields_per_reg; + + /* Reason registers have gaps. Do not care for now. */ + for (int reason = 0; reason < reason_cnt; reason++) { + int reg = ctrl->r->qm_rsn2cpuqid_ctrl + 4 * (reason / fields_per_reg); + int shift = (reason % fields_per_reg) * bits_per_field; + int ring = reason % RTETH_RX_RINGS; + + sw_w32_mask(mask << shift, ring << shift, reg); + } + } +} + +static void rteth_hw_ring_setup(struct rteth_ctrl *ctrl) +{ + for (int r = 0; r < RTETH_RX_RINGS; r++) + sw_w32(ctrl->rx_data_dma + + r * sizeof(struct rteth_rx) + offsetof(struct rteth_rx, ring), + ctrl->r->dma_rx_base + r * 4); + + for (int r = 0; r < RTETH_TX_RINGS; r++) + sw_w32(ctrl->tx_dma + + r * sizeof(struct rteth_tx) + offsetof(struct rteth_tx, ring), + ctrl->r->dma_tx_base + r * 4); +} + +static void rteth_838x_hw_en_rxtx(struct rteth_ctrl *ctrl) +{ + /* Truncate RX buffer to DEFAULT_MTU bytes, pad TX */ + sw_w32((DEFAULT_MTU << 16) | RX_TRUNCATE_EN_83XX | TX_PAD_EN_838X, ctrl->r->dma_if_ctrl); + + rteth_enable_all_rx_irqs(ctrl); + + /* Enable DMA, engine expects empty FCS field */ + sw_w32_mask(0, ctrl->r->tx_rx_enable, ctrl->r->dma_if_ctrl); + + /* Restart TX/RX to CPU port */ + sw_w32_mask(0x0, 0x3, ctrl->r->mac_l2_port_ctrl); + /* Set Speed, duplex, flow control + * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL + * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN + * | MEDIA_SEL + */ + sw_w32(0x6192F, ctrl->r->mac_force_mode_ctrl); + + /* Enable CRC checks on CPU-port */ + sw_w32_mask(0, BIT(3), ctrl->r->mac_l2_port_ctrl); +} + +static void rteth_839x_hw_en_rxtx(struct rteth_ctrl *ctrl) +{ + /* Setup CPU-Port: RX Buffer */ + sw_w32((DEFAULT_MTU << 5) | RX_TRUNCATE_EN_83XX, ctrl->r->dma_if_ctrl); + + rteth_enable_all_rx_irqs(ctrl); + + /* Enable DMA */ + sw_w32_mask(0, ctrl->r->tx_rx_enable, ctrl->r->dma_if_ctrl); + + /* Restart TX/RX to CPU port, enable CRC checking */ + sw_w32_mask(0x0, 0x3 | BIT(3), ctrl->r->mac_l2_port_ctrl); + + /* CPU port joins Lookup Miss Flooding Portmask */ + /* TODO: The code below should also work for the RTL838x */ + sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL); + sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0)); + sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL); + + /* Force CPU port link up */ + sw_w32_mask(0, 3, ctrl->r->mac_force_mode_ctrl); +} + +static void rteth_930x_hw_en_rxtx(struct rteth_ctrl *ctrl) +{ + /* Setup CPU-Port: RX Buffer truncated at DEFAULT_MTU Bytes */ + sw_w32((DEFAULT_MTU << 16) | RX_TRUNCATE_EN_93XX, ctrl->r->dma_if_ctrl); + + rteth_enable_all_rx_irqs(ctrl); + + /* Enable DMA */ + sw_w32_mask(0, ctrl->r->tx_rx_enable, ctrl->r->dma_if_ctrl); + + /* Restart TX/RX to CPU port, enable CRC checking */ + sw_w32_mask(0x0, 0x3 | BIT(4), ctrl->r->mac_l2_port_ctrl); + + sw_w32_mask(0, BIT(ctrl->r->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK); + sw_w32(0x217, ctrl->r->mac_force_mode_ctrl); +} + +static void rteth_931x_hw_en_rxtx(struct rteth_ctrl *ctrl) +{ + /* Setup CPU-Port: RX Buffer truncated at DEFAULT_MTU Bytes */ + sw_w32((DEFAULT_MTU << 16) | RX_TRUNCATE_EN_93XX, ctrl->r->dma_if_ctrl); + + rteth_enable_all_rx_irqs(ctrl); + + /* Enable DMA */ + sw_w32_mask(0, ctrl->r->tx_rx_enable, ctrl->r->dma_if_ctrl); + + /* Restart TX/RX to CPU port, enable CRC checking */ + sw_w32_mask(0x0, 0x3 | BIT(4), ctrl->r->mac_l2_port_ctrl); + + sw_w32_mask(0, BIT(ctrl->r->cpu_port), RTL931X_L2_UNKN_UC_FLD_PMSK); + sw_w32(0x2a1d, ctrl->r->mac_force_mode_ctrl); +} + +static void rteth_setup_ring_buffer(struct rteth_ctrl *ctrl) +{ + dma_addr_t rx_buf_dma = ctrl->rx_buf_dma; + char *rx_buf = ctrl->rx_buf; + + for (int r = 0; r < RTETH_RX_RINGS; r++) { + for (int i = 0; i < RTETH_RX_RING_SIZE; i++) { + ctrl->rx_data[r].packet[i].size = RING_BUFFER; + ctrl->rx_data[r].packet[i].dma = rx_buf_dma; + ctrl->rx_data[r].packet[i].buf = rx_buf; + ctrl->rx_data[r].ring[i] = ctrl->rx_data_dma + + sizeof(struct rteth_rx) * r + + offsetof(struct rteth_rx, packet) + + sizeof(struct rteth_packet) * i + + RTETH_OWN_CPU; + rx_buf += RING_BUFFER; + rx_buf_dma += RING_BUFFER; + } + + ctrl->rx_data[r].ring[RTETH_RX_RING_SIZE - 1] |= WRAP; + ctrl->rx_data[r].slot = 0; + } + + for (int r = 0; r < RTETH_TX_RINGS; r++) { + for (int i = 0; i < RTETH_TX_RING_SIZE; i++) { + ctrl->tx_data[r].packet[i].skb = NULL; + ctrl->tx_data[r].ring[i] = ctrl->tx_dma + + sizeof(struct rteth_tx) * r + + offsetof(struct rteth_tx, packet) + + sizeof(struct rteth_packet) * i; + } + + ctrl->tx_data[r].ring[RTETH_TX_RING_SIZE - 1] |= WRAP; + ctrl->tx_data[r].slot = 0; + } +} + +static void rteth_839x_setup_notify_ring_buffer(struct rteth_ctrl *ctrl) +{ + struct notify_b *b = ctrl->membase; + + for (int i = 0; i < NOTIFY_BLOCKS; i++) + b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0); + + sw_w32((u32)b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL); + sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL); + + /* Setup notification events */ + sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); /* RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN */ + sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); /* SUSPEND_NOTIFICATION_EN */ + + /* Enable Notification */ + sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL); + ctrl->lastEvent = 0; + + /* Make sure the ring structure is visible to the ASIC */ + mb(); + flush_cache_all(); +} + +static void rteth_838x_hw_init(struct rteth_ctrl *ctrl) +{ + /* Trap IGMP/MLD traffic to CPU-Port */ + sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL); + /* Flush learned FDB entries on link down of a port */ + sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0); +} + +static void rteth_839x_hw_init(struct rteth_ctrl *ctrl) +{ + /* Trap MLD and IGMP messages to CPU_PORT */ + sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL); + /* Flush learned FDB entries on link down of a port */ + sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0); +} + +static void rteth_930x_hw_init(struct rteth_ctrl *ctrl) +{ + /* Flush learned FDB entries on link down of a port */ + sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL); + /* Trap MLD and IGMP messages to CPU_PORT */ + sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL); +} + +static void rteth_931x_hw_init(struct rteth_ctrl *ctrl) +{ + /* Trap MLD and IGMP messages to CPU_PORT */ + sw_w32((0x2 << 3) | 0x2, RTL931X_VLAN_APP_PKT_CTRL); + /* Set PCIE_PWR_DOWN */ + sw_w32_mask(0, BIT(1), RTL931X_PS_SOC_CTRL); +} + +static int rteth_open(struct net_device *ndev) +{ + unsigned long flags; + struct rteth_ctrl *ctrl = netdev_priv(ndev); + + pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n", + __func__, RTETH_RX_RINGS, RTETH_RX_RING_SIZE, RTETH_TX_RINGS, RTETH_TX_RING_SIZE); + + spin_lock_irqsave(&ctrl->lock, flags); + ctrl->r->hw_reset(ctrl); + rteth_setup_cpu_rx_rings(ctrl); + rteth_setup_ring_buffer(ctrl); + if (ctrl->r->setup_notify_ring_buffer) + ctrl->r->setup_notify_ring_buffer(ctrl); + + rteth_hw_ring_setup(ctrl); + phylink_start(ctrl->phylink); + + for (int i = 0; i < RTETH_RX_RINGS; i++) + napi_enable(&ctrl->rx_qs[i].napi); + + ctrl->r->hw_init(ctrl); + ctrl->r->hw_en_rxtx(ctrl); + netif_tx_start_all_queues(ndev); + spin_unlock_irqrestore(&ctrl->lock, flags); + + return 0; +} + +static void rteth_838x_hw_stop(struct rteth_ctrl *ctrl) +{ + /* Block all ports */ + sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0)); + sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1)); + sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0); + + /* Disable FAST_AGE_OUT otherwise flush will hang */ + sw_w32_mask(BIT(23), 0, RTL838X_L2_CTRL_1); + + /* Flush L2 address cache */ + for (int i = 0; i <= ctrl->r->cpu_port; i++) { + sw_w32(BIT(26) | BIT(23) | i << 5, ctrl->r->l2_tbl_flush_ctrl); + do { } while (sw_r32(ctrl->r->l2_tbl_flush_ctrl) & BIT(26)); + } + + /* CPU-Port: Link down */ + sw_w32(0x6192C, ctrl->r->mac_force_mode_ctrl); +} + +static void rteth_839x_hw_stop(struct rteth_ctrl *ctrl) +{ + /* Flush L2 address cache */ + for (int i = 0; i <= ctrl->r->cpu_port; i++) { + sw_w32(BIT(28) | BIT(25) | i << 5, ctrl->r->l2_tbl_flush_ctrl); + do { } while (sw_r32(ctrl->r->l2_tbl_flush_ctrl) & BIT(28)); + } + + sw_w32(0x75, ctrl->r->mac_force_mode_ctrl); +} + +static void rteth_930x_hw_stop(struct rteth_ctrl *ctrl) +{ + /* TODO: L2 flush needed */ + + /* CPU-Port: Link down */ + sw_w32_mask(0x3, 0, ctrl->r->mac_force_mode_ctrl); +} + +static void rteth_931x_hw_stop(struct rteth_ctrl *ctrl) +{ + /* TODO: L2 flush needed */ + + /* CPU-Port: Link down */ + sw_w32_mask(BIT(0) | BIT(9), 0, ctrl->r->mac_force_mode_ctrl); +} + +static void rteth_hw_stop(struct rteth_ctrl *ctrl) +{ + /* Disable RX/TX from/to CPU-port */ + sw_w32_mask(0x3, 0, ctrl->r->mac_l2_port_ctrl); + + /* Disable traffic */ + sw_w32_mask(ctrl->r->tx_rx_enable, 0, ctrl->r->dma_if_ctrl); + mdelay(200); /* Test, whether this is needed */ + + /* family specific stop */ + ctrl->r->hw_stop(ctrl); + mdelay(100); + + rteth_disable_all_irqs(ctrl); + + /* Disable TX/RX DMA */ + sw_w32(0x00000000, ctrl->r->dma_if_ctrl); + mdelay(200); +} + +static int rteth_stop(struct net_device *ndev) +{ + struct rteth_ctrl *ctrl = netdev_priv(ndev); + + pr_info("in %s\n", __func__); + + phylink_stop(ctrl->phylink); + rteth_hw_stop(ctrl); + + for (int i = 0; i < RTETH_RX_RINGS; i++) + napi_disable(&ctrl->rx_qs[i].napi); + + netif_tx_stop_all_queues(ndev); + + return 0; +} + +static void rteth_838x_set_rx_mode(struct net_device *ndev) +{ + /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + * CTRL_0_FULL = GENMASK(21, 0) = 0x3FFFFF + */ + if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { + sw_w32(0x0, RTL838X_RMA_CTRL_0); + sw_w32(0x0, RTL838X_RMA_CTRL_1); + } + if (ndev->flags & IFF_ALLMULTI) + sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0); + if (ndev->flags & IFF_PROMISC) { + sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0); + sw_w32(0x7fff, RTL838X_RMA_CTRL_1); + } +} + +static void rteth_839x_set_rx_mode(struct net_device *ndev) +{ + /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC + * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00 + * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) + */ + if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { + sw_w32(0x0, RTL839X_RMA_CTRL_0); + sw_w32(0x0, RTL839X_RMA_CTRL_1); + sw_w32(0x0, RTL839X_RMA_CTRL_2); + sw_w32(0x0, RTL839X_RMA_CTRL_3); + } + if (ndev->flags & IFF_ALLMULTI) { + sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0); + sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1); + sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2); + } + if (ndev->flags & IFF_PROMISC) { + sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0); + sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1); + sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2); + sw_w32(0x3ff, RTL839X_RMA_CTRL_3); + } +} + +static void rteth_930x_set_rx_mode(struct net_device *ndev) +{ + /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC + * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00 + * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) + */ + if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC)) { + sw_w32(GENMASK(31, 2), RTL930X_RMA_CTRL_0); + sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_1); + sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_2); + } else { + sw_w32(0x0, RTL930X_RMA_CTRL_0); + sw_w32(0x0, RTL930X_RMA_CTRL_1); + sw_w32(0x0, RTL930X_RMA_CTRL_2); + } +} + +static void rtl931x_eth_set_multicast_list(struct net_device *ndev) +{ + /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) + * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC + * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00. + * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) + */ + if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC)) { + sw_w32(GENMASK(31, 2), RTL931X_RMA_CTRL_0); + sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_1); + sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_2); + } else { + sw_w32(0x0, RTL931X_RMA_CTRL_0); + sw_w32(0x0, RTL931X_RMA_CTRL_1); + sw_w32(0x0, RTL931X_RMA_CTRL_2); + } +} + +static void rteth_tx_timeout(struct net_device *ndev, unsigned int txqueue) +{ + unsigned long flags; + struct rteth_ctrl *ctrl = netdev_priv(ndev); + + pr_warn("%s\n", __func__); + spin_lock_irqsave(&ctrl->lock, flags); + rteth_hw_stop(ctrl); + rteth_hw_ring_setup(ctrl); + ctrl->r->hw_en_rxtx(ctrl); + netif_trans_update(ndev); + netif_start_queue(ndev); + spin_unlock_irqrestore(&ctrl->lock, flags); +} + +static int rteth_start_xmit(struct sk_buff *skb, struct net_device *netdev) +{ + struct rteth_ctrl *ctrl = netdev_priv(netdev); + int val, slot, len = skb->len, dest_port = -1; + int ring = skb_get_queue_mapping(skb); + struct device *dev = &ctrl->pdev->dev; + struct rteth_packet *packet; + dma_addr_t packet_dma; + + if (netdev_uses_dsa(netdev) && + skb->data[len - 4] == 0x80 && + skb->data[len - 3] < ctrl->r->cpu_port && + skb->data[len - 2] == 0x10 && + skb->data[len - 1] == 0x00) { + dest_port = skb->data[len - 3]; + /* space will be reused for 4 byte layer 2 FCS */ + } else { + /* No DSA tag, add space for 4 byte layer 2 FCS */ + len += ETH_FCS_LEN; + } + + len = max(ETH_ZLEN + ETH_FCS_LEN, len); + if (unlikely(skb_put_padto(skb, len))) { + netdev->stats.tx_errors++; + dev_warn(dev, "skb pad failed\n"); + + return NETDEV_TX_OK; + } + + slot = ctrl->tx_data[ring].slot; + packet = &ctrl->tx_data[ring].packet[slot]; + packet_dma = ctrl->tx_data[ring].ring[slot]; + + if (unlikely(packet_dma & RTETH_OWN_CPU)) { + netif_stop_subqueue(netdev, ring); + if (net_ratelimit()) + dev_warn(dev, "tx ring %d busy, waiting for slot %d\n", ring, slot); + + return NETDEV_TX_BUSY; + } + + packet->dma = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE); + if (unlikely(dma_mapping_error(dev, packet->dma))) { + dev_kfree_skb_any(skb); + netdev->stats.tx_errors++; + + return NETDEV_TX_OK; + } + + if (likely(packet->skb)) { + /* cleanup old data of this slot */ + dma_unmap_single(dev, packet->dma, packet->skb->len, DMA_TO_DEVICE); + dev_kfree_skb_any(packet->skb); + } + + if (dest_port >= 0) + ctrl->r->create_tx_header(packet, dest_port, 0); // TODO ok to set prio to 0? + + /* Transfer data and hand packet over to switch */ + packet->len = len; + packet->skb = skb; + dma_wmb(); + ctrl->tx_data[ring].ring[slot] = packet_dma | RTETH_OWN_CPU; + ctrl->tx_data[ring].slot = (slot + 1) % RTETH_TX_RING_SIZE; + wmb(); + + spin_lock(&ctrl->tx_lock); + + /* + * Issue send for 1 or 2 triggers. On some SoCs (especially RTL838x) there is a known + * bug, where the hardware sometimes reads empty values from the register. Work around + * that with a poll that checks if TX/RX is enabled in the register. + */ + if (read_poll_timeout(sw_r32, val, val & ctrl->r->tx_rx_enable, + 0, 5000, false, ctrl->r->dma_if_ctrl)) + dev_warn_once(dev, "DMA interface ctrl register read failed\n"); + + sw_w32(val | RTETH_TX_TRIGGER(ctrl, ring), ctrl->r->dma_if_ctrl); + + netdev->stats.tx_packets++; + netdev->stats.tx_bytes += len; + + spin_unlock(&ctrl->tx_lock); + + return NETDEV_TX_OK; +} + +static int rteth_hw_receive(struct net_device *dev, int ring, int budget) +{ + int slot, len, work_done = 0, rx_packets = 0, rx_bytes = 0; + struct rteth_ctrl *ctrl = netdev_priv(dev); + bool dsa = netdev_uses_dsa(dev); + struct rteth_packet *packet; + dma_addr_t packet_dma; + struct sk_buff *skb; + struct dsa_tag tag; + + while (work_done < budget) { + slot = ctrl->rx_data[ring].slot; + packet_dma = ctrl->rx_data[ring].ring[slot]; + rmb(); + + if (packet_dma & RTETH_OWN_CPU) + break; + + packet = &ctrl->rx_data[ring].packet[slot]; + len = packet->len; + + if (!len) { + netdev_err(dev, "empty packet received\n"); + break; + } else if (!dsa) { + len -= 4; + } + + skb = netdev_alloc_skb_ip_align(dev, len); + if (unlikely(!skb)) { + netdev_warn(dev, "low memory, packet dropped\n"); + dev->stats.rx_dropped++; + } else { + dma_sync_single_for_cpu(&ctrl->pdev->dev, packet->dma, len, DMA_FROM_DEVICE); + dma_rmb(); + skb_put_data(skb, packet->buf, len); + + if (dsa) { + ctrl->r->decode_tag(packet, &tag); + skb->data[len - 4] = 0x80; + skb->data[len - 3] = tag.port; + skb->data[len - 2] = 0x10; + skb->data[len - 1] = 0x00; + if (tag.l2_offloaded) + skb->data[len - 3] |= 0x40; + } + + skb->protocol = eth_type_trans(skb, dev); + if (dev->features & NETIF_F_RXCSUM) { + if (tag.crc_error) + skb_checksum_none_assert(skb); + else + skb->ip_summed = CHECKSUM_UNNECESSARY; + } + + rx_packets++; + rx_bytes += len; + napi_gro_receive(&ctrl->rx_qs[ring].napi, skb); + } + + ctrl->rx_data[ring].ring[slot] = packet_dma | RTETH_OWN_CPU; + ctrl->rx_data[ring].slot = (slot + 1) % RTETH_RX_RING_SIZE; + work_done++; + } + + spin_lock(&ctrl->rx_lock); + ctrl->r->update_counter(ctrl, ring, work_done); + dev->stats.rx_packets += rx_packets; + dev->stats.rx_bytes += rx_bytes; + spin_unlock(&ctrl->rx_lock); + + return work_done; +} + +static int rteth_poll_rx(struct napi_struct *napi, int budget) +{ + struct rtl838x_rx_q *rx_q = container_of(napi, struct rtl838x_rx_q, napi); + struct rteth_ctrl *ctrl = rx_q->ctrl; + int work_done, ring = rx_q->id; + + work_done = rteth_hw_receive(ctrl->netdev, ring, budget); + if (work_done < budget && napi_complete_done(napi, work_done)) + rteth_reenable_irq(ctrl, ring); + + return work_done; +} + +static void rteth_mac_config(struct phylink_config *config, + unsigned int mode, + const struct phylink_link_state *state) +{ + /* This is only being called for the master device, + * i.e. the CPU-Port. We don't need to do anything. + */ + + pr_info("In %s, mode %x\n", __func__, mode); +} + +static void rteth_mac_link_down(struct phylink_config *config, + unsigned int mode, + phy_interface_t interface) +{ + struct net_device *dev = container_of(config->dev, struct net_device, dev); + struct rteth_ctrl *ctrl = netdev_priv(dev); + + pr_debug("In %s\n", __func__); + /* Stop TX/RX to port */ + sw_w32_mask(0x03, 0, ctrl->r->mac_l2_port_ctrl); +} + +static void rteth_mac_link_up(struct phylink_config *config, + struct phy_device *phy, unsigned int mode, + phy_interface_t interface, int speed, int duplex, + bool tx_pause, bool rx_pause) +{ + struct net_device *dev = container_of(config->dev, struct net_device, dev); + struct rteth_ctrl *ctrl = netdev_priv(dev); + + pr_debug("In %s\n", __func__); + /* Restart TX/RX to port */ + sw_w32_mask(0, 0x03, ctrl->r->mac_l2_port_ctrl); +} + +static void rteth_set_mac_hw(struct net_device *dev, u8 *mac) +{ + u32 mac_lo = (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5]; + u32 mac_hi = (mac[0] << 8) | mac[1]; + struct rteth_ctrl *ctrl; + unsigned long flags; + + ctrl = netdev_priv(dev); + spin_lock_irqsave(&ctrl->lock, flags); + + for (int i = 0; i < RTETH_MAX_MAC_REGS; i++) + if (ctrl->r->mac_reg[i]) { + sw_w32(mac_hi, ctrl->r->mac_reg[i]); + sw_w32(mac_lo, ctrl->r->mac_reg[i] + 4); + } + + spin_unlock_irqrestore(&ctrl->lock, flags); +} + +static int rteth_set_mac_address(struct net_device *dev, void *p) +{ + const struct sockaddr *addr = p; + u8 *mac = (u8 *)(addr->sa_data); + + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + + dev_addr_set(dev, addr->sa_data); + rteth_set_mac_hw(dev, mac); + + pr_info("Using MAC %pM\n", dev->dev_addr); + + return 0; +} + +static int rteth_838x_init_mac(struct rteth_ctrl *ctrl) +{ + pr_info("%s\n", __func__); + /* fix timer for EEE */ + sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL); + sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL); + + /* Init VLAN. TODO: Understand what is being done, here */ + for (int i = 0; i <= 28; i++) + sw_w32(0, 0xd57c + i * 0x80); + + return 0; +} + +static int rteth_839x_init_mac(struct rteth_ctrl *ctrl) +{ + /* We will need to set-up EEE and the egress-rate limitation */ + return 0; +} + +static int rteth_930x_init_mac(struct rteth_ctrl *ctrl) +{ + return 0; +} + +static int rteth_931x_init_mac(struct rteth_ctrl *ctrl) +{ + pr_info("In %s\n", __func__); + + /* Initialize Encapsulation memory and wait until finished */ + sw_w32(0x1, RTL931X_MEM_ENCAP_INIT); + do { } while (sw_r32(RTL931X_MEM_ENCAP_INIT) & 1); + pr_info("%s: init ENCAP done\n", __func__); + + /* Initialize Managemen Information Base memory and wait until finished */ + sw_w32(0x1, RTL931X_MEM_MIB_INIT); + do { } while (sw_r32(RTL931X_MEM_MIB_INIT) & 1); + pr_info("%s: init MIB done\n", __func__); + + /* Initialize ACL (PIE) memory and wait until finished */ + sw_w32(0x1, RTL931X_MEM_ACL_INIT); + do { } while (sw_r32(RTL931X_MEM_ACL_INIT) & 1); + pr_info("%s: init ACL done\n", __func__); + + /* Initialize ALE memory and wait until finished */ + sw_w32(0xFFFFFFFF, RTL931X_MEM_ALE_INIT_0); + do { } while (sw_r32(RTL931X_MEM_ALE_INIT_0)); + sw_w32(0x7F, RTL931X_MEM_ALE_INIT_1); + sw_w32(0x7ff, RTL931X_MEM_ALE_INIT_2); + do { } while (sw_r32(RTL931X_MEM_ALE_INIT_2) & 0x7ff); + pr_info("%s: init ALE done\n", __func__); + + /* Enable ESD auto recovery */ + sw_w32(0x1, RTL931X_MDX_CTRL_RSVD); + + return 0; +} + +static int rteth_get_link_ksettings(struct net_device *ndev, + struct ethtool_link_ksettings *cmd) +{ + struct rteth_ctrl *ctrl = netdev_priv(ndev); + + pr_debug("%s called\n", __func__); + + return phylink_ethtool_ksettings_get(ctrl->phylink, cmd); +} + +static int rteth_set_link_ksettings(struct net_device *ndev, + const struct ethtool_link_ksettings *cmd) +{ + struct rteth_ctrl *ctrl = netdev_priv(ndev); + + pr_debug("%s called\n", __func__); + + return phylink_ethtool_ksettings_set(ctrl->phylink, cmd); +} + +static netdev_features_t rteth_fix_features(struct net_device *dev, + netdev_features_t features) +{ + return features; +} + +static int rteth_83xx_set_features(struct net_device *dev, netdev_features_t features) +{ + struct rteth_ctrl *ctrl = netdev_priv(dev); + + if ((features ^ dev->features) & NETIF_F_RXCSUM) { + if (!(features & NETIF_F_RXCSUM)) + sw_w32_mask(BIT(3), 0, ctrl->r->mac_l2_port_ctrl); + else + sw_w32_mask(0, BIT(3), ctrl->r->mac_l2_port_ctrl); + } + + return 0; +} + +static int rteth_93xx_set_features(struct net_device *dev, netdev_features_t features) +{ + struct rteth_ctrl *ctrl = netdev_priv(dev); + + if ((features ^ dev->features) & NETIF_F_RXCSUM) { + if (!(features & NETIF_F_RXCSUM)) + sw_w32_mask(BIT(4), 0, ctrl->r->mac_l2_port_ctrl); + else + sw_w32_mask(0, BIT(4), ctrl->r->mac_l2_port_ctrl); + } + + return 0; +} + +static int rteth_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data) +{ + struct dsa_switch *ds; + struct dsa_port *dp; + + if (!netdev_uses_dsa(dev)) + return -EOPNOTSUPP; + + dp = dev->dsa_ptr; + ds = dp->ds; + + if (!ds->ops->port_setup_tc) + return -EOPNOTSUPP; + + return ds->ops->port_setup_tc(ds, dp->index, type, type_data); +} + +static const struct net_device_ops rteth_838x_netdev_ops = { + .ndo_open = rteth_open, + .ndo_stop = rteth_stop, + .ndo_start_xmit = rteth_start_xmit, + .ndo_set_mac_address = rteth_set_mac_address, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_rx_mode = rteth_838x_set_rx_mode, + .ndo_tx_timeout = rteth_tx_timeout, + .ndo_set_features = rteth_83xx_set_features, + .ndo_fix_features = rteth_fix_features, + .ndo_setup_tc = rteth_setup_tc, +}; + +static const struct rteth_config rteth_838x_cfg = { + .cpu_port = RTETH_838X_CPU_PORT, + .rx_rings = 8, + .tx_rx_enable = 0xc, + .tx_trigger_mask = BIT(1), + .mac_l2_port_ctrl = RTETH_838X_MAC_L2_PORT_CTRL, + .qm_pkt2cpu_intpri_map = RTETH_838X_QM_PKT2CPU_INTPRI_MAP, + .qm_rsn2cpuqid_ctrl = RTETH_838X_QM_PKT2CPU_INTPRI_0, + .qm_rsn2cpuqid_cnt = RTETH_838X_QM_PKT2CPU_INTPRI_CNT, + .dma_if_intr_sts = RTETH_838X_DMA_IF_INTR_STS, + .dma_if_intr_msk = RTETH_838X_DMA_IF_INTR_MSK, + .dma_if_ctrl = RTL838X_DMA_IF_CTRL, + .mac_force_mode_ctrl = RTETH_838X_MAC_FORCE_MODE_CTRL, + .dma_rx_base = RTL838X_DMA_RX_BASE, + .dma_tx_base = RTL838X_DMA_TX_BASE, + .dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size, + .dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr, + .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0, + .mac_reg = { RTETH_838X_MAC_ADDR_CTRL, + RTETH_838X_MAC_ADDR_CTRL_ALE, + RTETH_838X_MAC_ADDR_CTRL_MAC }, + .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL, + .update_counter = rteth_83xx_update_counter, + .create_tx_header = rteth_838x_create_tx_header, + .decode_tag = rteth_838x_decode_tag, + .hw_en_rxtx = rteth_838x_hw_en_rxtx, + .hw_init = &rteth_838x_hw_init, + .hw_stop = &rteth_838x_hw_stop, + .hw_reset = &rteth_838x_hw_reset, + .init_mac = &rteth_838x_init_mac, + .netdev_ops = &rteth_838x_netdev_ops, +}; + +static const struct net_device_ops rteth_839x_netdev_ops = { + .ndo_open = rteth_open, + .ndo_stop = rteth_stop, + .ndo_start_xmit = rteth_start_xmit, + .ndo_set_mac_address = rteth_set_mac_address, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_rx_mode = rteth_839x_set_rx_mode, + .ndo_tx_timeout = rteth_tx_timeout, + .ndo_set_features = rteth_83xx_set_features, + .ndo_fix_features = rteth_fix_features, + .ndo_setup_tc = rteth_setup_tc, +}; + +static const struct rteth_config rteth_839x_cfg = { + .cpu_port = RTETH_839X_CPU_PORT, + .rx_rings = 8, + .tx_rx_enable = 0xc, + .tx_trigger_mask = BIT(1), + .mac_l2_port_ctrl = RTETH_839X_MAC_L2_PORT_CTRL, + .qm_pkt2cpu_intpri_map = RTETH_839X_QM_PKT2CPU_INTPRI_MAP, + .qm_rsn2cpuqid_ctrl = RTETH_839X_QM_PKT2CPU_INTPRI_0, + .qm_rsn2cpuqid_cnt = RTETH_839X_QM_PKT2CPU_INTPRI_CNT, + .dma_if_intr_sts = RTETH_839X_DMA_IF_INTR_STS, + .dma_if_intr_msk = RTETH_839X_DMA_IF_INTR_MSK, + .dma_if_ctrl = RTL839X_DMA_IF_CTRL, + .mac_force_mode_ctrl = RTETH_839X_MAC_FORCE_MODE_CTRL, + .dma_rx_base = RTL839X_DMA_RX_BASE, + .dma_tx_base = RTL839X_DMA_TX_BASE, + .dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size, + .dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr, + .rst_glb_ctrl = RTL839X_RST_GLB_CTRL, + .mac_reg = { RTETH_839X_MAC_ADDR_CTRL }, + .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL, + .update_counter = rteth_83xx_update_counter, + .create_tx_header = rteth_839x_create_tx_header, + .decode_tag = rteth_839x_decode_tag, + .hw_en_rxtx = rteth_839x_hw_en_rxtx, + .hw_init = &rteth_839x_hw_init, + .hw_stop = &rteth_839x_hw_stop, + .hw_reset = &rteth_839x_hw_reset, + .init_mac = &rteth_839x_init_mac, + .setup_notify_ring_buffer = &rteth_839x_setup_notify_ring_buffer, + .netdev_ops = &rteth_839x_netdev_ops, +}; + +static const struct net_device_ops rteth_930x_netdev_ops = { + .ndo_open = rteth_open, + .ndo_stop = rteth_stop, + .ndo_start_xmit = rteth_start_xmit, + .ndo_set_mac_address = rteth_set_mac_address, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_rx_mode = rteth_930x_set_rx_mode, + .ndo_tx_timeout = rteth_tx_timeout, + .ndo_set_features = rteth_93xx_set_features, + .ndo_fix_features = rteth_fix_features, + .ndo_setup_tc = rteth_setup_tc, +}; + +static const struct rteth_config rteth_930x_cfg = { + .cpu_port = RTETH_930X_CPU_PORT, + .rx_rings = 32, + .tx_rx_enable = 0x30, + .tx_trigger_mask = GENMASK(3, 2), + .mac_l2_port_ctrl = RTETH_930X_MAC_L2_PORT_CTRL, + .qm_rsn2cpuqid_ctrl = RTETH_930X_QM_RSN2CPUQID_CTRL_0, + .qm_rsn2cpuqid_cnt = RTETH_930X_QM_RSN2CPUQID_CTRL_CNT, + .dma_if_intr_sts = RTETH_930X_DMA_IF_INTR_STS, + .dma_if_intr_msk = RTETH_930X_DMA_IF_INTR_MSK, + .l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS, + .l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK, + .dma_if_ctrl = RTL930X_DMA_IF_CTRL, + .mac_force_mode_ctrl = RTETH_930X_MAC_FORCE_MODE_CTRL, + .dma_rx_base = RTL930X_DMA_RX_BASE, + .dma_tx_base = RTL930X_DMA_TX_BASE, + .dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size, + .dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr, + .rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0, + .mac_reg = { RTETH_930X_MAC_L2_ADDR_CTRL }, + .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL, + .update_counter = rteth_93xx_update_counter, + .create_tx_header = rteth_93xx_create_tx_header, + .decode_tag = rteth_930x_decode_tag, + .hw_en_rxtx = rteth_930x_hw_en_rxtx, + .hw_init = &rteth_930x_hw_init, + .hw_stop = &rteth_930x_hw_stop, + .hw_reset = &rteth_93xx_hw_reset, + .init_mac = &rteth_930x_init_mac, + .netdev_ops = &rteth_930x_netdev_ops, +}; + +static const struct net_device_ops rteth_931x_netdev_ops = { + .ndo_open = rteth_open, + .ndo_stop = rteth_stop, + .ndo_start_xmit = rteth_start_xmit, + .ndo_set_mac_address = rteth_set_mac_address, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_rx_mode = rtl931x_eth_set_multicast_list, + .ndo_tx_timeout = rteth_tx_timeout, + .ndo_set_features = rteth_93xx_set_features, + .ndo_fix_features = rteth_fix_features, + .ndo_setup_tc = rteth_setup_tc, +}; + +static const struct rteth_config rteth_931x_cfg = { + .cpu_port = RTETH_931X_CPU_PORT, + .rx_rings = 32, + .tx_rx_enable = 0x30, + .tx_trigger_mask = GENMASK(3, 2), + .mac_l2_port_ctrl = RTETH_931X_MAC_L2_PORT_CTRL, + .qm_rsn2cpuqid_ctrl = RTETH_931X_QM_RSN2CPUQID_CTRL_0, + .qm_rsn2cpuqid_cnt = RTETH_931X_QM_RSN2CPUQID_CTRL_CNT, + .dma_if_intr_sts = RTETH_931X_DMA_IF_INTR_STS, + .dma_if_intr_msk = RTETH_931X_DMA_IF_INTR_MSK, + .l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS, + .l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK, + .dma_if_ctrl = RTL931X_DMA_IF_CTRL, + .mac_force_mode_ctrl = RTETH_931X_MAC_FORCE_MODE_CTRL, + .dma_rx_base = RTL931X_DMA_RX_BASE, + .dma_tx_base = RTL931X_DMA_TX_BASE, + .dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size, + .dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr, + .rst_glb_ctrl = RTL931X_RST_GLB_CTRL, + .mac_reg = { RTETH_930X_MAC_L2_ADDR_CTRL }, + .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL, + .update_counter = rteth_93xx_update_counter, + .create_tx_header = rteth_93xx_create_tx_header, + .decode_tag = rteth_931x_decode_tag, + .hw_en_rxtx = rteth_931x_hw_en_rxtx, + .hw_init = &rteth_931x_hw_init, + .hw_stop = &rteth_931x_hw_stop, + .hw_reset = &rteth_93xx_hw_reset, + .init_mac = &rteth_931x_init_mac, + .netdev_ops = &rteth_931x_netdev_ops, +}; + +static const struct phylink_mac_ops rteth_mac_ops = { + .mac_config = rteth_mac_config, + .mac_link_down = rteth_mac_link_down, + .mac_link_up = rteth_mac_link_up, +}; + +static const struct ethtool_ops rteth_ethtool_ops = { + .get_link_ksettings = rteth_get_link_ksettings, + .set_link_ksettings = rteth_set_link_ksettings, +}; + +static int rteth_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct device_node *dn = pdev->dev.of_node; + struct rteth_ctrl *ctrl; + const struct rteth_config *cfg; + phy_interface_t phy_mode; + struct phylink *phylink; + u8 mac_addr[ETH_ALEN] = {0}; + int err = 0; + + pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n", + (u32)pdev, (u32)(&pdev->dev)); + + cfg = device_get_match_data(&pdev->dev); + + dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct rteth_ctrl), RTETH_TX_RINGS, RTETH_RX_RINGS); + if (!dev) + return -ENOMEM; + SET_NETDEV_DEV(dev, &pdev->dev); + ctrl = netdev_priv(dev); + ctrl->r = cfg; + + /* Allocate buffer memory */ + ctrl->membase = dmam_alloc_coherent(&pdev->dev, sizeof(struct notify_b), + (void *)&dev->mem_start, GFP_KERNEL); + if (!ctrl->membase) { + dev_err(&pdev->dev, "cannot allocate DMA buffer\n"); + return -ENOMEM; + } + + ctrl->rx_buf = dma_alloc_noncoherent(&pdev->dev, + RTETH_RX_RINGS * RTETH_RX_RING_SIZE * RING_BUFFER, + &ctrl->rx_buf_dma, DMA_FROM_DEVICE, GFP_KERNEL); + ctrl->rx_data = dmam_alloc_coherent(&pdev->dev, sizeof(struct rteth_rx) * RTETH_RX_RINGS, + &ctrl->rx_data_dma, GFP_KERNEL); + ctrl->tx_data = dmam_alloc_coherent(&pdev->dev, sizeof(struct rteth_tx) * RTETH_TX_RINGS, + &ctrl->tx_dma, GFP_KERNEL); + + spin_lock_init(&ctrl->lock); + spin_lock_init(&ctrl->rx_lock); + spin_lock_init(&ctrl->tx_lock); + + dev->ethtool_ops = &rteth_ethtool_ops; + dev->min_mtu = ETH_ZLEN; + dev->max_mtu = DEFAULT_MTU; + dev->features = NETIF_F_RXCSUM; + dev->hw_features = NETIF_F_RXCSUM; + dev->netdev_ops = ctrl->r->netdev_ops; + + /* Obtain device IRQ number */ + dev->irq = platform_get_irq(pdev, 0); + if (dev->irq < 0) + return -ENODEV; + + rteth_disable_all_irqs(ctrl); + err = devm_request_irq(&pdev->dev, dev->irq, rteth_net_irq, IRQF_SHARED, dev->name, dev); + if (err) { + dev_err(&pdev->dev, "%s: could not acquire interrupt: %d\n", + __func__, err); + return err; + } + + ctrl->r->init_mac(ctrl); + + /* Try to get mac address in the following order: + * 1) from device tree data + * 2) from internal registers set by bootloader + */ + err = of_get_mac_address(pdev->dev.of_node, mac_addr); + if (err == -EPROBE_DEFER) + return err; + + if (is_valid_ether_addr(mac_addr)) { + rteth_set_mac_hw(dev, mac_addr); + } else { + mac_addr[0] = (sw_r32(ctrl->r->mac_reg[0]) >> 8) & 0xff; + mac_addr[1] = sw_r32(ctrl->r->mac_reg[0]) & 0xff; + mac_addr[2] = (sw_r32(ctrl->r->mac_reg[0] + 4) >> 24) & 0xff; + mac_addr[3] = (sw_r32(ctrl->r->mac_reg[0] + 4) >> 16) & 0xff; + mac_addr[4] = (sw_r32(ctrl->r->mac_reg[0] + 4) >> 8) & 0xff; + mac_addr[5] = sw_r32(ctrl->r->mac_reg[0] + 4) & 0xff; + } + dev_addr_set(dev, mac_addr); + /* if the address is invalid, use a random value */ + if (!is_valid_ether_addr(dev->dev_addr)) { + struct sockaddr sa = { AF_UNSPEC }; + + netdev_warn(dev, "Invalid MAC address, using random\n"); + eth_hw_addr_random(dev); + memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN); + if (rteth_set_mac_address(dev, &sa)) + netdev_warn(dev, "Failed to set MAC address.\n"); + } + pr_info("Using MAC %pM\n", dev->dev_addr); + strscpy(dev->name, "eth%d", sizeof(dev->name)); + + ctrl->pdev = pdev; + ctrl->netdev = dev; + + for (int i = 0; i < RTETH_RX_RINGS; i++) { + ctrl->rx_qs[i].id = i; + ctrl->rx_qs[i].ctrl = ctrl; + netif_napi_add(dev, &ctrl->rx_qs[i].napi, rteth_poll_rx); + } + + platform_set_drvdata(pdev, dev); + + err = devm_register_netdev(&pdev->dev, dev); + if (err) + return err; + + phy_mode = PHY_INTERFACE_MODE_NA; + err = of_get_phy_mode(dn, &phy_mode); + if (err < 0) { + dev_err(&pdev->dev, "incorrect phy-mode\n"); + return -EINVAL; + } + + ctrl->phylink_config.dev = &dev->dev; + ctrl->phylink_config.type = PHYLINK_NETDEV; + ctrl->phylink_config.mac_capabilities = + MAC_10 | MAC_100 | MAC_1000FD | MAC_SYM_PAUSE | MAC_ASYM_PAUSE; + + __set_bit(PHY_INTERFACE_MODE_INTERNAL, ctrl->phylink_config.supported_interfaces); + + phylink = phylink_create(&ctrl->phylink_config, pdev->dev.fwnode, + phy_mode, &rteth_mac_ops); + + if (IS_ERR(phylink)) + return PTR_ERR(phylink); + ctrl->phylink = phylink; + + return 0; +} + +static void rteth_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + struct rteth_ctrl *ctrl = netdev_priv(dev); + + pr_info("Removing platform driver for rtl838x-eth\n"); + rteth_hw_stop(ctrl); + + netif_tx_stop_all_queues(dev); + + for (int i = 0; i < RTETH_RX_RINGS; i++) + netif_napi_del(&ctrl->rx_qs[i].napi); +} + +static const struct of_device_id rteth_of_ids[] = { + { + .compatible = "realtek,rtl8380-eth", + .data = &rteth_838x_cfg, + }, + { + .compatible = "realtek,rtl8392-eth", + .data = &rteth_839x_cfg, + }, + { + .compatible = "realtek,rtl9301-eth", + .data = &rteth_930x_cfg, + }, + { + .compatible = "realtek,rtl9311-eth", + .data = &rteth_931x_cfg, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rteth_of_ids); + +static struct platform_driver rtl838x_eth_driver = { + .probe = rteth_probe, + .remove = rteth_remove, + .driver = { + .name = KBUILD_MODNAME, + .pm = NULL, + .of_match_table = rteth_of_ids, + }, +}; + +module_platform_driver(rtl838x_eth_driver); + +MODULE_AUTHOR("B. Koblitz"); +MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.h b/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.h new file mode 100644 index 0000000000..b44dd305ab --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.h @@ -0,0 +1,275 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _RTL838X_ETH_H +#define _RTL838X_ETH_H + +#define RTETH_MAX_MAC_REGS 3 + +/* Register definition */ + +#define RTETH_838X_CPU_PORT 28 +#define RTETH_838X_DMA_IF_INTR_MSK (0x9f50) +#define RTETH_838X_DMA_IF_INTR_STS (0x9f54) +#define RTETH_838X_MAC_ADDR_CTRL (0xa9ec) +#define RTETH_838X_MAC_ADDR_CTRL_ALE (0x6b04) +#define RTETH_838X_MAC_ADDR_CTRL_MAC (0xa320) +#define RTETH_838X_MAC_FORCE_MODE_CTRL (0xa104 + RTETH_838X_CPU_PORT * 4) +#define RTETH_838X_MAC_L2_PORT_CTRL (0xd560 + RTETH_838X_CPU_PORT * 128) +#define RTETH_838X_QM_PKT2CPU_INTPRI_MAP (0x5f10) +#define RTETH_838X_QM_PKT2CPU_INTPRI_0 (0x5f04) +#define RTETH_838X_QM_PKT2CPU_INTPRI_CNT 3 + +#define RTETH_839X_CPU_PORT 52 +#define RTETH_839X_DMA_IF_INTR_MSK (0x7864) +#define RTETH_839X_DMA_IF_INTR_STS (0x7868) +#define RTETH_839X_MAC_ADDR_CTRL (0x02b4) +#define RTETH_839X_MAC_FORCE_MODE_CTRL (0x02bc + RTETH_839X_CPU_PORT * 4) +#define RTETH_839X_MAC_L2_PORT_CTRL (0x8004 + RTETH_839X_CPU_PORT * 128) +#define RTETH_839X_QM_PKT2CPU_INTPRI_MAP (0x1154) +#define RTETH_839X_QM_PKT2CPU_INTPRI_0 (0x1148) +#define RTETH_839X_QM_PKT2CPU_INTPRI_CNT 3 + +#define RTETH_930X_CPU_PORT 28 +#define RTETH_930X_DMA_IF_INTR_MSK (0xe010) +#define RTETH_930X_DMA_IF_INTR_STS (0xe01c) +#define RTETH_930X_MAC_FORCE_MODE_CTRL (0xca1c + RTETH_930X_CPU_PORT * 4) +#define RTETH_930X_MAC_L2_ADDR_CTRL (0xc714) +#define RTETH_930X_MAC_L2_PORT_CTRL (0x3268 + RTETH_930X_CPU_PORT * 64) +#define RTETH_930X_QM_RSN2CPUQID_CTRL_0 (0xa344) +#define RTETH_930X_QM_RSN2CPUQID_CTRL_CNT 11 + +#define RTETH_931X_CPU_PORT 56 +#define RTETH_931X_DMA_IF_INTR_MSK (0x0910) +#define RTETH_931X_DMA_IF_INTR_STS (0x091c) +#define RTETH_931X_MAC_FORCE_MODE_CTRL (0x0dcc + RTETH_931X_CPU_PORT * 4) +#define RTETH_931X_MAC_L2_ADDR_CTRL (0x135c) +#define RTETH_931X_MAC_L2_PORT_CTRL (0x6000 + RTETH_931X_CPU_PORT * 128) +#define RTETH_931X_QM_RSN2CPUQID_CTRL_0 (0xa9f4) +#define RTETH_931X_QM_RSN2CPUQID_CTRL_CNT 14 + +/* + * Reset + */ +#define RTL838X_RST_GLB_CTRL_0 (0x003c) +#define RTL839X_RST_GLB_CTRL (0x0014) +#define RTL930X_RST_GLB_CTRL_0 (0x000c) +#define RTL931X_RST_GLB_CTRL (0x0400) + +/* Switch interrupts */ +#define RTL839X_IMR_PORT_LINK_STS_CHG (0x0068) +#define RTL839X_ISR_PORT_LINK_STS_CHG (0x00a0) + +/* + * CPU port MAC control. On RTL93XX the functionality of the MAC port control register is + * split into MAC_L2_PORT_CTRL and MAC_PORT_CTRL and the L2 register holds the important + * bits for the driver. To avoid confusion on splitted models use the L2 naming convention + * for all targets. + */ + +/* DMA interrupt control and status registers */ +#define RTL838X_DMA_IF_CTRL (0x9f58) + +#define RTL839X_DMA_IF_CTRL (0x786c) + +#define RTL930X_DMA_IF_CTRL (0xe028) +#define RTL930X_L2_NTFY_IF_INTR_MSK (0xe04C) +#define RTL930X_L2_NTFY_IF_INTR_STS (0xe050) + +/* TODO: RTL931X_DMA_IF_CTRL has different bits meanings */ +#define RTL931X_DMA_IF_CTRL (0x0928) +#define RTL931X_L2_NTFY_IF_INTR_MSK (0x09E4) +#define RTL931X_L2_NTFY_IF_INTR_STS (0x09E8) + +#define RTL839X_DMA_IF_INTR_NOTIFY_MASK GENMASK(22, 20) + +/* Ringbuffer setup */ +#define RTL838X_DMA_RX_BASE (0x9f00) +#define RTL839X_DMA_RX_BASE (0x780c) +#define RTL930X_DMA_RX_BASE (0xdf00) +#define RTL931X_DMA_RX_BASE (0x0800) + +#define RTL838X_DMA_TX_BASE (0x9f40) +#define RTL839X_DMA_TX_BASE (0x784c) +#define RTL930X_DMA_TX_BASE (0xe000) +#define RTL931X_DMA_TX_BASE (0x0900) + +#define RTL838X_DMA_IF_RX_RING_SIZE (0xB7E4) +#define RTL839X_DMA_IF_RX_RING_SIZE (0x6038) +#define RTL930X_DMA_IF_RX_RING_SIZE (0x7C60) +#define RTL931X_DMA_IF_RX_RING_SIZE (0x2080) + +#define RTL838X_DMA_IF_RX_RING_CNTR (0xB7E8) +#define RTL839X_DMA_IF_RX_RING_CNTR (0x603c) +#define RTL930X_DMA_IF_RX_RING_CNTR (0x7C8C) +#define RTL931X_DMA_IF_RX_RING_CNTR (0x20AC) + +#define RTL838X_DMA_IF_TX_CUR_DESC_ADDR_CTRL (0x9F48) +#define RTL930X_DMA_IF_TX_CUR_DESC_ADDR_CTRL (0xE008) + +/* L2 features */ +#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180) +#define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2)) +#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) +#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) + +#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04) +#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08) + +#define RTL930X_L2_UNKN_UC_FLD_PMSK (0x9064) +#define RTL931X_L2_UNKN_UC_FLD_PMSK (0xC8F4) + +#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370) +#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0) +#define RTL930X_L2_TBL_FLUSH_CTRL (0x9404) +#define RTL931X_L2_TBL_FLUSH_CTRL (0xCD9C) + +/* MAC link state bits */ +#define FORCE_EN BIT(0) +#define FORCE_LINK_EN BIT(1) +#define NWAY_EN BIT(2) +#define DUPLX_MODE BIT(3) +#define TX_PAUSE_EN BIT(6) +#define RX_PAUSE_EN BIT(7) + +/* L2 Notification DMA interface */ +#define RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL (0x785C) +#define RTL839X_L2_NOTIFICATION_CTRL (0x7808) +#define RTL931X_L2_NTFY_RING_BASE_ADDR (0x09DC) +#define RTL931X_L2_NTFY_RING_CUR_ADDR (0x09E0) +#define RTL839X_L2_NOTIFICATION_CTRL (0x7808) +#define RTL931X_L2_NTFY_CTRL (0xCDC8) +#define RTL838X_L2_CTRL_0 (0x3200) +#define RTL838X_L2_CTRL_1 (0x3204) +#define RTL839X_L2_CTRL_0 (0x3800) +#define RTL930X_L2_CTRL (0x8FD8) +#define RTL931X_L2_CTRL (0xC800) + +/* TRAPPING to CPU-PORT */ +#define RTL838X_SPCL_TRAP_IGMP_CTRL (0x6984) +#define RTL838X_RMA_CTRL_0 (0x4300) +#define RTL838X_RMA_CTRL_1 (0x4304) +#define RTL839X_RMA_CTRL_0 (0x1200) + +#define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058) +#define RTL839X_RMA_CTRL_1 (0x1204) +#define RTL839X_RMA_CTRL_2 (0x1208) +#define RTL839X_RMA_CTRL_3 (0x120C) + +#define RTL930X_VLAN_APP_PKT_CTRL (0xA23C) +#define RTL930X_RMA_CTRL_0 (0x9E60) +#define RTL930X_RMA_CTRL_1 (0x9E64) +#define RTL930X_RMA_CTRL_2 (0x9E68) + +#define RTL931X_VLAN_APP_PKT_CTRL (0x96b0) +#define RTL931X_RMA_CTRL_0 (0x8800) +#define RTL931X_RMA_CTRL_1 (0x8804) +#define RTL931X_RMA_CTRL_2 (0x8808) + +/* Chip configuration registers of the RTL9310 */ +#define RTL931X_MEM_ENCAP_INIT (0x4854) +#define RTL931X_MEM_MIB_INIT (0x7E18) +#define RTL931X_MEM_ACL_INIT (0x40BC) +#define RTL931X_MEM_ALE_INIT_0 (0x83F0) +#define RTL931X_MEM_ALE_INIT_1 (0x83F4) +#define RTL931X_MEM_ALE_INIT_2 (0x82E4) +#define RTL931X_MDX_CTRL_RSVD (0x0fcc) +#define RTL931X_PS_SOC_CTRL (0x13f8) + +/* shared CPU tag definitions for RTL930X/RTL931X */ +#define RTL93XX_CPU_TAG1_FWD_MASK GENMASK(11, 8) + +#define RTL93XX_CPU_TAG1_FWD_ALE 0 +#define RTL93XX_CPU_TAG1_FWD_PHYSICAL 1 +#define RTL93XX_CPU_TAG1_FWD_LOGICAL 2 +#define RTL93XX_CPU_TAG1_FWD_TRUNK 3 +#define RTL93XX_CPU_TAG1_FWD_ONE_HOP 4 +#define RTL93XX_CPU_TAG1_FWD_LOGICAL_ONE_HOP 5 +#define RTL93XX_CPU_TAG1_FWD_UCST_CPU_MIN_PORT 6 +#define RTL93XX_CPU_TAG1_FWD_UCST_CPU 7 +#define RTL93XX_CPU_TAG1_FWD_BCST_CPU 8 + +#define RTL93XX_CPU_TAG1_IGNORE_STP_MASK GENMASK(2, 2) + +/* Default MTU with jumbo frames support */ +#define DEFAULT_MTU 9000 + +inline int rtl838x_dma_if_rx_ring_size(int i) +{ + return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2); +} + +inline int rtl839x_dma_if_rx_ring_size(int i) +{ + return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2); +} + +inline int rtl930x_dma_if_rx_ring_size(int i) +{ + return RTL930X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2); +} + +inline int rtl931x_dma_if_rx_ring_size(int i) +{ + return RTL931X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2); +} + +inline int rtl838x_dma_if_rx_ring_cntr(int i) +{ + return RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2); +} + +inline int rtl839x_dma_if_rx_ring_cntr(int i) +{ + return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2); +} + +inline int rtl930x_dma_if_rx_ring_cntr(int i) +{ + return RTL930X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2); +} + +inline int rtl931x_dma_if_rx_ring_cntr(int i) +{ + return RTL931X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2); +} + +struct p_hdr; +struct dsa_tag; +struct rteth_ctrl; +struct rteth_packet; + +struct rteth_config { + int cpu_port; + int rx_rings; + int tx_rx_enable; + int tx_trigger_mask; + int mac_l2_port_ctrl; + int qm_pkt2cpu_intpri_map; + int qm_rsn2cpuqid_ctrl; + int qm_rsn2cpuqid_cnt; + int dma_if_intr_sts; + int dma_if_intr_msk; + int l2_ntfy_if_intr_sts; + int l2_ntfy_if_intr_msk; + int dma_if_ctrl; + int mac_force_mode_ctrl; + int dma_rx_base; + int dma_tx_base; + int (*dma_if_rx_ring_size)(int ring); + int (*dma_if_rx_ring_cntr)(int ring); + int rst_glb_ctrl; + u32 mac_reg[RTETH_MAX_MAC_REGS]; + int l2_tbl_flush_ctrl; + void (*create_tx_header)(struct rteth_packet *h, unsigned int dest_port, int prio); + bool (*decode_tag)(struct rteth_packet *h, struct dsa_tag *tag); + void (*hw_en_rxtx)(struct rteth_ctrl *ctrl); + void (*hw_init)(struct rteth_ctrl *ctrl); + void (*hw_stop)(struct rteth_ctrl *ctrl); + void (*hw_reset)(struct rteth_ctrl *ctrl); + int (*init_mac)(struct rteth_ctrl *ctrl); + void (*setup_notify_ring_buffer)(struct rteth_ctrl *ctrl); + void (*update_counter)(struct rteth_ctrl *ctrl, int ring, int released); + const struct net_device_ops *netdev_ops; +}; + +#endif /* _RTL838X_ETH_H */ diff --git a/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto-serdes.c b/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto-serdes.c new file mode 100644 index 0000000000..c0d444dc2c --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto-serdes.c @@ -0,0 +1,541 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RTSDS_REG_CNT 32 +#define RTSDS_VAL_MASK GENMASK(15, 0) +#define RTSDS_SUBPAGE(page) (page % 64) + +#define RTSDS_MMD_PAGE_MASK GENMASK(15, 8) +#define RTSDS_MMD_REG_MASK GENMASK(7, 0) + +#define RTSDS_838X_SDS_CNT 6 +#define RTSDS_838X_PAGE_CNT 4 +#define RTSDS_838X_BASE 0xe780 + +#define RTSDS_839X_SDS_CNT 14 +#define RTSDS_839X_PAGE_CNT 12 +#define RTSDS_839X_BASE 0xa000 + +#define RTSDS_930X_SDS_CNT 12 +#define RTSDS_930X_PAGE_CNT 64 +#define RTSDS_930X_BASE 0x03b0 + +#define RTSDS_931X_SDS_CNT 14 +#define RTSDS_931X_PAGE_CNT 192 +#define RTSDS_931X_BASE 0x5638 + +#define RTSDS_93XX_CMD_READ 0 +#define RTSDS_93XX_CMD_WRITE BIT(1) +#define RTSDS_93XX_CMD_BUSY BIT(0) +#define RTSDS_93XX_CMD_SDS_MASK GENMASK(6, 2) +#define RTSDS_93XX_CMD_PAGE_MASK GENMASK(12, 7) +#define RTSDS_93XX_CMD_REG_MASK GENMASK(17, 13) + +struct rtsds_ctrl { + struct device *dev; + struct regmap *map; + struct mii_bus *bus; + const struct rtsds_config *cfg; +}; + +struct rtsds_config { + int sds_cnt; + int page_cnt; + int base; + int (*get_backing_sds)(int sds, int page); + int (*read)(struct rtsds_ctrl *ctrl, int sds, int page, int regnum); + int (*write)(struct rtsds_ctrl *ctrl, int sds, int page, int regnum, u16 value); +}; + +static bool rtsds_mmd_to_sds(struct rtsds_ctrl *ctrl, int addr, int devad, int mmd_regnum, + int *sds_page, int *sds_regnum) +{ + *sds_page = FIELD_GET(RTSDS_MMD_PAGE_MASK, mmd_regnum); + *sds_regnum = FIELD_GET(RTSDS_MMD_REG_MASK, mmd_regnum); + + return !(addr < 0 || addr >= ctrl->cfg->sds_cnt || + *sds_page < 0 || *sds_page >= ctrl->cfg->page_cnt || + *sds_regnum < 0 || *sds_regnum >= RTSDS_REG_CNT || + devad != MDIO_MMD_VEND1); +} + +#ifdef CONFIG_DEBUG_FS + +/* + * The SerDes offer a lot of magic that sill needs to be uncovered. Getting this info manually + * with mdio command line tools can be time consuming. Provide a convenient register dump. + */ + +#define RTSDS_DBG_PAGE_NAMES 48 +#define RTSDS_DBG_ROOT_DIR "realtek_otto_serdes" + +struct rtsds_debug_info { + struct rtsds_ctrl *ctrl; + int sds; +}; + +static const char * const rtsds_page_name[RTSDS_DBG_PAGE_NAMES] = { + [0] = "SDS", [1] = "SDS_EXT", + [2] = "FIB", [3] = "FIB_EXT", + [4] = "DTE", [5] = "DTE_EXT", + [6] = "TGX", [7] = "TGX_EXT", + [8] = "ANA_RG", [9] = "ANA_RG_EXT", + [10] = "ANA_TG", [11] = "ANA_TG_EXT", + [31] = "ANA_WDIG", + [32] = "ANA_MISC", [33] = "ANA_COM", + [34] = "ANA_SP", [35] = "ANA_SP_EXT", + [36] = "ANA_1G", [37] = "ANA_1G_EXT", + [38] = "ANA_2G", [39] = "ANA_2G_EXT", + [40] = "ANA_3G", [41] = "ANA_3G_EXT", + [42] = "ANA_5G", [43] = "ANA_5G_EXT", + [44] = "ANA_6G", [45] = "ANA_6G_EXT", + [46] = "ANA_10G", [47] = "ANA_10G_EXT", +}; + +static int rtsds_sds_to_mmd(int sds_page, int sds_regnum) +{ + return FIELD_PREP(RTSDS_MMD_PAGE_MASK, sds_page) | + FIELD_PREP(RTSDS_MMD_REG_MASK, sds_regnum); +} + +static int rtsds_dbg_registers_show(struct seq_file *seqf, void *unused) +{ + struct rtsds_debug_info *dbg_info = seqf->private; + struct rtsds_ctrl *ctrl = dbg_info->ctrl; + struct mii_bus *bus = ctrl->bus; + int sds = dbg_info->sds; + int regnum, page = 0; + int subpage; + + do { + subpage = RTSDS_SUBPAGE(page); + if (!subpage) { + seq_printf(seqf, "Back SDS %02d:", ctrl->cfg->get_backing_sds(sds, page)); + for (regnum = 0; regnum < RTSDS_REG_CNT; regnum++) + seq_printf(seqf, " %02X", regnum); + seq_puts(seqf, "\n"); + } + + if (subpage < RTSDS_DBG_PAGE_NAMES && rtsds_page_name[subpage]) + seq_printf(seqf, "%*s: ", -11, rtsds_page_name[subpage]); + else + seq_printf(seqf, "PAGE %02X : ", page); + + for (regnum = 0; regnum < RTSDS_REG_CNT; regnum++) + seq_printf(seqf, "%04X ", + mdiobus_c45_read(bus, sds, MDIO_MMD_VEND1, + rtsds_sds_to_mmd(page, regnum))); + seq_puts(seqf, "\n"); + } while (++page < ctrl->cfg->page_cnt); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(rtsds_dbg_registers); + +static int rtsds_debug_init(struct rtsds_ctrl *ctrl) +{ + struct rtsds_debug_info *dbg_info; + struct dentry *dir, *root; + char dirname[32]; + + root = debugfs_create_dir(RTSDS_DBG_ROOT_DIR, NULL); + if (IS_ERR(root)) + return PTR_ERR(root); + + for (int sds = 0; sds < ctrl->cfg->sds_cnt; sds++) { + dbg_info = devm_kzalloc(ctrl->dev, sizeof(*dbg_info), GFP_KERNEL); + if (!dbg_info) + return -ENOMEM; + + dbg_info->ctrl = ctrl; + dbg_info->sds = sds; + + snprintf(dirname, sizeof(dirname), "serdes.%d", sds); + dir = debugfs_create_dir(dirname, root); + + debugfs_create_file("registers", 0600, dir, dbg_info, + &rtsds_dbg_registers_fops); + } + + return 0; +} + +#endif /* CONFIG_DEBUG_FS */ + +/* + * The RTL838x has 6 SerDes. The 16 bit registers start at 0xbb00e780 and are mapped directly into + * 32 bit memory addresses. High 16 bits are always empty. A "lower" memory block serves pages 0/3 + * a "higher" memory block pages 1/2. + */ + +static int rtsds_838x_reg_offset(int sds, int page, int regnum) +{ + if (page == 0 || page == 3) + return (sds << 9) + (page << 7) + (regnum << 2); + + /* (page == 1 || page == 2) */ + return 0xb80 + (sds << 8) + (page << 7) + (regnum << 2); +} + +static int rtsds_838x_read(struct rtsds_ctrl *ctrl, int sds, int page, int regnum) +{ + int offset = rtsds_838x_reg_offset(sds, page, regnum); + int ret, value; + + ret = regmap_read(ctrl->map, ctrl->cfg->base + offset, &value); + + return ret ? ret : value & RTSDS_VAL_MASK; +} + +static int rtsds_838x_write(struct rtsds_ctrl *ctrl, int sds, int page, int regnum, u16 value) +{ + int offset = rtsds_838x_reg_offset(sds, page, regnum); + + return regmap_write(ctrl->map, ctrl->cfg->base + offset, value); +} + +/* + * The RTL839x has 14 SerDes starting at 0xbb00a000. 0-7, 10, 11 are 5GBit, 8, 9, 12, 13 are + * 10 GBit. Two adjacent SerDes are tightly coupled and share a 1024 bytes register area. Per 32 + * bit address two registers are stored. The first register is stored in the lower 2 bytes ("on + * the right" due to big endian) and the second register in the upper 2 bytes. The following + * register areas are known: + * + * - XSG0 (4 pages @ offset 0x000): for even SerDes + * - XSG1 (4 pages @ offset 0x100): for odd SerDes + * - TGRX (4 pages @ offset 0x200): for even 10G SerDes + * - ANA_RG (2 pages @ offset 0x300): for even 5G SerDes + * - ANA_RG (2 pages @ offset 0x380): for odd 5G SerDes + * - ANA_TG (2 pages @ offset 0x300): for even 10G SerDes + * - ANA_TG (2 pages @ offset 0x380): for odd 10G SerDes + * + * The most consistent mapping that aligns to the RTL93xx devices is: + * + * even 5G SerDes odd 5G SerDes even 10G SerDes odd 10G SerDes + * Page 0: XSG0/0 XSG1/0 XSG0/0 XSG1/0 + * Page 1: XSG0/1 XSG1/1 XSG0/1 XSG1/1 + * Page 2: XSG0/2 XSG1/2 XSG0/2 XSG1/2 + * Page 3: XSG0/3 XSG1/3 XSG0/3 XSG1/3 + * Page 4: TGRX/0 + * Page 5: TGRX/1 + * Page 6: TGRX/2 + * Page 7: TGRX/3 + * Page 8: ANA_RG ANA_RG + * Page 9: ANA_RG_EXT ANA_RG_EXT + * Page 10: ANA_TG ANA_TG + * Page 11: ANA_TG_EXT ANA_TG_EXT + */ + +static int rtsds_839x_reg_offset(int sds, int page, int regnum) +{ + int offset = ((sds & 0xfe) << 9) + ((regnum & 0xfe) << 1) + (page << 6); + int sds5g = (GENMASK(11, 10) | GENMASK(7, 0)) & BIT(sds); + + if (page < 4) + return offset + ((sds & 1) << 8); + else if ((page & 4) && (sds == 8 || sds == 12)) + return offset + 0x100; + else if (page >= 8 && page <= 9 && sds5g) + return offset + 0x100 + ((sds & 1) << 7); + else if (page >= 10 && !sds5g) + return offset + 0x80 + ((sds & 1) << 7); + + return -EINVAL; /* hole */ +} + +static int rtsds_839x_read(struct rtsds_ctrl *ctrl, int sds, int page, int regnum) +{ + int offset = rtsds_839x_reg_offset(sds, page, regnum); + int shift = regnum & 1 ? 16 : 0; + int ret, value; + + if (offset < 0) + return 0; + + ret = regmap_read(ctrl->map, ctrl->cfg->base + offset, &value); + + return ret ? ret : (value >> shift) & RTSDS_VAL_MASK; +} + +static int rtsds_839x_write(struct rtsds_ctrl *ctrl, int sds, int page, int regnum, u16 value) +{ + int offset = rtsds_839x_reg_offset(sds, page, regnum); + int write_value = value; + int neigh_value; + + if (offset < 0) + return 0; + + neigh_value = rtsds_839x_read(ctrl, sds, page, regnum ^ 1); + if (neigh_value < 0) + return neigh_value; + + if (regnum & 1) + write_value = (write_value << 16) + neigh_value; + else + write_value = (neigh_value << 16) + write_value; + + return regmap_write(ctrl->map, ctrl->cfg->base + offset, write_value); +} + +static int rtsds_83xx_get_backing_sds(int sds, int page) +{ + return sds; +} + +static int rtsds_rt93xx_io(struct rtsds_ctrl *ctrl, int sds, int page, int regnum, int cmd) +{ + int ret, op, value; + + op = FIELD_PREP(RTSDS_93XX_CMD_SDS_MASK, sds) | + FIELD_PREP(RTSDS_93XX_CMD_PAGE_MASK, page) | + FIELD_PREP(RTSDS_93XX_CMD_REG_MASK, regnum) | + RTSDS_93XX_CMD_BUSY | cmd; + + regmap_write(ctrl->map, ctrl->cfg->base, op); + ret = regmap_read_poll_timeout(ctrl->map, ctrl->cfg->base, value, + !(value & RTSDS_93XX_CMD_BUSY), 30, 1000000); + + if (ret < 0) { + dev_err(ctrl->dev, "SerDes I/O timed out\n"); + return -ETIMEDOUT; + } + + return 0; +} + +/* + * RTL93xx targets use a shared implementation. Their SerDes data is accessed through two IO + * registers which simulate commands to an internal MDIO bus. + * + * The RTL930x family has 12 SerDes of three types. + * + * - SerDes 0-1 exist on the RTL9301 and 9302B and are QSGMII capable + * - SerDes 2-9 are USXGMII capabable with either quad or single configuration + * - SerDes 10-11 are 10GBase-R capable + */ +static int rtsds_930x_get_backing_sds(int sds, int page) +{ + return sds; +} + +/* + * The RTL931x family has 14 "frontend" SerDes that are cascaded. All operations (e.g. reset) work + * on this frontend view while their registers are distributed over a total of least 26 background + * SerDes with 64 pages and 32 registers. Three types of SerDes exist: + * + * - Serdes 0,1 are "simple" and work on one background serdes. + * - "Even" SerDes with numbers 2, 4, 6, 8, 10, 12 work on two background SerDes. One analog and + * one digital. + * - "Odd" SerDes with numbers 3, 5, 7, 9, 11, 13 work on a total of 3 background SerDes (one + * analog and two digital) + * + * This maps to: + * + * Frontend SerDes | 0 1 2 3 4 5 6 7 8 9 10 11 12 13 + * -----------------+------------------------------------------ + * Backend SerDes 1 | 0 1 2 3 6 7 10 11 14 15 18 19 22 23 + * Backend SerDes 2 | 0 1 2 4 6 8 10 12 14 16 18 20 22 24 + * Backend SerDes 3 | 0 1 3 5 7 9 11 13 15 17 19 21 23 25 + * + * Note: In Realtek proprietary XSGMII mode (10G pumped SGMII) the frontend SerDes works on the + * two digital SerDes while in all other modes it works on the analog and the first digital + * SerDes. Overlapping (e.g. backend SerDes 7 can be analog or digital 2) is avoided by the + * existing hardware designs. + * + * Align this for readability by simulating a total of 192 pages and mix them as follows. + * + * frontend page "even" frontend SerDes "odd" frontend SerDes + * page 0x00-0x3f (analog): page 0x00-0x3f back SDS page 0x00-0x3f back SDS + * page 0x40-0x7f (digi 1): page 0x00-0x3f back SDS page 0x00-0x3f back SDS+1 + * page 0x80-0xbf (digi 2): page 0x00-0x3f back SDS+1 page 0x00-0x3f back SDS+2 + */ +static int rtsds_931x_get_backing_sds(int sds, int page) +{ + int map[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 }; + int backsds; + + /* First two RTL931x SerDes have 1:1 frontend/backend mapping */ + if (sds < 2) + return sds; + + backsds = map[sds]; + if (sds & 1) + backsds += (page >> 6); /* distribute "odd" to 3 background SerDes */ + else + backsds += (page >> 7); /* distribute "even" to 2 background SerDes */ + + return backsds; +} + +static int rtsds_93xx_read(struct rtsds_ctrl *ctrl, int sds, int page, int regnum) +{ + int subpage = RTSDS_SUBPAGE(page); + int ret, backsds, value; + + backsds = ctrl->cfg->get_backing_sds(sds, page); + ret = rtsds_rt93xx_io(ctrl, backsds, subpage, regnum, RTSDS_93XX_CMD_READ); + if (ret) + return ret; + + ret = regmap_read(ctrl->map, ctrl->cfg->base + 4, &value); + + return ret ? ret : value & RTSDS_VAL_MASK; +} + +static int rtsds_93xx_write(struct rtsds_ctrl *ctrl, int sds, int page, int regnum, u16 value) +{ + int subpage = RTSDS_SUBPAGE(page); + int ret, backsds; + + backsds = ctrl->cfg->get_backing_sds(sds, page); + ret = regmap_write(ctrl->map, ctrl->cfg->base + 4, value); + if (ret) + return ret; + + return rtsds_rt93xx_io(ctrl, backsds, subpage, regnum, RTSDS_93XX_CMD_WRITE); +} + +static int rtsds_read(struct mii_bus *bus, int addr, int devad, int regnum) +{ + struct rtsds_ctrl *ctrl = bus->priv; + int sds_page, sds_regnum; + + if (!rtsds_mmd_to_sds(ctrl, addr, devad, regnum, &sds_page, &sds_regnum)) + return -EINVAL; + + return ctrl->cfg->read(ctrl, addr, sds_page, sds_regnum); +} + +static int rtsds_write(struct mii_bus *bus, int addr, int devad, int regnum, u16 value) +{ + struct rtsds_ctrl *ctrl = bus->priv; + int sds_page, sds_regnum; + + if (!rtsds_mmd_to_sds(ctrl, addr, devad, regnum, &sds_page, &sds_regnum)) + return -EINVAL; + + return ctrl->cfg->write(ctrl, addr, sds_page, sds_regnum, value); +} + +static int rtsds_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct rtsds_ctrl *ctrl; + struct mii_bus *bus; + int ret; + + bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*ctrl)); + if (!bus) + return -ENOMEM; + + ctrl = bus->priv; + ctrl->map = syscon_node_to_regmap(np->parent); + if (IS_ERR(ctrl->map)) + return PTR_ERR(ctrl->map); + + ctrl->dev = dev; + ctrl->cfg = (const struct rtsds_config *)device_get_match_data(ctrl->dev); + ctrl->bus = bus; + + snprintf(bus->id, MII_BUS_ID_SIZE, "realtek-serdes-mdio"); + bus->name = "Realtek SerDes MDIO bus"; + bus->parent = dev; + bus->read_c45 = rtsds_read; + bus->write_c45 = rtsds_write; + bus->phy_mask = ~0ULL; + + ret = devm_of_mdiobus_register(dev, bus, dev->of_node); + if (ret) + return ret; + +#ifdef CONFIG_DEBUG_FS + rtsds_debug_init(ctrl); +#endif + + dev_info(dev, "Realtek SerDes mdio bus initialized, %d SerDes, %d pages, %d registers\n", + ctrl->cfg->sds_cnt, ctrl->cfg->page_cnt, RTSDS_REG_CNT); + + return 0; +} + +static const struct rtsds_config rtsds_838x_cfg = { + .sds_cnt = RTSDS_838X_SDS_CNT, + .page_cnt = RTSDS_838X_PAGE_CNT, + .base = RTSDS_838X_BASE, + .get_backing_sds = rtsds_83xx_get_backing_sds, + .read = rtsds_838x_read, + .write = rtsds_838x_write, +}; + +static const struct rtsds_config rtsds_839x_cfg = { + .sds_cnt = RTSDS_839X_SDS_CNT, + .page_cnt = RTSDS_839X_PAGE_CNT, + .base = RTSDS_839X_BASE, + .get_backing_sds = rtsds_83xx_get_backing_sds, + .read = rtsds_839x_read, + .write = rtsds_839x_write, +}; + +static const struct rtsds_config rtsds_930x_cfg = { + .sds_cnt = RTSDS_930X_SDS_CNT, + .page_cnt = RTSDS_930X_PAGE_CNT, + .base = RTSDS_930X_BASE, + .get_backing_sds = rtsds_930x_get_backing_sds, + .read = rtsds_93xx_read, + .write = rtsds_93xx_write, +}; + +static const struct rtsds_config rtsds_931x_cfg = { + .sds_cnt = RTSDS_931X_SDS_CNT, + .page_cnt = RTSDS_931X_PAGE_CNT, + .base = RTSDS_931X_BASE, + .get_backing_sds = rtsds_931x_get_backing_sds, + .read = rtsds_93xx_read, + .write = rtsds_93xx_write, +}; + +static const struct of_device_id rtsds_of_match[] = { + { + .compatible = "realtek,rtl8380-serdes-mdio", + .data = &rtsds_838x_cfg, + }, + { + .compatible = "realtek,rtl8392-serdes-mdio", + .data = &rtsds_839x_cfg, + }, + { + .compatible = "realtek,rtl9301-serdes-mdio", + .data = &rtsds_930x_cfg, + }, + { + .compatible = "realtek,rtl9311-serdes-mdio", + .data = &rtsds_931x_cfg, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtsds_of_match); + +static struct platform_driver rtsds_mdio_driver = { + .driver = { + .name = "realtek-otto-serdes-mdio", + .of_match_table = rtsds_of_match + }, + .probe = rtsds_probe, +}; +module_platform_driver(rtsds_mdio_driver); + +MODULE_AUTHOR("Markus Stockhausen "); +MODULE_DESCRIPTION("Realtek Otto SerDes MDIO bus"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c b/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c new file mode 100644 index 0000000000..d53e447c45 --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c @@ -0,0 +1,1066 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include + +#define RTMDIO_MAX_PHY 57 +#define RTMDIO_MAX_SMI_BUS 4 +#define RTMDIO_PAGE_SELECT 0x1f + +#define RTMDIO_PHY_AQR113C_A 0x31c31c12 +#define RTMDIO_PHY_AQR113C_B 0x31c31c13 +#define RTMDIO_PHY_AQR813 0x31c31cb2 +#define RTMDIO_PHY_RTL8218D 0x001cc983 +#define RTMDIO_PHY_RTL8218E 0x001cc984 +#define RTMDIO_PHY_RTL8221B_VB_CG 0x001cc849 +#define RTMDIO_PHY_RTL8221B_VM_CG 0x001cc84a +#define RTMDIO_PHY_RTL8224 0x001ccad0 +#define RTMDIO_PHY_RTL8226 0x001cc838 +#define RTMDIO_PHY_RTL8261 0x001ccaf3 + +#define RTMDIO_PHY_MAC_1G 3 +#define RTMDIO_PHY_MAC_2G_PLUS 1 + +#define RTMDIO_PHY_POLL_MMD(dev, reg, bit) ((bit << 21) | (dev << 16) | reg) + +/* MDIO bus registers/fields */ +#define RTMDIO_RUN BIT(0) + +#define RTMDIO_838X_PHY_PATCH_DONE BIT(15) +#define RTMDIO_838X_SMI_GLB_CTRL (0xa100) +#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0 (0xa1b8) +#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1 (0xa1bc) +#define RTMDIO_838X_CMD_FAIL 0 +#define RTMDIO_838X_CMD_READ_C22 0 +#define RTMDIO_838X_CMD_READ_C45 BIT(1) +#define RTMDIO_838X_CMD_WRITE_C22 BIT(2) +#define RTMDIO_838X_CMD_WRITE_C45 BIT(1) | BIT(2) +#define RTMDIO_838X_CMD_MASK GENMASK(2, 0) +#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2 (0xa1c0) +#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3 (0xa1c4) +#define RTMDIO_838X_SMI_POLL_CTRL (0xa17c) +#define RTMDIO_838X_SMI_PORT0_5_ADDR_CTRL (0xa1c8) + +#define RTMDIO_839X_PHYREG_CTRL (0x03E0) +#define RTMDIO_839X_PHYREG_PORT_CTRL (0x03E4) +#define RTMDIO_839X_PHYREG_ACCESS_CTRL (0x03DC) +#define RTMDIO_839X_CMD_FAIL BIT(1) +#define RTMDIO_839X_CMD_READ_C22 0 +#define RTMDIO_839X_CMD_READ_C45 BIT(2) +#define RTMDIO_839X_CMD_WRITE_C22 BIT(3) +#define RTMDIO_839X_CMD_WRITE_C45 BIT(2) | BIT(3) +#define RTMDIO_839X_CMD_MASK GENMASK(3, 0) +#define RTMDIO_839X_PHYREG_DATA_CTRL (0x03F0) +#define RTMDIO_839X_PHYREG_MMD_CTRL (0x03F4) +#define RTMDIO_839X_SMI_PORT_POLLING_CTRL (0x03fc) +#define RTMDIO_839X_SMI_GLB_CTRL (0x03f8) + +#define RTMDIO_930X_SMI_GLB_CTRL (0xCA00) +#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0 (0xCB70) +#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1 (0xCB74) +#define RTMDIO_930X_CMD_FAIL BIT(25) +#define RTMDIO_930X_CMD_READ_C22 0 +#define RTMDIO_930X_CMD_READ_C45 BIT(1) +#define RTMDIO_930X_CMD_WRITE_C22 BIT(2) +#define RTMDIO_930X_CMD_WRITE_C45 BIT(1) | BIT(2) +#define RTMDIO_930X_CMD_MASK GENMASK(2, 0) | BIT(25) +#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2 (0xCB78) +#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3 (0xCB7C) +#define RTMDIO_930X_SMI_PORT0_15_POLLING_SEL (0xCA08) +#define RTMDIO_930X_SMI_PORT16_27_POLLING_SEL (0xCA0C) +#define RTMDIO_930X_SMI_MAC_TYPE_CTRL (0xCA04) +#define RTMDIO_930X_SMI_PRVTE_POLLING_CTRL (0xCA10) +#define RTMDIO_930X_SMI_10G_POLLING_REG0_CFG (0xCBB4) +#define RTMDIO_930X_SMI_10G_POLLING_REG9_CFG (0xCBB8) +#define RTMDIO_930X_SMI_10G_POLLING_REG10_CFG (0xCBBC) +#define RTMDIO_930X_SMI_PORT0_5_ADDR_CTRL (0xCB80) + +#define RTMDIO_931X_SMI_PORT_POLLING_CTRL (0x0CCC) +#define RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL (0x0C14) +#define RTMDIO_931X_SMI_GLB_CTRL0 (0x0CC0) +#define RTMDIO_931X_SMI_GLB_CTRL1 (0x0CBC) +#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0 (0x0C00) +#define RTMDIO_931X_CMD_FAIL BIT(1) +#define RTMDIO_931X_CMD_READ_C22 0 +#define RTMDIO_931X_CMD_READ_C45 BIT(3) +#define RTMDIO_931X_CMD_WRITE_C22 BIT(4) +#define RTMDIO_931X_CMD_WRITE_C45 BIT(3) | BIT(4) +#define RTMDIO_931X_CMD_MASK GENMASK(4, 0) +#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_1 (0x0C04) +#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2 (0x0C08) +#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3 (0x0C10) +#define RTMDIO_931X_SMI_INDRT_ACCESS_MMD_CTRL (0x0C18) +#define RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL (0x0CAC) +#define RTMDIO_931X_SMY_PHY_ABLTY_MDIO 0x0 +#define RTMDIO_931X_SMI_PHY_ABLTY_SDS 0x2 +#define RTMDIO_931X_SMI_PORT_POLLING_SEL (0x0C9C) +#define RTMDIO_931X_SMI_PORT_ADDR_CTRL (0x0C74) +#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL0 (0x0CF0) +#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL1 (0x0CF4) +#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL2 (0x0CF8) +#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL3 (0x0CFC) +#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL4 (0x0D00) + +#define for_each_phy(ctrl, addr) \ + for_each_set_bit(addr, ctrl->valid_ports, RTMDIO_MAX_PHY) + +#define rtmdio_ctrl_from_bus(bus) \ + (((struct rtmdio_chan *)(bus)->priv)->ctrl) + +/* + * On all Realtek switch platforms the hardware periodically reads the link status of all + * PHYs. This is to some degree programmable, so that one can tell the hardware to read + * specific C22 registers from specific pages, or C45 registers, to determine the current + * link speed, duplex, flow-control, ... + * + * This happens without any need for the driver to do anything at runtime, completely + * invisible and in a parallel hardware thread, independent of the CPU running Linux. + * All one needs to do is to set it up once. Having the MAC link settings automatically + * follow the PHY link status also happens to be the only way to control MAC port status + * in a meaningful way, or at least it's the only way we fully understand, as this is + * what every vendor firmware is doing. + * + * The hardware PHY polling unit doesn't care about bus locking, it just assumes that all + * paged PHY operations are also done via the same hardware unit offering this PHY access + * abstractions. + * + * Additionally at least the RTL838x and RTL839x devices are known to have a so called + * raw mode. Using the special MAX_PAGE-1 with the MDIO controller found in Realtek + * SoCs allows to access the PHY in raw mode, ie. bypassing the cache and paging engine + * of the MDIO controller. E.g. for RTL838x this is 0xfff. + * + * On the other hand Realtek PHYs usually make use of select register 0x1f to switch + * pages. There is no problem to issue separate page and access bus calls to the PHYs + * when they are not attached to an Realtek SoC. The paradigm should be to keep the PHY + * implementation bus independent. + * + * To bring all this together we need a tricky bus design that intercepts select page + * calls but lets raw page accesses through. And especially knows how to handle raw + * accesses to the select register. Additionally we need the possibility to write to + * all 8 ports of the PHY individually. + * + * While the C45 clause stuff is pretty standard the legacy functions basically track + * the accesses and the state of the bus with the attributes page[], raw[] and portaddr + * of the bus_priv structure. The page selection works as follows: + * + * phy_write(phydev, RTMDIO_PAGE_SELECT, 12) : store internal page 12 in driver + * phy_write(phydev, 7, 33) : write page=12, reg=7, val=33 + * + * or simply + * + * phy_write_paged(phydev, 12, 7, 33) : write page=12, reg=7, val=33 + * + * Any Realtek PHY that will be connected to this bus must simply provide the standard + * page functions: + * + * define RTL821X_PAGE_SELECT 0x1f + * + * static int rtl821x_read_page(struct phy_device *phydev) + * { + * return __phy_read(phydev, RTL821X_PAGE_SELECT); + * } + * + * static int rtl821x_write_page(struct phy_device *phydev, int page) + * { + * return __phy_write(phydev, RTL821X_PAGE_SELECT, page); + * } + * + * In case there are non Realtek PHYs attached to the bus the logic might need to be + * reimplemented. For now it should be sufficient. + */ + +struct rtmdio_port { + struct device_node *dn; + int page; + bool raw; + u8 smi_addr; + u8 smi_bus; +}; + +struct rtmdio_bus { + bool is_c45; +}; + +struct rtmdio_ctrl { + struct regmap *map; + const struct rtmdio_config *cfg; + struct rtmdio_port port[RTMDIO_MAX_PHY]; + struct rtmdio_bus bus[RTMDIO_MAX_SMI_BUS]; + DECLARE_BITMAP(valid_ports, RTMDIO_MAX_PHY); +}; + +struct rtmdio_chan { + struct rtmdio_ctrl *ctrl; +}; + +struct rtmdio_config { + int num_phys; + int raw_page; + int bus_map_base; + int port_map_base; + int (*read_mmd_phy)(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val); + int (*read_phy)(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val); + int (*reset)(struct mii_bus *bus); + void (*setup_polling)(struct mii_bus *bus); + int (*write_mmd_phy)(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val); + int (*write_phy)(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val); +}; + +struct rtmdio_phy_info { + int mac_type; + bool has_giga_lite; + bool has_res_reg; + bool force_res; + unsigned int poll_duplex; + unsigned int poll_adv_1000; + unsigned int poll_lpa_1000; +}; + +static int rtmdio_run_cmd(struct mii_bus *bus, int cmd, int mask, int regnum, int fail) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + int ret, val; + + ret = regmap_update_bits(ctrl->map, regnum, mask, cmd | RTMDIO_RUN); + ret = regmap_read_poll_timeout(ctrl->map, regnum, val, !(val & RTMDIO_RUN), 20, 500000); + if (ret) + WARN_ONCE(1, "mdio bus access timed out\n"); + else if (val & fail) { + WARN_ONCE(1, "mdio bus access failed\n"); + ret = -EIO; + } + + return ret; +} + +static int rtmdio_838x_run_cmd(struct mii_bus *bus, int cmd) +{ + return rtmdio_run_cmd(bus, cmd, RTMDIO_838X_CMD_MASK, + RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1, RTMDIO_838X_CMD_FAIL); +} + +static int rtmdio_838x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + u32 park_page = 31; + int err; + + regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(addr)); + regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, addr << 16); + regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1, + reg << 20 | park_page << 15 | page << 3); + err = rtmdio_838x_run_cmd(bus, RTMDIO_838X_CMD_READ_C22); + if (!err) + err = regmap_read(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, val); + if (!err) + *val &= GENMASK(15, 0); + + return err; +} + +static int rtmdio_838x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + u32 park_page = 31; + + regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(addr)); + regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, val << 16); + regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1, + reg << 20 | park_page << 15 | page << 3); + + return rtmdio_838x_run_cmd(bus, RTMDIO_838X_CMD_WRITE_C22); +} + +static int rtmdio_838x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + int err; + + regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(addr)); + regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, addr << 16); + regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3, devnum << 16 | regnum); + err = rtmdio_838x_run_cmd(bus, RTMDIO_838X_CMD_READ_C45); + if (!err) + err = regmap_read(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, val); + if (!err) + *val &= GENMASK(15, 0); + + return err; +} + +static int rtmdio_838x_write_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + + regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(addr)); + regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, val << 16); + regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3, devnum << 16 | regnum); + + return rtmdio_838x_run_cmd(bus, RTMDIO_838X_CMD_WRITE_C45); +} + +static int rtmdio_839x_run_cmd(struct mii_bus *bus, int cmd) +{ + return rtmdio_run_cmd(bus, cmd, RTMDIO_839X_CMD_MASK, + RTMDIO_839X_PHYREG_ACCESS_CTRL, RTMDIO_839X_CMD_FAIL); +} + +static int rtmdio_839x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + int err; + + regmap_write(ctrl->map, RTMDIO_839X_PHYREG_CTRL, 0x1ff); + regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, addr << 16); + regmap_write(ctrl->map, RTMDIO_839X_PHYREG_ACCESS_CTRL, + reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23); + err = rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_READ_C22); + if (!err) + err = regmap_read(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, val); + if (!err) + *val &= GENMASK(15, 0); + + return err; +} + +static int rtmdio_839x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + + regmap_write(ctrl->map, RTMDIO_839X_PHYREG_CTRL, 0x1ff); + regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, val << 16); + regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL, BIT_ULL(addr)); + regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL + 4, BIT_ULL(addr) >> 32); + regmap_write(ctrl->map, RTMDIO_839X_PHYREG_ACCESS_CTRL, + reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23); + + return rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_WRITE_C22); +} + +static int rtmdio_839x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + int err; + + regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, addr << 16); + regmap_write(ctrl->map, RTMDIO_839X_PHYREG_MMD_CTRL, (devnum << 16) | (regnum & 0xffff)); + err = rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_READ_C45); + if (!err) + err = regmap_read(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, val); + if (!err) + *val &= GENMASK(15, 0); + + return err; +} + +static int rtmdio_839x_write_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + + regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL, BIT_ULL(addr)); + regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL + 4, BIT_ULL(addr) >> 32); + regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, val << 16); + regmap_write(ctrl->map, RTMDIO_839X_PHYREG_MMD_CTRL, (devnum << 16) | (regnum & 0xffff)); + + return rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_WRITE_C45); +} + +static int rtmdio_930x_run_cmd(struct mii_bus *bus, int cmd) +{ + return rtmdio_run_cmd(bus, cmd, RTMDIO_930X_CMD_MASK, + RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1, RTMDIO_930X_CMD_FAIL); +} + +static int rtmdio_930x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + u32 park_page = 31; + + regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0, BIT(addr)); + regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, val << 16); + regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1, + reg << 20 | page << 3 | park_page << 15); + + return rtmdio_930x_run_cmd(bus, RTMDIO_930X_CMD_WRITE_C22); +} + +static int rtmdio_930x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + u32 park_page = 31; + int err; + + regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, addr << 16); + regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1, + reg << 20 | page << 3 | park_page << 15); + err = rtmdio_930x_run_cmd(bus, RTMDIO_930X_CMD_READ_C22); + if (!err) + err = regmap_read(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, val); + if (!err) + *val &= GENMASK(15, 0); + + return err; +} + +static int rtmdio_930x_write_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + + regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0, BIT(addr)); + regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, val << 16); + regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3, (devnum << 16) | (regnum & 0xffff)); + + return rtmdio_930x_run_cmd(bus, RTMDIO_930X_CMD_WRITE_C45); +} + +static int rtmdio_930x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + int err; + + regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, addr << 16); + regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3, (devnum << 16) | (regnum & 0xffff)); + err = rtmdio_930x_run_cmd(bus, RTMDIO_930X_CMD_READ_C45); + if (!err) + err = regmap_read(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, val); + if (!err) + *val &= GENMASK(15, 0); + + return err; +} + +static int rtmdio_931x_run_cmd(struct mii_bus *bus, int cmd) +{ + return rtmdio_run_cmd(bus, cmd, RTMDIO_931X_CMD_MASK, + RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0, RTMDIO_931X_CMD_FAIL); +} + +static int rtmdio_931x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + u64 mask = BIT_ULL(addr); + + regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2, (u32)mask); + regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2 + 4, (u32)(mask >> 32)); + regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3, val); + regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0, reg << 6 | page << 11); + regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_1, 0x1ff); + + return rtmdio_931x_run_cmd(bus, RTMDIO_931X_CMD_WRITE_C22); +} + +static int rtmdio_931x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + int err; + + regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL, addr << 5); + regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0, reg << 6 | page << 11); + err = rtmdio_931x_run_cmd(bus, RTMDIO_931X_CMD_READ_C22); + if (!err) + err = regmap_read(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3, val); + if (!err) + *val >>= 16; + + return err; +} + +static int rtmdio_931x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + int err; + + regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL, addr << 5); + regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_MMD_CTRL, (devnum << 16) | (regnum & 0xffff)); + err = rtmdio_931x_run_cmd(bus, RTMDIO_931X_CMD_READ_C45); + if (!err) + err = regmap_read(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3, val); + if (!err) + *val >>= 16; + + return err; +} + +static int rtmdio_931x_write_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + u64 mask = BIT_ULL(addr); + + regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2, (u32)mask); + regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2 + 4, (u32)(mask >> 32)); + regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3, val); + regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_MMD_CTRL, (devnum << 16) | (regnum & 0xffff)); + + return rtmdio_931x_run_cmd(bus, RTMDIO_931X_CMD_WRITE_C45); +} + +static int rtmdio_read_c45(struct mii_bus *bus, int addr, int devnum, int regnum) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + int err, val; + + if (addr >= ctrl->cfg->num_phys) + return -ENODEV; + + err = (*ctrl->cfg->read_mmd_phy)(bus, addr, devnum, regnum, &val); + pr_debug("rd_MMD(adr=%d, dev=%d, reg=%d) = %d, err = %d\n", + addr, devnum, regnum, val, err); + return err ? err : val; +} + +static int rtmdio_read(struct mii_bus *bus, int addr, int regnum) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + int err, val; + + if (addr >= ctrl->cfg->num_phys) + return -ENODEV; + + if (regnum == RTMDIO_PAGE_SELECT && ctrl->port[addr].page != ctrl->cfg->raw_page) + return ctrl->port[addr].page; + + ctrl->port[addr].raw = (ctrl->port[addr].page == ctrl->cfg->raw_page); + + err = (*ctrl->cfg->read_phy)(bus, addr, ctrl->port[addr].page, regnum, &val); + pr_debug("rd_PHY(adr=%d, pag=%d, reg=%d) = %d, err = %d\n", + addr, ctrl->port[addr].page, regnum, val, err); + return err ? err : val; +} + +static int rtmdio_write_c45(struct mii_bus *bus, int addr, int devnum, int regnum, u16 val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + int err; + + if (addr >= ctrl->cfg->num_phys) + return -ENODEV; + + err = (*ctrl->cfg->write_mmd_phy)(bus, addr, devnum, regnum, val); + pr_debug("wr_MMD(adr=%d, dev=%d, reg=%d, val=%d) err = %d\n", + addr, devnum, regnum, val, err); + return err; +} + +static int rtmdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + int err, page; + + if (addr >= ctrl->cfg->num_phys) + return -ENODEV; + + page = ctrl->port[addr].page; + + if (regnum == RTMDIO_PAGE_SELECT) + ctrl->port[addr].page = val; + + if (!ctrl->port[addr].raw && + (regnum != RTMDIO_PAGE_SELECT || page == ctrl->cfg->raw_page)) { + ctrl->port[addr].raw = (page == ctrl->cfg->raw_page); + + err = (*ctrl->cfg->write_phy)(bus, addr, page, regnum, val); + pr_debug("wr_PHY(adr=%d, pag=%d, reg=%d, val=%d) err = %d\n", + addr, page, regnum, val, err); + return err; + } + + ctrl->port[addr].raw = false; + return 0; +} + +static void rtmdio_setup_smi_topology(struct rtmdio_ctrl *ctrl) +{ + u32 reg, mask, val, addr; + + for_each_phy(ctrl, addr) { + if (ctrl->cfg->bus_map_base) { + reg = (addr / 16) * 4; + mask = 0x3 << ((addr % 16) * 2); + val = ctrl->port[addr].smi_bus << ((addr % 16) * 2); + regmap_update_bits(ctrl->map, ctrl->cfg->bus_map_base + reg, mask, val); + } + + if (ctrl->cfg->port_map_base) { + reg = (addr / 6) * 4; + mask = 0x1f << ((addr % 6) * 5); + val = ctrl->port[addr].smi_addr << ((addr % 6) * 5); + regmap_update_bits(ctrl->map, ctrl->cfg->port_map_base + reg, mask, val); + } + } +} + +static u32 rtmdio_get_phy_id(struct phy_device *phydev) +{ + if (!phydev) + return 0; + + if (phydev->is_c45) { + for (int devad = 0; devad < MDIO_MMD_NUM; devad++) { + u32 phyid = phydev->c45_ids.device_ids[devad]; + + if (phyid && phyid != 0xffffffff) + return phyid; + } + } + + return phydev->phy_id; +} + +static int rtmdio_get_phy_info(struct mii_bus *bus, int addr, struct rtmdio_phy_info *phyinfo) +{ + struct phy_device *phydev = mdiobus_get_phy(bus, addr); + u32 phyid = rtmdio_get_phy_id(phydev); + int ret = 0; + + /* + * Depending on the attached PHY the polling mechanism must be fine tuned. Basically + * this boils down to which registers must be read and if there are any special + * features. + */ + memset(phyinfo, 0, sizeof(*phyinfo)); + + switch(phyid) { + case RTMDIO_PHY_AQR113C_A: + case RTMDIO_PHY_AQR113C_B: + case RTMDIO_PHY_AQR813: + phyinfo->mac_type = RTMDIO_PHY_MAC_2G_PLUS; + phyinfo->poll_duplex = RTMDIO_PHY_POLL_MMD(1, 0x0000, 8); + phyinfo->poll_adv_1000 = RTMDIO_PHY_POLL_MMD(7, 0xc400, 15); + phyinfo->poll_lpa_1000 = RTMDIO_PHY_POLL_MMD(7, 0xe820, 15); + break; + case RTMDIO_PHY_RTL8218D: + case RTMDIO_PHY_RTL8218E: + phyinfo->mac_type = RTMDIO_PHY_MAC_1G; + phyinfo->has_giga_lite = true; + break; + case RTMDIO_PHY_RTL8226: + case RTMDIO_PHY_RTL8221B_VB_CG: + case RTMDIO_PHY_RTL8221B_VM_CG: + case RTMDIO_PHY_RTL8224: + phyinfo->mac_type = RTMDIO_PHY_MAC_2G_PLUS; + phyinfo->has_giga_lite = true; + phyinfo->poll_duplex = RTMDIO_PHY_POLL_MMD(31, 0xa400, 8); + phyinfo->poll_adv_1000 = RTMDIO_PHY_POLL_MMD(31, 0xa412, 9); + phyinfo->poll_lpa_1000 = RTMDIO_PHY_POLL_MMD(31, 0xa414, 11); + break; + case RTMDIO_PHY_RTL8261: + phyinfo->mac_type = RTMDIO_PHY_MAC_2G_PLUS; + phyinfo->has_giga_lite = true; + phyinfo->has_res_reg = true; + break; + default: + pr_warn("skip polling setup for unknown PHY %08x on address %d\n", phyid, addr); + ret = -EINVAL; + break; + } + + return ret; +} + +static int rtmdio_838x_reset(struct mii_bus *bus) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + + /* + * PHY_PATCH_DONE enables phy control via SoC. This is required for phy access, + * including patching. Must always be set before the phys are probed. + */ + regmap_update_bits(ctrl->map, RTMDIO_838X_SMI_GLB_CTRL, + RTMDIO_838X_PHY_PATCH_DONE, RTMDIO_838X_PHY_PATCH_DONE); + + return 0; +} + +static void rtmdio_838x_setup_polling(struct mii_bus *bus) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + int combo_phy; + + /* Disable MAC polling for PHY config. It will be activated later in the DSA driver */ + regmap_write(ctrl->map, RTMDIO_838X_SMI_POLL_CTRL, 0); + + /* + * Control bits EX_PHY_MAN_xxx have an important effect on the detection of the media + * status (fibre/copper) of a PHY. Once activated, register MAC_LINK_MEDIA_STS can + * give the real media status (0=copper, 1=fibre). For now assume that if address 24 is + * PHY driven, it must be a combo PHY and media detection is needed. + */ + combo_phy = test_bit(24, ctrl->valid_ports) ? BIT(7) : 0; + regmap_update_bits(ctrl->map, RTMDIO_838X_SMI_GLB_CTRL, BIT(7), combo_phy); +} + +static int rtmdio_839x_reset(struct mii_bus *bus) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + + return 0; + + pr_debug("%s called\n", __func__); + /* BUG: The following does not work, but should! */ + /* Disable MAC polling the PHY so that we can start configuration */ + regmap_write(ctrl->map, RTMDIO_839X_SMI_PORT_POLLING_CTRL, 0); + regmap_write(ctrl->map, RTMDIO_839X_SMI_PORT_POLLING_CTRL + 4, 0); + /* Disable PHY polling via SoC */ + regmap_update_bits(ctrl->map, RTMDIO_839X_SMI_GLB_CTRL, BIT(7), 0); + + /* Probably should reset all PHYs here... */ + return 0; +} + +static int rtmdio_930x_reset(struct mii_bus *bus) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + unsigned int mask, val; + + /* Define C22/C45 bus feature set */ + for (int addr = 0; addr < RTMDIO_MAX_SMI_BUS; addr++) { + mask = BIT(16 + addr); + val = ctrl->bus[addr].is_c45 ? mask : 0; + regmap_update_bits(ctrl->map, RTMDIO_930X_SMI_GLB_CTRL, mask, val); + } + + return 0; +} + +static void rtmdio_930x_setup_polling(struct mii_bus *bus) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + struct rtmdio_phy_info phyinfo; + unsigned int mask, val, addr; + + /* set everthing to "SerDes driven" */ + regmap_write(ctrl->map, RTMDIO_930X_SMI_MAC_TYPE_CTRL, 0); + + /* Define PHY specific polling parameters */ + for_each_phy(ctrl, addr) { + if (rtmdio_get_phy_info(bus, addr, &phyinfo)) + continue; + + /* set to "PHY driven" */ + mask = addr > 23 ? 0x7 << ((addr - 24) * 3 + 12): 0x3 << ((addr / 4) * 2); + val = phyinfo.mac_type << (ffs(mask) - 1); + regmap_update_bits(ctrl->map, RTMDIO_930X_SMI_MAC_TYPE_CTRL, mask, val); + + /* polling via standard or resolution register */ + mask = BIT(20 + ctrl->port[addr].smi_bus); + val = phyinfo.has_res_reg ? mask : 0; + regmap_update_bits(ctrl->map, RTMDIO_930X_SMI_GLB_CTRL, mask, val); + + /* proprietary Realtek 1G/2.5 lite polling */ + mask = BIT(addr); + val = phyinfo.has_giga_lite ? mask : 0; + regmap_update_bits(ctrl->map, RTMDIO_930X_SMI_PRVTE_POLLING_CTRL, mask, val); + + /* special duplex/advertisement polling registers */ + if (phyinfo.poll_duplex || phyinfo.poll_adv_1000 || phyinfo.poll_lpa_1000) { + regmap_write(ctrl->map, RTMDIO_930X_SMI_10G_POLLING_REG0_CFG, phyinfo.poll_duplex); + regmap_write(ctrl->map, RTMDIO_930X_SMI_10G_POLLING_REG9_CFG, phyinfo.poll_adv_1000); + regmap_write(ctrl->map, RTMDIO_930X_SMI_10G_POLLING_REG10_CFG, phyinfo.poll_lpa_1000); + } + } +} + +static int rtmdio_931x_reset(struct mii_bus *bus) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + u32 c45_mask = 0; + + /* Disable polling for configuration purposes */ + regmap_write(ctrl->map, RTMDIO_931X_SMI_PORT_POLLING_CTRL, 0); + regmap_write(ctrl->map, RTMDIO_931X_SMI_PORT_POLLING_CTRL + 4, 0); + msleep(100); + + /* Define C22/C45 bus feature set */ + for (int i = 0; i < RTMDIO_MAX_SMI_BUS; i++) { + if (ctrl->bus[i].is_c45) + c45_mask |= 0x2 << (i * 2); /* Std. C45, non-standard is 0x3 */ + } + regmap_update_bits(ctrl->map, RTMDIO_931X_SMI_GLB_CTRL1, GENMASK(7, 0), c45_mask); + + return 0; +} + +static void rtmdio_931x_setup_polling(struct mii_bus *bus) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + struct rtmdio_phy_info phyinfo; + u32 addr; + + /* set everything to "SerDes driven" */ + for (int reg = 0; reg < 4; reg++) + regmap_write(ctrl->map, RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL + reg * 4, + RTMDIO_931X_SMI_PHY_ABLTY_SDS * 0x55555555U); + + /* Define PHY specific polling parameters */ + for_each_phy(ctrl, addr) { + u8 smi = ctrl->port[addr].smi_bus; + unsigned int mask, val; + + if (rtmdio_get_phy_info(bus, addr, &phyinfo)) + continue; + + /* set to "PHY driven" */ + mask = GENMASK(1, 0) << ((addr % 16) * 2); + val = RTMDIO_931X_SMY_PHY_ABLTY_MDIO << (ffs(mask) - 1); + regmap_update_bits(ctrl->map, RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL + (addr / 16) * 4, + mask, val); + mask = val = 0; + + /* PRVTE0 polling */ + mask |= BIT(20 + smi); + if (phyinfo.has_res_reg) + val |= BIT(20 + smi); + + /* PRVTE1 polling */ + mask |= BIT(24 + smi); + if (phyinfo.force_res) + val |= BIT(24 + smi); + + regmap_update_bits(ctrl->map, RTMDIO_931X_SMI_GLB_CTRL0, mask, val); + + /* polling std. or proprietary format (bit 0 of SMI_SETX_FMT_SEL) */ + mask = BIT(smi * 2); + val = phyinfo.force_res ? mask : 0; + regmap_update_bits(ctrl->map, RTMDIO_931X_SMI_GLB_CTRL1, mask, val); + + /* special polling registers */ + if (phyinfo.poll_duplex || phyinfo.poll_adv_1000 || phyinfo.poll_lpa_1000) { + regmap_write(ctrl->map, RTMDIO_931X_SMI_10GPHY_POLLING_SEL2, phyinfo.poll_duplex); + regmap_write(ctrl->map, RTMDIO_931X_SMI_10GPHY_POLLING_SEL3, phyinfo.poll_adv_1000); + regmap_write(ctrl->map, RTMDIO_931X_SMI_10GPHY_POLLING_SEL4, phyinfo.poll_lpa_1000); + } + } +} + +static int rtmdio_reset(struct mii_bus *bus) +{ + struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus); + + return ctrl->cfg->reset(bus); +} + +static int rtmdio_map_ports(struct device *dev) +{ + struct rtmdio_ctrl *ctrl = dev_get_drvdata(dev); + int smi_bus, smi_addr, addr; + + struct device_node *switch_node __free(device_node) = + of_get_child_by_name(dev->of_node->parent, "ethernet-switch"); + if (!switch_node) + return dev_err_probe(dev, -ENODEV, "%pfwP missing ethernet-switch\n", + of_fwnode_handle(dev->of_node->parent)); + + struct device_node *ports __free(device_node) = + of_get_child_by_name(switch_node, "ethernet-ports"); + if (!ports) + return dev_err_probe(dev, -ENODEV, "%pfwP missing ethernet-ports\n", + of_fwnode_handle(switch_node)); + + for_each_child_of_node_scoped(ports, port) { + if (of_property_read_u32(port, "reg", &addr)) + continue; + + struct device_node *phy __free(device_node) = + of_parse_phandle(port, "phy-handle", 0); + if (!phy) + continue; + + if (addr >= ctrl->cfg->num_phys) + return dev_err_probe(dev, -EINVAL, "%pfwP illegal port number\n", + of_fwnode_handle(port)); + + if (test_bit(addr, ctrl->valid_ports)) + return dev_err_probe(dev, -EINVAL, "%pfwP duplicated port number\n", + of_fwnode_handle(port)); + + if (of_property_read_u32(phy, "reg", &smi_addr)) + return dev_err_probe(dev, -EINVAL, "%pfwP no phy address\n", + of_fwnode_handle(phy)); + + /* relaxed check as RTL839x uses MDIO addresses 0..51 */ + if (smi_addr >= ctrl->cfg->num_phys) + return dev_err_probe(dev, -EINVAL, "%pfwP illegal phy address\n", + of_fwnode_handle(phy)); + + if (of_property_read_u32(phy->parent, "reg", &smi_bus)) + return dev_err_probe(dev, -EINVAL, "%pfwP no bus address\n", + of_fwnode_handle(phy->parent)); + + if (smi_bus >= RTMDIO_MAX_SMI_BUS) + return dev_err_probe(dev, -EINVAL, "%pfwP illegal bus number\n", + of_fwnode_handle(phy->parent)); + + if (of_device_is_compatible(phy, "ethernet-phy-ieee802.3-c45")) + ctrl->bus[smi_bus].is_c45 = true; + + ctrl->port[addr].smi_bus = smi_bus; + ctrl->port[addr].smi_addr = smi_addr; + ctrl->port[addr].dn = of_node_get(phy); + __set_bit(addr, ctrl->valid_ports); + } + + return 0; +} + +static int rtmdio_probe_one(struct device *dev, struct rtmdio_ctrl *ctrl) +{ + struct rtmdio_chan *chan; + struct mii_bus *bus; + int ret, addr; + + bus = devm_mdiobus_alloc_size(dev, sizeof(*chan)); + if (!bus) + return -ENOMEM; + + chan = bus->priv; + chan->ctrl = ctrl; + + bus->name = "Realtek MDIO bus"; + bus->reset = rtmdio_reset; + bus->read = rtmdio_read; + bus->write = rtmdio_write; + bus->read_c45 = rtmdio_read_c45; + bus->write_c45 = rtmdio_write_c45; + bus->parent = dev; + bus->phy_mask = ~0; + snprintf(bus->id, MII_BUS_ID_SIZE, "realtek-mdio"); + device_set_node(&bus->dev, of_fwnode_handle(dev->of_node)); + + ret = devm_mdiobus_register(dev, bus); + if (ret) + return dev_err_probe(dev, ret, "cannot register MDIO bus\n"); + + for_each_phy(ctrl, addr) { + if (!ret) + ret = fwnode_mdiobus_register_phy(bus, + of_fwnode_handle(ctrl->port[addr].dn), addr); + of_node_put(ctrl->port[addr].dn); + } + if (ret) + return ret; + + /* + * TODO: This polling setup needs to be relocated into rtmdio_probe(). It is a generic + * function and not bus specific. But this will require more rework of the data + * structures. For now it is easier to hand over the single bus that was just created. + */ + if (ctrl->cfg->setup_polling) + ctrl->cfg->setup_polling(bus); + + return 0; +} + +static int rtmdio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rtmdio_ctrl *ctrl; + int ret, addr; + + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + platform_set_drvdata(pdev, ctrl); + ctrl->cfg = (const struct rtmdio_config *)device_get_match_data(dev); + ctrl->map = syscon_node_to_regmap(pdev->dev.of_node->parent); + if (IS_ERR(ctrl->map)) + return PTR_ERR(ctrl->map); + + ret = rtmdio_map_ports(dev); + if (ret) { + for_each_phy(ctrl, addr) + of_node_put(ctrl->port[addr].dn); + return ret; + } + rtmdio_setup_smi_topology(ctrl); + + return rtmdio_probe_one(dev, ctrl); +} + +static const struct rtmdio_config rtmdio_838x_cfg = { + .num_phys = 28, + .raw_page = 4095, + .port_map_base = RTMDIO_838X_SMI_PORT0_5_ADDR_CTRL, + .read_mmd_phy = rtmdio_838x_read_mmd_phy, + .read_phy = rtmdio_838x_read_phy, + .reset = rtmdio_838x_reset, + .setup_polling = rtmdio_838x_setup_polling, + .write_mmd_phy = rtmdio_838x_write_mmd_phy, + .write_phy = rtmdio_838x_write_phy, +}; + +static const struct rtmdio_config rtmdio_839x_cfg = { + .num_phys = 52, + .raw_page = 8191, + .read_mmd_phy = rtmdio_839x_read_mmd_phy, + .read_phy = rtmdio_839x_read_phy, + .reset = rtmdio_839x_reset, + .write_mmd_phy = rtmdio_839x_write_mmd_phy, + .write_phy = rtmdio_839x_write_phy, +}; + +static const struct rtmdio_config rtmdio_930x_cfg = { + .num_phys = 28, + .raw_page = 4095, + .bus_map_base = RTMDIO_930X_SMI_PORT0_15_POLLING_SEL, + .port_map_base = RTMDIO_930X_SMI_PORT0_5_ADDR_CTRL, + .read_mmd_phy = rtmdio_930x_read_mmd_phy, + .read_phy = rtmdio_930x_read_phy, + .reset = rtmdio_930x_reset, + .setup_polling = rtmdio_930x_setup_polling, + .write_mmd_phy = rtmdio_930x_write_mmd_phy, + .write_phy = rtmdio_930x_write_phy, +}; + +static const struct rtmdio_config rtmdio_931x_cfg = { + .num_phys = 56, + .raw_page = 8191, + .bus_map_base = RTMDIO_931X_SMI_PORT_POLLING_SEL, + .port_map_base = RTMDIO_931X_SMI_PORT_ADDR_CTRL, + .read_mmd_phy = rtmdio_931x_read_mmd_phy, + .read_phy = rtmdio_931x_read_phy, + .reset = rtmdio_931x_reset, + .setup_polling = rtmdio_931x_setup_polling, + .write_mmd_phy = rtmdio_931x_write_mmd_phy, + .write_phy = rtmdio_931x_write_phy, +}; + +static const struct of_device_id rtmdio_ids[] = { + { + .compatible = "realtek,rtl8380-mdio", + .data = &rtmdio_838x_cfg, + }, + { + .compatible = "realtek,rtl8392-mdio", + .data = &rtmdio_839x_cfg, + }, + { + .compatible = "realtek,rtl9301-mdio", + .data = &rtmdio_930x_cfg, + }, + { + .compatible = "realtek,rtl9311-mdio", + .data = &rtmdio_931x_cfg, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtmdio_ids); + +static struct platform_driver rtmdio_driver = { + .probe = rtmdio_probe, + .driver = { + .name = "mdio-rtl-otto", + .of_match_table = rtmdio_ids, + }, +}; + +module_platform_driver(rtmdio_driver); + +MODULE_DESCRIPTION("RTL83xx/RTL93xx MDIO driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c new file mode 100644 index 0000000000..14ea03b1cd --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -0,0 +1,4281 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RTPCS_SDS_CNT 14 +#define RTPCS_PORT_CNT 57 +#define RTPCS_MAX_LINKS_PER_SDS 8 + +#define RTPCS_SPEED_10 0 +#define RTPCS_SPEED_100 1 +#define RTPCS_SPEED_1000 2 +#define RTPCS_SPEED_10000_LEGACY 3 +#define RTPCS_SPEED_10000 4 +#define RTPCS_SPEED_2500 5 +#define RTPCS_SPEED_5000 6 + +#define RTPCS_838X_CPU_PORT 28 +#define RTPCS_838X_SERDES_CNT 6 +#define RTPCS_838X_MAC_LINK_DUP_STS 0xa19c +#define RTPCS_838X_MAC_LINK_SPD_STS 0xa190 +#define RTPCS_838X_MAC_LINK_STS 0xa188 +#define RTPCS_838X_MAC_RX_PAUSE_STS 0xa1a4 +#define RTPCS_838X_MAC_TX_PAUSE_STS 0xa1a0 + +#define RTPCS_839X_CPU_PORT 52 +#define RTPCS_839X_SERDES_CNT 14 +#define RTPCS_839X_MAC_LINK_DUP_STS 0x03b0 +#define RTPCS_839X_MAC_LINK_SPD_STS 0x03a0 +#define RTPCS_839X_MAC_LINK_STS 0x0390 +#define RTPCS_839X_MAC_RX_PAUSE_STS 0x03c0 +#define RTPCS_839X_MAC_TX_PAUSE_STS 0x03b8 + +#define RTPCS_83XX_MAC_LINK_SPD_BITS 2 + +#define RTPCS_930X_CPU_PORT 28 +#define RTPCS_930X_SERDES_CNT 12 +#define RTPCS_930X_MAC_LINK_DUP_STS 0xcb28 +#define RTPCS_930X_MAC_LINK_SPD_STS 0xcb18 +#define RTPCS_930X_MAC_LINK_STS 0xcb10 +#define RTPCS_930X_MAC_RX_PAUSE_STS 0xcb30 +#define RTPCS_930X_MAC_TX_PAUSE_STS 0xcb2c + +#define RTPCS_931X_CPU_PORT 56 +#define RTPCS_931X_SERDES_CNT 14 +#define RTPCS_931X_MAC_LINK_DUP_STS 0x0ef0 +#define RTPCS_931X_MAC_LINK_SPD_STS 0x0ed0 +#define RTPCS_931X_MAC_LINK_STS 0x0ec0 +#define RTPCS_931X_MAC_RX_PAUSE_STS 0x0f00 +#define RTPCS_931X_MAC_TX_PAUSE_STS 0x0ef8 + +#define RTPCS_838X_SDS_CFG_REG 0x34 +#define RTPCS_838X_RST_GLB_CTRL_0 0x3c +#define RTPCS_838X_SDS_MODE_SEL 0x0028 +#define RTPCS_838X_INT_MODE_CTRL 0x005c +#define RTPCS_838X_PLL_CML_CTRL 0x0ff8 + +#define RTPCS_839X_MAC_SERDES_IF_CTRL 0x0008 + +#define RTPCS_93XX_MAC_LINK_SPD_BITS 4 + +#define RTPCS_93XX_MODEL_NAME_INFO (0x0004) +#define RTPCS_93XX_CHIP_INFO (0x0008) + +#define PHY_PAGE_2 2 +#define PHY_PAGE_4 4 + +#define RTL9300_PHY_ID_MASK 0xf0ffffff + +/* RTL930X SerDes supports the following modes: + * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100 + * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII + * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X + * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R + * 0x1b: 10GR1000BX_AUTO 0x1f: OFF + */ +#define RTPCS_930X_SDS_MODE_SGMII 0x02 +#define RTPCS_930X_SDS_MODE_1000BASEX 0x04 +#define RTPCS_930X_SDS_MODE_QSGMII 0x06 +#define RTPCS_930X_SDS_MODE_USXGMII 0x0d +#define RTPCS_930X_SDS_MODE_XSGMII 0x10 +#define RTPCS_930X_SDS_MODE_2500BASEX 0x16 +#define RTPCS_930X_SDS_MODE_10GBASER 0x1a +#define RTPCS_930X_SDS_OFF 0x1f +#define RTPCS_930X_SDS_MASK 0x1f + +/* RTL930X SerDes supports two submodes when mode is USXGMII: + * 0x00: USXGMII (aka USXGMII_SX) + * 0x02: 10G_QXGMII (aka USXGMII_QX) + */ +#define RTPCS_930X_SDS_SUBMODE_USXGMII_SX 0x0 +#define RTPCS_930X_SDS_SUBMODE_USXGMII_QX 0x2 + +/* Registers of the internal SerDes of the 9310 */ +#define RTPCS_931X_MAC_GROUP0_1_CTRL (0x13a4) +#define RTPCS_931X_MAC_GROUP2_3_CTRL (0x13a8) +#define RTPCS_931X_MAC_GROUP4_CTRL (0x13ac) +#define RTPCS_931X_MAC_GROUP5_CTRL (0x13b0) +#define RTPCS_931X_MAC_GROUP6_7_CTRL (0x13b4) +#define RTPCS_931X_MAC_GROUP8_11_CTRL (0x13b8) +#define RTL931X_SERDES_MODE_CTRL (0x13cc) +#define RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR (0x13F4) +#define RTL931X_MAC_SERDES_MODE_CTRL(sds) (0x136C + (((sds) << 2))) +#define RTPCS_931X_ISR_SERDES_RXIDLE (0x12f8) + +enum rtpcs_sds_mode { + RTPCS_SDS_MODE_OFF = 0, + + /* fiber modes */ + RTPCS_SDS_MODE_100BASEX, + RTPCS_SDS_MODE_1000BASEX, + RTPCS_SDS_MODE_2500BASEX, + RTPCS_SDS_MODE_10GBASER, + + /* mii modes */ + RTPCS_SDS_MODE_SGMII, + RTPCS_SDS_MODE_HISGMII, + RTPCS_SDS_MODE_QSGMII, + RTPCS_SDS_MODE_QHSGMII, + RTPCS_SDS_MODE_XSGMII, + + RTPCS_SDS_MODE_USXGMII_10GSXGMII, + RTPCS_SDS_MODE_USXGMII_10GDXGMII, + RTPCS_SDS_MODE_USXGMII_10GQXGMII, + RTPCS_SDS_MODE_USXGMII_5GSXGMII, + RTPCS_SDS_MODE_USXGMII_5GDXGMII, + RTPCS_SDS_MODE_USXGMII_2_5GSXGMII, +}; + +enum rtpcs_port_media { + RTPCS_PORT_MEDIA_NONE, + RTPCS_PORT_MEDIA_FIBER_100M, + RTPCS_PORT_MEDIA_FIBER_1G, + RTPCS_PORT_MEDIA_FIBER_2_5G, + RTPCS_PORT_MEDIA_FIBER_10G, + RTPCS_PORT_MEDIA_DAC_50CM, + RTPCS_PORT_MEDIA_DAC_100CM, + RTPCS_PORT_MEDIA_DAC_300CM, + RTPCS_PORT_MEDIA_DAC_500CM, +}; + +enum rtpcs_sds_pll_type { + RTPCS_SDS_PLL_TYPE_RING = 0, + RTPCS_SDS_PLL_TYPE_LC = 1, + RTPCS_SDS_PLL_TYPE_END, +}; + +enum rtpcs_sds_pll_speed { + RTPCS_SDS_PLL_SPD_1000 = 0, + RTPCS_SDS_PLL_SPD_2500 = 1, + RTPCS_SDS_PLL_SPD_10000 = 2, + RTPCS_SDS_PLL_SPD_END, +}; + +enum rtpcs_chip_version { + RTPCS_CHIP_V1 = 0, + RTPCS_CHIP_V2, +}; + +struct rtpcs_ctrl; +struct rtpcs_serdes; + +struct rtpcs_serdes_ops { + int (*read)(struct rtpcs_serdes *sds, int page, int regnum, int bithigh, int bitlow); + int (*write)(struct rtpcs_serdes *sds, int page, int regnum, int bithigh, int bitlow, + u16 value); + + /* optional */ + int (*xsg_write)(struct rtpcs_serdes *sds, int page, int regnum, int bithigh, int bitlow, + u16 value); + + int (*set_autoneg)(struct rtpcs_serdes *sds, unsigned int neg_mode, + const unsigned long *advertising); + void (*restart_autoneg)(struct rtpcs_serdes *sds); + + /* CMU management */ + int (*get_pll_select)(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type *pll); + int (*set_pll_select)(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode, + enum rtpcs_sds_pll_type pll); + int (*reset_cmu)(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll); + /* online reconfiguration of a running SerDes to another PLL */ + int (*reconfigure_to_pll)(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll); +}; + +struct rtpcs_sds_reg_field { + u8 page; + u8 reg; + u8 msb; + u8 lsb; +}; + +struct rtpcs_sds_regs { + struct rtpcs_sds_reg_field an_enable; + struct rtpcs_sds_reg_field an_restart; + struct rtpcs_sds_reg_field an_advertise; +}; + +struct rtpcs_serdes { + struct rtpcs_ctrl *ctrl; + const struct rtpcs_serdes_ops *ops; + const struct rtpcs_sds_regs *regs; + enum rtpcs_sds_mode hw_mode; + u8 id; + u8 num_of_links; + bool first_start; + + bool rx_pol_inv; + bool tx_pol_inv; +}; + +struct rtpcs_ctrl { + struct device *dev; + struct regmap *map; + struct mii_bus *bus; + const struct rtpcs_config *cfg; + struct rtpcs_serdes serdes[RTPCS_SDS_CNT]; + struct rtpcs_link *link[RTPCS_PORT_CNT]; + struct mutex lock; + + /* meaning and source may be family-specific */ + enum rtpcs_chip_version chip_version; +}; + +struct rtpcs_link { + struct rtpcs_ctrl *ctrl; + struct phylink_pcs pcs; + struct rtpcs_serdes *sds; + int port; +}; + +struct rtpcs_config { + int cpu_port; + int mac_link_dup_sts; + int mac_link_spd_bits; + int mac_link_spd_sts; + int mac_link_sts; + int mac_rx_pause_sts; + int mac_tx_pause_sts; + u8 serdes_count; + + const struct phylink_pcs_ops *pcs_ops; + const struct rtpcs_serdes_ops *sds_ops; + const struct rtpcs_sds_regs *sds_regs; + int (*init_serdes_common)(struct rtpcs_ctrl *ctrl); + int (*setup_serdes)(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode); +}; + +struct rtpcs_sds_config { + u8 page; + u8 reg; + u16 data; +}; + +static int rtpcs_sds_to_mmd(int sds_page, int sds_regnum) +{ + return (sds_page << 8) + sds_regnum; +} + +/* + * Basic helpers + * + * These work on the plain SerDes ID. They shouldn't be used except for + * implementing the SerDes read/write ops. + */ + +static int __rtpcs_sds_read_raw(struct rtpcs_ctrl *ctrl, int sds_id, int page, int regnum, + int bithigh, int bitlow) +{ + int mmd_regnum = rtpcs_sds_to_mmd(page, regnum); + u16 mask; + int val; + + if (WARN_ON(bithigh < bitlow)) + return -EINVAL; + + mask = GENMASK(bithigh, bitlow); + val = mdiobus_c45_read(ctrl->bus, sds_id, MDIO_MMD_VEND1, mmd_regnum); + if (val < 0) + return val; + + return (val & mask) >> bitlow; +} + +static int __rtpcs_sds_write_raw(struct rtpcs_ctrl *ctrl, int sds_id, int page, int regnum, + int bithigh, int bitlow, u16 value) +{ + int mmd_regnum = rtpcs_sds_to_mmd(page, regnum); + u16 mask, set; + + if (WARN_ON(bithigh < bitlow)) + return -EINVAL; + + if (bithigh == 15 && bitlow == 0) + return mdiobus_c45_write(ctrl->bus, sds_id, MDIO_MMD_VEND1, mmd_regnum, value); + + mask = GENMASK(bithigh, bitlow); + set = (value << bitlow) & mask; + return mdiobus_c45_modify(ctrl->bus, sds_id, MDIO_MMD_VEND1, mmd_regnum, mask, set); +} + +/* Generic implementations, if no special behavior is needed */ + +static int rtpcs_generic_sds_op_read(struct rtpcs_serdes *sds, int page, int regnum, int bithigh, + int bitlow) +{ + return __rtpcs_sds_read_raw(sds->ctrl, sds->id, page, regnum, bithigh, bitlow); +} + +static int rtpcs_generic_sds_op_write(struct rtpcs_serdes *sds, int page, int regnum, int bithigh, + int bitlow, u16 value) +{ + return __rtpcs_sds_write_raw(sds->ctrl, sds->id, page, regnum, bithigh, bitlow, value); +} + +/* Convenience helpers */ + +static int rtpcs_sds_read_bits(struct rtpcs_serdes *sds, int page, int regnum, int bithigh, + int bitlow) +{ + return sds->ops->read(sds, page, regnum, bithigh, bitlow); +} + +static int rtpcs_sds_write_bits(struct rtpcs_serdes *sds, int page, int regnum, int bithigh, + int bitlow, u16 value) +{ + return sds->ops->write(sds, page, regnum, bithigh, bitlow, value); +} + +static int rtpcs_sds_read(struct rtpcs_serdes *sds, int page, int regnum) +{ + return sds->ops->read(sds, page, regnum, 15, 0); +} + +static int rtpcs_sds_write(struct rtpcs_serdes *sds, int page, int regnum, u16 value) +{ + return sds->ops->write(sds, page, regnum, 15, 0, value); +} + +__maybe_unused +static int rtpcs_sds_read_field(struct rtpcs_serdes *sds, const struct rtpcs_sds_reg_field *field) +{ + return sds->ops->read(sds, field->page, field->reg, field->msb, field->lsb); +} + +static int rtpcs_sds_write_field(struct rtpcs_serdes *sds, const struct rtpcs_sds_reg_field *field, + u16 value) +{ + return sds->ops->write(sds, field->page, field->reg, field->msb, field->lsb, value); +} + +__maybe_unused +static int rtpcs_sds_xsg_write_bits(struct rtpcs_serdes *sds, int page, int regnum, int bithigh, + int bitlow, u16 value) +{ + if (!sds->ops->xsg_write) + return -ENOTSUPP; + + return sds->ops->xsg_write(sds, page, regnum, bithigh, bitlow, value); +} + +__maybe_unused +static int rtpcs_sds_xsg_write(struct rtpcs_serdes *sds, int page, int regnum, u16 value) +{ + if (!sds->ops->xsg_write) + return -ENOTSUPP; + + return sds->ops->xsg_write(sds, page, regnum, 15, 0, value); +} + +/* Other helpers */ + +__maybe_unused +static int rtpcs_sds_modify(struct rtpcs_serdes *sds, int page, int regnum, + u16 mask, u16 set) +{ + int mmd_regnum = rtpcs_sds_to_mmd(page, regnum); + + return mdiobus_c45_modify(sds->ctrl->bus, sds->id, MDIO_MMD_VEND1, + mmd_regnum, mask, set); +} + +static struct rtpcs_serdes *rtpcs_sds_get_even(struct rtpcs_serdes *sds) +{ + u32 even_sds = sds->id & ~1; + return &sds->ctrl->serdes[even_sds]; +} + +static struct rtpcs_serdes *rtpcs_sds_get_odd(struct rtpcs_serdes *sds) +{ + u32 odd_sds = sds->id | 1; + return &sds->ctrl->serdes[odd_sds]; +} + +static struct rtpcs_serdes *rtpcs_sds_get_neighbor(struct rtpcs_serdes *sds) +{ + u32 nb_sds = sds->id ^ 1; + return &sds->ctrl->serdes[nb_sds]; +} + +static int rtpcs_regmap_read_bits(struct rtpcs_ctrl *ctrl, int base, int bithigh, int bitlow) +{ + int offset = base + (bitlow / 32) * 4; + int bits = bithigh + 1 - bitlow; + int shift = bitlow % 32; + int value; + + regmap_read(ctrl->map, offset, &value); + value = (value >> shift) & (BIT(bits) - 1); + + return value; +} + +static struct rtpcs_link *rtpcs_phylink_pcs_to_link(struct phylink_pcs *pcs) +{ + return container_of(pcs, struct rtpcs_link, pcs); +} + +static int rtpcs_sds_determine_hw_mode(struct rtpcs_serdes *sds, + phy_interface_t if_mode, + enum rtpcs_sds_mode *hw_mode) +{ + u8 n_links = sds->num_of_links; + + /* turn off SerDes when there are no links */ + if (!n_links) { + *hw_mode = RTPCS_SDS_MODE_OFF; + return 0; + } + + switch (if_mode) { + case PHY_INTERFACE_MODE_NA: + *hw_mode = RTPCS_SDS_MODE_OFF; + break; + case PHY_INTERFACE_MODE_100BASEX: + *hw_mode = RTPCS_SDS_MODE_100BASEX; + break; + case PHY_INTERFACE_MODE_1000BASEX: + *hw_mode = RTPCS_SDS_MODE_1000BASEX; + break; + case PHY_INTERFACE_MODE_2500BASEX: + *hw_mode = RTPCS_SDS_MODE_2500BASEX; + break; + case PHY_INTERFACE_MODE_10GBASER: + *hw_mode = RTPCS_SDS_MODE_10GBASER; + break; + case PHY_INTERFACE_MODE_SGMII: + *hw_mode = RTPCS_SDS_MODE_SGMII; + break; + case PHY_INTERFACE_MODE_QSGMII: + *hw_mode = RTPCS_SDS_MODE_QSGMII; + break; + case PHY_INTERFACE_MODE_USXGMII: + if (n_links == 1) + *hw_mode = RTPCS_SDS_MODE_USXGMII_10GSXGMII; + else if (n_links == 2) + *hw_mode = RTPCS_SDS_MODE_USXGMII_10GDXGMII; + else if (n_links <= 4) + *hw_mode = RTPCS_SDS_MODE_USXGMII_10GQXGMII; + else if (n_links <= 8) + *hw_mode = RTPCS_SDS_MODE_XSGMII; + + break; + case PHY_INTERFACE_MODE_10G_QXGMII: + *hw_mode = RTPCS_SDS_MODE_USXGMII_10GQXGMII; + break; + default: + return -ENOTSUPP; + } + + /* TODO: check if the particular SerDes supports the mode */ + + return 0; +} + +/* Generic auto-negotiation config */ + +static int rtpcs_generic_sds_set_autoneg(struct rtpcs_serdes *sds, unsigned int neg_mode, + const unsigned long *advertising) +{ + u16 bmcr, adv, adv_old; + bool changed = false; + int ret; + + if ((sds->hw_mode == RTPCS_SDS_MODE_1000BASEX) || + (sds->hw_mode == RTPCS_SDS_MODE_2500BASEX)) { + adv = ADVERTISE_1000XFULL; + if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, + advertising)) + adv |= ADVERTISE_1000XPAUSE; + if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, + advertising)) + adv |= ADVERTISE_1000XPSE_ASYM; + + adv_old = rtpcs_sds_read_field(sds, &sds->regs->an_advertise); + if (adv_old < 0) + return adv_old; + + if (adv != adv_old) { + changed = true; + ret = rtpcs_sds_write_field(sds, &sds->regs->an_advertise, adv); + if (ret < 0) + return ret; + } + } + + bmcr = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ? 1 : 0; + + ret = rtpcs_sds_write_field(sds, &sds->regs->an_enable, bmcr); + if (ret < 0) + return ret; + + return changed; +} + +static void rtpcs_generic_sds_restart_autoneg(struct rtpcs_serdes *sds) +{ + rtpcs_sds_write_field(sds, &sds->regs->an_restart, 0x1); +} + +static int rtpcs_sds_select_pll_speed(enum rtpcs_sds_mode hw_mode, enum rtpcs_sds_pll_speed *speed) +{ + switch (hw_mode) { + case RTPCS_SDS_MODE_1000BASEX: + case RTPCS_SDS_MODE_SGMII: + case RTPCS_SDS_MODE_QSGMII: + *speed = RTPCS_SDS_PLL_SPD_1000; + break; + case RTPCS_SDS_MODE_2500BASEX: + *speed = RTPCS_SDS_PLL_SPD_2500; + break; + case RTPCS_SDS_MODE_10GBASER: + case RTPCS_SDS_MODE_XSGMII: + case RTPCS_SDS_MODE_USXGMII_10GSXGMII: + case RTPCS_SDS_MODE_USXGMII_10GDXGMII: + case RTPCS_SDS_MODE_USXGMII_10GQXGMII: + case RTPCS_SDS_MODE_USXGMII_5GSXGMII: + case RTPCS_SDS_MODE_USXGMII_5GDXGMII: + case RTPCS_SDS_MODE_USXGMII_2_5GSXGMII: + *speed = RTPCS_SDS_PLL_SPD_10000; + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +static int rtpcs_sds_apply_config(struct rtpcs_serdes *sds, + const struct rtpcs_sds_config *config, size_t count) +{ + int ret; + + for (size_t i = 0; i < count; i++) { + ret = rtpcs_sds_write(sds, config[i].page, config[i].reg, config[i].data); + if (ret) + return ret; + } + return 0; +} + +static int rtpcs_sds_apply_config_xsg(struct rtpcs_serdes *sds, + const struct rtpcs_sds_config *config, size_t count) +{ + int ret; + + for (size_t i = 0; i < count; i++) { + ret = rtpcs_sds_xsg_write(sds, config[i].page, config[i].reg, config[i].data); + if (ret) + return ret; + } + return 0; +} + +/* Variant-specific functions */ + +/* RTL838X */ + +#define SDS(ctrl,n) (&(ctrl)->serdes[n]) + +static void rtpcs_838x_sds_patch_01_qsgmii_6275b(struct rtpcs_ctrl *ctrl) +{ + /* CKREFBUF_S0S1 for QSGMII */ + regmap_write_bits(ctrl->map, RTPCS_838X_PLL_CML_CTRL, 0xf, 0xf); + + rtpcs_sds_write(SDS(ctrl, 0), 1, 3, 0xf46f); + rtpcs_sds_write(SDS(ctrl, 0), 1, 2, 0x85fa); + rtpcs_sds_write(SDS(ctrl, 1), 1, 2, 0x85fa); + rtpcs_sds_write(SDS(ctrl, 0), 1, 6, 0x20d8); + rtpcs_sds_write(SDS(ctrl, 1), 1, 6, 0x20d8); + rtpcs_sds_write(SDS(ctrl, 0), 1, 17, 0xb7c9); + rtpcs_sds_write(SDS(ctrl, 1), 1, 11, 0x482); + rtpcs_sds_write(SDS(ctrl, 1), 1, 10, 0x80c7); + rtpcs_sds_write(SDS(ctrl, 0), 1, 18, 0xab8e); + rtpcs_sds_write(SDS(ctrl, 0), 1, 11, 0x482); + rtpcs_sds_write(SDS(ctrl, 0), 1, 19, 0x24ab); + rtpcs_sds_write(SDS(ctrl, 1), 1, 17, 0x4208); + rtpcs_sds_write(SDS(ctrl, 1), 1, 18, 0xc208); + rtpcs_sds_write(SDS(ctrl, 0), 2, 25, 0x303); + rtpcs_sds_write(SDS(ctrl, 1), 2, 25, 0x303); + rtpcs_sds_write(SDS(ctrl, 0), 1, 14, 0xfcc2); + rtpcs_sds_write(SDS(ctrl, 1), 1, 14, 0xfcc2); + + rtpcs_sds_write(SDS(ctrl, 0), 1, 9, 0x8e64); + rtpcs_sds_write(SDS(ctrl, 0), 1, 9, 0x8c64); + + rtpcs_sds_write(SDS(ctrl, 1), 1, 9, 0x8e64); + rtpcs_sds_write(SDS(ctrl, 1), 1, 9, 0x8c64); +} + +static void rtpcs_838x_sds_patch_23_qsgmii_6275b(struct rtpcs_ctrl *ctrl) +{ + rtpcs_sds_write(SDS(ctrl, 2), 1, 3, 0xf46d); + rtpcs_sds_write(SDS(ctrl, 2), 1, 2, 0x85fa); + rtpcs_sds_write(SDS(ctrl, 3), 1, 2, 0x85fa); + rtpcs_sds_write(SDS(ctrl, 2), 1, 6, 0x20d8); + rtpcs_sds_write(SDS(ctrl, 3), 1, 6, 0x20d8); + rtpcs_sds_write(SDS(ctrl, 2), 1, 17, 0xb7c9); + rtpcs_sds_write(SDS(ctrl, 2), 1, 18, 0xab8e); + rtpcs_sds_write(SDS(ctrl, 2), 1, 11, 0x482); + rtpcs_sds_write(SDS(ctrl, 3), 1, 11, 0x482); + rtpcs_sds_write(SDS(ctrl, 2), 1, 19, 0x24ab); + rtpcs_sds_write(SDS(ctrl, 3), 1, 17, 0x4208); + rtpcs_sds_write(SDS(ctrl, 3), 1, 18, 0xc208); + rtpcs_sds_write(SDS(ctrl, 2), 2, 25, 0x303); + rtpcs_sds_write(SDS(ctrl, 3), 2, 25, 0x303); + rtpcs_sds_write(SDS(ctrl, 2), 1, 14, 0xfcc2); + rtpcs_sds_write(SDS(ctrl, 3), 1, 14, 0xfcc2); + + rtpcs_sds_write(SDS(ctrl, 2), 1, 9, 0x8e64); + rtpcs_sds_write(SDS(ctrl, 2), 1, 9, 0x8c64); + + rtpcs_sds_write(SDS(ctrl, 3), 1, 9, 0x8e64); + rtpcs_sds_write(SDS(ctrl, 3), 1, 9, 0x8c64); +} + +static void rtpcs_838x_sds_patch_4_fiber_6275b(struct rtpcs_ctrl *ctrl) +{ + rtpcs_sds_write(SDS(ctrl, 4), 1, 2, 0x85fa); + rtpcs_sds_write(SDS(ctrl, 4), 1, 11, 0x1482); + rtpcs_sds_write(SDS(ctrl, 4), 1, 6, 0x20d8); + rtpcs_sds_write(SDS(ctrl, 4), 1, 10, 0xc3); + rtpcs_sds_write(SDS(ctrl, 4), 1, 17, 0xb7c9); + rtpcs_sds_write(SDS(ctrl, 4), 1, 18, 0xab8e); + rtpcs_sds_write(SDS(ctrl, 4), 2, 25, 0x303); + rtpcs_sds_write(SDS(ctrl, 4), 1, 14, 0xfcc2); + + rtpcs_sds_write(SDS(ctrl, 4), 1, 9, 0x8e64); + rtpcs_sds_write(SDS(ctrl, 4), 1, 9, 0x8c64); +} + +static void rtpcs_838x_sds_patch_4_qsgmii_6275b(struct rtpcs_ctrl *ctrl) +{ + rtpcs_sds_write(SDS(ctrl, 4), 1, 3, 0xf46d); + rtpcs_sds_write(SDS(ctrl, 4), 1, 2, 0x85fa); + rtpcs_sds_write(SDS(ctrl, 4), 1, 11, 0x0482); + rtpcs_sds_write(SDS(ctrl, 4), 1, 6, 0x20d8); + rtpcs_sds_write(SDS(ctrl, 4), 1, 10, 0x58c7); + rtpcs_sds_write(SDS(ctrl, 4), 1, 17, 0xb7c9); + rtpcs_sds_write(SDS(ctrl, 4), 1, 18, 0xab8e); + rtpcs_sds_write(SDS(ctrl, 4), 2, 25, 0x303); + rtpcs_sds_write(SDS(ctrl, 4), 1, 14, 0xfcc2); + + rtpcs_sds_write(SDS(ctrl, 4), 1, 9, 0x8e64); + rtpcs_sds_write(SDS(ctrl, 4), 1, 9, 0x8c64); +} + +static void rtpcs_838x_sds_patch_5_fiber_6275b(struct rtpcs_ctrl *ctrl) +{ + rtpcs_sds_write(SDS(ctrl, 5), 1, 2, 0x85fa); + rtpcs_sds_write(SDS(ctrl, 5), 1, 3, 0x00); + rtpcs_sds_write(SDS(ctrl, 5), 1, 4, 0xdccc); + rtpcs_sds_write(SDS(ctrl, 5), 1, 5, 0x00); + rtpcs_sds_write(SDS(ctrl, 5), 1, 6, 0x3600); + rtpcs_sds_write(SDS(ctrl, 5), 1, 7, 0x03); + rtpcs_sds_write(SDS(ctrl, 5), 1, 8, 0x79aa); + rtpcs_sds_write(SDS(ctrl, 5), 1, 9, 0x8c64); + rtpcs_sds_write(SDS(ctrl, 5), 1, 10, 0xc3); + rtpcs_sds_write(SDS(ctrl, 5), 1, 11, 0x1482); + rtpcs_sds_write(SDS(ctrl, 5), 2, 24, 0x14aa); + rtpcs_sds_write(SDS(ctrl, 5), 2, 25, 0x303); + rtpcs_sds_write(SDS(ctrl, 5), 1, 14, 0xf002); + rtpcs_sds_write(SDS(ctrl, 5), 2, 27, 0x4bf); + + rtpcs_sds_write(SDS(ctrl, 5), 1, 9, 0x8e64); + rtpcs_sds_write(SDS(ctrl, 5), 1, 9, 0x8c64); +} + +static void rtpcs_838x_sds_reset(struct rtpcs_serdes *sds) +{ + rtpcs_sds_write_bits(sds, 2, 0, 11, 11, 0x0); /* FIB_REG0 CFG_FIB_PDOWN */ + + /* analog reset */ + rtpcs_sds_write_bits(sds, 0, 0, 1, 0, 0x0); /* REG0 EN_RX/EN_TX */ + rtpcs_sds_write_bits(sds, 0, 0, 1, 0, 0x3); /* REG0 EN_RX/EN_TX */ + + /* digital reset */ + rtpcs_sds_write_bits(sds, 0, 3, 6, 6, 0x1); /* REG3 SOFT_RST */ + rtpcs_sds_write_bits(sds, 0, 3, 6, 6, 0x0); /* REG3 SOFT_RST */ + + dev_info(sds->ctrl->dev, "SerDes %d reset\n", sds->id); +} + +static bool rtpcs_838x_sds_is_hw_mode_supported(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + switch (sds->id) { + case 0 ... 3: + return hw_mode == RTPCS_SDS_MODE_QSGMII; + case 4: + return hw_mode == RTPCS_SDS_MODE_QSGMII || + hw_mode == RTPCS_SDS_MODE_SGMII || + hw_mode == RTPCS_SDS_MODE_1000BASEX; + case 5: + return hw_mode == RTPCS_SDS_MODE_SGMII || + hw_mode == RTPCS_SDS_MODE_1000BASEX; + default: + return false; + } +} + +static int rtpcs_838x_sds_power(struct rtpcs_serdes *sds, bool power_on) +{ + u8 sds_id = sds->id; + int ret; + u8 val; + + val = power_on ? 0 : BIT(sds_id); + + ret = regmap_write_bits(sds->ctrl->map, RTPCS_838X_SDS_CFG_REG, BIT(sds_id), val); + if (ret) + return ret; + + if (sds_id >= 4) + ret = regmap_write_bits(sds->ctrl->map, RTPCS_838X_SDS_CFG_REG, + BIT(sds_id) << 2, val << 2); /* SDS*_PHY_MODE */ + + return ret; +} + +static int rtpcs_838x_sds_set_mode(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + u8 sds_mode_shift, int_mode_shift; + u32 sds_mode_val, int_mode_val; + + switch (hw_mode) { + case RTPCS_SDS_MODE_1000BASEX: + sds_mode_val = 0x4; + int_mode_val = 0x1; + break; + case RTPCS_SDS_MODE_SGMII: + sds_mode_val = 0x2; + int_mode_val = 0x2; + break; + case RTPCS_SDS_MODE_QSGMII: + sds_mode_val = 0x6; + int_mode_val = 0x5; + break; + default: + return -EINVAL; + } + + /* Configure SerDes module mode (all SDS 0-5) */ + sds_mode_shift = (5 - sds->id) * 5; + regmap_write_bits(sds->ctrl->map, RTPCS_838X_SDS_MODE_SEL, + 0x1f << sds_mode_shift, sds_mode_val << sds_mode_shift); + + /* Configure MAC interface mode (only SDS 4-5) */ + if (sds->id >= 4) { + int_mode_shift = (sds->id == 5) ? 3 : 0; + regmap_write_bits(sds->ctrl->map, RTPCS_838X_INT_MODE_CTRL, + 0x7 << int_mode_shift, int_mode_val << int_mode_shift); + } + + return 0; +} + +static int rtpcs_838x_sds_patch(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + struct rtpcs_ctrl *ctrl = sds->ctrl; + u8 sds_id = sds->id; + + rtpcs_sds_write(sds, 0, 1, 0xf00); + mdelay(1); + rtpcs_sds_write(sds, 0, 2, 0x7060); + mdelay(1); + + if (sds_id >= 4) { + rtpcs_sds_write(sds, 2, 30, 0x71e); + mdelay(1); + rtpcs_sds_write(sds, 0, 4, 0x74d); + mdelay(1); + } + + switch (hw_mode) { + case RTPCS_SDS_MODE_1000BASEX: + if (sds_id == 4) + rtpcs_838x_sds_patch_4_fiber_6275b(ctrl); + else if (sds_id == 5) + rtpcs_838x_sds_patch_5_fiber_6275b(ctrl); + + break; + case RTPCS_SDS_MODE_QSGMII: + if (sds_id == 0 || sds_id == 1) + rtpcs_838x_sds_patch_01_qsgmii_6275b(ctrl); + else if (sds_id == 2 || sds_id == 3) + rtpcs_838x_sds_patch_23_qsgmii_6275b(ctrl); + else if (sds_id == 4) + rtpcs_838x_sds_patch_4_qsgmii_6275b(ctrl); + + break; + default: + break; + } + + return 0; +} + +static int rtpcs_838x_init_serdes_common(struct rtpcs_ctrl *ctrl) +{ + dev_dbg(ctrl->dev, "Init RTL838X SerDes common\n"); + + /* power off and reset all SerDes */ + regmap_write(ctrl->map, RTPCS_838X_SDS_CFG_REG, 0x3f); + regmap_write(ctrl->map, RTPCS_838X_RST_GLB_CTRL_0, 0x10); /* SW_SERDES_RST */ + return 0; +} + +static int rtpcs_838x_setup_serdes(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + int ret; + + if (!rtpcs_838x_sds_is_hw_mode_supported(sds, hw_mode)) + return -ENOTSUPP; + + rtpcs_838x_sds_power(sds, false); + + /* take reset */ + rtpcs_sds_write(sds, 0x0, 0x0, 0xc00); + rtpcs_sds_write(sds, 0x0, 0x3, 0x7146); + + ret = rtpcs_838x_sds_set_mode(sds, hw_mode); + if (ret) + return ret; + + sds->hw_mode = hw_mode; + + rtpcs_838x_sds_patch(sds, hw_mode); + rtpcs_838x_sds_reset(sds); + + /* release reset */ + rtpcs_sds_write(sds, 0, 3, 0x7106); + + rtpcs_838x_sds_power(sds, true); + + /* + * Run a switch queue reset after the first start of a SerDes. This recovers ports that + * were already connected during boot and will not pass traffic. Sometimes the bug can + * be seen in registers INGR_DBG_REG0-INGR_DBG_REG2 but this is quite erratic. The SDK + * seems to have no issues because it starts all SerDes then PHYs and runs a queue reset + * finally during NIC start. + * + * Of course this is totally wrong here and should be part of the DSA driver. But + * implementing it over there requires more tricks than this (e.g. delayed work). + */ + if (sds->first_start) + regmap_write(sds->ctrl->map, RTPCS_838X_RST_GLB_CTRL_0, 0x4); + + return 0; +} + +/* RTL839X */ + +static void rtpcs_839x_sds_reset(struct rtpcs_serdes *sds) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + struct rtpcs_serdes *odd_sds = rtpcs_sds_get_odd(sds); + + bool is_10g_sds = (sds->id == 8 || sds->id == 9 || sds->id == 12 || + sds->id == 13); + + /* FIXME: The reset sequence seems to break some of the 5G SerDes + * though the SDK is calling it for all SerDes during init. Until + * this is solved, skip reset. + */ + if (!is_10g_sds) + return; + + if (is_10g_sds) { + rtpcs_sds_write_bits(odd_sds, 0xb, 0x1d, 3, 0, 0x5); + msleep(500); + rtpcs_sds_write_bits(odd_sds, 0xb, 0x1d, 3, 0, 0xf); + rtpcs_sds_write_bits(odd_sds, 0xb, 0x1d, 3, 0, 0x0); + + rtpcs_sds_write_bits(even_sds, 0xa, 0x10, 3, 3, 0x0); + rtpcs_sds_write_bits(even_sds, 0xb, 0x0, 15, 15, 0x1); + msleep(100); + rtpcs_sds_write_bits(even_sds, 0xb, 0x0, 15, 15, 0x0); + } else { + rtpcs_sds_write(odd_sds, 0x9, 0x1, 0x0050); + rtpcs_sds_write(odd_sds, 0x9, 0x1, 0x00f0); + rtpcs_sds_write(odd_sds, 0x9, 0x1, 0x0000); + + rtpcs_sds_write_bits(sds, 0x8, 0x14, 0, 0, 0x0); + rtpcs_sds_write_bits(sds, 0x8, 0x14, 9, 9, 0x1); + msleep(100); + rtpcs_sds_write_bits(sds, 0x8, 0x14, 9, 9, 0x0); + } + + rtpcs_sds_write(even_sds, 0x0, 0x3, 0x7146); + msleep(100); + rtpcs_sds_write(even_sds, 0x0, 0x3, 0x7106); + + rtpcs_sds_write(odd_sds, 0x0, 0x3, 0x7146); + msleep(100); + rtpcs_sds_write(odd_sds, 0x0, 0x3, 0x7106); +} + +static int rtpcs_839x_sds_set_mode(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + u32 mode_val, reg, shift; + + switch (hw_mode) { + case RTPCS_SDS_MODE_OFF: + mode_val = 0x0; + break; +/* + case RTPCS_SDS_MODE_100BASEX: + mode_val = 0x8; + break; + case RTPCS_SDS_MODE_1000BASEX: + case RTPCS_SDS_MODE_SGMII: + mode_val = 0x7; + break; +*/ + case RTPCS_SDS_MODE_QSGMII: + mode_val = 0x6; + break; + default: + return -ENOTSUPP; + } + + reg = RTPCS_839X_MAC_SERDES_IF_CTRL + (sds->id / 8) * 4; + shift = (sds->id % 8) * 4; + return regmap_write_bits(sds->ctrl->map, reg, 0xf << shift, + mode_val << shift); +} + +static void rtpcs_839x_sds_init(struct rtpcs_serdes *sds) +{ + bool is_even = sds->id % 2 == 0; + + /* + * This function is quite "mystic". It has been taken over from the vendor SDK function + * rtl839x_serdes_patch_init(). There is not much documentation about it but one could + * lookup the fields from the field headers. The 5G SerDes seem to work out of the box + * so only setup the 10G SerDes for now. + */ + if (sds->id != 8 && sds->id != 9 && sds->id != 12 && sds->id != 13) + return; + + /* Part 1: register setup */ + rtpcs_sds_write(sds, 0xa, 0x0, 0x5800); + rtpcs_sds_write(sds, 0xa, 0x1, 0x4000); + rtpcs_sds_write(sds, 0xa, 0x2, is_even ? 0x5400 : 0x5000); + rtpcs_sds_write(sds, 0xa, 0x3, 0x0000); + rtpcs_sds_write(sds, 0xa, 0x4, 0x0000); + rtpcs_sds_write(sds, 0xa, 0x5, 0x4000); + rtpcs_sds_write(sds, 0xa, 0x6, 0x4000); + rtpcs_sds_write(sds, 0xa, 0x7, 0xffff); + rtpcs_sds_write(sds, 0xa, 0x8, 0xffff); + rtpcs_sds_write(sds, 0xa, 0x9, 0x806f); + rtpcs_sds_write(sds, 0xa, 0xa, 0x0004); + rtpcs_sds_write(sds, 0xa, 0xb, 0x0000); + rtpcs_sds_write(sds, 0xa, 0xc, 0x0000); + rtpcs_sds_write(sds, 0xa, 0xd, 0x0000); + rtpcs_sds_write(sds, 0xa, 0xe, 0x0a00); + rtpcs_sds_write(sds, 0xa, 0xf, 0x2000); + rtpcs_sds_write(sds, 0xa, 0x10, 0xf00e); + rtpcs_sds_write(sds, 0xa, 0x11, is_even ? 0xf04a : 0xfdab); + rtpcs_sds_write(sds, 0xa, 0x12, is_even ? 0x97b3 : 0x96ea); + rtpcs_sds_write(sds, 0xa, 0x13, 0x5318); + rtpcs_sds_write(sds, 0xa, 0x14, 0x0f03); + rtpcs_sds_write(sds, 0xa, 0x15, 0x0000); + rtpcs_sds_write(sds, 0xa, 0x16, 0x0000); + rtpcs_sds_write(sds, 0xa, 0x17, 0x0000); + rtpcs_sds_write(sds, 0xa, 0x18, 0x0000); + rtpcs_sds_write(sds, 0xa, 0x19, 0x0000); + rtpcs_sds_write(sds, 0xa, 0x1a, 0xffff); + rtpcs_sds_write(sds, 0xa, 0x1b, 0x0000); + rtpcs_sds_write(sds, 0xa, 0x1c, 0x1203); + rtpcs_sds_write(sds, 0xa, 0x1d, 0x0000); + rtpcs_sds_write(sds, 0xa, 0x1e, 0xa052); + rtpcs_sds_write(sds, 0xa, 0x1f, 0x9a00); + rtpcs_sds_write(sds, 0xb, 0x0, 0x00f5); + rtpcs_sds_write(sds, 0xb, 0x1, 0xf000); + rtpcs_sds_write(sds, 0xb, 0x2, is_even ? 0x41ff : 0x4079); + rtpcs_sds_write(sds, 0xb, 0x3, 0x0000); + rtpcs_sds_write(sds, 0xb, 0x4, is_even ? 0x39ff : 0x93fa); + rtpcs_sds_write(sds, 0xb, 0x5, 0x3340); + rtpcs_sds_write(sds, 0xb, 0x6, is_even ? 0x40aa : 0x4280); + rtpcs_sds_write(sds, 0xb, 0x7, 0x0000); + rtpcs_sds_write(sds, 0xb, 0x8, 0x801f); + rtpcs_sds_write(sds, 0xb, 0x9, 0x0000); + rtpcs_sds_write(sds, 0xb, 0xa, 0x619c); + rtpcs_sds_write(sds, 0xb, 0xb, 0xffed); + rtpcs_sds_write(sds, 0xb, 0xc, 0x29ff); + rtpcs_sds_write(sds, 0xb, 0xd, 0x29ff); + rtpcs_sds_write(sds, 0xb, 0xe, is_even ? 0x4e10 : 0x4c50); + rtpcs_sds_write(sds, 0xb, 0xf, is_even ? 0x4e10 : 0x4c50); + rtpcs_sds_write(sds, 0xb, 0x10, 0x0000); + rtpcs_sds_write(sds, 0xb, 0x11, 0x0000); + rtpcs_sds_write(sds, 0x0, 0xc, 0x08ec); + if (!is_even) + rtpcs_sds_write(sds, 0xb, 0x1f, 0x003f); + + /* Part 2: register bit patching (contains some "reset flips") */ + rtpcs_sds_write_bits(sds, 0x0, 0x7, 14, 14, 0x0001); + rtpcs_sds_write_bits(sds, 0xb, 0x9, 15, 0, 0x417f); + rtpcs_sds_write_bits(sds, 0xa, 0x1c, 9, 9, 0x0000); + rtpcs_sds_write_bits(sds, 0xa, 0x1c, 12, 10, 0x0000); + rtpcs_sds_write_bits(sds, 0xa, 0x1c, 5, 3, 0x0005); + rtpcs_sds_write_bits(sds, 0xa, 0x1c, 8, 6, 0x0000); + rtpcs_sds_write_bits(sds, 0xa, 0x1c, 2, 0, 0x0002); + rtpcs_sds_write_bits(sds, 0xb, 0x1, 15, 0, 0xc440); + if (is_even) + rtpcs_sds_write_bits(sds, 0xb, 0x6, 3, 3, 0x0000); + rtpcs_sds_write_bits(sds, 0xa, 0x5, 15, 0, 0x8000); + rtpcs_sds_write_bits(sds, 0xa, 0x6, 15, 0, 0x8000); + rtpcs_sds_write_bits(sds, 0xa, 0xa, 15, 0, 0x0000); + rtpcs_sds_write_bits(sds, 0xa, 0x1e, 15, 0, 0x0002); + rtpcs_sds_write_bits(sds, 0xa, 0x1f, 15, 0, 0xbe00); + if (is_even) { + rtpcs_sds_write_bits(sds, 0xb, 0xe, 10, 10, 0x0000); + rtpcs_sds_write_bits(sds, 0xb, 0xf, 10, 10, 0x0000); + rtpcs_sds_write_bits(sds, 0xb, 0xe, 14, 14, 0x0000); + rtpcs_sds_write_bits(sds, 0xb, 0xf, 14, 14, 0x0000); + } + rtpcs_sds_write_bits(sds, 0xa, 0x10, 5, 5, 0x0000); + rtpcs_sds_write_bits(sds, 0xb, 0x9, 8, 8, 0x0000); + rtpcs_sds_write_bits(sds, 0xa, 0x3, 15, 12, 0x000f); + rtpcs_sds_write_bits(sds, 0xa, 0x1f, 13, 12, 0x0003); + rtpcs_sds_write_bits(sds, 0xa, 0x1f, 11, 9, 0x0007); + rtpcs_sds_write_bits(sds, 0xb, 0x1, 15, 15, 0x0001); + rtpcs_sds_write_bits(sds, 0xb, 0x1, 14, 14, 0x0001); + rtpcs_sds_write_bits(sds, 0xb, 0x1, 13, 13, 0x0000); + rtpcs_sds_write_bits(sds, 0xb, 0x1, 12, 12, 0x0000); + rtpcs_sds_write_bits(sds, 0xb, 0x1, 11, 9, 0x0002); + rtpcs_sds_write_bits(sds, 0xb, 0x1, 8, 6, 0x0002); + rtpcs_sds_write_bits(sds, 0xb, 0x1, 5, 3, 0x0000); + rtpcs_sds_write_bits(sds, 0xb, 0x1, 2, 0, 0x0000); + rtpcs_sds_write_bits(sds, 0xb, 0xc, 9, 9, 0x0001); + rtpcs_sds_write_bits(sds, 0xb, 0xd, 9, 9, 0x0001); + rtpcs_sds_write_bits(sds, 0xb, 0x8, 5, 5, 0x0001); + rtpcs_sds_write_bits(sds, 0xb, 0x8, 6, 6, 0x0000); + rtpcs_sds_write_bits(sds, 0xa, 0x1c, 15, 15, 0x0000); + rtpcs_sds_write_bits(sds, 0xa, 0x10, 15, 12, 0x0000); + rtpcs_sds_write_bits(sds, 0xa, 0x13, 4, 4, 0x0000); + rtpcs_sds_write_bits(sds, 0xa, 0x13, 9, 9, 0x0000); + rtpcs_sds_write_bits(sds, 0xa, 0x13, 3, 0, 0x0008); + rtpcs_sds_write_bits(sds, 0xa, 0x13, 8, 5, 0x0008); +} + +static int rtpcs_839x_init_serdes_common(struct rtpcs_ctrl *ctrl) +{ + for (int sds_id = 0; sds_id < ctrl->cfg->serdes_count; sds_id++) + rtpcs_839x_sds_init(&ctrl->serdes[sds_id]); + + for (int sds_id = 0; sds_id < ctrl->cfg->serdes_count; sds_id++) + rtpcs_839x_sds_reset(&ctrl->serdes[sds_id]); + + return 0; +} + +static int rtpcs_839x_setup_serdes(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + int ret; + + /* Don't touch 5G SerDes, they are already properly configured + * at startup for QSGMII. Thus, connected PHYs should work out + * of the box. + */ + if (sds->id != 8 && sds->id != 9 && sds->id != 12 && sds->id != 13) + return 0; + + ret = rtpcs_839x_sds_set_mode(sds, hw_mode); + if (ret < 0) + return ret; + + sds->hw_mode = hw_mode; + + rtpcs_839x_sds_reset(sds); + return 0; +} + +/* RTL93XX */ + +static int rtpcs_93xx_sds_set_autoneg(struct rtpcs_serdes *sds, unsigned int neg_mode, + const unsigned long *advertising) +{ + u16 en_val; + + switch (sds->hw_mode) { + case RTPCS_SDS_MODE_XSGMII: /* XSG N-way state */ + en_val = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ? 0x0 : 0x1; + + return rtpcs_sds_xsg_write_bits(sds, 0x0, 0x2, 9, 8, en_val); + default: + return rtpcs_generic_sds_set_autoneg(sds, neg_mode, advertising); + } +} + +static int rtpcs_93xx_init_serdes_common(struct rtpcs_ctrl *ctrl) +{ + u32 model_info = 0; + int rl_vid, val; + + regmap_read(ctrl->map, RTPCS_93XX_MODEL_NAME_INFO, &model_info); + if (model_info & BIT(4)) + dev_warn(ctrl->dev, "ES chip variants may not work properly!\n"); + + val = 0xa0000; /* CHIP_INFO_EN */ + regmap_write(ctrl->map, RTPCS_93XX_CHIP_INFO, val); + regmap_read(ctrl->map, RTPCS_93XX_CHIP_INFO, &val); + rl_vid = FIELD_GET(GENMASK(31, 28), val); + + if (rl_vid & BIT(0)) + ctrl->chip_version = RTPCS_CHIP_V2; + + val = 0; + regmap_write(ctrl->map, RTPCS_93XX_CHIP_INFO, val); + + dev_dbg(ctrl->dev, "chip_version %u\n", ctrl->chip_version + 1); + return 0; +} + +static int rtpcs_93xx_sds_get_pll_config(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll, + enum rtpcs_sds_pll_speed *speed) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int sbit, speed_val; + + /* + * PLL config is shared between adjacent SerDes in the even lane. Each SerDes defines + * what PLL it needs (ring or LC) while the PLL itself stores the current speed. + */ + + sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; + speed_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, sbit + 3, sbit); + if (speed_val < 0) + return speed_val; + + /* bit 0 is force-bit, bits [3:1] are speed selector */ + *speed = (enum rtpcs_sds_pll_speed)(speed_val >> 1); + return 0; +} + +static int rtpcs_93xx_sds_set_pll_config(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll, + enum rtpcs_sds_pll_speed speed) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; + int ret; + + if (speed >= RTPCS_SDS_PLL_SPD_END) + return -EINVAL; + + if (pll >= RTPCS_SDS_PLL_TYPE_END) + return -EINVAL; + + if ((pll == RTPCS_SDS_PLL_TYPE_RING) && (speed == RTPCS_SDS_PLL_SPD_10000)) + return -EINVAL; + + /* + * A SerDes clock can either be taken from the low speed ring PLL or the high speed + * LC PLL. As it is unclear if disabling PLLs has any positive or negative effect, + * always activate both. + */ + ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 0, 0xf); + if (ret < 0) + return ret; + + /* bit 0 is force-bit, bits [3:1] are speed selector */ + ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, (speed << 1) | BIT(0)); + if (ret < 0) + return ret; + + if (sds->ops->reset_cmu) + ret = sds->ops->reset_cmu(sds, pll); + + return ret; +} + +static int rtpcs_93xx_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode) +{ + struct rtpcs_serdes *nb_sds = rtpcs_sds_get_neighbor(sds); + enum rtpcs_sds_pll_speed speed, neighbor_speed; + enum rtpcs_sds_pll_type pll, neighbor_pll; + bool speed_changed = true; + int ret; + + /* + * A SerDes pair on RTL93xx is driven by a shared CMU with two PLLs: + * + * - a low speed ring PLL which can generate signals of 1.25G and 3.125G for link + * speeds of 1G/2.5G + * - a high speed LC PLL which can additionally generate a 10.3125G signal for + * 10G link speeds + * + * To drive the pair at different speeds, each SerDes must use its own PLL and we + * must wisely assign the PLLs to the SerDes based on their needs. The logic boils + * down to the following rules: + * + * - use ring PLL for slow 1G speeds + * - use LC PLL for fast 10G speeds + * - for 2.5G prefer ring over LC PLL + * + * For the case that we want to configure 10G speed but the LC PLL is already used + * by the neighbor SerDes and running with a slower speed, there's no way to avoid + * reconfiguration. The neighbor SerDes is reconfigured online to the ring PLL. + */ + + if (hw_mode == RTPCS_SDS_MODE_OFF) + return 0; + + ret = rtpcs_sds_select_pll_speed(hw_mode, &speed); + if (ret < 0) + return ret; + + if (nb_sds->hw_mode == RTPCS_SDS_MODE_OFF) { + pll = (speed == RTPCS_SDS_PLL_SPD_10000) ? RTPCS_SDS_PLL_TYPE_LC + : RTPCS_SDS_PLL_TYPE_RING; + goto pll_setup; + } + + ret = nb_sds->ops->get_pll_select(nb_sds, &neighbor_pll); + if (ret < 0) + return ret; + + ret = rtpcs_93xx_sds_get_pll_config(nb_sds, neighbor_pll, &neighbor_speed); + if (ret < 0) + return ret; + + if (speed == neighbor_speed) { + speed_changed = false; + pll = neighbor_pll; + } else if (neighbor_pll == RTPCS_SDS_PLL_TYPE_RING) + pll = RTPCS_SDS_PLL_TYPE_LC; + else if (speed == RTPCS_SDS_PLL_SPD_10000) { + pr_info("%s: SDS %d needs LC PLL, reconfigure SDS %d to use ring PLL\n", + __func__, sds->id, nb_sds->id); + + ret = nb_sds->ops->reconfigure_to_pll(nb_sds, RTPCS_SDS_PLL_TYPE_RING); + if (ret < 0) + return ret; + + pll = RTPCS_SDS_PLL_TYPE_LC; + } else + pll = RTPCS_SDS_PLL_TYPE_RING; + +pll_setup: + if (speed_changed) { + ret = rtpcs_93xx_sds_set_pll_config(sds, pll, speed); + if (ret < 0) + return ret; + } + + ret = sds->ops->set_pll_select(sds, hw_mode, pll); + if (ret < 0) + return ret; + + pr_info("%s: SDS %d using %s PLL for mode %d\n", __func__, sds->id, + pll == RTPCS_SDS_PLL_TYPE_LC ? "LC" : "ring", hw_mode); + return ret; +} + +/* RTL930X */ + +/* + * RTL930X needs a special mapping from logic SerDes ID to physical SerDes ID, + * which takes the page into account. This applies to most of read/write calls. + */ +static int rtpcs_930x_sds_get_phys_sds_id(int sds_id, int page) +{ + if (sds_id == 3 && page < 4) + return 10; + + return sds_id; +} + +static int rtpcs_930x_sds_op_read(struct rtpcs_serdes *sds, int page, int regnum, int bithigh, + int bitlow) +{ + int sds_id = rtpcs_930x_sds_get_phys_sds_id(sds->id, page); + + return __rtpcs_sds_read_raw(sds->ctrl, sds_id, page, regnum, bithigh, bitlow); +} + +static int rtpcs_930x_sds_op_write(struct rtpcs_serdes *sds, int page, int regnum, int bithigh, + int bitlow, u16 value) +{ + int sds_id = rtpcs_930x_sds_get_phys_sds_id(sds->id, page); + + return __rtpcs_sds_write_raw(sds->ctrl, sds_id, page, regnum, bithigh, bitlow, value); +} + +/* + * Realtek uses some nasty logic for digital parts of SerDes 2 and 3. + * + * This implements 'dal_longan_sds_xsg_field_write' and a combination of + * '_rtl9300_serdes_index_to_physical' and '_rtl9300_serdes_reg_write' from the SDK. + */ +static int rtpcs_930x_sds_op_xsg_write(struct rtpcs_serdes *sds, int page, int regnum, + int bithigh, int bitlow, u16 value) +{ + int phys_sds_id, ret; + + switch (sds->id) { + case 2: + phys_sds_id = 2; + break; + case 3: + phys_sds_id = 10; + break; + default: + return -ENOTSUPP; + } + + if (page >= 4) + return sds->ops->write(sds, page, regnum, bithigh, bitlow, value); + + ret = __rtpcs_sds_write_raw(sds->ctrl, phys_sds_id, page, regnum, bithigh, bitlow, value); + if (ret) + return ret; + + return __rtpcs_sds_write_raw(sds->ctrl, phys_sds_id + 1, page, regnum, bithigh, bitlow, + value); +} + +static const u16 rtpcs_930x_sds_mode_regs[] = { + 0x0194, 0x0194, 0x0194, 0x0194, /* SDS_MODE_SEL_0 */ + 0x02a0, 0x02a0, 0x02a0, 0x02a0, /* SDS_MODE_SEL_1 */ + 0x02a4, 0x02a4, /* SDS_MODE_SEL_2 */ + 0x0198, 0x0198 /* SDS_MODE_SEL_3 */ +}; +static const u8 rtpcs_930x_sds_mode_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6 }; + +static const u16 rtpcs_930x_sds_submode_regs[] = { + 0x1cc, 0x1cc, /* SDS_SUBMODE_CTRL0 */ + 0x2d8, 0x2d8, 0x2d8, 0x2d8,0x2d8, 0x2d8 /* SDS_SUBMODE_CTRL1 */ +}; +static const u8 rtpcs_930x_sds_submode_lsb[] = { 0, 5, 0, 5, 10, 15, 20, 25 }; + +__always_unused +static int __rtpcs_930x_sds_get_mac_mode(struct rtpcs_serdes *sds) +{ + u8 sds_id = sds->id; + int mode_val, ret; + + ret = regmap_read(sds->ctrl->map, rtpcs_930x_sds_mode_regs[sds_id], &mode_val); + if (ret < 0) + return ret; + + mode_val >>= rtpcs_930x_sds_mode_lsb[sds_id]; + return mode_val & RTPCS_930X_SDS_MASK; +} + +static int __rtpcs_930x_sds_set_mac_mode(struct rtpcs_serdes *sds, u32 mode) +{ + u8 sds_id = sds->id; + int ret; + + ret = regmap_write_bits(sds->ctrl->map, rtpcs_930x_sds_mode_regs[sds_id], + RTPCS_930X_SDS_MASK << rtpcs_930x_sds_mode_lsb[sds_id], + mode << rtpcs_930x_sds_mode_lsb[sds_id]); + mdelay(10); + + return ret; +} + +__always_unused +static int __rtpcs_930x_sds_get_usxgmii_submode(struct rtpcs_serdes *sds) +{ + u8 sds_id = sds->id; + int submode, ret; + + if (sds_id < 2 || sds_id > 9) { + pr_err("%s: SerDes %u doesn't support USXGMII submode\n", __func__, sds_id); + return -ENOTSUPP; + } + + ret = regmap_read(sds->ctrl->map, rtpcs_930x_sds_submode_regs[sds_id], &submode); + if (ret < 0) + return ret; + + submode >>= rtpcs_930x_sds_submode_lsb[sds_id]; + return submode & RTPCS_930X_SDS_MASK; +} + +static int __rtpcs_930x_sds_set_usxgmii_submode(struct rtpcs_serdes *sds, u32 submode) +{ + u8 sds_id = sds->id; + + if (sds_id < 2 || sds_id > 9) { + pr_err("%s: SerDes %u doesn't support USXGMII submode\n", __func__, sds_id); + return -ENOTSUPP; + } + + if (submode != RTPCS_930X_SDS_SUBMODE_USXGMII_SX && + submode != RTPCS_930X_SDS_SUBMODE_USXGMII_QX) { + pr_err("%s: unsupported submode 0x%x\n", __func__, submode); + return -ENOTSUPP; + } + + return regmap_write_bits(sds->ctrl->map, rtpcs_930x_sds_submode_regs[sds_id - 2], + RTPCS_930X_SDS_MASK << rtpcs_930x_sds_submode_lsb[sds_id - 2], + submode << rtpcs_930x_sds_submode_lsb[sds_id - 2]); +} + +static void rtpcs_930x_sds_rx_reset(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + int page = 0x2e; /* 10GR and USXGMII */ + + if (hw_mode == RTPCS_SDS_MODE_1000BASEX) + page = 0x24; + + rtpcs_sds_write_bits(sds, page, 0x15, 4, 4, 0x1); + mdelay(5); + rtpcs_sds_write_bits(sds, page, 0x15, 4, 4, 0x0); +} + +static int rtpcs_930x_sds_get_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type *pll) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int pbit = (sds == even_sds) ? 4 : 6; + int pll_sel; + + pll_sel = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, pbit + 1, pbit); + if (pll_sel < 0) + return pll_sel; + + /* bit 0 is force-bit, bit 1 is PLL selector */ + *pll = (enum rtpcs_sds_pll_type)(pll_sel >> 1); + return 0; +} + +static int rtpcs_930x_sds_set_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode, + enum rtpcs_sds_pll_type pll) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int pbit = (sds == even_sds) ? 4 : 6; + + /* Selecting the PLL a SerDes is done in the even lane register */ + + /* bit 0 is force-bit, bit 1 is PLL selector */ + return rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, (pll << 1) | BIT(0)); +} + +static int rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int reset_sequence[4] = { 3, 2, 3, 1 }; + int bit, i, ret; + + /* + * After the PLL speed has changed, the CMU must take over the new values. The models + * of the Otto platform have different reset sequences. Luckily it always boils down + * to flipping two bits in a special sequence. + */ + + bit = pll == RTPCS_SDS_PLL_TYPE_LC ? 2 : 0; + + for (i = 0; i < ARRAY_SIZE(reset_sequence); i++) { + ret = rtpcs_sds_write_bits(even_sds, 0x21, 0x0b, bit + 1, bit, + reset_sequence[i]); + if (ret < 0) + return ret; + } + return 0; +} + +static int rtpcs_930x_sds_wait_clock_ready(struct rtpcs_serdes *sds) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int i, ready, ready_cnt = 0, bit = (sds == even_sds) ? 4 : 5; + + /* + * While reconfiguring a SerDes it might take some time until its clock is in sync with + * the PLL. During that timespan the ready signal might toggle randomly. According to + * GPL sources it is enough to verify that 3 consecutive clock ready checks say "ok". + */ + + for (i = 0; i < 20; i++) { + usleep_range(10000, 15000); + + rtpcs_sds_write(even_sds, 0x1f, 0x02, 53); + ready = rtpcs_sds_read_bits(even_sds, 0x1f, 0x14, bit, bit); + + ready_cnt = ready ? ready_cnt + 1 : 0; + if (ready_cnt >= 3) + return 0; + } + + return -EBUSY; +} + +static int __rtpcs_930x_sds_get_ip_mode(struct rtpcs_serdes *sds) +{ + return rtpcs_sds_read_bits(sds, 0x1f, 0x09, 11, 7); +} + +static int __rtpcs_930x_sds_set_ip_mode(struct rtpcs_serdes *sds, u32 mode) +{ + /* BIT(0) is force mode enable bit */ + return rtpcs_sds_write_bits(sds, 0x1f, 0x09, 11, 6, (mode & 0x1f) << 1 | BIT(0)); +} + +static void rtpcs_930x_sds_set_power(struct rtpcs_serdes *sds, bool on) +{ + int power_down = on ? 0x0 : 0x3; + int rx_enable = on ? 0x3 : 0x1; + + rtpcs_sds_write_bits(sds, 0x20, 0x00, 7, 6, power_down); + rtpcs_sds_write_bits(sds, 0x20, 0x00, 5, 4, rx_enable); +} + +static int rtpcs_930x_sds_reconfigure_to_pll(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll) +{ + enum rtpcs_sds_pll_speed speed; + enum rtpcs_sds_pll_type old_pll; + int mode, ret; + + mode = __rtpcs_930x_sds_get_ip_mode(sds); + + ret = rtpcs_930x_sds_get_pll_select(sds, &old_pll); + if (ret < 0) + return ret; + + ret = rtpcs_93xx_sds_get_pll_config(sds, old_pll, &speed); + if (ret < 0) + return ret; + + rtpcs_930x_sds_set_power(sds, false); + __rtpcs_930x_sds_set_ip_mode(sds, RTPCS_930X_SDS_OFF); + + ret = rtpcs_93xx_sds_set_pll_config(sds, pll, speed); + if (ret < 0) + return ret; + + ret = rtpcs_930x_sds_set_pll_select(sds, sds->hw_mode, pll); + if (ret < 0) + return ret; + + __rtpcs_930x_sds_set_ip_mode(sds, mode); + if (rtpcs_930x_sds_wait_clock_ready(sds)) + pr_err("%s: SDS %d could not sync clock\n", __func__, sds->id); + + rtpcs_930x_sds_set_power(sds, true); + return 0; +} + +static void rtpcs_930x_sds_reset_state_machine(struct rtpcs_serdes *sds) +{ + rtpcs_sds_write_bits(sds, 0x06, 0x02, 12, 12, 0x01); /* SM_RESET bit */ + usleep_range(10000, 20000); + rtpcs_sds_write_bits(sds, 0x06, 0x02, 12, 12, 0x00); + usleep_range(10000, 20000); +} + +static int rtpcs_930x_sds_init_state_machine(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + int loopback, link, cnt = 20, ret = -EBUSY; + + if (hw_mode != RTPCS_SDS_MODE_10GBASER) + return 0; + /* + * After a SerDes mode change it takes some time until the frontend state machine + * works properly for 10G. To verify operation readyness run a connection check via + * loopback. + */ + loopback = rtpcs_sds_read_bits(sds, 0x06, 0x01, 2, 2); /* CFG_AFE_LPK bit */ + rtpcs_sds_write_bits(sds, 0x06, 0x01, 2, 2, 0x01); + + while (cnt-- && ret) { + rtpcs_930x_sds_reset_state_machine(sds); + link = rtpcs_sds_read_bits(sds, 0x05, 0x00, 12, 12); /* 10G link state (latched) */ + link = rtpcs_sds_read_bits(sds, 0x05, 0x00, 12, 12); + if (link) + ret = 0; + } + + rtpcs_sds_write_bits(sds, 0x06, 0x01, 2, 2, loopback); + rtpcs_930x_sds_reset_state_machine(sds); + + return ret; +} + +static int rtpcs_930x_sds_get_hw_mode_val(enum rtpcs_sds_mode hw_mode) +{ + switch (hw_mode) { + case RTPCS_SDS_MODE_OFF: + return RTPCS_930X_SDS_OFF; + case RTPCS_SDS_MODE_SGMII: + return RTPCS_930X_SDS_MODE_SGMII; + case RTPCS_SDS_MODE_1000BASEX: + return RTPCS_930X_SDS_MODE_1000BASEX; + case RTPCS_SDS_MODE_2500BASEX: + return RTPCS_930X_SDS_MODE_2500BASEX; + case RTPCS_SDS_MODE_10GBASER: + return RTPCS_930X_SDS_MODE_10GBASER; + case RTPCS_SDS_MODE_QSGMII: + return RTPCS_930X_SDS_MODE_QSGMII; + case RTPCS_SDS_MODE_XSGMII: + return RTPCS_930X_SDS_MODE_XSGMII; + case RTPCS_SDS_MODE_USXGMII_10GSXGMII: + case RTPCS_SDS_MODE_USXGMII_10GQXGMII: + return RTPCS_930X_SDS_MODE_USXGMII; + default: + return -ENOTSUPP; + } +} + +static int rtpcs_930x_sds_set_ip_mode(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + int mode_val, ret; + + /* + * TODO: Usually one would expect that it is enough to modify the SDS_MODE_SEL_* + * registers (lets call it MAC setup). It seems as if this complex sequence is only + * needed for modes that cannot be set by the SoC itself. Additionally it is unclear + * if this sequence should quit early in case of errors. + */ + + mode_val = rtpcs_930x_sds_get_hw_mode_val(hw_mode); + if (mode_val < 0) { + pr_err("%s: SDS %d does not support mode %d\n", __func__, + sds->id, hw_mode); + return mode_val; + } + + rtpcs_930x_sds_set_power(sds, false); + ret = __rtpcs_930x_sds_set_ip_mode(sds, RTPCS_930X_SDS_OFF); + if (ret < 0) + return ret; + + if (hw_mode == RTPCS_SDS_MODE_OFF) + return 0; + + ret = rtpcs_93xx_sds_config_cmu(sds, hw_mode); + if (ret < 0) + pr_err("%s: SDS %d could not configure PLL for mode %d: %d\n", __func__, + sds->id, hw_mode, ret); + + ret = __rtpcs_930x_sds_set_ip_mode(sds, mode_val); + if (ret < 0) + return ret; + + if (rtpcs_930x_sds_wait_clock_ready(sds)) + pr_err("%s: SDS %d could not sync clock\n", __func__, sds->id); + + if (rtpcs_930x_sds_init_state_machine(sds, hw_mode)) + pr_err("%s: SDS %d could not reset state machine\n", __func__, + sds->id); + + rtpcs_930x_sds_set_power(sds, true); + rtpcs_930x_sds_rx_reset(sds, hw_mode); + return 0; +} + +static int rtpcs_930x_sds_set_mac_mode(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + int submode_val = -1; + int mode_val, ret; + + mode_val = rtpcs_930x_sds_get_hw_mode_val(hw_mode); + if (mode_val < 0) + return mode_val; + + switch (hw_mode) { + case RTPCS_SDS_MODE_USXGMII_10GSXGMII: + submode_val = RTPCS_930X_SDS_SUBMODE_USXGMII_SX; + break; + case RTPCS_SDS_MODE_USXGMII_10GQXGMII: + submode_val = RTPCS_930X_SDS_SUBMODE_USXGMII_QX; + break; + default: + break; + } + + /* SerDes off first. */ + ret = __rtpcs_930x_sds_set_mac_mode(sds, RTPCS_930X_SDS_OFF); + if (ret < 0) + return ret; + + if (hw_mode == RTPCS_SDS_MODE_OFF) + return 0; + + /* Set the mode. */ + ret = __rtpcs_930x_sds_set_mac_mode(sds, mode_val); + if (ret < 0) + return ret; + + /* Set the submode if needed. */ + if (submode_val >= 0) { + ret = __rtpcs_930x_sds_set_usxgmii_submode(sds, submode_val); + if (ret < 0) + return ret; + } + + return 0; +} + +static int rtpcs_930x_sds_set_mode(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + /* + * Several modes can be configured via MAC setup, just by setting + * a register to a specific value and the MAC will configure + * "everything" as needed. For some modes, this seems incomplete and + * we need to do manual configuration in the SerDes IP core itself. + */ + + switch (hw_mode) { + case RTPCS_SDS_MODE_SGMII: + case RTPCS_SDS_MODE_1000BASEX: + case RTPCS_SDS_MODE_2500BASEX: + case RTPCS_SDS_MODE_10GBASER: + return rtpcs_930x_sds_set_ip_mode(sds, hw_mode); + default: + return rtpcs_930x_sds_set_mac_mode(sds, hw_mode); + } +} + +static void rtpcs_930x_sds_tx_config(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + /* parameters: rtl9303_80G_txParam_s2 */ + int impedance = 0x8; + int pre_amp = 0x2; + int main_amp = 0x9; + int post_amp = 0x2; + int pre_en = 0x1; + int post_en = 0x1; + int page; + + switch (hw_mode) { + case RTPCS_SDS_MODE_1000BASEX: + case RTPCS_SDS_MODE_SGMII: + pre_amp = 0x1; + main_amp = 0x9; + post_amp = 0x1; + page = 0x25; + break; + case RTPCS_SDS_MODE_2500BASEX: + pre_amp = 0; + post_amp = 0x8; + pre_en = 0; + page = 0x29; + break; + case RTPCS_SDS_MODE_10GBASER: + case RTPCS_SDS_MODE_USXGMII_10GSXGMII: + case RTPCS_SDS_MODE_USXGMII_10GQXGMII: + case RTPCS_SDS_MODE_XSGMII: + pre_en = 0; + pre_amp = 0; + main_amp = 0x10; + post_amp = 0; + post_en = 0; + page = 0x2f; + break; + case RTPCS_SDS_MODE_QSGMII: + return; + default: + pr_err("%s: unsupported SerDes hw mode\n", __func__); + return; + } + + rtpcs_sds_write_bits(sds, page, 0x01, 15, 11, pre_amp); + rtpcs_sds_write_bits(sds, page, 0x06, 4, 0, post_amp); + rtpcs_sds_write_bits(sds, page, 0x07, 0, 0, pre_en); + rtpcs_sds_write_bits(sds, page, 0x07, 3, 3, post_en); + rtpcs_sds_write_bits(sds, page, 0x07, 8, 4, main_amp); + rtpcs_sds_write_bits(sds, page, 0x18, 15, 12, impedance); +} + +__always_unused +static void rtpcs_930x_sds_rxcal_dcvs_manual(struct rtpcs_serdes *sds, + u32 dcvs_id, bool manual, u32 dvcs_list[]) +{ + if (manual) { + switch (dcvs_id) { + case 0: + rtpcs_sds_write_bits(sds, 0x2e, 0x1e, 14, 14, 0x1); + rtpcs_sds_write_bits(sds, 0x2f, 0x03, 5, 5, dvcs_list[0]); + rtpcs_sds_write_bits(sds, 0x2f, 0x03, 4, 0, dvcs_list[1]); + break; + case 1: + rtpcs_sds_write_bits(sds, 0x2e, 0x1e, 13, 13, 0x1); + rtpcs_sds_write_bits(sds, 0x2e, 0x1d, 15, 15, dvcs_list[0]); + rtpcs_sds_write_bits(sds, 0x2e, 0x1d, 14, 11, dvcs_list[1]); + break; + case 2: + rtpcs_sds_write_bits(sds, 0x2e, 0x1e, 12, 12, 0x1); + rtpcs_sds_write_bits(sds, 0x2e, 0x1d, 10, 10, dvcs_list[0]); + rtpcs_sds_write_bits(sds, 0x2e, 0x1d, 9, 6, dvcs_list[1]); + break; + case 3: + rtpcs_sds_write_bits(sds, 0x2e, 0x1e, 11, 11, 0x1); + rtpcs_sds_write_bits(sds, 0x2e, 0x1d, 5, 5, dvcs_list[0]); + rtpcs_sds_write_bits(sds, 0x2e, 0x1d, 4, 1, dvcs_list[1]); + break; + case 4: + rtpcs_sds_write_bits(sds, 0x2e, 0x01, 15, 15, 0x1); + rtpcs_sds_write_bits(sds, 0x2e, 0x11, 10, 10, dvcs_list[0]); + rtpcs_sds_write_bits(sds, 0x2e, 0x11, 9, 6, dvcs_list[1]); + break; + case 5: + rtpcs_sds_write_bits(sds, 0x2e, 0x02, 11, 11, 0x1); + rtpcs_sds_write_bits(sds, 0x2e, 0x11, 4, 4, dvcs_list[0]); + rtpcs_sds_write_bits(sds, 0x2e, 0x11, 3, 0, dvcs_list[1]); + break; + default: + break; + } + } else { + switch (dcvs_id) { + case 0: + rtpcs_sds_write_bits(sds, 0x2e, 0x1e, 14, 14, 0x0); + break; + case 1: + rtpcs_sds_write_bits(sds, 0x2e, 0x1e, 13, 13, 0x0); + break; + case 2: + rtpcs_sds_write_bits(sds, 0x2e, 0x1e, 12, 12, 0x0); + break; + case 3: + rtpcs_sds_write_bits(sds, 0x2e, 0x1e, 11, 11, 0x0); + break; + case 4: + rtpcs_sds_write_bits(sds, 0x2e, 0x01, 15, 15, 0x0); + break; + case 5: + rtpcs_sds_write_bits(sds, 0x2e, 0x02, 11, 11, 0x0); + break; + default: + break; + } + mdelay(1); + } +} + +__always_unused +static void rtpcs_930x_sds_rxcal_dcvs_get(struct rtpcs_serdes *sds, + u32 dcvs_id, u32 dcvs_list[]) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + u32 dcvs_sign_out = 0, dcvs_coef_bin = 0; + bool dcvs_manual; + + if (sds == even_sds) + rtpcs_sds_write(sds, 0x1f, 0x2, 0x2f); + else + rtpcs_sds_write(even_sds, 0x1f, 0x2, 0x31); + + rtpcs_sds_write_bits(sds, 0x2e, 0x15, 9, 9, 0x1); /* REG0_RX_EN_TEST */ + rtpcs_sds_write_bits(sds, 0x21, 0x06, 11, 6, 0x20); /* REG0_RX_DEBUG_SEL */ + + switch (dcvs_id) { + case 0: + rtpcs_sds_write_bits(sds, 0x2f, 0x0c, 5, 0, 0x22); + mdelay(1); + + /* ##DCVS0 Read Out */ + dcvs_sign_out = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 4, 4); + dcvs_coef_bin = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 3, 0); + dcvs_manual = !!rtpcs_sds_read_bits(sds, 0x2e, 0x1e, 14, 14); + break; + + case 1: + rtpcs_sds_write_bits(sds, 0x2f, 0x0c, 5, 0, 0x23); + mdelay(1); + + /* ##DCVS0 Read Out */ + dcvs_coef_bin = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 4, 4); + dcvs_coef_bin = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 3, 0); + dcvs_manual = !!rtpcs_sds_read_bits(sds, 0x2e, 0x1e, 13, 13); + break; + + case 2: + rtpcs_sds_write_bits(sds, 0x2f, 0x0c, 5, 0, 0x24); + mdelay(1); + + /* ##DCVS0 Read Out */ + dcvs_sign_out = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 4, 4); + dcvs_coef_bin = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 3, 0); + dcvs_manual = !!rtpcs_sds_read_bits(sds, 0x2e, 0x1e, 12, 12); + break; + case 3: + rtpcs_sds_write_bits(sds, 0x2f, 0x0c, 5, 0, 0x25); + mdelay(1); + + /* ##DCVS0 Read Out */ + dcvs_sign_out = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 4, 4); + dcvs_coef_bin = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 3, 0); + dcvs_manual = rtpcs_sds_read_bits(sds, 0x2e, 0x1e, 11, 11); + break; + + case 4: + rtpcs_sds_write_bits(sds, 0x2f, 0x0c, 5, 0, 0x2c); + mdelay(1); + + /* ##DCVS0 Read Out */ + dcvs_sign_out = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 4, 4); + dcvs_coef_bin = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 3, 0); + dcvs_manual = !!rtpcs_sds_read_bits(sds, 0x2e, 0x01, 15, 15); + break; + + case 5: + rtpcs_sds_write_bits(sds, 0x2f, 0x0c, 5, 0, 0x2d); + mdelay(1); + + /* ##DCVS0 Read Out */ + dcvs_sign_out = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 4, 4); + dcvs_coef_bin = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 3, 0); + dcvs_manual = rtpcs_sds_read_bits(sds, 0x2e, 0x02, 11, 11); + break; + + default: + break; + } + + pr_info("%s: DCVS %u sign = %s, manual = %u, even coefficient = %u\n", __func__, + dcvs_id, dcvs_sign_out ? "-" : "+", dcvs_manual, dcvs_coef_bin); + + dcvs_list[0] = dcvs_sign_out; + dcvs_list[1] = dcvs_coef_bin; +} + +static void rtpcs_930x_sds_rxcal_leq_manual(struct rtpcs_serdes *sds, + bool manual, u32 leq_gray) +{ + if (manual) { + rtpcs_sds_write_bits(sds, 0x2e, 0x18, 15, 15, 0x1); + rtpcs_sds_write_bits(sds, 0x2e, 0x16, 14, 10, leq_gray); + } else { + rtpcs_sds_write_bits(sds, 0x2e, 0x18, 15, 15, 0x0); + mdelay(100); + } +} + +static void rtpcs_930x_sds_rxcal_leq_offset_manual(struct rtpcs_serdes *sds, + bool manual, u32 offset) +{ + if (manual) { + rtpcs_sds_write_bits(sds, 0x2e, 0x17, 6, 2, offset); + } else { + rtpcs_sds_write_bits(sds, 0x2e, 0x17, 6, 2, offset); + mdelay(1); + } +} + +#define GRAY_BITS 5 +static u32 rtpcs_930x_sds_rxcal_gray_to_binary(u32 gray_code) +{ + int i, j, m; + u32 g[GRAY_BITS]; + u32 c[GRAY_BITS]; + u32 leq_binary = 0; + + for (i = 0; i < GRAY_BITS; i++) + g[i] = (gray_code & BIT(i)) >> i; + + m = GRAY_BITS - 1; + + c[m] = g[m]; + + for (i = 0; i < m; i++) { + c[i] = g[i]; + for (j = i + 1; j < GRAY_BITS; j++) + c[i] = c[i] ^ g[j]; + } + + for (i = 0; i < GRAY_BITS; i++) + leq_binary += c[i] << i; + + return leq_binary; +} + +static u32 rtpcs_930x_sds_rxcal_leq_read(struct rtpcs_serdes *sds) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + u32 leq_gray, leq_bin; + bool leq_manual; + + rtpcs_sds_write(even_sds, 0x1f, 0x2, (sds == even_sds) ? 0x2f : 0x31); /* REG_DBGO_SEL */ + rtpcs_sds_write_bits(sds, 0x2e, 0x15, 9, 9, 0x1); /* REG0_RX_EN_TEST */ + rtpcs_sds_write_bits(sds, 0x21, 0x06, 11, 6, 0x10); /* REG0_RX_DEBUG_SEL */ + mdelay(1); + + /* ##LEQ Read Out */ + leq_gray = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 7, 3); + leq_manual = !!rtpcs_sds_read_bits(sds, 0x2e, 0x18, 15, 15); + leq_bin = rtpcs_930x_sds_rxcal_gray_to_binary(leq_gray); + + pr_info("LEQ gray: %u, LEQ bin: %u", leq_gray, leq_bin); + pr_info("LEQ manual: %u", leq_manual); + + return leq_bin; +} + +static void rtpcs_930x_sds_rxcal_vth_manual(struct rtpcs_serdes *sds, + bool manual, u32 vth_list[]) +{ + if (manual) { + rtpcs_sds_write_bits(sds, 0x2e, 0x0f, 13, 13, 0x1); + rtpcs_sds_write_bits(sds, 0x2e, 0x13, 5, 3, vth_list[0]); + rtpcs_sds_write_bits(sds, 0x2e, 0x13, 2, 0, vth_list[1]); + } else { + rtpcs_sds_write_bits(sds, 0x2e, 0x0f, 13, 13, 0x0); + mdelay(10); + } +} + +static void rtpcs_930x_sds_rxcal_vth_get(struct rtpcs_serdes *sds, + u32 vth_list[]) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int vth_manual; + + rtpcs_sds_write(even_sds, 0x1f, 0x2, (sds == even_sds) ? 0x2f : 0x31); /* REG_DBGO_SEL */ + rtpcs_sds_write_bits(sds, 0x2e, 0x15, 9, 9, 0x1); /* REG0_RX_EN_TEST */ + rtpcs_sds_write_bits(sds, 0x21, 0x06, 11, 6, 0x20); /* REG0_RX_DEBUG_SEL */ + rtpcs_sds_write_bits(sds, 0x2f, 0x0c, 5, 0, 0xc); /* REG0_COEF_SEL */ + + mdelay(1); + + /* ##VthP & VthN Read Out */ + vth_list[0] = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 2, 0); /* v_thp set bin */ + vth_list[1] = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 5, 3); /* v_thn set bin */ + vth_manual = rtpcs_sds_read_bits(sds, 0x2e, 0x0f, 13, 13); + + pr_info("vthp_set_bin = %d, vthn_set_bin = %d, manual = %d\n", vth_list[0], vth_list[1], + vth_manual); +} + +static void rtpcs_930x_sds_rxcal_tap_manual(struct rtpcs_serdes *sds, + int tap_id, bool manual, u32 tap_list[]) +{ + if (manual) { + switch (tap_id) { + case 0: + /* ##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value */ + rtpcs_sds_write_bits(sds, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1); + rtpcs_sds_write_bits(sds, 0x2f, 0x03, 5, 5, tap_list[0]); + rtpcs_sds_write_bits(sds, 0x2f, 0x03, 4, 0, tap_list[1]); + break; + case 1: + rtpcs_sds_write_bits(sds, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1); + rtpcs_sds_write_bits(sds, 0x21, 0x07, 6, 6, tap_list[0]); + rtpcs_sds_write_bits(sds, 0x2e, 0x09, 11, 6, tap_list[1]); + rtpcs_sds_write_bits(sds, 0x21, 0x07, 5, 5, tap_list[2]); + rtpcs_sds_write_bits(sds, 0x2f, 0x12, 5, 0, tap_list[3]); + break; + case 2: + rtpcs_sds_write_bits(sds, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1); + rtpcs_sds_write_bits(sds, 0x2e, 0x09, 5, 5, tap_list[0]); + rtpcs_sds_write_bits(sds, 0x2e, 0x09, 4, 0, tap_list[1]); + rtpcs_sds_write_bits(sds, 0x2e, 0x0a, 11, 11, tap_list[2]); + rtpcs_sds_write_bits(sds, 0x2e, 0x0a, 10, 6, tap_list[3]); + break; + case 3: + rtpcs_sds_write_bits(sds, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1); + rtpcs_sds_write_bits(sds, 0x2e, 0x0a, 5, 5, tap_list[0]); + rtpcs_sds_write_bits(sds, 0x2e, 0x0a, 4, 0, tap_list[1]); + rtpcs_sds_write_bits(sds, 0x2e, 0x06, 5, 5, tap_list[2]); + rtpcs_sds_write_bits(sds, 0x2e, 0x06, 4, 0, tap_list[3]); + break; + case 4: + rtpcs_sds_write_bits(sds, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1); + rtpcs_sds_write_bits(sds, 0x2f, 0x01, 5, 5, tap_list[0]); + rtpcs_sds_write_bits(sds, 0x2f, 0x01, 4, 0, tap_list[1]); + rtpcs_sds_write_bits(sds, 0x2e, 0x06, 11, 11, tap_list[2]); + rtpcs_sds_write_bits(sds, 0x2e, 0x06, 10, 6, tap_list[3]); + break; + default: + break; + } + } else { + rtpcs_sds_write_bits(sds, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x0); + mdelay(10); + } +} + +static void rtpcs_930x_sds_rxcal_tap_get(struct rtpcs_serdes *sds, + u32 tap_id, u32 tap_list[]) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + u32 tap0_sign_out; + u32 tap0_coef_bin; + u32 tap_sign_out_even; + u32 tap_coef_bin_even; + u32 tap_sign_out_odd; + u32 tap_coef_bin_odd; + bool tap_manual; + + rtpcs_sds_write(even_sds, 0x1f, 0x2, (sds == even_sds) ? 0x2f : 0x31); /* REG_DBGO_SEL */ + rtpcs_sds_write_bits(sds, 0x2e, 0x15, 9, 9, 0x1); /* REG0_RX_EN_TEST */ + rtpcs_sds_write_bits(sds, 0x21, 0x06, 11, 6, 0x20); /* REG0_RX_DEBUG_SEL */ + + if (!tap_id) { + rtpcs_sds_write_bits(sds, 0x2f, 0x0c, 5, 0, 0); /* REG0_COEF_SEL */ + /* ##Tap1 Even Read Out */ + mdelay(1); + tap0_sign_out = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 5, 5); + tap0_coef_bin = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 4, 0); + + pr_info("tap0: coef_bin = %d, sign = %s\n", tap0_coef_bin, + tap0_sign_out ? "-" : "+"); + + tap_list[0] = tap0_sign_out; + tap_list[1] = tap0_coef_bin; + + tap_manual = !!rtpcs_sds_read_bits(sds, 0x2e, 0x0f, 7, 7); + pr_info("tap0: manual = %u\n", tap_manual); + } else { + rtpcs_sds_write_bits(sds, 0x2f, 0x0c, 5, 0, tap_id); /* REG0_COEF_SEL */ + mdelay(1); + /* ##Tap1 Even Read Out */ + tap_sign_out_even = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 5, 5); + tap_coef_bin_even = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 4, 0); + + rtpcs_sds_write_bits(sds, 0x2f, 0x0c, 5, 0, (tap_id + 5)); /* REG0_COEF_SEL */ + /* ##Tap1 Odd Read Out */ + tap_sign_out_odd = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 5, 5); + tap_coef_bin_odd = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 4, 0); + + pr_info("tap%u: even coefficient = %u, sign = %s\n", tap_id, tap_coef_bin_even, + tap_sign_out_even ? "-" : "+"); + + pr_info("tap%u: odd coefficient = %u, sign = %s\n", tap_id, tap_coef_bin_odd, + tap_sign_out_odd ? "-" : "+"); + + tap_list[0] = tap_sign_out_even; + tap_list[1] = tap_coef_bin_even; + tap_list[2] = tap_sign_out_odd; + tap_list[3] = tap_coef_bin_odd; + + tap_manual = rtpcs_sds_read_bits(sds, 0x2e, 0x0f, tap_id + 7, tap_id + 7); + pr_info("tap%u: manual = %d\n", tap_id, tap_manual); + } +} + +static void rtpcs_930x_sds_do_rx_calibration_1(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + /* From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam */ + int tap0_init_val = 0x1f; /* Initial Decision Fed Equalizer 0 tap */ + int vth_min = 0x1; + + pr_info("start_1.1.1 initial value for sds %d\n", sds->id); + rtpcs_sds_write(sds, 6, 0, 0); + + /* FGCAL */ + rtpcs_sds_write_bits(sds, 0x2e, 0x01, 14, 14, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x1c, 10, 5, 0x20); + rtpcs_sds_write_bits(sds, 0x2f, 0x02, 0, 0, 0x01); + + /* DCVS */ + rtpcs_sds_write_bits(sds, 0x2e, 0x1e, 14, 11, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x01, 15, 15, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x02, 11, 11, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x1c, 4, 0, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x1d, 15, 11, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x1d, 10, 6, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x1d, 5, 1, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x02, 10, 6, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x11, 4, 0, 0x00); + rtpcs_sds_write_bits(sds, 0x2f, 0x00, 3, 0, 0x0f); + rtpcs_sds_write_bits(sds, 0x2e, 0x04, 6, 6, 0x01); + rtpcs_sds_write_bits(sds, 0x2e, 0x04, 7, 7, 0x01); + + /* LEQ (Long Term Equivalent signal level) */ + rtpcs_sds_write_bits(sds, 0x2e, 0x16, 14, 8, 0x00); + + /* DFE (Decision Fed Equalizer) */ + rtpcs_sds_write_bits(sds, 0x2f, 0x03, 5, 0, tap0_init_val); + rtpcs_sds_write_bits(sds, 0x2e, 0x09, 11, 6, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x09, 5, 0, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x0a, 5, 0, 0x00); + rtpcs_sds_write_bits(sds, 0x2f, 0x01, 5, 0, 0x00); + rtpcs_sds_write_bits(sds, 0x2f, 0x12, 5, 0, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x0a, 11, 6, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x06, 5, 0, 0x00); + rtpcs_sds_write_bits(sds, 0x2f, 0x01, 5, 0, 0x00); + + /* Vth */ + rtpcs_sds_write_bits(sds, 0x2e, 0x13, 5, 3, 0x07); + rtpcs_sds_write_bits(sds, 0x2e, 0x13, 2, 0, 0x07); + rtpcs_sds_write_bits(sds, 0x2f, 0x0b, 5, 3, vth_min); + + pr_info("end_1.1.1 --\n"); + + pr_info("start_1.1.2 Load DFE init. value\n"); + + rtpcs_sds_write_bits(sds, 0x2e, 0x0f, 13, 7, 0x7f); + + pr_info("end_1.1.2\n"); + + pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n"); + + rtpcs_sds_write_bits(sds, 0x2e, 0x17, 7, 7, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x17, 6, 2, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x0c, 8, 8, 0x00); + rtpcs_sds_write_bits(sds, 0x2e, 0x0b, 4, 4, 0x01); + rtpcs_sds_write_bits(sds, 0x2e, 0x12, 14, 14, 0x00); + rtpcs_sds_write_bits(sds, 0x2f, 0x02, 15, 15, 0x00); + + pr_info("end_1.1.3 --\n"); + + pr_info("start_1.1.4 offset cali setting\n"); + + rtpcs_sds_write_bits(sds, 0x2e, 0x0f, 15, 14, 0x03); + + pr_info("end_1.1.4\n"); + + pr_info("start_1.1.5 LEQ and DFE setting\n"); + + /* assume this is equivalent with (PHY_TYPE == SERDES && MEDIA == FIBER_10G) for now */ + if (hw_mode == RTPCS_SDS_MODE_10GBASER) { + rtpcs_sds_write_bits(sds, 0x2e, 0x03, 13, 8, 0x1f); + rtpcs_sds_write_bits(sds, 0x2e, 0x00, 13, 13, 0x01); + rtpcs_sds_write_bits(sds, 0x2e, 0x16, 14, 8, 0x00); /* REG0_FILTER_OUT */ + } + + /* REG0_LEQ_DC_GAIN */ + rtpcs_sds_write_bits(sds, 0x2e, 0x16, 3, 2, 0x02); /* REG0_LEQ_DC_GAIN, 0x01 for short DACs */ + rtpcs_sds_write_bits(sds, 0x2e, 0x0f, 6, 0, 0x5f); + rtpcs_sds_write_bits(sds, 0x2f, 0x05, 7, 2, 0x1f); + rtpcs_sds_write_bits(sds, 0x2e, 0x19, 9, 5, 0x1f); + rtpcs_sds_write_bits(sds, 0x2f, 0x0b, 15, 9, 0x3c); + rtpcs_sds_write_bits(sds, 0x2e, 0x0b, 1, 0, 0x03); + + pr_info("end_1.1.5\n"); +} + +static void rtpcs_930x_sds_do_rx_calibration_2_1(struct rtpcs_serdes *sds) +{ + pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n"); + + /* Gray config endis to 1 */ + rtpcs_sds_write_bits(sds, 0x2f, 0x02, 2, 2, 0x01); + + /* ForegroundOffsetCal_Manual(auto mode) */ + rtpcs_sds_write_bits(sds, 0x2e, 0x01, 14, 14, 0x00); + + pr_info("end_1.2.1"); +} + +static void rtpcs_930x_sds_do_rx_calibration_2_2(struct rtpcs_serdes *sds) +{ + /* Force Rx-Run = 0 */ + rtpcs_sds_write_bits(sds, 0x2e, 0x15, 8, 8, 0x0); + + rtpcs_930x_sds_rx_reset(sds, RTPCS_SDS_MODE_10GBASER); +} + +static void rtpcs_930x_sds_do_rx_calibration_2_3(struct rtpcs_serdes *sds) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + u32 fgcal_binary, fgcal_gray; + u32 offset_range; + + pr_info("start_1.2.3 Foreground Calibration\n"); + + for (int run = 0; run < 10; run++) { + /* REG_DBGO_SEL */ + rtpcs_sds_write(even_sds, 0x1f, 0x2, (sds == even_sds) ? 0x2f : 0x31); + rtpcs_sds_write_bits(sds, 0x2e, 0x15, 9, 9, 0x1); /* REG0_RX_EN_TEST */ + rtpcs_sds_write_bits(sds, 0x21, 0x06, 11, 6, 0x20); /* REG0_RX_DEBUG_SEL */ + + rtpcs_sds_write_bits(sds, 0x2f, 0x0c, 5, 0, 0xf); /* REG0_COEF_SEL */ + /* ##FGCAL read gray */ + fgcal_gray = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 5, 0); + rtpcs_sds_write_bits(sds, 0x2f, 0x0c, 5, 0, 0xe); /* REG0_COEF_SEL */ + /* ##FGCAL read binary */ + fgcal_binary = rtpcs_sds_read_bits(sds, 0x1f, 0x14, 5, 0); + + if (fgcal_binary <= 60 && fgcal_binary >= 3) + break; + + pr_info("%s: fgcal_gray = %d, fgcal_binary = %d\n", __func__, fgcal_gray, + fgcal_binary); + + offset_range = rtpcs_sds_read_bits(sds, 0x2e, 0x15, 15, 14); + if (offset_range == 3) { + pr_info("%s: Foreground Calibration result marginal!", __func__); + break; + } + + offset_range++; + rtpcs_sds_write_bits(sds, 0x2e, 0x15, 15, 14, offset_range); + rtpcs_930x_sds_do_rx_calibration_2_2(sds); + } + pr_info("%s: end_1.2.3\n", __func__); +} + +static void rtpcs_930x_sds_do_rx_calibration_2(struct rtpcs_serdes *sds) +{ + rtpcs_930x_sds_rx_reset(sds, RTPCS_SDS_MODE_10GBASER); + rtpcs_930x_sds_do_rx_calibration_2_1(sds); + rtpcs_930x_sds_do_rx_calibration_2_2(sds); + rtpcs_930x_sds_do_rx_calibration_2_3(sds); +} + +static void rtpcs_930x_sds_rxcal_3_1(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + pr_info("start_1.3.1"); + + /* ##1.3.1 */ + if (hw_mode != RTPCS_SDS_MODE_10GBASER && + hw_mode != RTPCS_SDS_MODE_1000BASEX && + hw_mode != RTPCS_SDS_MODE_SGMII) + rtpcs_sds_write_bits(sds, 0x2e, 0xc, 8, 8, 0); + + rtpcs_sds_write_bits(sds, 0x2e, 0x17, 7, 7, 0x0); + rtpcs_930x_sds_rxcal_leq_manual(sds, false, 0); + + pr_info("end_1.3.1"); +} + +static void rtpcs_930x_sds_rxcal_3_2(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + u32 sum10 = 0, avg10, int10; + int dac_long_cable_offset; + bool eq_hold_enabled; + int i; + + if (hw_mode == RTPCS_SDS_MODE_10GBASER || + hw_mode == RTPCS_SDS_MODE_1000BASEX || + hw_mode == RTPCS_SDS_MODE_SGMII) { + /* rtl9300_rxCaliConf_serdes_myParam */ + dac_long_cable_offset = 3; + eq_hold_enabled = true; + } else { + /* rtl9300_rxCaliConf_phy_myParam */ + dac_long_cable_offset = 0; + eq_hold_enabled = false; + } + + if (hw_mode != RTPCS_SDS_MODE_10GBASER) + pr_warn("%s: LEQ only valid for 10GR!\n", __func__); + + pr_info("start_1.3.2"); + + for (i = 0; i < 10; i++) { + sum10 += rtpcs_930x_sds_rxcal_leq_read(sds); + mdelay(10); + } + + avg10 = (sum10 / 10) + (((sum10 % 10) >= 5) ? 1 : 0); + int10 = sum10 / 10; + + pr_info("sum10:%u, avg10:%u, int10:%u", sum10, avg10, int10); + + if (hw_mode == RTPCS_SDS_MODE_10GBASER || + hw_mode == RTPCS_SDS_MODE_1000BASEX || + hw_mode == RTPCS_SDS_MODE_SGMII) { + if (dac_long_cable_offset) { + rtpcs_930x_sds_rxcal_leq_offset_manual(sds, 1, + dac_long_cable_offset); + rtpcs_sds_write_bits(sds, 0x2e, 0x17, 7, 7, + eq_hold_enabled); + if (hw_mode == RTPCS_SDS_MODE_10GBASER) + rtpcs_930x_sds_rxcal_leq_manual(sds, + true, avg10); + } else { + if (sum10 >= 5) { + rtpcs_930x_sds_rxcal_leq_offset_manual(sds, 1, 3); + rtpcs_sds_write_bits(sds, 0x2e, 0x17, 7, 7, 0x1); + if (hw_mode == RTPCS_SDS_MODE_10GBASER) + rtpcs_930x_sds_rxcal_leq_manual(sds, true, avg10); + } else { + rtpcs_930x_sds_rxcal_leq_offset_manual(sds, 1, 0); + rtpcs_sds_write_bits(sds, 0x2e, 0x17, 7, 7, 0x1); + if (hw_mode == RTPCS_SDS_MODE_10GBASER) + rtpcs_930x_sds_rxcal_leq_manual(sds, true, avg10); + } + } + } + + pr_info("Sds:%u LEQ = %u", sds->id, rtpcs_930x_sds_rxcal_leq_read(sds)); + + pr_info("end_1.3.2"); +} + +__always_unused +static void rtpcs_930x_sds_do_rx_calibration_3(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + rtpcs_930x_sds_rxcal_3_1(sds, hw_mode); + + if (hw_mode == RTPCS_SDS_MODE_10GBASER || + hw_mode == RTPCS_SDS_MODE_1000BASEX || + hw_mode == RTPCS_SDS_MODE_SGMII) + rtpcs_930x_sds_rxcal_3_2(sds, hw_mode); +} + +static void rtpcs_930x_sds_do_rx_calibration_4_1(struct rtpcs_serdes *sds) +{ + u32 vth_list[2] = {0, 0}; + u32 tap0_list[4] = {0, 0, 0, 0}; + + pr_info("start_1.4.1"); + + /* ##1.4.1 */ + rtpcs_930x_sds_rxcal_vth_manual(sds, false, vth_list); + rtpcs_930x_sds_rxcal_tap_manual(sds, 0, false, tap0_list); + mdelay(200); + + pr_info("end_1.4.1"); +} + +static void rtpcs_930x_sds_do_rx_calibration_4_2(struct rtpcs_serdes *sds) +{ + u32 vth_list[2]; + u32 tap_list[4]; + + pr_info("start_1.4.2"); + + rtpcs_930x_sds_rxcal_vth_get(sds, vth_list); + rtpcs_930x_sds_rxcal_vth_manual(sds, true, vth_list); + + mdelay(100); + + rtpcs_930x_sds_rxcal_tap_get(sds, 0, tap_list); + rtpcs_930x_sds_rxcal_tap_manual(sds, 0, true, tap_list); + + pr_info("end_1.4.2"); +} + +static void rtpcs_930x_sds_do_rx_calibration_4(struct rtpcs_serdes *sds) +{ + rtpcs_930x_sds_do_rx_calibration_4_1(sds); + rtpcs_930x_sds_do_rx_calibration_4_2(sds); +} + +static void rtpcs_930x_sds_do_rx_calibration_5_2(struct rtpcs_serdes *sds) +{ + u32 tap1_list[4] = {0}; + u32 tap2_list[4] = {0}; + u32 tap3_list[4] = {0}; + u32 tap4_list[4] = {0}; + + pr_info("start_1.5.2"); + + rtpcs_930x_sds_rxcal_tap_manual(sds, 1, false, tap1_list); + rtpcs_930x_sds_rxcal_tap_manual(sds, 2, false, tap2_list); + rtpcs_930x_sds_rxcal_tap_manual(sds, 3, false, tap3_list); + rtpcs_930x_sds_rxcal_tap_manual(sds, 4, false, tap4_list); + + mdelay(30); + + pr_info("end_1.5.2"); +} + +static void rtpcs_930x_sds_do_rx_calibration_5(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + if (hw_mode == RTPCS_SDS_MODE_10GBASER) /* dfeTap1_4Enable true */ + rtpcs_930x_sds_do_rx_calibration_5_2(sds); +} + +static void rtpcs_930x_sds_do_rx_calibration_dfe_disable(struct rtpcs_serdes *sds) +{ + u32 tap1_list[4] = {0}; + u32 tap2_list[4] = {0}; + u32 tap3_list[4] = {0}; + u32 tap4_list[4] = {0}; + + rtpcs_930x_sds_rxcal_tap_manual(sds, 1, true, tap1_list); + rtpcs_930x_sds_rxcal_tap_manual(sds, 2, true, tap2_list); + rtpcs_930x_sds_rxcal_tap_manual(sds, 3, true, tap3_list); + rtpcs_930x_sds_rxcal_tap_manual(sds, 4, true, tap4_list); + + mdelay(10); +} + +static void rtpcs_930x_sds_do_rx_calibration(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + u32 latch_sts; + + rtpcs_930x_sds_do_rx_calibration_1(sds, hw_mode); + rtpcs_930x_sds_do_rx_calibration_2(sds); + rtpcs_930x_sds_do_rx_calibration_4(sds); + rtpcs_930x_sds_do_rx_calibration_5(sds, hw_mode); + mdelay(20); + + /* Do this only for 10GR mode */ + if (hw_mode == RTPCS_SDS_MODE_10GBASER) { + pr_info("%s: SDS enabled\n", __func__); + latch_sts = rtpcs_sds_read_bits(sds, 0x4, 1, 2, 2); + mdelay(1); + latch_sts = rtpcs_sds_read_bits(sds, 0x4, 1, 2, 2); + if (latch_sts) { + rtpcs_930x_sds_do_rx_calibration_dfe_disable(sds); + rtpcs_930x_sds_do_rx_calibration_4(sds); + rtpcs_930x_sds_do_rx_calibration_5(sds, hw_mode); + } + } +} + +static int rtpcs_930x_sds_sym_err_reset(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + int channel, channels; + + switch (hw_mode) { + case RTPCS_SDS_MODE_10GBASER: + case RTPCS_SDS_MODE_USXGMII_10GSXGMII: + /* Read twice to clear */ + rtpcs_sds_read(sds, 0x5, 0x1); + rtpcs_sds_read(sds, 0x5, 0x1); + return 0; + + case RTPCS_SDS_MODE_XSGMII: + case RTPCS_SDS_MODE_QSGMII: + channels = 4; + break; + + default: + channels = 1; + } + + for (channel = 0; channel < channels; channel++) { + if (hw_mode == RTPCS_SDS_MODE_XSGMII) { + rtpcs_sds_xsg_write_bits(sds, 0x1, 0x18, 2, 0, channel); + rtpcs_sds_xsg_write_bits(sds, 0x1, 0x3, 15, 8, 0x0); + rtpcs_sds_xsg_write_bits(sds, 0x1, 0x2, 15, 0, 0x0); + } else { + rtpcs_sds_write_bits(sds, 0x1, 0x18, 2, 0, channel); + rtpcs_sds_write_bits(sds, 0x1, 0x3, 15, 8, 0x0); + rtpcs_sds_write_bits(sds, 0x1, 0x2, 15, 0, 0x0); + } + } + + if (channels > 1) { + if (hw_mode == RTPCS_SDS_MODE_XSGMII) { + rtpcs_sds_xsg_write_bits(sds, 0x1, 0x0, 15, 0, 0x0); + rtpcs_sds_xsg_write_bits(sds, 0x1, 0x1, 15, 8, 0x0); + } else { + rtpcs_sds_write_bits(sds, 0x1, 0x0, 15, 0, 0x0); + rtpcs_sds_write_bits(sds, 0x1, 0x1, 15, 8, 0x0); + } + } + + return 0; +} + +static u32 rtpcs_930x_sds_sym_err_get(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + u32 v = 0; + + switch (hw_mode) { + case RTPCS_SDS_MODE_QSGMII: + case RTPCS_SDS_MODE_XSGMII: + v = rtpcs_sds_read_bits(sds, 0x1, 0x1, 15, 8) << 16; /* ALL_SYMBOLERR_CNT_NEW_23_16 */ + v |= rtpcs_sds_read_bits(sds, 0x1, 0x0, 15, 0); /* ALL_SYMBOLERR_CNT_NEW_15_0 */ + break; + + case RTPCS_SDS_MODE_USXGMII_10GQXGMII: + break; + + case RTPCS_SDS_MODE_1000BASEX: + case RTPCS_SDS_MODE_SGMII: + case RTPCS_SDS_MODE_10GBASER: + case RTPCS_SDS_MODE_USXGMII_10GSXGMII: + v = rtpcs_sds_read(sds, 0x5, 0x1); + v &= 0xff; + break; + + default: + rtpcs_sds_write_bits(sds, 0x1, 24, 2, 0, 0); + + v = rtpcs_sds_read_bits(sds, 0x1, 0x3, 15, 8) << 16; /* MUX_SYMBOLERR_CNT_NEW_23_16 */ + v |= rtpcs_sds_read_bits(sds, 0x1, 0x2, 15, 0); /* MUX_SYMBOLERR_CNT_NEW_15_0 */ + } + + return v; +} + +static int rtpcs_930x_sds_check_calibration(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + u32 errors1, errors2; + + rtpcs_930x_sds_sym_err_reset(sds, hw_mode); + rtpcs_930x_sds_sym_err_reset(sds, hw_mode); + + /* Count errors during 1ms */ + errors1 = rtpcs_930x_sds_sym_err_get(sds, hw_mode); + mdelay(1); + errors2 = rtpcs_930x_sds_sym_err_get(sds, hw_mode); + + switch (hw_mode) { + case RTPCS_SDS_MODE_XSGMII: + if ((errors2 - errors1 > 100) || + (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) { + pr_info("%s XSGMII error rate too high\n", __func__); + return 1; + } + break; + default: + if (errors2 > 0) { + pr_info("%s: symbol error rate too high\n", __func__); + return 1; + } + break; + } + + return 0; +} + +static void rtpcs_930x_phy_enable_10g_1g(struct rtpcs_serdes *sds) +{ + + u32 v; + + /* Enable 1GBit PHY */ + v = rtpcs_sds_read(sds, PHY_PAGE_2, MII_BMCR); + pr_info("%s 1gbit phy: %08x\n", __func__, v); + v &= ~BMCR_PDOWN; + rtpcs_sds_write(sds, PHY_PAGE_2, MII_BMCR, v); + pr_info("%s 1gbit phy enabled: %08x\n", __func__, v); + + /* Enable 10GBit PHY */ + v = rtpcs_sds_read(sds, PHY_PAGE_4, MII_BMCR); + pr_info("%s 10gbit phy: %08x\n", __func__, v); + v &= ~BMCR_PDOWN; + rtpcs_sds_write(sds, PHY_PAGE_4, MII_BMCR, v); + pr_info("%s 10gbit phy after: %08x\n", __func__, v); + + /* dal_longan_construct_mac_default_10gmedia_fiber */ + v = rtpcs_sds_read(sds, 0x1f, 11); + pr_info("%s set medium: %08x\n", __func__, v); + v |= BIT(1); + rtpcs_sds_write(sds, 0x1f, 11, v); + pr_info("%s set medium after: %08x\n", __func__, v); +} + +static int rtpcs_930x_sds_10g_idle(struct rtpcs_serdes *sds) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + ktime_t timeout; + int bit, busy; + + bit = (sds == even_sds) ? 0 : 1; + timeout = ktime_add_us(ktime_get(), 10000); /* timeout after 10 msecs */ + + do { + rtpcs_sds_write(even_sds, 0x1f, 0x2, 53); + busy = rtpcs_sds_read_bits(even_sds, 0x1f, 0x14, bit, bit); + if (busy < 0) + return busy; + + if (!busy) + return 0; + + usleep_range(100, 200); /* wait ~100 usecs before retry */ + } while (ktime_before(ktime_get(), timeout)); + + pr_warn("%s: WARNING Waiting for RX idle timed out, SDS %d\n", + __func__, sds->id); + return -ETIMEDOUT; +} + +static int rtpcs_930x_sds_set_polarity(struct rtpcs_serdes *sds, + bool tx_inv, bool rx_inv) +{ + u8 rx_val = rx_inv ? 1 : 0; + u8 tx_val = tx_inv ? 1 : 0; + u32 val; + int ret; + + /* 10GR */ + val = (tx_val << 1) | rx_val; + ret = rtpcs_sds_write_bits(sds, 0x6, 0x2, 14, 13, val); + if (ret) + return ret; + + /* 1G */ + val = (rx_val << 1) | tx_val; + return rtpcs_sds_write_bits(sds, 0x0, 0x0, 9, 8, val); +} + +static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_ana_com[] = { + {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, + {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, + {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008} +}; + +static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_ana_1g[] = { + {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, + {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311}, + {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, + {0x25, 0x00, 0x820F}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF}, + {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, + {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, + {0x25, 0x11, 0x8840} +}; + +static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_ana_3g[] = { + {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000}, {0x28, 0x0B, 0x1892}, + {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4}, {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, + {0x28, 0x16, 0x00C9}, {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400}, + {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF}, + {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001}, {0x29, 0x09, 0xFFD4}, + {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F}, {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, + {0x29, 0x11, 0x8840}, +}; + +static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_ana_10g[] = { + {0x2E, 0x00, 0xA668}, {0x2E, 0x01, 0x2088}, {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, + {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, + {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001}, + {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300}, {0x2F, 0x02, 0x1217}, + {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C}, {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, + {0x2F, 0x09, 0xFFD4}, {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121}, + {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, +}; + +static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_usxgmii_xsgmii[] = { + {0x2E, 0x12, 0x0484}, {0x2F, 0x02, 0x1017}, {0x2F, 0x07, 0x8104} +}; + +static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_5g_qsgmii[] = +{ + {0x21, 0x00, 0x3C91},{0x21, 0x02, 0xB602},{0x21, 0x07, 0xFA66},{0x21, 0x0A, 0xDF40}, + {0x2A, 0x02, 0x35A1},{0x2A, 0x03, 0x6960}, +}; + +static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_final_even[] = +{ + {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, + {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109}, {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, + {0x2D, 0x1C, 0x1109}, {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, + {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x66E1}, +}; + +static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_final_odd[] = +{ + {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, + {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808} +}; + +static void rtpcs_930x_sds_usxgmii_config(struct rtpcs_serdes *sds, bool nway_en, + u32 opcode, u32 am_period, + u32 all_am_markers, u32 an_table, + u32 sync_bit) +{ + /* this comes from USXGMII patch sequences of the SDK */ + rtpcs_sds_write(sds, 0x06, 0x00, 0x0000); + rtpcs_sds_write(sds, 0x06, 0x0D, 0x0F00); + rtpcs_sds_write(sds, 0x06, 0x1D, 0x0600); + rtpcs_sds_write(sds, 0x07, 0x06, 0x1401); /* CFG_QHSG_TXCFG_MAC_CH0 */ + + /* + * Controls the USXGMII AN mode. Two states are currently known: + * - 0x03: generic/standard-compliant mode + * - 0xaa: Realtek-proprietary mode (e.g. RTL8224) + */ + rtpcs_sds_write_bits(sds, 0x7, 0x10, 7, 0, opcode); /* CFG_QHSG_AN_OPC */ + /* CFG_QHSG_AN_EN_CHX: bits [3:0] enable AN on channels 3..0 */ + rtpcs_sds_write_bits(sds, 0x7, 0x11, 3, 0, nway_en ? 0xf : 0); + + rtpcs_sds_write_bits(sds, 0x6, 0x12, 15, 0, am_period); + rtpcs_sds_write_bits(sds, 0x6, 0x13, 7, 0, all_am_markers); /* CFG_AM0_M0 */ + rtpcs_sds_write_bits(sds, 0x6, 0x13, 15, 8, all_am_markers); /* CFG_AM0_M1 */ + rtpcs_sds_write_bits(sds, 0x6, 0x14, 7, 0, all_am_markers); /* CFG_AM0_M2 */ + rtpcs_sds_write_bits(sds, 0x6, 0x14, 15, 8, all_am_markers); /* CFG_AM1_M0 */ + rtpcs_sds_write_bits(sds, 0x6, 0x15, 7, 0, all_am_markers); /* CFG_AM1_M1 */ + rtpcs_sds_write_bits(sds, 0x6, 0x15, 15, 8, all_am_markers); /* CFG_AM1_M2 */ + rtpcs_sds_write_bits(sds, 0x6, 0x16, 7, 0, all_am_markers); /* CFG_AM2_M0 */ + rtpcs_sds_write_bits(sds, 0x6, 0x16, 15, 8, all_am_markers); /* CFG_AM2_M1 */ + rtpcs_sds_write_bits(sds, 0x6, 0x17, 7, 0, all_am_markers); /* CFG_AM2_M2 */ + rtpcs_sds_write_bits(sds, 0x6, 0x17, 15, 8, all_am_markers); /* CFG_AM3_M0 */ + rtpcs_sds_write_bits(sds, 0x6, 0x18, 7, 0, all_am_markers); /* CFG_AM3_M1 */ + rtpcs_sds_write_bits(sds, 0x6, 0x18, 15, 8, all_am_markers); /* CFG_AM3_M2 */ + rtpcs_sds_write_bits(sds, 0x6, 0xe, 10, 10, an_table); + rtpcs_sds_write_bits(sds, 0x6, 0x1d, 11, 10, sync_bit); + + rtpcs_sds_write_bits(sds, 0x06, 0x03, 15, 15, 0x1); /* FP_TGR3_CFG_EEE_EN */ +} + +static int rtpcs_930x_sds_config_hw_mode(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode) +{ + int (*apply_fn)(struct rtpcs_serdes *, const struct rtpcs_sds_config *, size_t); + bool is_xsgmii = (hw_mode == RTPCS_SDS_MODE_XSGMII); + bool is_even_sds = (sds == rtpcs_sds_get_even(sds)); + int ret; + + apply_fn = is_xsgmii ? rtpcs_sds_apply_config_xsg : rtpcs_sds_apply_config; + + /* USXGMII-QX broken, rely on bootloader setup */ + if (hw_mode == RTPCS_SDS_MODE_USXGMII_10GQXGMII) + return 0; + + if (hw_mode == RTPCS_SDS_MODE_QSGMII) { + if (sds->id >= 2) + return -ENOTSUPP; + + return rtpcs_sds_apply_config(sds, rtpcs_930x_sds_cfg_5g_qsgmii, + ARRAY_SIZE(rtpcs_930x_sds_cfg_5g_qsgmii)); + } + + if (hw_mode != RTPCS_SDS_MODE_USXGMII_10GSXGMII && + hw_mode != RTPCS_SDS_MODE_USXGMII_10GQXGMII) { + if (is_xsgmii) + rtpcs_sds_xsg_write(sds, 0x00, 0x0E, 0x3053); + else { + rtpcs_sds_write(sds, 0x00, 0x0E, 0x3053); + rtpcs_sds_write(sds, 0x01, 0x14, 0x0100); + } + } + + ret = apply_fn(sds, rtpcs_930x_sds_cfg_ana_com, ARRAY_SIZE(rtpcs_930x_sds_cfg_ana_com)); + if (ret < 0) + return ret; + + switch (hw_mode) { + case RTPCS_SDS_MODE_1000BASEX: + case RTPCS_SDS_MODE_SGMII: + ret = rtpcs_sds_apply_config(sds, rtpcs_930x_sds_cfg_ana_1g, + ARRAY_SIZE(rtpcs_930x_sds_cfg_ana_1g)); + if (ret < 0) + return ret; + + break; + + case RTPCS_SDS_MODE_10GBASER: + rtpcs_sds_write(sds, 0x06, 0x0D, 0x0F00); + rtpcs_sds_write(sds, 0x06, 0x00, 0x0000); + rtpcs_sds_write(sds, 0x06, 0x01, 0xC800); + /* + * TODO: Do the 1G and 3G sequences need to be applied? The SDK usually + * uses a 10GR-1000BX automatic mode covering all speeds. But in Linux, + * we switch the mode on demand so might only need to apply one sequence + * at a time. + */ + ret = rtpcs_sds_apply_config(sds, rtpcs_930x_sds_cfg_ana_1g, + ARRAY_SIZE(rtpcs_930x_sds_cfg_ana_1g)); + if (ret < 0) + return ret; + + ret = rtpcs_sds_apply_config(sds, rtpcs_930x_sds_cfg_ana_3g, + ARRAY_SIZE(rtpcs_930x_sds_cfg_ana_3g)); + if (ret < 0) + return ret; + + ret = rtpcs_sds_apply_config(sds, rtpcs_930x_sds_cfg_ana_10g, + ARRAY_SIZE(rtpcs_930x_sds_cfg_ana_10g)); + if (ret < 0) + return ret; + + rtpcs_sds_write(sds, 0x2F, 0x14, 0xE008); + break; + + case RTPCS_SDS_MODE_2500BASEX: + ret = rtpcs_sds_apply_config(sds, rtpcs_930x_sds_cfg_ana_1g, + ARRAY_SIZE(rtpcs_930x_sds_cfg_ana_1g)); + if (ret < 0) + return ret; + + ret = rtpcs_sds_apply_config(sds, rtpcs_930x_sds_cfg_ana_3g, + ARRAY_SIZE(rtpcs_930x_sds_cfg_ana_3g)); + if (ret < 0) + return ret; + + break; + + case RTPCS_SDS_MODE_XSGMII: + case RTPCS_SDS_MODE_USXGMII_10GSXGMII: + ret = apply_fn(sds, rtpcs_930x_sds_cfg_ana_10g, + ARRAY_SIZE(rtpcs_930x_sds_cfg_ana_10g)); + if (ret < 0) + return ret; + + ret = apply_fn(sds, rtpcs_930x_sds_cfg_usxgmii_xsgmii, + ARRAY_SIZE(rtpcs_930x_sds_cfg_usxgmii_xsgmii)); + if (ret < 0) + return ret; + + if (hw_mode == RTPCS_SDS_MODE_USXGMII_10GSXGMII) + /* opcode 0x03: standard/generic USXGMII mode */ + rtpcs_930x_sds_usxgmii_config(sds, true, 0x03, 0xa4, 0, 1, 0x1); + break; + + default: + return 0; + } + + if (is_even_sds) + ret = apply_fn(sds, rtpcs_930x_sds_cfg_final_even, + ARRAY_SIZE(rtpcs_930x_sds_cfg_final_even)); + else + ret = apply_fn(sds, rtpcs_930x_sds_cfg_final_odd, + ARRAY_SIZE(rtpcs_930x_sds_cfg_final_odd)); + + if (ret < 0) + return ret; + + if (hw_mode == RTPCS_SDS_MODE_10GBASER && is_even_sds) + rtpcs_sds_write(sds, 0x2F, 0x1D, 0x76E1); + + return 0; +} + +__always_unused +static int rtpcs_930x_sds_cmu_band_get(struct rtpcs_serdes *sds) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + struct rtpcs_serdes *odd_sds = rtpcs_sds_get_odd(sds); + u32 page; + u32 en; + u32 cmu_band; + +/* page = rtl9300_sds_cmu_page_get(sds); */ + page = 0x25; /* 10GR and 1000BX */ + + rtpcs_sds_write_bits(even_sds, page, 0x1c, 15, 15, 1); + rtpcs_sds_write_bits(odd_sds, page, 0x1c, 15, 15, 1); + + en = rtpcs_sds_read_bits(even_sds, page, 27, 1, 1); + if (!en) { /* Auto mode */ + rtpcs_sds_write(even_sds, 0x1f, 0x02, 31); + + cmu_band = rtpcs_sds_read_bits(even_sds, 0x1f, 0x15, 5, 1); + } else { + cmu_band = rtpcs_sds_read_bits(even_sds, page, 30, 4, 0); + } + + return cmu_band; +} + +static int rtpcs_930x_setup_serdes(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + int calib_tries = 0, ret; + + /* Turn Off Serdes */ + ret = rtpcs_930x_sds_set_mode(sds, RTPCS_SDS_MODE_OFF); + if (ret < 0) + return ret; + + /* Apply configuration for a hardware mode to SerDes */ + ret = rtpcs_930x_sds_config_hw_mode(sds, hw_mode); + if (ret < 0) + return ret; + + /* Maybe use dal_longan_sds_init */ + + /* dal_longan_construct_serdesConfig_init */ /* Serdes Construct */ + rtpcs_930x_phy_enable_10g_1g(sds); + + /* Set SDS polarity */ + rtpcs_930x_sds_set_polarity(sds, sds->tx_pol_inv, sds->rx_pol_inv); + + /* Enable SDS in desired mode */ + ret = rtpcs_930x_sds_set_mode(sds, hw_mode); + if (ret < 0) + return ret; + + sds->hw_mode = hw_mode; + + /* Enable Fiber RX */ + rtpcs_sds_write_bits(sds, 0x20, 2, 12, 12, 0); + + if (hw_mode == RTPCS_SDS_MODE_QSGMII) + goto skip_cali; + + /* Calibrate SerDes receiver in loopback mode */ + rtpcs_930x_sds_10g_idle(sds); + do { + rtpcs_930x_sds_do_rx_calibration(sds, hw_mode); + calib_tries++; + mdelay(50); + } while (rtpcs_930x_sds_check_calibration(sds, hw_mode) && calib_tries < 3); + if (calib_tries >= 3) + pr_warn("%s: SerDes RX calibration failed\n", __func__); + +skip_cali: + /* Leave loopback mode */ + rtpcs_930x_sds_tx_config(sds, hw_mode); + + return 0; +} + +/* RTL931X */ + +/* + * The SerDes MDIO driver maps page regions to different background SerDes. + * 0x00 - 0x3f analog SDS + * 0x40 - 0x7f digital SDS 1 + * 0x80 - 0xbf digital SDS 2 + * + * An XSG write operates on digital SDS 1 and digital SDS 2. Map that to the + * page ranges accordingly. + */ +static int rtpcs_931x_sds_op_xsg_write(struct rtpcs_serdes *sds, int page, int regnum, + int bithigh, int bitlow, u16 value) +{ + int ret; + + ret = __rtpcs_sds_write_raw(sds->ctrl, sds->id, page + 0x40, regnum, bithigh, bitlow, + value); + if (ret) + return ret; + + return __rtpcs_sds_write_raw(sds->ctrl, sds->id, page + 0x80, regnum, bithigh, bitlow, + value); +} + +__maybe_unused +static int rtpcs_931x_sds_fiber_get_symerr(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + int symerr, val, val2; + + switch (hw_mode) { + case RTPCS_SDS_MODE_10GBASER: + symerr = rtpcs_sds_read_bits(sds, 0x5, 0x1, 7, 0); + break; + case RTPCS_SDS_MODE_1000BASEX: + rtpcs_sds_write_bits(sds, 0x41, 0x18, 2, 0, 0x0); + + val = rtpcs_sds_read_bits(sds, 0x41, 0x3, 15, 8); + val2 = rtpcs_sds_read_bits(sds, 0x41, 0x2, 15, 0); + symerr = (val << 16) | val2; + break; + default: + symerr = -EINVAL; + } + + return symerr; +} + +static void rtpcs_931x_sds_clear_symerr(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + switch (hw_mode) { + case RTPCS_SDS_MODE_SGMII: + case RTPCS_SDS_MODE_HISGMII: + case RTPCS_SDS_MODE_XSGMII: + for (int i = 0; i < 4; ++i) { + rtpcs_sds_write_bits(sds, 0x41, 0x18, 2, 0, i); + rtpcs_sds_write_bits(sds, 0x41, 0x3, 15, 8, 0x0); + rtpcs_sds_write_bits(sds, 0x41, 0x2, 15, 0, 0x0); + } + + for (int i = 0; i < 4; ++i) { + rtpcs_sds_write_bits(sds, 0x81, 0x18, 2, 0, i); + rtpcs_sds_write_bits(sds, 0x81, 0x3, 15, 8, 0x0); + rtpcs_sds_write_bits(sds, 0x81, 0x2, 15, 0, 0x0); + } + + rtpcs_sds_write_bits(sds, 0x41, 0x0, 15, 0, 0x0); + rtpcs_sds_write_bits(sds, 0x41, 0x1, 15, 8, 0x0); + rtpcs_sds_write_bits(sds, 0x81, 0x0, 15, 0, 0x0); + rtpcs_sds_write_bits(sds, 0x81, 0x1, 15, 8, 0x0); + break; + case RTPCS_SDS_MODE_1000BASEX: + rtpcs_sds_write_bits(sds, 0x41, 0x18, 2, 0, 0x0); + rtpcs_sds_write_bits(sds, 0x41, 0x3, 15, 8, 0x0); + rtpcs_sds_write_bits(sds, 0x41, 0x2, 15, 0, 0x0); + break; + case RTPCS_SDS_MODE_10GBASER: + /* to be verified: clear on read? */ + rtpcs_sds_read_bits(sds, 0x5, 0x1, 7, 0); + break; + case RTPCS_SDS_MODE_OFF: + default: + break; + } +} + +/** + * rtpcs_931x_sds_reset_leq_dfe() - Reset LEQ + DFE to a baseline. + * + * @sds: Reference to SerDes instance + * + * Reset both LEQ and DFE in the RX path to baseline configuration. I.e. + * sets LEQ and DFE to manual mode and sets certain values (mostly 0) for + * LEQ and DFE coefficients/parameters. + * + * LEQ and DFE can run in two modes: + * * manual: specific values are set and used + * * auto: both adapt their parameters automatically + * + */ +static int rtpcs_931x_sds_reset_leq_dfe(struct rtpcs_serdes *sds) +{ + rtpcs_sds_write_bits(sds, 0x2e, 0xd, 6, 0, 0x0); /* [6:2] LEQ gain */ + rtpcs_sds_write_bits(sds, 0x2e, 0xd, 7, 7, 0x1); /* LEQ manual 1=true,0=false */ + + rtpcs_sds_write_bits(sds, 0x2e, 0x1c, 5, 0, 0x1e); /* TAP0 */ + rtpcs_sds_write_bits(sds, 0x2e, 0x1d, 11, 0, 0x0); /* TAP1 [11:6] ODD | [5:0] EVEN */ + rtpcs_sds_write_bits(sds, 0x2e, 0x1f, 11, 0, 0x0); /* TAP2 [11:6] ODD | [5:0] EVEN */ + rtpcs_sds_write_bits(sds, 0x2f, 0x0, 11, 0, 0x0); /* TAP3 [11:6] ODD | [5:0] EVEN */ + rtpcs_sds_write_bits(sds, 0x2f, 0x1, 11, 0, 0x0); /* TAP4 [11:6] ODD | [5:0] EVEN */ + + rtpcs_sds_write_bits(sds, 0x2e, 0xf, 12, 6, 0x7f); /* set manual mode */ + rtpcs_sds_write(sds, 0x2f, 0x12, 0xaaa); /* [11:8] VTHN | [7:4] VTHP */ + + return 0; +} + +static int rtpcs_931x_sds_power(struct rtpcs_serdes *sds, bool power_on) +{ + u32 en_val = power_on ? 0 : BIT(sds->id); + + return regmap_write_bits(sds->ctrl->map, + RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR, + BIT(sds->id), en_val); +} + +/* + * rtpcs_931x_sds_set_mac_mode + * + * Set the SerDes mode in the MAC's registers. + */ +static int rtpcs_931x_sds_set_mac_mode(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + u32 mode_val; + int shift = ((sds->id & 0x3) << 3); + + switch (hw_mode) { + case RTPCS_SDS_MODE_OFF: + mode_val = 0x1f; + break; + case RTPCS_SDS_MODE_QSGMII: + mode_val = 0x6; + break; + case RTPCS_SDS_MODE_HISGMII: + mode_val = 0x12; + break; + case RTPCS_SDS_MODE_XSGMII: + mode_val = 0x10; + break; + case RTPCS_SDS_MODE_USXGMII_10GSXGMII: + case RTPCS_SDS_MODE_USXGMII_10GDXGMII: + case RTPCS_SDS_MODE_USXGMII_10GQXGMII: + case RTPCS_SDS_MODE_USXGMII_5GSXGMII: + case RTPCS_SDS_MODE_USXGMII_5GDXGMII: + case RTPCS_SDS_MODE_USXGMII_2_5GSXGMII: + mode_val = 0xd; + break; + case RTPCS_SDS_MODE_SGMII: + mode_val = 0x2; + break; + default: + return -EINVAL; + } + + mode_val |= BIT(7); /* force mode bit */ + return regmap_write_bits(sds->ctrl->map, + RTL931X_SERDES_MODE_CTRL + 4 * (sds->id >> 2), + 0xff << shift, mode_val << shift); +} + +/* + * rtpcs_931x_sds_set_ip_mode + * + * Set the SerDes mode in the SerDes IP block's registers. + */ +static int rtpcs_931x_sds_set_ip_mode(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + u32 mode_val; + + /* clear symbol error count before changing mode */ + rtpcs_931x_sds_clear_symerr(sds, hw_mode); + rtpcs_931x_sds_set_mac_mode(sds, RTPCS_SDS_MODE_OFF); + + switch (hw_mode) { + case RTPCS_SDS_MODE_OFF: + mode_val = 0x3f; + break; + + case RTPCS_SDS_MODE_SGMII: + mode_val = 0x5; + break; + + case RTPCS_SDS_MODE_1000BASEX: + /* serdes mode FIBER1G */ + mode_val = 0x9; + break; + + case RTPCS_SDS_MODE_2500BASEX: + /* available SDK code doesn't have this value. based on brute-forcing + * the SerDes mode register field until the link is working + */ + mode_val = 0x2d; + break; + + case RTPCS_SDS_MODE_10GBASER: + mode_val = 0x35; + break; +/* case MII_10GR1000BX_AUTO: + mode_val = 0x39; + break; */ + + case RTPCS_SDS_MODE_USXGMII_10GSXGMII: + case RTPCS_SDS_MODE_USXGMII_10GDXGMII: + case RTPCS_SDS_MODE_USXGMII_10GQXGMII: + case RTPCS_SDS_MODE_USXGMII_5GSXGMII: + case RTPCS_SDS_MODE_USXGMII_5GDXGMII: + case RTPCS_SDS_MODE_USXGMII_2_5GSXGMII: + mode_val = 0x1b; + break; + case RTPCS_SDS_MODE_HISGMII: + mode_val = 0x25; + break; + default: + return -ENOTSUPP; + } + + pr_info("%s writing analog SerDes Mode value %02x\n", __func__, mode_val); + return rtpcs_sds_write_bits(sds, 0x1f, 0x9, 11, 6, mode_val); +} + +static int rtpcs_931x_sds_set_mode(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + if (hw_mode == RTPCS_SDS_MODE_XSGMII) + return rtpcs_931x_sds_set_mac_mode(sds, hw_mode); + else + return rtpcs_931x_sds_set_ip_mode(sds, hw_mode); +} + +static void rtpcs_931x_sds_reset(struct rtpcs_serdes *sds) +{ + struct rtpcs_ctrl *ctrl = sds->ctrl; + u32 sds_id = sds->id; + u32 v, o_mode; + int shift = ((sds_id & 0x3) << 3); + + /* TODO: We need to lock this! */ + + rtpcs_931x_sds_power(sds, false); + + regmap_read(ctrl->map, RTL931X_SERDES_MODE_CTRL + 4 * (sds_id >> 2), &o_mode); + v = BIT(7) | 0x1F; + regmap_write_bits(ctrl->map, RTL931X_SERDES_MODE_CTRL + 4 * (sds_id >> 2), + 0xff << shift, v << shift); + regmap_write(ctrl->map, RTL931X_SERDES_MODE_CTRL + 4 * (sds_id >> 2), o_mode); + + rtpcs_931x_sds_power(sds, true); +} + +static void rtpcs_931x_sds_rx_reset(struct rtpcs_serdes *sds) +{ + if (sds->id < 2) + return; + + rtpcs_sds_write(sds, 0x2e, 0x12, 0x2740); + rtpcs_sds_write(sds, 0x2f, 0x0, 0x0); /* [11:6] DFE_TAP3_ODD | [5:0] DFE_TAP3_EVEN */ + rtpcs_sds_write(sds, 0x2f, 0x2, 0x2010); + rtpcs_sds_write(sds, 0x20, 0x0, 0xc10); + + rtpcs_sds_write(sds, 0x2e, 0x12, 0x27c0); + rtpcs_sds_write(sds, 0x2f, 0x0, 0xc000); /* [11:6] DFE_TAP3_ODD | [5:0] DFE_TAP3_EVEN */ + rtpcs_sds_write(sds, 0x2f, 0x2, 0x6010); + rtpcs_sds_write(sds, 0x20, 0x0, 0xc30); + + mdelay(50); +} + +static int rtpcs_931x_sds_cmu_page_get(enum rtpcs_sds_mode hw_mode) +{ + switch (hw_mode) { + case RTPCS_SDS_MODE_SGMII: + case RTPCS_SDS_MODE_1000BASEX: + return 0x24; /* ANA_1G */ + case RTPCS_SDS_MODE_2500BASEX: + return 0x28; /* ANA_3G */ + case RTPCS_SDS_MODE_QSGMII: + return 0x2a; /* ANA_5G/6G */ + // return 0x34; + case RTPCS_SDS_MODE_XSGMII: + case RTPCS_SDS_MODE_USXGMII_10GSXGMII: + case RTPCS_SDS_MODE_USXGMII_10GDXGMII: + case RTPCS_SDS_MODE_USXGMII_10GQXGMII: + case RTPCS_SDS_MODE_USXGMII_5GSXGMII: + case RTPCS_SDS_MODE_USXGMII_5GDXGMII: + case RTPCS_SDS_MODE_USXGMII_2_5GSXGMII: + case RTPCS_SDS_MODE_10GBASER: + return 0x2e; /* ANA_10G */ + default: + return -ENOTSUPP; + } +} + +static int rtpcs_931x_sds_get_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type *pll) +{ + int cmu_page, pll_sel; + + cmu_page = rtpcs_931x_sds_cmu_page_get(sds->hw_mode); + if (cmu_page < 0) + return cmu_page; + + pll_sel = rtpcs_sds_read_bits(sds, cmu_page, 0x7, 15, 15); + if (pll_sel < 0) + return pll_sel; + + *pll = (enum rtpcs_sds_pll_type)pll_sel; + return 0; +} + +static int rtpcs_931x_sds_set_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode, + enum rtpcs_sds_pll_type pll) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int cmu_page, ret, val; + int frc_lc_mode_bit; + + cmu_page = rtpcs_931x_sds_cmu_page_get(hw_mode); + if (cmu_page < 0) + return cmu_page; + + /* + * bits [5:4] (even) / [7:6] (odd) are used by RTL930x as selector. The selector + * for RTL931x SerDes is in the CMU page of each SerDes, depending on the hardware + * mode. + * + * Here, the SDK calls them 'frc_lc_mode' and 'frc_lc_mode_val'. However, they don't + * seem to have any effect and thus their purpose is unknown. So just set them as + * the SDK does. + */ + val = (pll == RTPCS_SDS_PLL_TYPE_LC) ? 0x3 : 0x1; + frc_lc_mode_bit = (sds == even_sds) ? 4 : 6; + ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, frc_lc_mode_bit + 1, + frc_lc_mode_bit, val); + if (ret < 0) + return ret; + + return rtpcs_sds_write_bits(sds, cmu_page, 0x7, 15, 15, pll); +} + +static int rtpcs_931x_sds_reconfigure_to_pll(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll) +{ + enum rtpcs_sds_pll_type tmp_pll; + enum rtpcs_sds_pll_speed speed; + enum rtpcs_sds_mode tmp_mode; + int ret; + + /* assume we always reconfigure to the other PLL */ + tmp_pll = (pll == RTPCS_SDS_PLL_TYPE_LC) ? RTPCS_SDS_PLL_TYPE_RING : RTPCS_SDS_PLL_TYPE_LC; + + ret = rtpcs_93xx_sds_get_pll_config(sds, tmp_pll, &speed); + if (ret < 0) + return ret; + + tmp_mode = sds->hw_mode; + + /* turn off SerDes for reconfiguration */ + ret = rtpcs_931x_sds_power(sds, false); + if (ret < 0) + return ret; + + ret = rtpcs_931x_sds_set_mode(sds, RTPCS_SDS_MODE_OFF); + if (ret < 0) + return ret; + + /* reconfigure to other PLL */ + ret = rtpcs_93xx_sds_set_pll_config(sds, pll, speed); + if (ret < 0) + return ret; + + ret = rtpcs_931x_sds_set_pll_select(sds, sds->hw_mode, pll); + if (ret < 0) + return ret; + + /* turn on SerDes again */ + ret = rtpcs_931x_sds_set_mode(sds, tmp_mode); + if (ret < 0) + return ret; + + return rtpcs_931x_sds_power(sds, true); +} + +static int rtpcs_931x_sds_cmu_band_set(struct rtpcs_serdes *sds, + bool enable, u32 band, + enum rtpcs_sds_mode hw_mode) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int page = rtpcs_931x_sds_cmu_page_get(hw_mode); + int en_val; + + if (page < 0) + return -EINVAL; + + page += 1; + en_val = enable ? 0 : 1; + + rtpcs_sds_write_bits(even_sds, page, 0x7, 13, 13, en_val); + rtpcs_sds_write_bits(even_sds, page, 0x7, 11, 11, en_val); + rtpcs_sds_write_bits(even_sds, page, 0x7, 4, 0, band); + + rtpcs_931x_sds_reset(even_sds); + + return 0; +} + +__maybe_unused +static int rtpcs_931x_sds_cmu_band_get(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int page = rtpcs_931x_sds_cmu_page_get(hw_mode); + + if (page < 0) + return -EINVAL; + + page += 1; + rtpcs_sds_write(even_sds, 0x1f, 0x02, 73); + rtpcs_sds_write_bits(even_sds, page, 0x5, 15, 15, 0x1); + + return rtpcs_sds_read_bits(even_sds, 0x1f, 0x15, 8, 3); +} + +__always_unused +static int rtpcs_931x_sds_link_sts_get(struct rtpcs_serdes *sds) +{ + u32 sts, sts1, latch_sts, latch_sts1; + + switch (sds->hw_mode) { + case RTPCS_SDS_MODE_XSGMII: + sts = rtpcs_sds_read_bits(sds, 0x41, 29, 8, 0); + sts1 = rtpcs_sds_read_bits(sds, 0x81, 29, 8, 0); + latch_sts = rtpcs_sds_read_bits(sds, 0x41, 30, 8, 0); + latch_sts1 = rtpcs_sds_read_bits(sds, 0x81, 30, 8, 0); + break; + + case RTPCS_SDS_MODE_SGMII: + case RTPCS_SDS_MODE_HISGMII: + case RTPCS_SDS_MODE_2500BASEX: + sts = rtpcs_sds_read_bits(sds, 0x41, 29, 8, 0); + latch_sts = rtpcs_sds_read_bits(sds, 0x41, 30, 8, 0); + break; + + default: + sts = rtpcs_sds_read_bits(sds, 0x5, 0, 12, 12); + latch_sts = rtpcs_sds_read_bits(sds, 0x4, 1, 2, 2); + latch_sts1 = rtpcs_sds_read_bits(sds, 0x42, 1, 2, 2); + sts1 = rtpcs_sds_read_bits(sds, 0x42, 1, 2, 2); + } + + pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__, + sds->id, sts, sts1, latch_sts, latch_sts1); + + return sts1; +} + +static int rtpcs_931x_sds_set_polarity(struct rtpcs_serdes *sds, + bool tx_inv, bool rx_inv) +{ + u8 rx_val = rx_inv ? 1 : 0; + u8 tx_val = tx_inv ? 1 : 0; + u32 val; + int ret; + + /* 10gr_*_inv */ + val = (tx_val << 1) | rx_val; + ret = rtpcs_sds_write_bits(sds, 0x6, 0x2, 14, 13, val); + if (ret) + return ret; + + /* xsg_*_inv */ + val = (rx_val << 1) | tx_val; + ret = rtpcs_sds_write_bits(sds, 0x40, 0x0, 9, 8, val); + if (ret) + return ret; + + return rtpcs_sds_write_bits(sds, 0x80, 0x0, 9, 8, val); +} + +static int rtpcs_931x_sds_set_port_media(struct rtpcs_serdes *sds, + enum rtpcs_port_media port_media) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + bool is_dac, is_10g; + + /* + * SDK identifies this as some kind of gating. It's enabled + * here and later deactivated for non-10G. + * (from DMS1250 SDK) + */ + rtpcs_sds_write_bits(sds, 0x5f, 0x1, 0, 0, 0x1); + + /* media none behavior */ + rtpcs_sds_write(sds, 0x2e, 0x12, 0x2740); + rtpcs_sds_write(sds, 0x2f, 0x0, 0x0); /* [11:6] DFE_TAP3_ODD | [5:0] DFE_TAP3_EVEN */ + rtpcs_sds_write(sds, 0x2f, 0x2, 0x2010); + rtpcs_sds_write(sds, 0x20, 0x0, 0xcd1); /* from 930x: [7:6] POWER_DOWN OF ?? */ + rtpcs_sds_write_bits(sds, 0x2e, 0xf, 5, 0, 0x4); + + rtpcs_sds_write_bits(sds, 0x2a, 0x12, 7, 6, 0x1); + /* TODO: can we drop this in favor of turning off SerDes ealier? */ + rtpcs_931x_sds_set_mode(sds, RTPCS_SDS_MODE_OFF); + + if (port_media == RTPCS_PORT_MEDIA_NONE) + return 0; + + rtpcs_sds_write(sds, 0x21, 0x19, 0xf0f0); /* from XS1930-10 SDK */ + rtpcs_sds_write(even_sds, 0x2e, 0x8, 0x0294); /* [10:7] impedance */ + + /* from _phy_rtl9310_sds_init, DMS1250 SDK */ + rtpcs_sds_write_bits(sds, 0x2e, 0xe, 13, 11, 0x0); + rtpcs_931x_sds_rx_reset(sds); + rtpcs_931x_sds_reset_leq_dfe(sds); + + is_dac = (port_media == RTPCS_PORT_MEDIA_DAC_50CM || + port_media == RTPCS_PORT_MEDIA_DAC_100CM || + port_media == RTPCS_PORT_MEDIA_DAC_300CM || + port_media == RTPCS_PORT_MEDIA_DAC_500CM); + is_10g = is_dac || port_media == RTPCS_PORT_MEDIA_FIBER_10G; + + if (port_media != RTPCS_PORT_MEDIA_FIBER_100M) { + rtpcs_sds_write_bits(sds, 0x20, 0x0, 11, 10, 0x0); + rtpcs_sds_write_bits(sds, 0x2a, 0x7, 15, 15, is_dac ? 0x1 : 0x0); + rtpcs_sds_write_bits(sds, 0x20, 0x0, 11, 10, 0x3); + } + + switch (port_media) { + case RTPCS_PORT_MEDIA_DAC_50CM: + case RTPCS_PORT_MEDIA_DAC_100CM: + rtpcs_sds_write_bits(sds, 0x2e, 0x1, 15, 0, 0x1340); + rtpcs_sds_write(sds, 0x21, 0x19, 0xf0a5); /* from XS1930-10 SDK */ + rtpcs_sds_write(even_sds, 0x2e, 0x8, 0x02a0); /* [10:7] impedance */ + break; + + case RTPCS_PORT_MEDIA_DAC_300CM: + case RTPCS_PORT_MEDIA_DAC_500CM: + rtpcs_sds_write_bits(sds, 0x2e, 0x1, 15, 0, 0x5200); + rtpcs_sds_write(sds, 0x21, 0x19, 0xf0a5); /* from XS1930-10 SDK */ + rtpcs_sds_write(even_sds, 0x2e, 0x8, 0x02a0); /* [10:7] impedance */ + break; + + case RTPCS_PORT_MEDIA_FIBER_10G: + /* + * TODO: this would need to be saved during early init, before + * actually changing any SerDes settings. Then restored here. + * see phy_rtl9310_init in SDK + */ + // rtpcs_sds_write(sds, 0x2e, 0x1, phy_rtl9310_10g_tx[unit][sds]); + rtpcs_sds_write_bits(sds, 0x2e, 0xf, 5, 0, 0x2); /* from DMS1250 SDK */ + break; + default: + break; + } + + /* CFG_LINKDW_SEL? (same semantics as 930x) */ + rtpcs_sds_write_bits(sds, 0x6, 0xd, 6, 6, is_dac ? 0x0 : 0x1); + + if (is_10g) { + rtpcs_sds_write(sds, 0x2e, 0x12, 0x27c0); + rtpcs_sds_write(sds, 0x2f, 0x0, 0xc000); /* [11:6] DFE_TAP3_ODD | [5:0] DFE_TAP3_EVEN */ + rtpcs_sds_write(sds, 0x2f, 0x2, 0x6010); + } + + /* FIXME: is this redundant with the writes below? */ + rtpcs_sds_write(sds, 0x20, 0x0, 0xc30); /* from 930x: [7:6] POWER_DOWN OF ?? */ + rtpcs_sds_write_bits(sds, 0x20, 0x0, 9, 0, 0x30); + rtpcs_sds_write_bits(sds, 0x2a, 0x12, 7, 6, 0x3); + + rtpcs_sds_write_bits(sds, 0x20, 0x0, 11, 10, 0x1); + rtpcs_sds_write_bits(sds, 0x20, 0x0, 11, 10, 0x3); + + /* clear pending SerDes RX idle interrupt flag */ + regmap_write_bits(sds->ctrl->map, RTPCS_931X_ISR_SERDES_RXIDLE, + BIT(sds->id - 2), BIT(sds->id - 2)); + + /* Gating as mentioned above, deactivated here for non-10G */ + if (!is_10g) + rtpcs_sds_write_bits(sds, 0x5f, 0x1, 0, 0, 0x0); + + return 0; +} + +static int rtpcs_931x_sds_config_fiber_1g(struct rtpcs_serdes *sds) +{ + rtpcs_sds_write_bits(sds, 0x43, 0x12, 15, 14, 0x0); + + rtpcs_sds_write_bits(sds, 0x42, 0x0, 6, 6, 0x1); + rtpcs_sds_write_bits(sds, 0x42, 0x0, 13, 13, 0x0); + + return 0; +} + +static int rtpcs_931x_sds_config_hw_mode(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + switch (hw_mode) { + case RTPCS_SDS_MODE_OFF: + break; + + case RTPCS_SDS_MODE_1000BASEX: + rtpcs_931x_sds_config_fiber_1g(sds); + break; + + case RTPCS_SDS_MODE_2500BASEX: + rtpcs_sds_write_bits(sds, 0x41, 0x14, 8, 8, 1); + break; + + case RTPCS_SDS_MODE_10GBASER: /* 10GR1000BX_AUTO */ + /* configure 10GR fiber mode=1 */ + rtpcs_sds_write_bits(sds, 0x1f, 0xb, 1, 1, 1); + + rtpcs_931x_sds_config_fiber_1g(sds); + + /* init auto */ + rtpcs_sds_write_bits(sds, 0x1f, 13, 15, 0, 0x109e); + rtpcs_sds_write_bits(sds, 0x1f, 0x6, 14, 10, 0x8); + rtpcs_sds_write_bits(sds, 0x1f, 0x7, 10, 4, 0x7f); + break; + + case RTPCS_SDS_MODE_SGMII: + rtpcs_sds_write_bits(sds, 0x24, 0x9, 15, 15, 0); + + /* TODO: where does this come from? SDK doesn't have this. */ + rtpcs_931x_sds_cmu_band_set(sds, true, 62, RTPCS_SDS_MODE_SGMII); + break; + + case RTPCS_SDS_MODE_XSGMII: + rtpcs_sds_write_bits(sds, 0x40, 0xE, 12, 12, 1); + rtpcs_sds_write_bits(sds, 0x80, 0xE, 12, 12, 1); + break; + + case RTPCS_SDS_MODE_USXGMII_10GSXGMII: + case RTPCS_SDS_MODE_USXGMII_10GDXGMII: + case RTPCS_SDS_MODE_USXGMII_10GQXGMII: + case RTPCS_SDS_MODE_USXGMII_5GSXGMII: + case RTPCS_SDS_MODE_USXGMII_5GDXGMII: + case RTPCS_SDS_MODE_USXGMII_2_5GSXGMII: + u32 op_code = 0x6003; + + rtpcs_931x_sds_reset_leq_dfe(sds); + rtpcs_931x_sds_rx_reset(sds); + + rtpcs_sds_write(sds, 0x7, 0x10, op_code); + rtpcs_sds_write(sds, 0x6, 0x1d, 0x0480); + rtpcs_sds_write(sds, 0x6, 0xe, 0x0400); + break; + + case RTPCS_SDS_MODE_QSGMII: + default: + return -ENOTSUPP; + } + + return 0; +} + +static int rtpcs_931x_setup_serdes(struct rtpcs_serdes *sds, + enum rtpcs_sds_mode hw_mode) +{ + u32 board_sds_tx[] = { + 0x1a00, 0x1a00, 0x0200, 0x0200, 0x0200, 0x0200, + 0x01a3, 0x01a3, 0x01a3, 0x01a3, 0x01e3, 0x01e3 + }; + u32 board_sds_tx2[] = { + 0x0dc0, 0x01c0, 0x0200, 0x0180, 0x0160, 0x0123, + 0x0123, 0x0163, 0x01a3, 0x01a0, 0x01c3, 0x09c3, + }; + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + struct rtpcs_ctrl *ctrl = sds->ctrl; + u32 sds_id = sds->id; + u32 val; + int ret; + + /* + * TODO: USXGMII is currently the swiss army knife to declare 10G + * multi port PHYs. Real devices use other modes instead. Especially + * + * - RTL8224 is driven in 10G_QXGMII + * - RTL8218D/E are driven in (Realtek proprietary) XSGMII (10G SGMII) + * + * For now, disable "USXGMII" modes we cannot configure properly. Only + * USXGMII_10GSXGMII is configured properly for now. + */ + if (hw_mode == RTPCS_SDS_MODE_USXGMII_10GDXGMII || + hw_mode == RTPCS_SDS_MODE_USXGMII_10GQXGMII || + hw_mode == RTPCS_SDS_MODE_XSGMII) + return 0; + + val = rtpcs_sds_read_bits(sds, 0x1F, 0x9, 11, 6); + + pr_info("%s: fibermode %08X stored mode 0x%x", __func__, + rtpcs_sds_read(sds, 0x1f, 0x9), val); + pr_info("%s: SGMII mode %08X in 0x24 0x9", __func__, + rtpcs_sds_read(sds, 0x24, 0x9)); + pr_info("%s: CMU mode %08X stored even SDS %d", __func__, + rtpcs_sds_read(even_sds, 0x20, 0x12), even_sds->id); + pr_info("%s: serdes_mode_ctrl %08X", __func__, RTL931X_SERDES_MODE_CTRL + 4 * (sds_id >> 2)); + pr_info("%s CMU page 0x24 0x7 %08x\n", __func__, rtpcs_sds_read(sds, 0x24, 0x7)); + pr_info("%s CMU page 0x26 0x7 %08x\n", __func__, rtpcs_sds_read(sds, 0x26, 0x7)); + pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtpcs_sds_read(sds, 0x28, 0x7)); + pr_info("%s XSG page 0x0 0xe %08x\n", __func__, rtpcs_sds_read(sds, 0x40, 0xe)); + pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__, rtpcs_sds_read(sds, 0x80, 0xe)); + pr_info("%s: 2.5gbit %08X", __func__, rtpcs_sds_read(sds, 0x41, 0x14)); + + rtpcs_931x_sds_power(sds, false); + + ret = rtpcs_931x_sds_config_hw_mode(sds, hw_mode); + if (ret < 0) + return ret; + + ret = rtpcs_93xx_sds_config_cmu(sds, hw_mode); + if (ret < 0) + return ret; + + switch (hw_mode) { + case RTPCS_SDS_MODE_OFF: + ret = rtpcs_931x_sds_set_port_media(sds, RTPCS_PORT_MEDIA_NONE); + break; + case RTPCS_SDS_MODE_2500BASEX: + ret = rtpcs_931x_sds_set_port_media(sds, RTPCS_PORT_MEDIA_FIBER_2_5G); + break; + case RTPCS_SDS_MODE_10GBASER: + ret = rtpcs_931x_sds_set_port_media(sds, RTPCS_PORT_MEDIA_FIBER_10G); + break; + case RTPCS_SDS_MODE_SGMII: + case RTPCS_SDS_MODE_1000BASEX: + ret = rtpcs_931x_sds_set_port_media(sds, RTPCS_PORT_MEDIA_FIBER_1G); + break; + default: + break; + } + + if (sds_id >= 2) { + if (ctrl->chip_version == RTPCS_CHIP_V2) + /* consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit)) */ + rtpcs_sds_write(sds, 0x2E, 0x1, board_sds_tx2[sds_id - 2]); + else + rtpcs_sds_write(sds, 0x2E, 0x1, board_sds_tx[sds_id - 2]); + } + + rtpcs_931x_sds_set_polarity(sds, sds->tx_pol_inv, sds->rx_pol_inv); + + rtpcs_931x_sds_power(sds, true); + + ret = rtpcs_931x_sds_set_mode(sds, hw_mode); + if (ret < 0) + return ret; + + sds->hw_mode = hw_mode; + + return 0; +} + +/** + * rtpcs_931x_init_mac_groups - Initialize MAC groups + * + * RTL931x organizes MACs into 12 groups (one per SerDes) that must be explicitly + * enabled before link establishment. Without initialization, link may fail or + * packets may be corrupted, especially in USXGMII/XSGMII modes. + * + * Simply enable all MACs by writing 0xffffffff to all group registers. Unused + * MACs and reserved bits are harmless, avoiding complex per-SerDes logic. + * + * This lives in the PCS driver since groups are tied to SerDes, and the DSA + * driver has no SerDes awareness. + */ +static int rtpcs_931x_init_mac_groups(struct rtpcs_ctrl *ctrl) +{ + static const u32 mac_group_regs[] = { + RTPCS_931X_MAC_GROUP0_1_CTRL, + RTPCS_931X_MAC_GROUP2_3_CTRL, + RTPCS_931X_MAC_GROUP4_CTRL, + RTPCS_931X_MAC_GROUP5_CTRL, + RTPCS_931X_MAC_GROUP6_7_CTRL, + RTPCS_931X_MAC_GROUP8_11_CTRL, + }; + int ret; + + for (int i = 0; i < ARRAY_SIZE(mac_group_regs); i++) { + ret = regmap_write(ctrl->map, mac_group_regs[i], 0xffffffff); + if (ret) + return ret; + } + + return 0; +} + +static int rtpcs_931x_init(struct rtpcs_ctrl *ctrl) +{ + int ret; + + ret = rtpcs_931x_init_mac_groups(ctrl); + if (ret < 0) + return ret; + + return rtpcs_93xx_init_serdes_common(ctrl); +} + +/* Common functions */ + +static void rtpcs_pcs_get_state(struct phylink_pcs *pcs, struct phylink_link_state *state) +{ + struct rtpcs_link *link = rtpcs_phylink_pcs_to_link(pcs); + struct rtpcs_ctrl *ctrl = link->ctrl; + int port = link->port; + int linkup, speed; + + state->link = 0; + state->speed = SPEED_UNKNOWN; + state->duplex = DUPLEX_UNKNOWN; + state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); + + /* Read MAC side link twice */ + for (int i = 0; i < 2; i++) + linkup = rtpcs_regmap_read_bits(ctrl, ctrl->cfg->mac_link_sts, port, port); + + if (!linkup) + return; + + state->link = 1; + state->duplex = rtpcs_regmap_read_bits(ctrl, ctrl->cfg->mac_link_dup_sts, port, port); + + speed = rtpcs_regmap_read_bits(ctrl, ctrl->cfg->mac_link_spd_sts, + ctrl->cfg->mac_link_spd_bits * (port + 1) - 1, + ctrl->cfg->mac_link_spd_bits * port); + switch (speed) { + case RTPCS_SPEED_10: + state->speed = SPEED_10; + break; + case RTPCS_SPEED_100: + state->speed = SPEED_100; + break; + case RTPCS_SPEED_1000: + state->speed = SPEED_1000; + break; + case RTPCS_SPEED_10000: + case RTPCS_SPEED_10000_LEGACY: + /* + * The legacy mode is ok so far with minor inconsistencies. On RTL838x this flag + * is either 500M or 2G. It might be that MAC_GLITE_STS register tells more. On + * RTL839x this is either 500M or 10G. More info might be in MAC_LINK_500M_STS. + * Without support for the 500M modes simply resolve to 10G. + */ + state->speed = SPEED_10000; + break; + case RTPCS_SPEED_2500: + state->speed = SPEED_2500; + break; + case RTPCS_SPEED_5000: + state->speed = SPEED_5000; + break; + default: + dev_err(ctrl->dev, "unknown speed %d\n", speed); + } + + if (rtpcs_regmap_read_bits(ctrl, ctrl->cfg->mac_rx_pause_sts, port, port)) + state->pause |= MLO_PAUSE_RX; + if (rtpcs_regmap_read_bits(ctrl, ctrl->cfg->mac_tx_pause_sts, port, port)) + state->pause |= MLO_PAUSE_TX; +} + +static void rtpcs_pcs_an_restart(struct phylink_pcs *pcs) +{ + struct rtpcs_link *link = rtpcs_phylink_pcs_to_link(pcs); + struct rtpcs_ctrl *ctrl = link->ctrl; + struct rtpcs_serdes *sds = link->sds; + + mutex_lock(&ctrl->lock); + sds->ops->restart_autoneg(sds); + mutex_unlock(&ctrl->lock); +} + +static int rtpcs_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, + phy_interface_t interface, const unsigned long *advertising, + bool permit_pause_to_mac) +{ + struct rtpcs_link *link = rtpcs_phylink_pcs_to_link(pcs); + struct rtpcs_ctrl *ctrl = link->ctrl; + struct rtpcs_serdes *sds = link->sds; + enum rtpcs_sds_mode hw_mode; + int ret; + + ret = rtpcs_sds_determine_hw_mode(sds, interface, &hw_mode); + if (ret < 0) { + dev_err(ctrl->dev, "SerDes %u doesn't support %s mode\n", sds->id, + phy_modes(interface)); + return -ENOTSUPP; + } + + mutex_lock(&ctrl->lock); + + if (sds->hw_mode != hw_mode) { + dev_info(ctrl->dev, "configure SerDes %u for mode %s\n", sds->id, + phy_modes(interface)); + + ret = ctrl->cfg->setup_serdes(sds, hw_mode); + if (ret < 0) + goto out; + + sds->first_start = false; + } else { + dev_dbg(ctrl->dev, "SerDes %u already in mode %s, no change\n", + sds->id, phy_modes(interface)); + } + + ret = sds->ops->set_autoneg(sds, neg_mode, advertising); + +out: + mutex_unlock(&ctrl->lock); + return ret; +} + +struct phylink_pcs *rtpcs_create(struct device *dev, struct device_node *np, int port); +struct phylink_pcs *rtpcs_create(struct device *dev, struct device_node *np, int port) +{ + struct platform_device *pdev; + struct device_node *pcs_np; + struct rtpcs_serdes *sds; + struct rtpcs_ctrl *ctrl; + struct rtpcs_link *link; + u32 sds_id; + + if (!np || !of_device_is_available(np)) + return ERR_PTR(-ENODEV); + + pcs_np = of_get_parent(np); + if (!pcs_np) + return ERR_PTR(-ENODEV); + + if (!of_device_is_available(pcs_np)) { + of_node_put(pcs_np); + return ERR_PTR(-ENODEV); + } + + pdev = of_find_device_by_node(pcs_np); + of_node_put(pcs_np); + if (!pdev) + return ERR_PTR(-EPROBE_DEFER); + + ctrl = platform_get_drvdata(pdev); + if (!ctrl) { + put_device(&pdev->dev); + return ERR_PTR(-EPROBE_DEFER); + } + + if (port < 0 || port > ctrl->cfg->cpu_port) + return ERR_PTR(-EINVAL); + + if (of_property_read_u32(np, "reg", &sds_id)) + return ERR_PTR(-EINVAL); + if (sds_id >= ctrl->cfg->serdes_count) + return ERR_PTR(-EINVAL); + + sds = &ctrl->serdes[sds_id]; + if (rtpcs_sds_read(sds, 0, 0) < 0) + return ERR_PTR(-EINVAL); + if (sds->num_of_links >= RTPCS_MAX_LINKS_PER_SDS) + return ERR_PTR(-ERANGE); + + link = kzalloc(sizeof(*link), GFP_KERNEL); + if (!link) { + put_device(&pdev->dev); + return ERR_PTR(-ENOMEM); + } + + device_link_add(dev, ctrl->dev, DL_FLAG_AUTOREMOVE_CONSUMER); + + sds->num_of_links++; + link->ctrl = ctrl; + link->port = port; + link->sds = sds; + link->pcs.ops = ctrl->cfg->pcs_ops; + link->pcs.neg_mode = true; + + ctrl->link[port] = link; + + dev_dbg(ctrl->dev, "phylink_pcs created, port %d, sds %d\n", port, sds_id); + + return &link->pcs; +} +EXPORT_SYMBOL(rtpcs_create); + +static struct mii_bus *rtpcs_probe_serdes_bus(struct rtpcs_ctrl *ctrl) +{ + struct device_node *np; + struct mii_bus *bus; + + np = of_find_compatible_node(NULL, NULL, "realtek,otto-serdes-mdio"); + if (!np) { + dev_err(ctrl->dev, "SerDes mdio bus not found in DT"); + return ERR_PTR(-ENODEV); + } + + bus = of_mdio_find_bus(np); + of_node_put(np); + if (!bus) { + dev_warn(ctrl->dev, "SerDes mdio bus not (yet) active"); + return ERR_PTR(-EPROBE_DEFER); + } + + if (!of_device_is_available(np)) { + dev_err(ctrl->dev, "SerDes mdio bus not usable"); + return ERR_PTR(-ENODEV); + } + + return bus; +} + +static int rtpcs_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct device_node *child; + struct rtpcs_serdes *sds; + struct rtpcs_ctrl *ctrl; + u32 sds_id; + int i, ret; + + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + mutex_init(&ctrl->lock); + + ctrl->dev = dev; + ctrl->cfg = (const struct rtpcs_config *)device_get_match_data(ctrl->dev); + ctrl->map = syscon_node_to_regmap(np->parent); + if (IS_ERR(ctrl->map)) + return PTR_ERR(ctrl->map); + + ctrl->bus = rtpcs_probe_serdes_bus(ctrl); + if (IS_ERR(ctrl->bus)) + return PTR_ERR(ctrl->bus); + + for (i = 0; i < ctrl->cfg->serdes_count; i++) { + sds = &ctrl->serdes[i]; + + sds->ctrl = ctrl; + sds->first_start = true; + sds->id = i; + sds->ops = ctrl->cfg->sds_ops; + sds->regs = ctrl->cfg->sds_regs; + } + + for_each_child_of_node(dev->of_node, child) { + ret = of_property_read_u32(child, "reg", &sds_id); + if (ret) + return ret; + if (sds_id >= ctrl->cfg->serdes_count) + return -EINVAL; + + sds = &ctrl->serdes[sds_id]; + sds->rx_pol_inv = of_property_read_bool(child, "realtek,pnswap-rx"); + sds->tx_pol_inv = of_property_read_bool(child, "realtek,pnswap-tx"); + } + + if (ctrl->cfg->init_serdes_common) { + ret = ctrl->cfg->init_serdes_common(ctrl); + if (ret) + return ret; + } + + /* + * rtpcs_create() relies on that fact that data is attached to the platform device to + * determine if the driver is ready. Do this after everything is initialized properly. + */ + platform_set_drvdata(pdev, ctrl); + + dev_info(dev, "Realtek PCS driver initialized\n"); + + return 0; +} + +static const struct phylink_pcs_ops rtpcs_838x_pcs_ops = { + .pcs_an_restart = rtpcs_pcs_an_restart, + .pcs_config = rtpcs_pcs_config, + .pcs_get_state = rtpcs_pcs_get_state, +}; + +static const struct rtpcs_serdes_ops rtpcs_838x_sds_ops = { + .read = rtpcs_generic_sds_op_read, + .write = rtpcs_generic_sds_op_write, + .set_autoneg = rtpcs_generic_sds_set_autoneg, + .restart_autoneg = rtpcs_generic_sds_restart_autoneg, +}; + +static const struct rtpcs_sds_regs rtpcs_838x_sds_regs = { + .an_enable = { .page = 0x2, .reg = MII_BMCR, .msb = 12, .lsb = 12 }, + .an_restart = { .page = 0x2, .reg = MII_BMCR, .msb = 9, .lsb = 9 }, + .an_advertise = { .page = 0x2, .reg = MII_ADVERTISE, .msb = 15, .lsb = 0 }, +}; + +static const struct rtpcs_config rtpcs_838x_cfg = { + .cpu_port = RTPCS_838X_CPU_PORT, + .mac_link_dup_sts = RTPCS_838X_MAC_LINK_DUP_STS, + .mac_link_spd_sts = RTPCS_838X_MAC_LINK_SPD_STS, + .mac_link_spd_bits = RTPCS_83XX_MAC_LINK_SPD_BITS, + .mac_link_sts = RTPCS_838X_MAC_LINK_STS, + .mac_rx_pause_sts = RTPCS_838X_MAC_RX_PAUSE_STS, + .mac_tx_pause_sts = RTPCS_838X_MAC_TX_PAUSE_STS, + .serdes_count = RTPCS_838X_SERDES_CNT, + .pcs_ops = &rtpcs_838x_pcs_ops, + .sds_ops = &rtpcs_838x_sds_ops, + .sds_regs = &rtpcs_838x_sds_regs, + .init_serdes_common = rtpcs_838x_init_serdes_common, + .setup_serdes = rtpcs_838x_setup_serdes, +}; + +static const struct phylink_pcs_ops rtpcs_839x_pcs_ops = { + .pcs_an_restart = rtpcs_pcs_an_restart, + .pcs_config = rtpcs_pcs_config, + .pcs_get_state = rtpcs_pcs_get_state, +}; + +static const struct rtpcs_serdes_ops rtpcs_839x_sds_ops = { + .read = rtpcs_generic_sds_op_read, + .write = rtpcs_generic_sds_op_write, + .set_autoneg = rtpcs_generic_sds_set_autoneg, + .restart_autoneg = rtpcs_generic_sds_restart_autoneg, +}; + +static const struct rtpcs_sds_regs rtpcs_839x_sds_regs = { + .an_enable = { .page = 0x2, .reg = MII_BMCR, .msb = 12, .lsb = 12 }, + .an_restart = { .page = 0x2, .reg = MII_BMCR, .msb = 9, .lsb = 9 }, + .an_advertise = { .page = 0x2, .reg = MII_ADVERTISE, .msb = 15, .lsb = 0 }, +}; + +static const struct rtpcs_config rtpcs_839x_cfg = { + .cpu_port = RTPCS_839X_CPU_PORT, + .mac_link_dup_sts = RTPCS_839X_MAC_LINK_DUP_STS, + .mac_link_spd_sts = RTPCS_839X_MAC_LINK_SPD_STS, + .mac_link_spd_bits = RTPCS_83XX_MAC_LINK_SPD_BITS, + .mac_link_sts = RTPCS_839X_MAC_LINK_STS, + .mac_rx_pause_sts = RTPCS_839X_MAC_RX_PAUSE_STS, + .mac_tx_pause_sts = RTPCS_839X_MAC_TX_PAUSE_STS, + .serdes_count = RTPCS_839X_SERDES_CNT, + .pcs_ops = &rtpcs_839x_pcs_ops, + .sds_ops = &rtpcs_839x_sds_ops, + .sds_regs = &rtpcs_839x_sds_regs, + .init_serdes_common = rtpcs_839x_init_serdes_common, + .setup_serdes = rtpcs_839x_setup_serdes, +}; + +static const struct phylink_pcs_ops rtpcs_930x_pcs_ops = { + .pcs_an_restart = rtpcs_pcs_an_restart, + .pcs_config = rtpcs_pcs_config, + .pcs_get_state = rtpcs_pcs_get_state, +}; + +static const struct rtpcs_serdes_ops rtpcs_930x_sds_ops = { + .read = rtpcs_930x_sds_op_read, + .write = rtpcs_930x_sds_op_write, + .xsg_write = rtpcs_930x_sds_op_xsg_write, + .set_autoneg = rtpcs_93xx_sds_set_autoneg, + .restart_autoneg = rtpcs_generic_sds_restart_autoneg, + .get_pll_select = rtpcs_930x_sds_get_pll_select, + .set_pll_select = rtpcs_930x_sds_set_pll_select, + .reset_cmu = rtpcs_930x_sds_reset_cmu, + .reconfigure_to_pll = rtpcs_930x_sds_reconfigure_to_pll, +}; + +static const struct rtpcs_sds_regs rtpcs_930x_sds_regs = { + .an_enable = { .page = 0x2, .reg = MII_BMCR, .msb = 12, .lsb = 12 }, + .an_restart = { .page = 0x2, .reg = MII_BMCR, .msb = 9, .lsb = 9 }, + .an_advertise = { .page = 0x2, .reg = MII_ADVERTISE, .msb = 15, .lsb = 0 }, +}; + +static const struct rtpcs_config rtpcs_930x_cfg = { + .cpu_port = RTPCS_930X_CPU_PORT, + .mac_link_dup_sts = RTPCS_930X_MAC_LINK_DUP_STS, + .mac_link_spd_sts = RTPCS_930X_MAC_LINK_SPD_STS, + .mac_link_spd_bits = RTPCS_93XX_MAC_LINK_SPD_BITS, + .mac_link_sts = RTPCS_930X_MAC_LINK_STS, + .mac_rx_pause_sts = RTPCS_930X_MAC_RX_PAUSE_STS, + .mac_tx_pause_sts = RTPCS_930X_MAC_TX_PAUSE_STS, + .serdes_count = RTPCS_930X_SERDES_CNT, + .pcs_ops = &rtpcs_930x_pcs_ops, + .sds_ops = &rtpcs_930x_sds_ops, + .sds_regs = &rtpcs_930x_sds_regs, + .init_serdes_common = rtpcs_93xx_init_serdes_common, + .setup_serdes = rtpcs_930x_setup_serdes, +}; + +static const struct phylink_pcs_ops rtpcs_931x_pcs_ops = { + .pcs_an_restart = rtpcs_pcs_an_restart, + .pcs_config = rtpcs_pcs_config, + .pcs_get_state = rtpcs_pcs_get_state, +}; + +static const struct rtpcs_serdes_ops rtpcs_931x_sds_ops = { + .read = rtpcs_generic_sds_op_read, + .write = rtpcs_generic_sds_op_write, + .xsg_write = rtpcs_931x_sds_op_xsg_write, + .set_autoneg = rtpcs_93xx_sds_set_autoneg, + .restart_autoneg = rtpcs_generic_sds_restart_autoneg, + .get_pll_select = rtpcs_931x_sds_get_pll_select, + .set_pll_select = rtpcs_931x_sds_set_pll_select, + .reconfigure_to_pll = rtpcs_931x_sds_reconfigure_to_pll, +}; + +static const struct rtpcs_sds_regs rtpcs_931x_sds_regs = { + .an_enable = { .page = 0x42, .reg = MII_BMCR, .msb = 12, .lsb = 12 }, + .an_restart = { .page = 0x42, .reg = MII_BMCR, .msb = 9, .lsb = 9 }, + .an_advertise = { .page = 0x42, .reg = MII_ADVERTISE, .msb = 15, .lsb = 0 }, +}; + +static const struct rtpcs_config rtpcs_931x_cfg = { + .cpu_port = RTPCS_931X_CPU_PORT, + .mac_link_dup_sts = RTPCS_931X_MAC_LINK_DUP_STS, + .mac_link_spd_sts = RTPCS_931X_MAC_LINK_SPD_STS, + .mac_link_spd_bits = RTPCS_93XX_MAC_LINK_SPD_BITS, + .mac_link_sts = RTPCS_931X_MAC_LINK_STS, + .mac_rx_pause_sts = RTPCS_931X_MAC_RX_PAUSE_STS, + .mac_tx_pause_sts = RTPCS_931X_MAC_TX_PAUSE_STS, + .serdes_count = RTPCS_931X_SERDES_CNT, + .pcs_ops = &rtpcs_931x_pcs_ops, + .sds_ops = &rtpcs_931x_sds_ops, + .sds_regs = &rtpcs_931x_sds_regs, + .init_serdes_common = rtpcs_931x_init, + .setup_serdes = rtpcs_931x_setup_serdes, +}; + +static const struct of_device_id rtpcs_of_match[] = { + { + .compatible = "realtek,rtl8380-pcs", + .data = &rtpcs_838x_cfg, + }, + { + .compatible = "realtek,rtl8392-pcs", + .data = &rtpcs_839x_cfg, + }, + { + .compatible = "realtek,rtl9301-pcs", + .data = &rtpcs_930x_cfg, + }, + { + .compatible = "realtek,rtl9311-pcs", + .data = &rtpcs_931x_cfg, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtpcs_of_match); + +static struct platform_driver rtpcs_driver = { + .driver = { + .name = "realtek-otto-pcs", + .of_match_table = rtpcs_of_match + }, + .probe = rtpcs_probe, +}; +module_platform_driver(rtpcs_driver); + +MODULE_AUTHOR("Markus Stockhausen "); +MODULE_AUTHOR("Jonas Jelonek "); +MODULE_DESCRIPTION("Realtek Otto SerDes PCS driver"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/realtek/files-6.12/drivers/net/phy/realtek/realtek_multiport.c b/target/linux/realtek/files-6.12/drivers/net/phy/realtek/realtek_multiport.c new file mode 100644 index 0000000000..3074e57858 --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/net/phy/realtek/realtek_multiport.c @@ -0,0 +1,707 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Realtek RTL838X Ethernet MDIO interface driver + * + * Copyright (C) 2020 B. Koblitz + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Realtek PHYs have three special page registers. Register 31 (page select) switches the + * register pages and gives access to special registers that are mapped into register + * range 16-24. Register 30 (extended page select) does basically the same. It especially + * grants access to special internal data like fibre, copper or serdes setup. Register + * 29 is a write only companion of register 30. As it flips back to 0 and register 30 + * shows the original write content it should be avoided at all cost. + */ +#define RTL821x_PAGE_SELECT 0x1f +#define RTL821x_EXT_PAGE_SELECT 0x1e + +#define RTL8XXX_PAGE_MAIN 0x0000 +#define RTL821X_PAGE_PORT 0x0266 +#define RTL821X_PAGE_POWER 0x0a40 +#define RTL821X_PAGE_GPHY 0x0a42 +#define RTL821X_PAGE_MAC 0x0a43 +#define RTL821X_PAGE_STATE 0x0b80 +#define RTL821X_PAGE_PATCH 0x0b82 +#define RTL821X_MAC_SDS_PAGE(sds, page) (0x404 + (sds) * 0x20 + (page)) + +#define RTL821X_PHYCR2 0x19 +#define RTL821X_PHYCR2_PHY_EEE_ENABLE BIT(5) + +#define RTL821X_MEDIA_PAGE_AUTO 0 +#define RTL821X_MEDIA_PAGE_COPPER 1 +#define RTL821X_MEDIA_PAGE_FIBRE 3 +#define RTL821X_MEDIA_PAGE_INTERNAL 8 + +#define RTL821X_JOIN_FIRST 0 +#define RTL821X_JOIN_LAST 1 +#define RTL821X_JOIN_OTHER 2 + +#define RTL8214FC_MEDIA_COPPER BIT(11) + +#define PHY_ID_RTL8214C 0x001cc942 +#define PHY_ID_RTL8218B_E 0x001cc980 +#define PHY_ID_RTL8214_OR_8218 0x001cc981 +#define PHY_ID_RTL8218D 0x001cc983 +#define PHY_ID_RTL8218E 0x001cc984 +#define PHY_ID_RTL8218B_I 0x001cca40 + +/* These PHYs share the same id (0x001cc981) */ +#define PHY_IS_NOT_RTL821X 0 +#define PHY_IS_RTL8214FC 1 +#define PHY_IS_RTL8214FB 2 +#define PHY_IS_RTL8218B_E 3 + +struct rtl821x_shared_priv { + int base_addr; + int ports; +}; + +/* TODO: for kernel 6.18 drop this function and use it from phy_package library instead */ +static void *phy_package_get_priv(struct phy_device *phydev) +{ + return phydev->shared->priv; +} + +static int rtl821x_package_join(struct phy_device *phydev, int ports) +{ + struct rtl821x_shared_priv *shared_priv; + int base_addr = phydev->mdio.addr & ~(ports - 1); + + devm_phy_package_join(&phydev->mdio.dev, phydev, base_addr, + sizeof(struct rtl821x_shared_priv)); + + shared_priv = phy_package_get_priv(phydev); + shared_priv->base_addr = base_addr; + shared_priv->ports++; + + if (shared_priv->ports == 1) + return RTL821X_JOIN_FIRST; + + if (shared_priv->ports == ports) + return RTL821X_JOIN_LAST; + + return RTL821X_JOIN_OTHER; +} + +static inline struct phy_device *get_package_phy(struct phy_device *phydev, int port) +{ + struct rtl821x_shared_priv *shared_priv = phy_package_get_priv(phydev); + + return mdiobus_get_phy(phydev->mdio.bus, shared_priv->base_addr + port); +} + +static inline struct phy_device *get_base_phy(struct phy_device *phydev) +{ + return get_package_phy(phydev, 0); +} + +static int rtl821x_match_phy_device(struct phy_device *phydev) +{ + int oldpage, oldxpage, chip_mode, chip_cfg_mode; + struct mii_bus *bus = phydev->mdio.bus; + int addr = phydev->mdio.addr & ~3; + + if (phydev->phy_id == PHY_ID_RTL8218B_E) + return PHY_IS_RTL8218B_E; + + if (phydev->phy_id != PHY_ID_RTL8214_OR_8218) + return PHY_IS_NOT_RTL821X; + + /* + * RTL8214FC and RTL8218B are the same PHYs with different configurations. That info is + * stored in the first PHY of the package. In all known configurations packages start at + * bus addresses that are multiples of four. Avoid paged access as this is not available + * during detection. + */ + + oldpage = mdiobus_read(bus, addr, RTL821x_PAGE_SELECT); + oldxpage = mdiobus_read(bus, addr, RTL821x_EXT_PAGE_SELECT); + + mdiobus_write(bus, addr, RTL821x_EXT_PAGE_SELECT, 0x8); + mdiobus_write(bus, addr, RTL821x_PAGE_SELECT, 0x278); + mdiobus_write(bus, addr, 0x12, 0x455); + mdiobus_write(bus, addr, RTL821x_PAGE_SELECT, 0x260); + chip_mode = mdiobus_read(bus, addr, 0x12); + dev_dbg(&phydev->mdio.dev, "got RTL8218B/RTL8214Fx chip mode %04x\n", chip_mode); + + mdiobus_write(bus, addr, RTL821x_EXT_PAGE_SELECT, oldxpage); + mdiobus_write(bus, addr, RTL821x_PAGE_SELECT, oldpage); + + /* no values while reading the 5th port during 5-8th port detection of RTL8218B */ + if (!chip_mode) + return PHY_IS_RTL8218B_E; + + chip_cfg_mode = (chip_mode >> 4) & 0xf; + chip_mode &= 0xf; + + if (chip_mode == 0xd || chip_mode == 0xf) + return PHY_IS_RTL8218B_E; + + if (chip_mode == 0x4 || chip_mode == 0x6) + return PHY_IS_RTL8214FC; + + if (chip_mode != 0xc && chip_mode != 0xe) + return PHY_IS_NOT_RTL821X; + + if (chip_cfg_mode == 0x4 || chip_cfg_mode == 0x6) + return PHY_IS_RTL8214FC; + + return PHY_IS_RTL8214FB; +} + +static int rtl8218b_ext_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) +{ + return rtl821x_match_phy_device(phydev) == PHY_IS_RTL8218B_E; +} + +static int rtl8214fc_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) +{ + return rtl821x_match_phy_device(phydev) == PHY_IS_RTL8214FC; +} + +static int rtl821x_read_page(struct phy_device *phydev) +{ + return __phy_read(phydev, RTL821x_PAGE_SELECT); +} + +static int rtl821x_write_page(struct phy_device *phydev, int page) +{ + return __phy_write(phydev, RTL821x_PAGE_SELECT, page); +} + +static bool __rtl8214fc_media_is_fibre(struct phy_device *phydev) +{ + struct phy_device *basephy = get_base_phy(phydev); + static int regs[] = {16, 19, 20, 21}; + int reg = regs[phydev->mdio.addr & 3]; + int oldpage, oldxpage, val; + + oldpage = __phy_read(basephy, RTL821x_PAGE_SELECT); + oldxpage = __phy_read(basephy, RTL821x_EXT_PAGE_SELECT); + + __phy_write(basephy, RTL821x_EXT_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL); + __phy_write(basephy, RTL821x_PAGE_SELECT, RTL821X_PAGE_PORT); + val = __phy_read(basephy, reg); + + __phy_write(basephy, RTL821x_EXT_PAGE_SELECT, oldxpage); + __phy_write(basephy, RTL821x_PAGE_SELECT, oldpage); + + return !(val & RTL8214FC_MEDIA_COPPER); +} + +static bool rtl8214fc_media_is_fibre(struct phy_device *phydev) +{ + int ret; + + phy_lock_mdio_bus(phydev); + ret = __rtl8214fc_media_is_fibre(phydev); + phy_unlock_mdio_bus(phydev); + + return ret; +} + +static void rtl8214fc_power_set(struct phy_device *phydev, int port, bool on) +{ + int page = port == PORT_FIBRE ? RTL821X_MEDIA_PAGE_FIBRE : RTL821X_MEDIA_PAGE_COPPER; + int oldxpage = __phy_read(phydev, RTL821x_EXT_PAGE_SELECT); + int pdown = on ? 0 : BMCR_PDOWN; + + phydev_info(phydev, "power %s %s\n", on ? "on" : "off", + port == PORT_FIBRE ? "fibre" : "copper"); + + phy_write(phydev, RTL821x_EXT_PAGE_SELECT, page); + phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, pdown); + phy_write(phydev, RTL821x_EXT_PAGE_SELECT, oldxpage); +} + +static int rtl8214fc_suspend(struct phy_device *phydev) +{ + rtl8214fc_power_set(phydev, PORT_MII, false); + rtl8214fc_power_set(phydev, PORT_FIBRE, false); + + return 0; +} + +static int rtl8214fc_resume(struct phy_device *phydev) +{ + bool set_fibre = rtl8214fc_media_is_fibre(phydev); + + rtl8214fc_power_set(phydev, PORT_MII, !set_fibre); + rtl8214fc_power_set(phydev, PORT_FIBRE, set_fibre); + + return 0; +} + +static void rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre) +{ + struct phy_device *basephy = get_base_phy(phydev); + int oldxpage = phy_read(basephy, RTL821x_EXT_PAGE_SELECT); + int copper = set_fibre ? 0 : RTL8214FC_MEDIA_COPPER; + static int regs[] = {16, 19, 20, 21}; + int reg = regs[phydev->mdio.addr & 3]; + + phydev_info(phydev, "switch to %s\n", set_fibre ? "fibre" : "copper"); + phy_write(basephy, RTL821x_EXT_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL); + phy_modify_paged(basephy, RTL821X_PAGE_PORT, reg, RTL8214FC_MEDIA_COPPER, copper); + phy_write(basephy, RTL821x_EXT_PAGE_SELECT, oldxpage); + + if (!phydev->suspended) { + rtl8214fc_power_set(phydev, PORT_MII, !set_fibre); + rtl8214fc_power_set(phydev, PORT_FIBRE, set_fibre); + } +} + +static int rtl8214fc_set_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, const void *data) +{ + /* + * The RTL8214FC driver usually detects insertion of SFP modules and automatically toggles + * between copper and fiber. There may be cases where the user wants to switch the port on + * demand. Usually ethtool offers to change the port of a multiport network card with + * "ethtool -s lan25 port fibre/tp" if the driver supports it. This does not work for + * attached phys. For more details see phy_ethtool_ksettings_set(). To avoid patching the + * kernel misuse the phy downshift tunable to offer that feature. For this use + * "ethtool --set-phy-tunable lan25 downshift on/off". + */ + switch (tuna->id) { + case ETHTOOL_PHY_DOWNSHIFT: + rtl8214fc_media_set(phydev, !rtl8214fc_media_is_fibre(phydev)); + return 0; + default: + return -EOPNOTSUPP; + } +} + +static int rtl8214fc_get_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, void *data) +{ + /* Needed to make rtl8214fc_set_tunable() work */ + return 0; +} + +static int rtl8214fc_get_features(struct phy_device *phydev) +{ + int ret = 0; + + ret = genphy_read_abilities(phydev); + if (ret) + return ret; + /* + * The RTL8214FC only advertises TP capabilities in the standard registers. This is + * independent from what fibre/copper combination is currently activated. For now just + * announce the superset of all possible features. + */ + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported); + + return 0; +} + +static int rtl8214fc_read_status(struct phy_device *phydev) +{ + bool changed; + int ret; + + if (rtl8214fc_media_is_fibre(phydev)) { + phydev->port = PORT_FIBRE; + ret = genphy_c37_read_status(phydev, &changed); + } else { + phydev->port = PORT_MII; /* for now aligend with rest of code */ + ret = genphy_read_status(phydev); + } + + return ret; +} + +static int rtl8214fc_config_aneg(struct phy_device *phydev) +{ + int ret; + + if (rtl8214fc_media_is_fibre(phydev)) + ret = genphy_c37_config_aneg(phydev); + else + ret = genphy_config_aneg(phydev); + + return ret; +} + +static int rtl821x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) +{ + struct mii_bus *bus = phydev->mdio.bus; + int addr = phydev->mdio.addr; + int ret; + + /* + * The RTL821x PHYs are usually only C22 capable and are defined accordingly in DTS. + * Nevertheless GPL source drops clearly indicate that EEE features can be accessed + * directly via C45. Testing shows that C45 over C22 (as used in kernel EEE framework) + * works as well but only as long as PHY polling is disabled in the SOC. To avoid ugly + * hacks pass through C45 accesses for important EEE registers. Maybe some day the mdio + * bus can intercept these patterns and switch off/on polling on demand. That way this + * phy device driver can avoid handling special cases on its own. + */ + + if ((devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) || + (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) || + (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE)) + ret = __mdiobus_c45_read(bus, addr, devnum, regnum); + else + ret = -EOPNOTSUPP; + + return ret; +} + +static int rtl821x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, u16 val) +{ + struct mii_bus *bus = phydev->mdio.bus; + int addr = phydev->mdio.addr; + int ret; + + /* see rtl821x_read_mmd() */ + if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) + ret = __mdiobus_c45_write(bus, addr, devnum, regnum, val); + else + ret = -EOPNOTSUPP; + + return ret; +} + +static int rtl8214fc_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) +{ + if (__rtl8214fc_media_is_fibre(phydev)) + return -EOPNOTSUPP; + + return rtl821x_read_mmd(phydev, devnum, regnum); +} + +static int rtl8214fc_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, u16 val) +{ + if (__rtl8214fc_media_is_fibre(phydev)) + return -EOPNOTSUPP; + + return rtl821x_write_mmd(phydev, devnum, regnum, val); +} + +static int rtl8214fc_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, }; + DECLARE_PHY_INTERFACE_MASK(interfaces); + struct phy_device *phydev = upstream; + phy_interface_t iface; + + sfp_parse_support(phydev->sfp_bus, id, support, interfaces); + iface = sfp_select_interface(phydev->sfp_bus, support); + + phydev_info(phydev, "%s SFP module inserted\n", phy_modes(iface)); + + rtl8214fc_media_set(phydev, true); + + return 0; +} + +static void rtl8214fc_sfp_remove(void *upstream) +{ + struct phy_device *phydev = upstream; + + rtl8214fc_media_set(phydev, false); +} + +static const struct sfp_upstream_ops rtl8214fc_sfp_ops = { + .attach = phy_sfp_attach, + .detach = phy_sfp_detach, + .module_insert = rtl8214fc_sfp_insert, + .module_remove = rtl8214fc_sfp_remove, +}; + +static int rtl8214c_phy_probe(struct phy_device *phydev) +{ + rtl821x_package_join(phydev, 4); + + return 0; +} + +static int rtl8218x_phy_probe(struct phy_device *phydev) +{ + rtl821x_package_join(phydev, 8); + + return 0; +} + +static int rtl821x_config_init(struct phy_device *phydev) +{ + /* Disable PHY-mode EEE so LPI is passed to the MAC */ + phy_modify_paged(phydev, RTL821X_PAGE_MAC, RTL821X_PHYCR2, + RTL821X_PHYCR2_PHY_EEE_ENABLE, 0); + + return 0; +} + +static int rtl8218d_config_init(struct phy_device *phydev) +{ + int oldpage, oldxpage; + bool is_qsgmii; + int chip_info; + + rtl821x_config_init(phydev); + + if (phydev->mdio.addr % 8) + return 0; + /* + * The RTl8218D has two MAC (aka SoC side) operation modes. Either dual QSGMII + * or single XSGMII (Realtek proprietary) link. The mode is usually configured via + * strapping pins CHIP_MODE1/2. For the moment offer a configuration that at least + * works for RTL93xx devices. This sequence even "revives" a PHY that has been hard + * reset with + * + * phy_write(phydev, 0x1e, 0x8); + * phy_write_paged(phydev, 0x262, 0x10, 0x1); + */ + oldpage = phy_read(phydev, RTL821x_PAGE_SELECT); + oldxpage = phy_read(phydev, RTL821x_EXT_PAGE_SELECT); + + phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0x8); + chip_info = phy_read_paged(phydev, 0x327, 0x15); + is_qsgmii = (phy_read_paged(phydev, 0x260, 0x12) & 0xf0) == 0xd0; + + pr_info("RTL8218D (chip_id=%d, rev_id=%d) on port %d running in %s mode\n", + (chip_info >> 7) & 0x7, chip_info & 0x7f, phydev->mdio.addr, + is_qsgmii ? "QSGMII" : "XSGMII"); + + if (is_qsgmii) { + for (int sds = 0; sds < 2; sds++) { + /* unknown amplification value */ + phy_modify_paged(phydev, 0x4a8 + sds * 0x100, 0x12, BIT(3), 0); + /* main aplification */ + phy_modify_paged(phydev, 0x4ab + sds * 0x100, 0x16, 0x3e0, 0x1e0); + /* unknown LCCMU value */ + phy_write_paged(phydev, 0x4ac + sds * 0x100, 0x15, 0x4380); + } + } else { + /* serdes 0/1 disable auto negotiation */ + phy_modify_paged(phydev, 0x400, 0x12, 0, BIT(8)); + phy_modify_paged(phydev, 0x500, 0x12, 0, BIT(8)); + /* unknown eye configuration */ + phy_modify_paged(phydev, 0x4b8, 0x12, BIT(3), 0); + } + + /* reset serdes 0 */ + phy_write_paged(phydev, 0x400, 0x10, 0x1700); + phy_write_paged(phydev, 0x400, 0x10, 0x1703); + + /* reset serdes 1 */ + phy_write_paged(phydev, 0x500, 0x10, 0x1400); + phy_write_paged(phydev, 0x500, 0x10, 0x1403); + + phy_write(phydev, RTL821x_EXT_PAGE_SELECT, oldxpage); + phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); + + return 0; +} + +static void rtl8218b_cmu_reset(struct phy_device *phydev, int reset_id) +{ + int bitpos = reset_id * 2; + + /* CMU seems to have 8 pairs of reset bits that always work the same way */ + phy_modify_paged(phydev, 0x467, 0x14, 0, BIT(bitpos)); + phy_modify_paged(phydev, 0x467, 0x14, 0, BIT(bitpos + 1)); + phy_write_paged(phydev, 0x467, 0x14, 0x0); +} + +static int rtl8218b_config_init(struct phy_device *phydev) +{ + int oldpage, oldxpage; + + rtl821x_config_init(phydev); + + if (phydev->mdio.addr % 8) + return 0; + /* + * Realtek provides two ways of initializing the PHY package. Either by U-Boot or via + * vendor software and SDK. In case U-Boot setup is missing, run basic configuration + * so that ports at least get link up and pass traffic. + */ + + oldpage = phy_read(phydev, RTL821x_PAGE_SELECT); + oldxpage = phy_read(phydev, RTL821x_EXT_PAGE_SELECT); + phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0x8); + + /* activate 32/40 bit redundancy algorithm for first MAC serdes */ + phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(0, 1), 0x14, 0, BIT(3)); + /* magic CMU setting for stable connectivity of first MAC serdes */ + phy_write_paged(phydev, 0x462, 0x15, 0x6e58); + /* magic setting for rate select 10G full */ + phy_write_paged(phydev, 0x464, 0x15, 0x202a); + /* magic setting for variable gain amplifier */ + phy_modify_paged(phydev, 0x464, 0x12, 0, 0x1f80); + /* magic setting for equalizer of second MAC serdes */ + phy_write_paged(phydev, RTL821X_MAC_SDS_PAGE(1, 8), 0x12, 0x2020); + /* unknown magic for second MAC serdes */ + phy_write_paged(phydev, RTL821X_MAC_SDS_PAGE(1, 9), 0x11, 0xc014); + rtl8218b_cmu_reset(phydev, 0); + + for (int sds = 0; sds < 2; sds++) { + /* disable ring PLL for serdes 2+3 */ + phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(sds + 1, 8), 0x11, BIT(15), 0); + /* force negative clock edge */ + phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(sds, 0), 0x17, 0, BIT(14)); + rtl8218b_cmu_reset(phydev, 5 + sds); + /* soft reset */ + phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(sds, 0), 0x13, 0, BIT(6)); + phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(sds, 0), 0x13, BIT(6), 0); + } + + phy_write(phydev, RTL821x_EXT_PAGE_SELECT, oldxpage); + phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); + + return 0; +} + +static int rtl8214fc_phy_probe(struct phy_device *phydev) +{ + static int regs[] = {16, 19, 20, 21}; + int ret; + + rtl821x_package_join(phydev, 4); + + /* + * Normally phy_probe() only initializes PHY structures and setup is run in + * config_init(). The RTL8214FC needs configuration before SFP probing while + * the preferred media is still copper. This way all SFP events (even before + * the first config_init()) will find a consistent port state. + */ + + /* Step 1 - package setup: Due to similar design reuse RTL8218B coding */ + ret = rtl8218b_config_init(phydev); + if (ret) + return ret; + + if (phydev->mdio.addr % 8 == 0) { + /* Force all ports to copper */ + phy_write(phydev, RTL821x_EXT_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL); + for (int port = 0; port < 4; port++) + phy_modify_paged(phydev, 0x266, regs[port], 0, GENMASK(11, 10)); + } + + /* Step 2 - port setup */ + phy_write(phydev, RTL821x_EXT_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE); + /* set fiber SerDes RX to negative edge */ + phy_modify_paged(phydev, 0x8, 0x17, 0, BIT(14)); + /* auto negotiation disable link on */ + phy_modify_paged(phydev, 0x8, 0x14, 0, BIT(2)); + /* disable fiber 100MBit */ + phy_modify_paged(phydev, 0x8, 0x11, BIT(5), 0); + phy_write(phydev, RTL821x_EXT_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); + + /* Disable EEE. 0xa5d/0x10 is the same as MDIO_MMD_AN / MDIO_AN_EEE_ADV */ + phy_write_paged(phydev, 0xa5d, 0x10, 0x0000); + + return phy_sfp_probe(phydev, &rtl8214fc_sfp_ops); +} + +static struct phy_driver rtl83xx_phy_driver[] = { + { + PHY_ID_MATCH_EXACT(PHY_ID_RTL8214C), + .name = "Realtek RTL8214C", + .features = PHY_GBIT_FEATURES, + .probe = rtl8214c_phy_probe, + .read_page = rtl821x_read_page, + .write_page = rtl821x_write_page, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, + { + .match_phy_device = rtl8214fc_match_phy_device, + .name = "Realtek RTL8214FC", + .config_aneg = rtl8214fc_config_aneg, + .get_features = rtl8214fc_get_features, + .get_tunable = rtl8214fc_get_tunable, + .probe = rtl8214fc_phy_probe, + .read_mmd = rtl8214fc_read_mmd, + .read_page = rtl821x_read_page, + .read_status = rtl8214fc_read_status, + .resume = rtl8214fc_resume, + .set_tunable = rtl8214fc_set_tunable, + .suspend = rtl8214fc_suspend, + .write_mmd = rtl8214fc_write_mmd, + .write_page = rtl821x_write_page, + }, + { + .match_phy_device = rtl8218b_ext_match_phy_device, + .name = "Realtek RTL8218B (external)", + .config_init = rtl8218b_config_init, + .features = PHY_GBIT_FEATURES, + .probe = rtl8218x_phy_probe, + .read_mmd = rtl821x_read_mmd, + .read_page = rtl821x_read_page, + .resume = genphy_resume, + .suspend = genphy_suspend, + .write_mmd = rtl821x_write_mmd, + .write_page = rtl821x_write_page, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I), + .name = "Realtek RTL8218B (internal)", + .config_init = rtl821x_config_init, + .features = PHY_GBIT_FEATURES, + .probe = rtl8218x_phy_probe, + .read_mmd = rtl821x_read_mmd, + .read_page = rtl821x_read_page, + .resume = genphy_resume, + .suspend = genphy_suspend, + .write_mmd = rtl821x_write_mmd, + .write_page = rtl821x_write_page, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_RTL8218D), + .name = "REALTEK RTL8218D", + .config_init = rtl8218d_config_init, + .features = PHY_GBIT_FEATURES, + .probe = rtl8218x_phy_probe, + .read_mmd = rtl821x_read_mmd, + .read_page = rtl821x_read_page, + .resume = genphy_resume, + .suspend = genphy_suspend, + .write_mmd = rtl821x_write_mmd, + .write_page = rtl821x_write_page, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_RTL8218E), + .name = "REALTEK RTL8218E", + .config_init = rtl821x_config_init, + .features = PHY_GBIT_FEATURES, + .probe = rtl8218x_phy_probe, + .read_mmd = rtl821x_read_mmd, + .read_page = rtl821x_read_page, + .resume = genphy_resume, + .suspend = genphy_suspend, + .write_mmd = rtl821x_write_mmd, + .write_page = rtl821x_write_page, + }, +}; + +module_phy_driver(rtl83xx_phy_driver); + +static const struct mdio_device_id __maybe_unused rtl83xx_tbl[] = { + { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214_OR_8218) }, + { } +}; + +MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl); + +MODULE_AUTHOR("B. Koblitz"); +MODULE_DESCRIPTION("RTL83xx PHY driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/realtek/files-6.12/drivers/thermal/realtek-thermal.c b/target/linux/realtek/files-6.12/drivers/thermal/realtek-thermal.c new file mode 100644 index 0000000000..e2cbf0c89a --- /dev/null +++ b/target/linux/realtek/files-6.12/drivers/thermal/realtek-thermal.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Realtek thermal sensor driver + * + * Copyright (C) 2025 Bjørn Mork > + */ + +#include +#include +#include +#include +#include +#include "thermal_hwmon.h" + +#define RTL8380_THERMAL_METER_CTRL0 0x98 +#define RTL8380_THERMAL_METER_CTRL1 0x9c +#define RTL8380_THERMAL_METER_CTRL2 0xa0 +#define RTL8380_THERMAL_METER_RESULT 0xa4 +#define RTL8380_TM_ENABLE BIT(0) +#define RTL8380_TEMP_VALID BIT(8) +#define RTL8380_TEMP_OUT_MASK GENMASK(6, 0) + +#define RTL8390_THERMAL_METER0_CTRL0 0x274 +#define RTL8390_THERMAL_METER0_CTRL1 0x278 +#define RTL8390_THERMAL_METER0_CTRL2 0x27c +#define RTL8390_THERMAL_METER0_RESULT 0x280 +#define RTL8390_THERMAL_METER1_CTRL0 0x284 +#define RTL8390_THERMAL_METER1_CTRL1 0x288 +#define RTL8390_THERMAL_METER1_CTRL2 0x28c +#define RTL8390_THERMAL_METER1_RESULT 0x290 +#define RTL8390_TM_ENABLE BIT(0) +#define RTL8390_TEMP_VALID BIT(8) +#define RTL8390_TEMP_OUT_MASK GENMASK(6, 0) + +#define RTL9300_THERMAL_METER_CTRL0 0x60 +#define RTL9300_THERMAL_METER_CTRL1 0x64 +#define RTL9300_THERMAL_METER_CTRL2 0x68 +#define RTL9300_THERMAL_METER_RESULT0 0x6c +#define RTL9300_THERMAL_METER_RESULT1 0x70 +#define RTL9300_TM_ENABLE BIT(16) +#define RTL9300_TEMP_VALID BIT(24) +#define RTL9300_TEMP_OUT_MASK GENMASK(23, 16) +#define RTL9300_SAMPLE_DLY_SHIFT (16) +#define RTL9300_SAMPLE_DLY_MASK GENMASK(RTL9300_SAMPLE_DLY_SHIFT + 15, RTL9300_SAMPLE_DLY_SHIFT) +#define RTL9300_COMPARE_DLY_SHIFT (0) +#define RTL9300_COMPARE_DLY_MASK GENMASK(RTL9300_COMPARE_DLY_SHIFT + 15, RTL9300_COMPARE_DLY_SHIFT) + +#define RTL9607_THERMAL_CTRL_0 0x150 +#define RTL9607_REG_PPOW BIT(29) +#define RTL9607_THERMAL_CTRL_2 0x158 +#define RTL9607_THERMAL_CTRL_5 0x164 +#define RTL9607_THERMAL_STS_0 0x178 +#define RTL9607_TEMP_OUT_MASK GENMASK(18, 0) +#define RTL9607_TEMP_OUT_SIGN BIT(18) +#define RTL9607_TEMP_OUT_INT GENMASK(17, 10) +#define RTL9607_TEMP_OUT_FLOAT GENMASK(9, 0) + +struct realtek_thermal_priv { + struct regmap *regmap; + bool enabled; +}; + +static void rtl8380_thermal_init(struct realtek_thermal_priv *priv) +{ + priv->enabled = !regmap_update_bits(priv->regmap, RTL8380_THERMAL_METER_CTRL0, RTL8380_TM_ENABLE, RTL8380_TM_ENABLE); +} + +static int rtl8380_get_temp(struct thermal_zone_device *tz, int *res) +{ + struct realtek_thermal_priv *priv = thermal_zone_device_priv(tz); + int offset = thermal_zone_get_offset(tz); + int slope = thermal_zone_get_slope(tz); + u32 val; + int ret; + + if (!priv->enabled) + rtl8380_thermal_init(priv); + + ret = regmap_read(priv->regmap, RTL8380_THERMAL_METER_RESULT, &val); + if (ret) + return ret; + + if (!(val & RTL8380_TEMP_VALID)) + return -EAGAIN; + + *res = FIELD_GET(RTL8380_TEMP_OUT_MASK, val) * slope + offset; + return 0; +} + +static const struct thermal_zone_device_ops rtl8380_ops = { + .get_temp = rtl8380_get_temp, +}; + +static void rtl8390_thermal_init(struct realtek_thermal_priv *priv) +{ + priv->enabled = !regmap_update_bits(priv->regmap, RTL8390_THERMAL_METER0_CTRL0, RTL8390_TM_ENABLE, RTL8390_TM_ENABLE); +} + +static int rtl8390_get_temp(struct thermal_zone_device *tz, int *res) +{ + struct realtek_thermal_priv *priv = thermal_zone_device_priv(tz); + int offset = thermal_zone_get_offset(tz); + int slope = thermal_zone_get_slope(tz); + u32 val; + int ret; + + if (!priv->enabled) + rtl8390_thermal_init(priv); + /* assume sensor0 is the CPU, both sensor0 & sensor1 report same values +/- 1 degree C */ + ret = regmap_read(priv->regmap, RTL8390_THERMAL_METER0_RESULT, &val); + if (ret) + return ret; + + if (!(val & RTL8390_TEMP_VALID)) + return -EAGAIN; + + *res = FIELD_GET(RTL8390_TEMP_OUT_MASK, val) * slope + offset; + return 0; +} + +static const struct thermal_zone_device_ops rtl8390_ops = { + .get_temp = rtl8390_get_temp, +}; + +static void rtl9300_thermal_init(struct realtek_thermal_priv *priv) +{ + /* increasing sample delay makes get_temp() succeed more often */ + regmap_update_bits(priv->regmap, RTL9300_THERMAL_METER_CTRL1, RTL9300_SAMPLE_DLY_MASK, 0x0800 << RTL9300_SAMPLE_DLY_SHIFT); + priv->enabled = !regmap_update_bits(priv->regmap, RTL9300_THERMAL_METER_CTRL2, RTL9300_TM_ENABLE, RTL9300_TM_ENABLE); +} + +static int rtl9300_get_temp(struct thermal_zone_device *tz, int *res) +{ + struct realtek_thermal_priv *priv = thermal_zone_device_priv(tz); + int offset = thermal_zone_get_offset(tz); + int slope = thermal_zone_get_slope(tz); + u32 val; + int ret; + + if (!priv->enabled) + rtl9300_thermal_init(priv); + + ret = regmap_read(priv->regmap, RTL9300_THERMAL_METER_RESULT0, &val); + if (ret) + return ret; + if (!(val & RTL9300_TEMP_VALID)) + return -EAGAIN; + + *res = FIELD_GET(RTL9300_TEMP_OUT_MASK, val) * slope + offset; + return 0; +} + +static const struct thermal_zone_device_ops rtl9300_ops = { + .get_temp = rtl9300_get_temp, +}; + +static void rtl9607_thermal_init(struct realtek_thermal_priv *priv) +{ + priv->enabled = !regmap_update_bits(priv->regmap, RTL9607_THERMAL_CTRL_0, RTL9607_REG_PPOW, RTL9607_REG_PPOW); +} + +static int rtl9607_get_temp(struct thermal_zone_device *tz, int *res) +{ + struct realtek_thermal_priv *priv = thermal_zone_device_priv(tz); + int offset = thermal_zone_get_offset(tz); + int slope = thermal_zone_get_slope(tz); + u32 val; + int ret; + + if (!priv->enabled) + rtl9607_thermal_init(priv); + + ret = regmap_read(priv->regmap, RTL9607_THERMAL_STS_0, &val); + if (ret) + return ret; + + /* + * The temperature sensor output consist of sign at bit 18, integer part at bits 17~10 + * and fractional point with 0.5 scaling at bits 9~0. + * For simplicity, we only care about the integer part. + */ + *res = FIELD_GET(RTL9607_TEMP_OUT_INT, val) * slope + offset; + + return 0; +} + +static const struct thermal_zone_device_ops rtl9607_ops = { + .get_temp = rtl9607_get_temp, +}; + +static int realtek_thermal_probe(struct platform_device *pdev) +{ + struct realtek_thermal_priv *priv; + struct thermal_zone_device *tzdev; + struct device *dev = &pdev->dev; + struct regmap *regmap; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + regmap = syscon_node_to_regmap(dev->of_node->parent); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + priv->regmap = regmap; + tzdev = devm_thermal_of_zone_register(dev, 0, priv, device_get_match_data(dev)); + if (IS_ERR(tzdev)) + return PTR_ERR(tzdev); + + return devm_thermal_add_hwmon_sysfs(dev, tzdev); +} + +static const struct of_device_id realtek_sensor_ids[] = { + { .compatible = "realtek,rtl8380-thermal", .data = &rtl8380_ops, }, + { .compatible = "realtek,rtl8390-thermal", .data = &rtl8390_ops, }, + { .compatible = "realtek,rtl9300-thermal", .data = &rtl9300_ops, }, + { .compatible = "realtek,rtl9607-thermal", .data = &rtl9607_ops, }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, realtek_sensor_ids); + +static struct platform_driver realtek_thermal_driver = { + .probe = realtek_thermal_probe, + .driver = { + .name = "realtek-thermal", + .of_match_table = realtek_sensor_ids, + }, +}; + +module_platform_driver(realtek_thermal_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Bjørn Mork "); +MODULE_DESCRIPTION("Realtek temperature sensor"); diff --git a/target/linux/realtek/files-6.12/include/dt-bindings/clock/rtl83xx-clk.h b/target/linux/realtek/files-6.12/include/dt-bindings/clock/rtl83xx-clk.h new file mode 100644 index 0000000000..3937052cc5 --- /dev/null +++ b/target/linux/realtek/files-6.12/include/dt-bindings/clock/rtl83xx-clk.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2022 Markus Stockhausen + * + * RTL83XX clock indices + */ +#ifndef __DT_BINDINGS_CLOCK_RTL83XX_H +#define __DT_BINDINGS_CLOCK_RTL83XX_H + +#define CLK_CPU 0 +#define CLK_MEM 1 +#define CLK_LXB 2 +#define CLK_COUNT 3 + +#endif /* __DT_BINDINGS_CLOCK_RTL83XX_H */ diff --git a/target/linux/realtek/files-6.12/net/dsa/tag_rtl_otto.c b/target/linux/realtek/files-6.12/net/dsa/tag_rtl_otto.c new file mode 100644 index 0000000000..08a9915584 --- /dev/null +++ b/target/linux/realtek/files-6.12/net/dsa/tag_rtl_otto.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * net/dsa/tag_trailer.c - Trailer tag format handling + * Copyright (c) 2008-2009 Marvell Semiconductor + */ + +#include +#include +#include + +#include "tag.h" + +#define RTL_OTTO_NAME "rtl_otto" + +/* + * TODO: This driver was copied over from trailer tagging. It will be developed + * downstream in OpenWrt in conjunction with the Realtek Otto ethernet driver. + * For now rely on the old trailer handling and keep everything as is. + */ + +static struct sk_buff *rtl_otto_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct dsa_port *dp = dsa_user_to_port(dev); + u8 *trailer; + + trailer = skb_put(skb, 4); + trailer[0] = 0x80; + trailer[1] = dp->index; + trailer[2] = 0x10; + trailer[3] = 0x00; + + return skb; +} + +static struct sk_buff *rtl_otto_rcv(struct sk_buff *skb, struct net_device *dev) +{ + u8 *trailer; + int source_port; + + if (skb_linearize(skb)) + return NULL; + + trailer = skb_tail_pointer(skb) - 4; + + if (trailer[0] != 0x80 || (trailer[1] & 0x80) != 0x00 || + (trailer[2] & 0xef) != 0x00 || trailer[3] != 0x00) + return NULL; + + if (trailer[1] & 0x40) + skb->offload_fwd_mark = 1; + + source_port = trailer[1] & 0x3f; + + skb->dev = dsa_conduit_find_user(dev, 0, source_port); + if (!skb->dev) + return NULL; + + if (pskb_trim_rcsum(skb, skb->len - 4)) + return NULL; + + return skb; +} + +static const struct dsa_device_ops rtl_otto_netdev_ops = { + .name = RTL_OTTO_NAME, + .proto = DSA_TAG_PROTO_RTL_OTTO, + .xmit = rtl_otto_xmit, + .rcv = rtl_otto_rcv, + .needed_tailroom = 4, +}; + +MODULE_DESCRIPTION("DSA tag driver for Realtek Otto switches (RTL83xx/RTL93xx)"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_RTL_OTTO, RTL_OTTO_NAME); + +module_dsa_tag_driver(rtl_otto_netdev_ops); diff --git a/target/linux/realtek/patches-6.12/001-v6.13-spi-mem-add-realtek-nand-controller.patch b/target/linux/realtek/patches-6.12/001-v6.13-spi-mem-add-realtek-nand-controller.patch new file mode 100644 index 0000000000..1828e776f9 --- /dev/null +++ b/target/linux/realtek/patches-6.12/001-v6.13-spi-mem-add-realtek-nand-controller.patch @@ -0,0 +1,481 @@ +From 42d20a6a61b8fccbb57d80df1ccde7dd82d5bbd6 Mon Sep 17 00:00:00 2001 +From: Chris Packham +Date: Wed, 16 Oct 2024 11:54:34 +1300 +Subject: [PATCH] spi: spi-mem: Add Realtek SPI-NAND controller + +Add a driver for the SPI-NAND controller on the RTL9300 family of +devices. + +The controller supports +* Serial/Dual/Quad data with +* PIO and DMA data read/write operation +* Configurable flash access timing + +There is a separate ECC controller on the RTL9300 which isn't currently +supported (instead we rely on the on-die ECC supported by most SPI-NAND +chips). + +Signed-off-by: Chris Packham +Link: https://patch.msgid.link/20241015225434.3970360-4-chris.packham@alliedtelesis.co.nz +Signed-off-by: Mark Brown +--- + MAINTAINERS | 6 + + drivers/spi/Kconfig | 11 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-realtek-rtl-snand.c | 405 ++++++++++++++++++++++++++++ + 4 files changed, 423 insertions(+) + create mode 100644 drivers/spi/spi-realtek-rtl-snand.c + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -19507,6 +19507,12 @@ S: Maintained + F: Documentation/devicetree/bindings/net/dsa/realtek.yaml + F: drivers/net/dsa/realtek/* + ++REALTEK SPI-NAND ++M: Chris Packham ++S: Maintained ++F: Documentation/devicetree/bindings/spi/realtek,rtl9301-snand.yaml ++F: drivers/spi/spi-realtek-rtl-snand.c ++ + REALTEK WIRELESS DRIVER (rtlwifi family) + M: Ping-Ke Shih + L: linux-wireless@vger.kernel.org +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -843,6 +843,17 @@ config SPI_PXA2XX + config SPI_PXA2XX_PCI + def_tristate SPI_PXA2XX && PCI && COMMON_CLK + ++config SPI_REALTEK_SNAND ++ tristate "Realtek SPI-NAND Flash Controller" ++ depends on MACH_REALTEK_RTL || COMPILE_TEST ++ select REGMAP ++ help ++ This enables support for the SPI-NAND Flash controller on ++ Realtek SoCs. ++ ++ This driver does not support generic SPI. The implementation ++ only supports the spi-mem interface. ++ + config SPI_ROCKCHIP + tristate "Rockchip SPI controller driver" + depends on ARCH_ROCKCHIP || COMPILE_TEST +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -120,6 +120,7 @@ obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockc + obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o + obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o + obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o ++obj-$(CONFIG_SPI_REALTEK_SNAND) += spi-realtek-rtl-snand.o + obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o + obj-$(CONFIG_SPI_RSPI) += spi-rspi.o + obj-$(CONFIG_SPI_RZV2M_CSI) += spi-rzv2m-csi.o +--- /dev/null ++++ b/drivers/spi/spi-realtek-rtl-snand.c +@@ -0,0 +1,405 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SNAFCFR 0x00 ++#define SNAFCFR_DMA_IE BIT(20) ++#define SNAFCCR 0x04 ++#define SNAFWCMR 0x08 ++#define SNAFRCMR 0x0c ++#define SNAFRDR 0x10 ++#define SNAFWDR 0x14 ++#define SNAFDTR 0x18 ++#define SNAFDRSAR 0x1c ++#define SNAFDIR 0x20 ++#define SNAFDIR_DMA_IP BIT(0) ++#define SNAFDLR 0x24 ++#define SNAFSR 0x40 ++#define SNAFSR_NFCOS BIT(3) ++#define SNAFSR_NFDRS BIT(2) ++#define SNAFSR_NFDWS BIT(1) ++ ++#define CMR_LEN(len) ((len) - 1) ++#define CMR_WID(width) (((width) >> 1) << 28) ++ ++struct rtl_snand { ++ struct device *dev; ++ struct regmap *regmap; ++ struct completion comp; ++}; ++ ++static irqreturn_t rtl_snand_irq(int irq, void *data) ++{ ++ struct rtl_snand *snand = data; ++ u32 val = 0; ++ ++ regmap_read(snand->regmap, SNAFSR, &val); ++ if (val & (SNAFSR_NFCOS | SNAFSR_NFDRS | SNAFSR_NFDWS)) ++ return IRQ_NONE; ++ ++ regmap_write(snand->regmap, SNAFDIR, SNAFDIR_DMA_IP); ++ complete(&snand->comp); ++ ++ return IRQ_HANDLED; ++} ++ ++static bool rtl_snand_supports_op(struct spi_mem *mem, ++ const struct spi_mem_op *op) ++{ ++ if (!spi_mem_default_supports_op(mem, op)) ++ return false; ++ if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1) ++ return false; ++ return true; ++} ++ ++static void rtl_snand_set_cs(struct rtl_snand *snand, int cs, bool active) ++{ ++ u32 val; ++ ++ if (active) ++ val = ~(1 << (4 * cs)); ++ else ++ val = ~0; ++ ++ regmap_write(snand->regmap, SNAFCCR, val); ++} ++ ++static int rtl_snand_wait_ready(struct rtl_snand *snand) ++{ ++ u32 val; ++ ++ return regmap_read_poll_timeout(snand->regmap, SNAFSR, val, !(val & SNAFSR_NFCOS), ++ 0, 2 * USEC_PER_MSEC); ++} ++ ++static int rtl_snand_xfer_head(struct rtl_snand *snand, int cs, const struct spi_mem_op *op) ++{ ++ int ret; ++ u32 val, len = 0; ++ ++ rtl_snand_set_cs(snand, cs, true); ++ ++ val = op->cmd.opcode << 24; ++ len = 1; ++ if (op->addr.nbytes && op->addr.buswidth == 1) { ++ val |= op->addr.val << ((3 - op->addr.nbytes) * 8); ++ len += op->addr.nbytes; ++ } ++ ++ ret = rtl_snand_wait_ready(snand); ++ if (ret) ++ return ret; ++ ++ ret = regmap_write(snand->regmap, SNAFWCMR, CMR_LEN(len)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_write(snand->regmap, SNAFWDR, val); ++ if (ret) ++ return ret; ++ ++ ret = rtl_snand_wait_ready(snand); ++ if (ret) ++ return ret; ++ ++ if (op->addr.buswidth > 1) { ++ val = op->addr.val << ((3 - op->addr.nbytes) * 8); ++ len = op->addr.nbytes; ++ ++ ret = regmap_write(snand->regmap, SNAFWCMR, ++ CMR_WID(op->addr.buswidth) | CMR_LEN(len)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_write(snand->regmap, SNAFWDR, val); ++ if (ret) ++ return ret; ++ ++ ret = rtl_snand_wait_ready(snand); ++ if (ret) ++ return ret; ++ } ++ ++ if (op->dummy.nbytes) { ++ val = 0; ++ ++ ret = regmap_write(snand->regmap, SNAFWCMR, ++ CMR_WID(op->dummy.buswidth) | CMR_LEN(op->dummy.nbytes)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_write(snand->regmap, SNAFWDR, val); ++ if (ret) ++ return ret; ++ ++ ret = rtl_snand_wait_ready(snand); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void rtl_snand_xfer_tail(struct rtl_snand *snand, int cs) ++{ ++ rtl_snand_set_cs(snand, cs, false); ++} ++ ++static int rtl_snand_xfer(struct rtl_snand *snand, int cs, const struct spi_mem_op *op) ++{ ++ unsigned int pos, nbytes; ++ int ret; ++ u32 val, len = 0; ++ ++ ret = rtl_snand_xfer_head(snand, cs, op); ++ if (ret) ++ goto out_deselect; ++ ++ if (op->data.dir == SPI_MEM_DATA_IN) { ++ pos = 0; ++ len = op->data.nbytes; ++ ++ while (pos < len) { ++ nbytes = len - pos; ++ if (nbytes > 4) ++ nbytes = 4; ++ ++ ret = rtl_snand_wait_ready(snand); ++ if (ret) ++ goto out_deselect; ++ ++ ret = regmap_write(snand->regmap, SNAFRCMR, ++ CMR_WID(op->data.buswidth) | CMR_LEN(nbytes)); ++ if (ret) ++ goto out_deselect; ++ ++ ret = rtl_snand_wait_ready(snand); ++ if (ret) ++ goto out_deselect; ++ ++ ret = regmap_read(snand->regmap, SNAFRDR, &val); ++ if (ret) ++ goto out_deselect; ++ ++ memcpy(op->data.buf.in + pos, &val, nbytes); ++ ++ pos += nbytes; ++ } ++ } else if (op->data.dir == SPI_MEM_DATA_OUT) { ++ pos = 0; ++ len = op->data.nbytes; ++ ++ while (pos < len) { ++ nbytes = len - pos; ++ if (nbytes > 4) ++ nbytes = 4; ++ ++ memcpy(&val, op->data.buf.out + pos, nbytes); ++ ++ pos += nbytes; ++ ++ ret = regmap_write(snand->regmap, SNAFWCMR, CMR_LEN(nbytes)); ++ if (ret) ++ goto out_deselect; ++ ++ ret = regmap_write(snand->regmap, SNAFWDR, val); ++ if (ret) ++ goto out_deselect; ++ ++ ret = rtl_snand_wait_ready(snand); ++ if (ret) ++ goto out_deselect; ++ } ++ } ++ ++out_deselect: ++ rtl_snand_xfer_tail(snand, cs); ++ ++ if (ret) ++ dev_err(snand->dev, "transfer failed %d\n", ret); ++ ++ return ret; ++} ++ ++static int rtl_snand_dma_xfer(struct rtl_snand *snand, int cs, const struct spi_mem_op *op) ++{ ++ int ret; ++ dma_addr_t buf_dma; ++ enum dma_data_direction dir; ++ u32 trig; ++ ++ ret = rtl_snand_xfer_head(snand, cs, op); ++ if (ret) ++ goto out_deselect; ++ ++ if (op->data.dir == SPI_MEM_DATA_IN) { ++ dir = DMA_FROM_DEVICE; ++ trig = 0; ++ } else if (op->data.dir == SPI_MEM_DATA_OUT) { ++ dir = DMA_TO_DEVICE; ++ trig = 1; ++ } else { ++ ret = -EOPNOTSUPP; ++ goto out_deselect; ++ } ++ ++ buf_dma = dma_map_single(snand->dev, op->data.buf.in, op->data.nbytes, dir); ++ ret = dma_mapping_error(snand->dev, buf_dma); ++ if (ret) ++ goto out_deselect; ++ ++ ret = regmap_write(snand->regmap, SNAFDIR, SNAFDIR_DMA_IP); ++ if (ret) ++ goto out_unmap; ++ ++ ret = regmap_update_bits(snand->regmap, SNAFCFR, SNAFCFR_DMA_IE, SNAFCFR_DMA_IE); ++ if (ret) ++ goto out_unmap; ++ ++ reinit_completion(&snand->comp); ++ ++ ret = regmap_write(snand->regmap, SNAFDRSAR, buf_dma); ++ if (ret) ++ goto out_disable_int; ++ ++ ret = regmap_write(snand->regmap, SNAFDLR, ++ CMR_WID(op->data.buswidth) | (op->data.nbytes & 0xffff)); ++ if (ret) ++ goto out_disable_int; ++ ++ ret = regmap_write(snand->regmap, SNAFDTR, trig); ++ if (ret) ++ goto out_disable_int; ++ ++ if (!wait_for_completion_timeout(&snand->comp, usecs_to_jiffies(20000))) ++ ret = -ETIMEDOUT; ++ ++ if (ret) ++ goto out_disable_int; ++ ++out_disable_int: ++ regmap_update_bits(snand->regmap, SNAFCFR, SNAFCFR_DMA_IE, 0); ++out_unmap: ++ dma_unmap_single(snand->dev, buf_dma, op->data.nbytes, dir); ++out_deselect: ++ rtl_snand_xfer_tail(snand, cs); ++ ++ if (ret) ++ dev_err(snand->dev, "transfer failed %d\n", ret); ++ ++ return ret; ++} ++ ++static bool rtl_snand_dma_op(const struct spi_mem_op *op) ++{ ++ switch (op->data.dir) { ++ case SPI_MEM_DATA_IN: ++ case SPI_MEM_DATA_OUT: ++ return op->data.nbytes > 32; ++ default: ++ return false; ++ } ++} ++ ++static int rtl_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) ++{ ++ struct rtl_snand *snand = spi_controller_get_devdata(mem->spi->controller); ++ int cs = spi_get_chipselect(mem->spi, 0); ++ ++ dev_dbg(snand->dev, "cs %d op cmd %02x %d:%d, dummy %d:%d, addr %08llx@%d:%d, data %d:%d\n", ++ cs, op->cmd.opcode, ++ op->cmd.buswidth, op->cmd.nbytes, op->dummy.buswidth, ++ op->dummy.nbytes, op->addr.val, op->addr.buswidth, ++ op->addr.nbytes, op->data.buswidth, op->data.nbytes); ++ ++ if (rtl_snand_dma_op(op)) ++ return rtl_snand_dma_xfer(snand, cs, op); ++ else ++ return rtl_snand_xfer(snand, cs, op); ++} ++ ++static const struct spi_controller_mem_ops rtl_snand_mem_ops = { ++ .supports_op = rtl_snand_supports_op, ++ .exec_op = rtl_snand_exec_op, ++}; ++ ++static const struct of_device_id rtl_snand_match[] = { ++ { .compatible = "realtek,rtl9301-snand" }, ++ { .compatible = "realtek,rtl9302b-snand" }, ++ { .compatible = "realtek,rtl9302c-snand" }, ++ { .compatible = "realtek,rtl9303-snand" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, rtl_snand_match); ++ ++static int rtl_snand_probe(struct platform_device *pdev) ++{ ++ struct rtl_snand *snand; ++ struct device *dev = &pdev->dev; ++ struct spi_controller *ctrl; ++ void __iomem *base; ++ const struct regmap_config rc = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = 4, ++ .cache_type = REGCACHE_NONE, ++ }; ++ int irq, ret; ++ ++ ctrl = devm_spi_alloc_host(dev, sizeof(*snand)); ++ if (!ctrl) ++ return -ENOMEM; ++ ++ snand = spi_controller_get_devdata(ctrl); ++ snand->dev = dev; ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ snand->regmap = devm_regmap_init_mmio(dev, base, &rc); ++ if (IS_ERR(snand->regmap)) ++ return PTR_ERR(snand->regmap); ++ ++ init_completion(&snand->comp); ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return irq; ++ ++ ret = dma_set_mask(snand->dev, DMA_BIT_MASK(32)); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to set DMA mask\n"); ++ ++ ret = devm_request_irq(dev, irq, rtl_snand_irq, 0, "rtl-snand", snand); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to request irq\n"); ++ ++ ctrl->num_chipselect = 2; ++ ctrl->mem_ops = &rtl_snand_mem_ops; ++ ctrl->bits_per_word_mask = SPI_BPW_MASK(8); ++ ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; ++ device_set_node(&ctrl->dev, dev_fwnode(dev)); ++ ++ return devm_spi_register_controller(dev, ctrl); ++} ++ ++static struct platform_driver rtl_snand_driver = { ++ .driver = { ++ .name = "realtek-rtl-snand", ++ .of_match_table = rtl_snand_match, ++ }, ++ .probe = rtl_snand_probe, ++}; ++module_platform_driver(rtl_snand_driver); ++ ++MODULE_DESCRIPTION("Realtek SPI-NAND Flash Controller Driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/realtek/patches-6.12/002-v6.13-spi-mem-rtl-snand-correctly-handle-dma-transfers.patch b/target/linux/realtek/patches-6.12/002-v6.13-spi-mem-rtl-snand-correctly-handle-dma-transfers.patch new file mode 100644 index 0000000000..a929c67097 --- /dev/null +++ b/target/linux/realtek/patches-6.12/002-v6.13-spi-mem-rtl-snand-correctly-handle-dma-transfers.patch @@ -0,0 +1,96 @@ +From 25d284715845a465a1a3693a09cf8b6ab8bd9caf Mon Sep 17 00:00:00 2001 +From: Chris Packham +Date: Thu, 31 Oct 2024 08:49:20 +1300 +Subject: [PATCH] spi: spi-mem: rtl-snand: Correctly handle DMA transfers + +The RTL9300 has some limitations on the maximum DMA transfers possible. +For reads this is 2080 bytes (520*4) for writes this is 520 bytes. Deal +with this by splitting transfers into appropriately sized parts. + +Fixes: 42d20a6a61b8 ("spi: spi-mem: Add Realtek SPI-NAND controller") +Signed-off-by: Chris Packham +Link: https://patch.msgid.link/20241030194920.3202282-1-chris.packham@alliedtelesis.co.nz +Signed-off-by: Mark Brown +--- + drivers/spi/spi-realtek-rtl-snand.c | 46 +++++++++++++++++++---------- + 1 file changed, 30 insertions(+), 16 deletions(-) + +--- a/drivers/spi/spi-realtek-rtl-snand.c ++++ b/drivers/spi/spi-realtek-rtl-snand.c +@@ -231,19 +231,22 @@ out_deselect: + + static int rtl_snand_dma_xfer(struct rtl_snand *snand, int cs, const struct spi_mem_op *op) + { ++ unsigned int pos, nbytes; + int ret; + dma_addr_t buf_dma; + enum dma_data_direction dir; +- u32 trig; ++ u32 trig, len, maxlen; + + ret = rtl_snand_xfer_head(snand, cs, op); + if (ret) + goto out_deselect; + + if (op->data.dir == SPI_MEM_DATA_IN) { ++ maxlen = 2080; + dir = DMA_FROM_DEVICE; + trig = 0; + } else if (op->data.dir == SPI_MEM_DATA_OUT) { ++ maxlen = 520; + dir = DMA_TO_DEVICE; + trig = 1; + } else { +@@ -264,26 +267,37 @@ static int rtl_snand_dma_xfer(struct rtl + if (ret) + goto out_unmap; + +- reinit_completion(&snand->comp); ++ pos = 0; ++ len = op->data.nbytes; + +- ret = regmap_write(snand->regmap, SNAFDRSAR, buf_dma); +- if (ret) +- goto out_disable_int; ++ while (pos < len) { ++ nbytes = len - pos; ++ if (nbytes > maxlen) ++ nbytes = maxlen; + +- ret = regmap_write(snand->regmap, SNAFDLR, +- CMR_WID(op->data.buswidth) | (op->data.nbytes & 0xffff)); +- if (ret) +- goto out_disable_int; ++ reinit_completion(&snand->comp); + +- ret = regmap_write(snand->regmap, SNAFDTR, trig); +- if (ret) +- goto out_disable_int; ++ ret = regmap_write(snand->regmap, SNAFDRSAR, buf_dma + pos); ++ if (ret) ++ goto out_disable_int; + +- if (!wait_for_completion_timeout(&snand->comp, usecs_to_jiffies(20000))) +- ret = -ETIMEDOUT; ++ pos += nbytes; + +- if (ret) +- goto out_disable_int; ++ ret = regmap_write(snand->regmap, SNAFDLR, ++ CMR_WID(op->data.buswidth) | nbytes); ++ if (ret) ++ goto out_disable_int; ++ ++ ret = regmap_write(snand->regmap, SNAFDTR, trig); ++ if (ret) ++ goto out_disable_int; ++ ++ if (!wait_for_completion_timeout(&snand->comp, usecs_to_jiffies(20000))) ++ ret = -ETIMEDOUT; ++ ++ if (ret) ++ goto out_disable_int; ++ } + + out_disable_int: + regmap_update_bits(snand->regmap, SNAFCFR, SNAFCFR_DMA_IE, 0); diff --git a/target/linux/realtek/patches-6.12/003-v6.13-01-dt-bindings-i2c-Add-Realtek-RTL-I2C-Controller.patch b/target/linux/realtek/patches-6.12/003-v6.13-01-dt-bindings-i2c-Add-Realtek-RTL-I2C-Controller.patch new file mode 100644 index 0000000000..8ec0d04127 --- /dev/null +++ b/target/linux/realtek/patches-6.12/003-v6.13-01-dt-bindings-i2c-Add-Realtek-RTL-I2C-Controller.patch @@ -0,0 +1,84 @@ +From c5eda0333076e031197816454998a918f1de0831 Mon Sep 17 00:00:00 2001 +From: Chris Packham +Date: Fri, 1 Nov 2024 09:03:46 +1300 +Subject: [PATCH] dt-bindings: i2c: Add Realtek RTL I2C Controller + +Add dt-schema for the I2C controller on the RTL9300 Ethernet switch +with integrated SoC. + +Signed-off-by: Chris Packham +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Andi Shyti + +--- /dev/null ++++ b/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml +@@ -0,0 +1,69 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/i2c/realtek,rtl9301-i2c.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Realtek RTL I2C Controller ++ ++maintainers: ++ - Chris Packham ++ ++description: ++ The RTL9300 SoC has two I2C controllers. Each of these has an SCL line (which ++ if not-used for SCL can be a GPIO). There are 8 common SDA lines that can be ++ assigned to either I2C controller. ++ ++properties: ++ compatible: ++ oneOf: ++ - items: ++ - enum: ++ - realtek,rtl9302b-i2c ++ - realtek,rtl9302c-i2c ++ - realtek,rtl9303-i2c ++ - const: realtek,rtl9301-i2c ++ - const: realtek,rtl9301-i2c ++ ++ reg: ++ description: Register offset and size this I2C controller. ++ ++ "#address-cells": ++ const: 1 ++ ++ "#size-cells": ++ const: 0 ++ ++patternProperties: ++ '^i2c@[0-7]$': ++ $ref: /schemas/i2c/i2c-controller.yaml ++ unevaluatedProperties: false ++ ++ properties: ++ reg: ++ description: The SDA pin associated with the I2C bus. ++ maxItems: 1 ++ ++ required: ++ - reg ++ ++required: ++ - compatible ++ - reg ++ ++additionalProperties: false ++ ++examples: ++ - | ++ i2c@36c { ++ compatible = "realtek,rtl9301-i2c"; ++ reg = <0x36c 0x14>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ i2c@2 { ++ reg = <2>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; diff --git a/target/linux/realtek/patches-6.12/003-v6.13-02-i2c-Add-driver-for-the-RTL9300-I2C-controller.patch b/target/linux/realtek/patches-6.12/003-v6.13-02-i2c-Add-driver-for-the-RTL9300-I2C-controller.patch new file mode 100644 index 0000000000..d5229284a0 --- /dev/null +++ b/target/linux/realtek/patches-6.12/003-v6.13-02-i2c-Add-driver-for-the-RTL9300-I2C-controller.patch @@ -0,0 +1,493 @@ +From c366be720235301fdadf67e6f1ea6ff32669c074 Mon Sep 17 00:00:00 2001 +From: Chris Packham +Date: Wed, 6 Nov 2024 13:18:35 +1300 +Subject: [PATCH] i2c: Add driver for the RTL9300 I2C controller + +Add support for the I2C controller on the RTL9300 SoC. There are two I2C +controllers in the RTL9300 that are part of the Ethernet switch register +block. Each of these controllers owns a SCL pin (GPIO8 for the fiorst +I2C controller, GPIO17 for the second). There are 8 possible SDA pins +(GPIO9-16) that can be assigned to either I2C controller. This +relationship is represented in the device tree with a child node for +each SDA line in use. + +This is based on the openwrt implementation[1] but has been +significantly modified + +[1] - https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.c + +Signed-off-by: Chris Packham +Reviewed-by: Andi Shyti +Signed-off-by: Andi Shyti + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -20164,6 +20164,13 @@ S: Maintained + T: git https://github.com/pkshih/rtw.git + F: drivers/net/wireless/realtek/rtl8xxxu/ + ++RTL9300 I2C DRIVER (rtl9300-i2c) ++M: Chris Packham ++L: linux-i2c@vger.kernel.org ++S: Maintained ++F: Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml ++F: drivers/i2c/busses/i2c-rtl9300.c ++ + RTRS TRANSPORT DRIVERS + M: Md. Haris Iqbal + M: Jack Wang +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -1062,6 +1062,16 @@ config I2C_RK3X + This driver can also be built as a module. If so, the module will + be called i2c-rk3x. + ++config I2C_RTL9300 ++ tristate "Realtek RTL9300 I2C controller" ++ depends on MACH_REALTEK_RTL || COMPILE_TEST ++ help ++ Say Y here to include support for the I2C controller in Realtek ++ RTL9300 SoCs. ++ ++ This driver can also be built as a module. If so, the module will ++ be called i2c-rtl9300. ++ + config I2C_RZV2M + tristate "Renesas RZ/V2M adapter" + depends on ARCH_RENESAS || COMPILE_TEST +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -103,6 +103,7 @@ obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom- + obj-$(CONFIG_I2C_QUP) += i2c-qup.o + obj-$(CONFIG_I2C_RIIC) += i2c-riic.o + obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o ++obj-$(CONFIG_I2C_RTL9300) += i2c-rtl9300.o + obj-$(CONFIG_I2C_RZV2M) += i2c-rzv2m.o + obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o + obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o +--- /dev/null ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -0,0 +1,423 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++enum rtl9300_bus_freq { ++ RTL9300_I2C_STD_FREQ, ++ RTL9300_I2C_FAST_FREQ, ++}; ++ ++struct rtl9300_i2c; ++ ++struct rtl9300_i2c_chan { ++ struct i2c_adapter adap; ++ struct rtl9300_i2c *i2c; ++ enum rtl9300_bus_freq bus_freq; ++ u8 sda_pin; ++}; ++ ++#define RTL9300_I2C_MUX_NCHAN 8 ++ ++struct rtl9300_i2c { ++ struct regmap *regmap; ++ struct device *dev; ++ struct rtl9300_i2c_chan chans[RTL9300_I2C_MUX_NCHAN]; ++ u32 reg_base; ++ u8 sda_pin; ++ struct mutex lock; ++}; ++ ++#define RTL9300_I2C_MST_CTRL1 0x0 ++#define RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS 8 ++#define RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK GENMASK(31, 8) ++#define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS 4 ++#define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK GENMASK(6, 4) ++#define RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL BIT(3) ++#define RTL9300_I2C_MST_CTRL1_RWOP BIT(2) ++#define RTL9300_I2C_MST_CTRL1_I2C_FAIL BIT(1) ++#define RTL9300_I2C_MST_CTRL1_I2C_TRIG BIT(0) ++#define RTL9300_I2C_MST_CTRL2 0x4 ++#define RTL9300_I2C_MST_CTRL2_RD_MODE BIT(15) ++#define RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS 8 ++#define RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK GENMASK(14, 8) ++#define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS 4 ++#define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK GENMASK(7, 4) ++#define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS 2 ++#define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK GENMASK(3, 2) ++#define RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS 0 ++#define RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK GENMASK(1, 0) ++#define RTL9300_I2C_MST_DATA_WORD0 0x8 ++#define RTL9300_I2C_MST_DATA_WORD1 0xc ++#define RTL9300_I2C_MST_DATA_WORD2 0x10 ++#define RTL9300_I2C_MST_DATA_WORD3 0x14 ++ ++#define RTL9300_I2C_MST_GLB_CTRL 0x384 ++ ++static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len) ++{ ++ u32 val, mask; ++ int ret; ++ ++ val = len << RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS; ++ mask = RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK; ++ ++ ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val); ++ if (ret) ++ return ret; ++ ++ val = reg << RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS; ++ mask = RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK; ++ ++ return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val); ++} ++ ++static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, u8 sda_pin) ++{ ++ int ret; ++ u32 val, mask; ++ ++ ret = regmap_update_bits(i2c->regmap, RTL9300_I2C_MST_GLB_CTRL, BIT(sda_pin), BIT(sda_pin)); ++ if (ret) ++ return ret; ++ ++ val = (sda_pin << RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS) | ++ RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL; ++ mask = RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK | RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL; ++ ++ return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val); ++} ++ ++static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan, ++ u16 addr, u16 len) ++{ ++ u32 val, mask; ++ ++ val = chan->bus_freq << RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS; ++ mask = RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK; ++ ++ val |= addr << RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS; ++ mask |= RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK; ++ ++ val |= ((len - 1) & 0xf) << RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS; ++ mask |= RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK; ++ ++ mask |= RTL9300_I2C_MST_CTRL2_RD_MODE; ++ ++ return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val); ++} ++ ++static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len) ++{ ++ u32 vals[4] = {}; ++ int i, ret; ++ ++ if (len > 16) ++ return -EIO; ++ ++ ret = regmap_bulk_read(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, ++ vals, ARRAY_SIZE(vals)); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < len; i++) { ++ buf[i] = vals[i/4] & 0xff; ++ vals[i/4] >>= 8; ++ } ++ ++ return 0; ++} ++ ++static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len) ++{ ++ u32 vals[4] = {}; ++ int i; ++ ++ if (len > 16) ++ return -EIO; ++ ++ for (i = 0; i < len; i++) { ++ if (i % 4 == 0) ++ vals[i/4] = 0; ++ vals[i/4] <<= 8; ++ vals[i/4] |= buf[i]; ++ } ++ ++ return regmap_bulk_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, ++ vals, ARRAY_SIZE(vals)); ++} ++ ++static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data) ++{ ++ return regmap_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, data); ++} ++ ++static int rtl9300_i2c_execute_xfer(struct rtl9300_i2c *i2c, char read_write, ++ int size, union i2c_smbus_data *data, int len) ++{ ++ u32 val, mask; ++ int ret; ++ ++ val = read_write == I2C_SMBUS_WRITE ? RTL9300_I2C_MST_CTRL1_RWOP : 0; ++ mask = RTL9300_I2C_MST_CTRL1_RWOP; ++ ++ val |= RTL9300_I2C_MST_CTRL1_I2C_TRIG; ++ mask |= RTL9300_I2C_MST_CTRL1_I2C_TRIG; ++ ++ ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val); ++ if (ret) ++ return ret; ++ ++ ret = regmap_read_poll_timeout(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, ++ val, !(val & RTL9300_I2C_MST_CTRL1_I2C_TRIG), 100, 2000); ++ if (ret) ++ return ret; ++ ++ if (val & RTL9300_I2C_MST_CTRL1_I2C_FAIL) ++ return -EIO; ++ ++ if (read_write == I2C_SMBUS_READ) { ++ if (size == I2C_SMBUS_BYTE || size == I2C_SMBUS_BYTE_DATA) { ++ ret = regmap_read(i2c->regmap, ++ i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val); ++ if (ret) ++ return ret; ++ data->byte = val & 0xff; ++ } else if (size == I2C_SMBUS_WORD_DATA) { ++ ret = regmap_read(i2c->regmap, ++ i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val); ++ if (ret) ++ return ret; ++ data->word = val & 0xffff; ++ } else { ++ ret = rtl9300_i2c_read(i2c, &data->block[0], len); ++ if (ret) ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int rtl9300_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, unsigned short flags, ++ char read_write, u8 command, int size, ++ union i2c_smbus_data *data) ++{ ++ struct rtl9300_i2c_chan *chan = i2c_get_adapdata(adap); ++ struct rtl9300_i2c *i2c = chan->i2c; ++ int len = 0, ret; ++ ++ mutex_lock(&i2c->lock); ++ if (chan->sda_pin != i2c->sda_pin) { ++ ret = rtl9300_i2c_config_io(i2c, chan->sda_pin); ++ if (ret) ++ goto out_unlock; ++ i2c->sda_pin = chan->sda_pin; ++ } ++ ++ switch (size) { ++ case I2C_SMBUS_QUICK: ++ ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 0); ++ if (ret) ++ goto out_unlock; ++ ret = rtl9300_i2c_reg_addr_set(i2c, 0, 0); ++ if (ret) ++ goto out_unlock; ++ break; ++ ++ case I2C_SMBUS_BYTE: ++ if (read_write == I2C_SMBUS_WRITE) { ++ ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 0); ++ if (ret) ++ goto out_unlock; ++ ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); ++ if (ret) ++ goto out_unlock; ++ } else { ++ ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 1); ++ if (ret) ++ goto out_unlock; ++ ret = rtl9300_i2c_reg_addr_set(i2c, 0, 0); ++ if (ret) ++ goto out_unlock; ++ } ++ break; ++ ++ case I2C_SMBUS_BYTE_DATA: ++ ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); ++ if (ret) ++ goto out_unlock; ++ ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 1); ++ if (ret) ++ goto out_unlock; ++ if (read_write == I2C_SMBUS_WRITE) { ++ ret = rtl9300_i2c_writel(i2c, data->byte); ++ if (ret) ++ goto out_unlock; ++ } ++ break; ++ ++ case I2C_SMBUS_WORD_DATA: ++ ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); ++ if (ret) ++ goto out_unlock; ++ ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 2); ++ if (ret) ++ goto out_unlock; ++ if (read_write == I2C_SMBUS_WRITE) { ++ ret = rtl9300_i2c_writel(i2c, data->word); ++ if (ret) ++ goto out_unlock; ++ } ++ break; ++ ++ case I2C_SMBUS_BLOCK_DATA: ++ ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); ++ if (ret) ++ goto out_unlock; ++ ret = rtl9300_i2c_config_xfer(i2c, chan, addr, data->block[0]); ++ if (ret) ++ goto out_unlock; ++ if (read_write == I2C_SMBUS_WRITE) { ++ ret = rtl9300_i2c_write(i2c, &data->block[1], data->block[0]); ++ if (ret) ++ goto out_unlock; ++ } ++ len = data->block[0]; ++ break; ++ ++ default: ++ dev_err(&adap->dev, "Unsupported transaction %d\n", size); ++ ret = -EOPNOTSUPP; ++ goto out_unlock; ++ } ++ ++ ret = rtl9300_i2c_execute_xfer(i2c, read_write, size, data, len); ++ ++out_unlock: ++ mutex_unlock(&i2c->lock); ++ ++ return ret; ++} ++ ++static u32 rtl9300_i2c_func(struct i2c_adapter *a) ++{ ++ return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | ++ I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | ++ I2C_FUNC_SMBUS_BLOCK_DATA; ++} ++ ++static const struct i2c_algorithm rtl9300_i2c_algo = { ++ .smbus_xfer = rtl9300_i2c_smbus_xfer, ++ .functionality = rtl9300_i2c_func, ++}; ++ ++static struct i2c_adapter_quirks rtl9300_i2c_quirks = { ++ .flags = I2C_AQ_NO_CLK_STRETCH, ++ .max_read_len = 16, ++ .max_write_len = 16, ++}; ++ ++static int rtl9300_i2c_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct rtl9300_i2c *i2c; ++ u32 clock_freq, sda_pin; ++ int ret, i = 0; ++ struct fwnode_handle *child; ++ ++ i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); ++ if (!i2c) ++ return -ENOMEM; ++ ++ i2c->regmap = syscon_node_to_regmap(dev->parent->of_node); ++ if (IS_ERR(i2c->regmap)) ++ return PTR_ERR(i2c->regmap); ++ i2c->dev = dev; ++ ++ mutex_init(&i2c->lock); ++ ++ ret = device_property_read_u32(dev, "reg", &i2c->reg_base); ++ if (ret) ++ return ret; ++ ++ platform_set_drvdata(pdev, i2c); ++ ++ if (device_get_child_node_count(dev) >= RTL9300_I2C_MUX_NCHAN) ++ return dev_err_probe(dev, -EINVAL, "Too many channels\n"); ++ ++ device_for_each_child_node(dev, child) { ++ struct rtl9300_i2c_chan *chan = &i2c->chans[i]; ++ struct i2c_adapter *adap = &chan->adap; ++ ++ ret = fwnode_property_read_u32(child, "reg", &sda_pin); ++ if (ret) ++ return ret; ++ ++ ret = fwnode_property_read_u32(child, "clock-frequency", &clock_freq); ++ if (ret) ++ clock_freq = I2C_MAX_STANDARD_MODE_FREQ; ++ ++ switch (clock_freq) { ++ case I2C_MAX_STANDARD_MODE_FREQ: ++ chan->bus_freq = RTL9300_I2C_STD_FREQ; ++ break; ++ ++ case I2C_MAX_FAST_MODE_FREQ: ++ chan->bus_freq = RTL9300_I2C_FAST_FREQ; ++ break; ++ default: ++ dev_warn(i2c->dev, "SDA%d clock-frequency %d not supported using default\n", ++ sda_pin, clock_freq); ++ break; ++ } ++ ++ chan->sda_pin = sda_pin; ++ chan->i2c = i2c; ++ adap = &i2c->chans[i].adap; ++ adap->owner = THIS_MODULE; ++ adap->algo = &rtl9300_i2c_algo; ++ adap->quirks = &rtl9300_i2c_quirks; ++ adap->retries = 3; ++ adap->dev.parent = dev; ++ i2c_set_adapdata(adap, chan); ++ adap->dev.of_node = to_of_node(child); ++ snprintf(adap->name, sizeof(adap->name), "%s SDA%d\n", dev_name(dev), sda_pin); ++ i++; ++ ++ ret = devm_i2c_add_adapter(dev, adap); ++ if (ret) ++ return ret; ++ } ++ i2c->sda_pin = 0xff; ++ ++ return 0; ++} ++ ++static const struct of_device_id i2c_rtl9300_dt_ids[] = { ++ { .compatible = "realtek,rtl9301-i2c" }, ++ { .compatible = "realtek,rtl9302b-i2c" }, ++ { .compatible = "realtek,rtl9302c-i2c" }, ++ { .compatible = "realtek,rtl9303-i2c" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids); ++ ++static struct platform_driver rtl9300_i2c_driver = { ++ .probe = rtl9300_i2c_probe, ++ .driver = { ++ .name = "i2c-rtl9300", ++ .of_match_table = i2c_rtl9300_dt_ids, ++ }, ++}; ++ ++module_platform_driver(rtl9300_i2c_driver); ++ ++MODULE_DESCRIPTION("RTL9300 I2C controller driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/realtek/patches-6.12/004-v6.16-dt-bindings-i2c-realtek-rtl9301-Fix-missing-reg-cons.patch b/target/linux/realtek/patches-6.12/004-v6.16-dt-bindings-i2c-realtek-rtl9301-Fix-missing-reg-cons.patch new file mode 100644 index 0000000000..c460eb1a40 --- /dev/null +++ b/target/linux/realtek/patches-6.12/004-v6.16-dt-bindings-i2c-realtek-rtl9301-Fix-missing-reg-cons.patch @@ -0,0 +1,27 @@ +From 5f05fc6e2218db7ecc52c60eb34b707fe69262c2 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Wed, 2 Jul 2025 08:15:31 +0200 +Subject: [PATCH] dt-bindings: i2c: realtek,rtl9301: Fix missing 'reg' + constraint + +Lists should have fixed amount if items, so add missing constraint to +the 'reg' property (only one address space entry). + +Fixes: c5eda0333076 ("dt-bindings: i2c: Add Realtek RTL I2C Controller") +Cc: # v6.13+ +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250702061530.6940-2-krzysztof.kozlowski@linaro.org + +--- a/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml ++++ b/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml +@@ -26,7 +26,8 @@ properties: + - const: realtek,rtl9301-i2c + + reg: +- description: Register offset and size this I2C controller. ++ items: ++ - description: Register offset and size this I2C controller. + + "#address-cells": + const: 1 diff --git a/target/linux/realtek/patches-6.12/005-01-v6.17-i2c-rtl9300-Fix-out-of-bounds-bug-in-rtl9300_i2c_smb.patch b/target/linux/realtek/patches-6.12/005-01-v6.17-i2c-rtl9300-Fix-out-of-bounds-bug-in-rtl9300_i2c_smb.patch new file mode 100644 index 0000000000..2ffb659643 --- /dev/null +++ b/target/linux/realtek/patches-6.12/005-01-v6.17-i2c-rtl9300-Fix-out-of-bounds-bug-in-rtl9300_i2c_smb.patch @@ -0,0 +1,38 @@ +From 57f312b955938fc4663f430cb57a71f2414f601b Mon Sep 17 00:00:00 2001 +From: Alex Guo +Date: Sun, 10 Aug 2025 20:05:13 +0200 +Subject: [PATCH] i2c: rtl9300: Fix out-of-bounds bug in rtl9300_i2c_smbus_xfer + +The data->block[0] variable comes from user. Without proper check, +the variable may be very large to cause an out-of-bounds bug. + +Fix this bug by checking the value of data->block[0] first. + +1. commit 39244cc75482 ("i2c: ismt: Fix an out-of-bounds bug in + ismt_access()") +2. commit 92fbb6d1296f ("i2c: xgene-slimpro: Fix out-of-bounds bug in + xgene_slimpro_i2c_xfer()") + +Fixes: c366be720235 ("i2c: Add driver for the RTL9300 I2C controller") +Signed-off-by: Alex Guo +Cc: # v6.13+ +Reviewed-by: Chris Packham +Tested-by: Chris Packham +Reviewed-by: Wolfram Sang +Signed-off-by: Sven Eckelmann +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250810-i2c-rtl9300-multi-byte-v5-1-cd9dca0db722@narfation.org + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -281,6 +281,10 @@ static int rtl9300_i2c_smbus_xfer(struct + ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); + if (ret) + goto out_unlock; ++ if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) { ++ ret = -EINVAL; ++ goto out_unlock; ++ } + ret = rtl9300_i2c_config_xfer(i2c, chan, addr, data->block[0]); + if (ret) + goto out_unlock; diff --git a/target/linux/realtek/patches-6.12/005-02-v6.17-i2c-rtl9300-Fix-multi-byte-I2C-write.patch b/target/linux/realtek/patches-6.12/005-02-v6.17-i2c-rtl9300-Fix-multi-byte-I2C-write.patch new file mode 100644 index 0000000000..ac6bb52603 --- /dev/null +++ b/target/linux/realtek/patches-6.12/005-02-v6.17-i2c-rtl9300-Fix-multi-byte-I2C-write.patch @@ -0,0 +1,75 @@ +From d67b740b9edfa46310355e2b68050f79ebf05a4c Mon Sep 17 00:00:00 2001 +From: Harshal Gohel +Date: Sun, 10 Aug 2025 20:05:14 +0200 +Subject: [PATCH] i2c: rtl9300: Fix multi-byte I2C write + +The RTL93xx I2C controller has 4 32 bit registers to store the bytes for +the upcoming I2C transmission. The first byte is stored in the +least-significant byte of the first register. And the last byte in the most +significant byte of the last register. A map of the transferred bytes to +their order in the registers is: + +reg 0: 0x04_03_02_01 +reg 1: 0x08_07_06_05 +reg 2: 0x0c_0b_0a_09 +reg 3: 0x10_0f_0e_0d + +The i2c_read() function basically demonstrates how the hardware would pick +up bytes from this register set. But the i2c_write() function was just +pushing bytes one after another to the least significant byte of a register +AFTER shifting the last one to the next more significant byte position. + +If you would then have tried to send a buffer with numbers 1-11 using +i2c_write(), you would have ended up with following register content: + +reg 0: 0x01_02_03_04 +reg 1: 0x05_06_07_08 +reg 2: 0x00_09_0a_0b +reg 3: 0x00_00_00_00 + +On the wire, you would then have seen: + + Sr Addr Wr [A] 04 A 03 A 02 A 01 A 08 A 07 A 06 A 05 A 0b A 0a A 09 A P + +But the correct data transmission was expected to be + + Sr Addr Wr [A] 01 A 02 A 03 A 04 A 05 A 06 A 07 A 08 A 09 A 0a A 0b A P + +Because of this multi-byte ordering problem, only single byte i2c_write() +operations were executed correctly (on the wire). + +By shifting the byte directly to the correct end position in the register, +it is possible to avoid this incorrect byte ordering and fix multi-byte +transmissions. + +The second initialization (to 0) of vals was also be dropped because this +array is initialized to 0 on the stack by using `= {};`. This makes the +fix a lot more readable. + +Fixes: c366be720235 ("i2c: Add driver for the RTL9300 I2C controller") +Signed-off-by: Harshal Gohel +Cc: # v6.13+ +Co-developed-by: Sven Eckelmann +Signed-off-by: Sven Eckelmann +Reviewed-by: Chris Packham +Tested-by: Chris Packham +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250810-i2c-rtl9300-multi-byte-v5-2-cd9dca0db722@narfation.org + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -143,10 +143,10 @@ static int rtl9300_i2c_write(struct rtl9 + return -EIO; + + for (i = 0; i < len; i++) { +- if (i % 4 == 0) +- vals[i/4] = 0; +- vals[i/4] <<= 8; +- vals[i/4] |= buf[i]; ++ unsigned int shift = (i % 4) * 8; ++ unsigned int reg = i / 4; ++ ++ vals[reg] |= buf[i] << shift; + } + + return regmap_bulk_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, diff --git a/target/linux/realtek/patches-6.12/005-03-v6.17-i2c-rtl9300-Increase-timeout-for-transfer-polling.patch b/target/linux/realtek/patches-6.12/005-03-v6.17-i2c-rtl9300-Increase-timeout-for-transfer-polling.patch new file mode 100644 index 0000000000..bfb4f4875d --- /dev/null +++ b/target/linux/realtek/patches-6.12/005-03-v6.17-i2c-rtl9300-Increase-timeout-for-transfer-polling.patch @@ -0,0 +1,37 @@ +From ceee7776c010c5f09d30985c9e5223b363a6172a Mon Sep 17 00:00:00 2001 +From: Sven Eckelmann +Date: Sun, 10 Aug 2025 20:05:15 +0200 +Subject: [PATCH] i2c: rtl9300: Increase timeout for transfer polling + +The timeout for transfers was only set to 2ms. Because of this relatively +low limit, 12-byte read operations to the frontend MCU of a RTL8239 POE PSE +chip cluster was consistently resulting in a timeout. + +The original OpenWrt downstream driver [1] was not using any timeout limit +at all. This is also possible by setting the timeout_us parameter of +regmap_read_poll_timeout() to 0. But since the driver currently implements +the ETIMEDOUT error, it is more sensible to increase the timeout in such a +way that communication with the (quite common) Realtek I2C-connected POE +management solution is possible. + +[1] https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/realtek/files-6.12/drivers/i2c/busses/i2c-rtl9300.c;h=c4d973195ef39dc56d6207e665d279745525fcac#l202 + +Fixes: c366be720235 ("i2c: Add driver for the RTL9300 I2C controller") +Signed-off-by: Sven Eckelmann +Cc: # v6.13+ +Reviewed-by: Chris Packham +Tested-by: Chris Packham +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250810-i2c-rtl9300-multi-byte-v5-3-cd9dca0db722@narfation.org + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -175,7 +175,7 @@ static int rtl9300_i2c_execute_xfer(stru + return ret; + + ret = regmap_read_poll_timeout(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, +- val, !(val & RTL9300_I2C_MST_CTRL1_I2C_TRIG), 100, 2000); ++ val, !(val & RTL9300_I2C_MST_CTRL1_I2C_TRIG), 100, 100000); + if (ret) + return ret; + diff --git a/target/linux/realtek/patches-6.12/005-04-v6.17-i2c-rtl9300-Add-missing-count-byte-for-SMBus-Block-O.patch b/target/linux/realtek/patches-6.12/005-04-v6.17-i2c-rtl9300-Add-missing-count-byte-for-SMBus-Block-O.patch new file mode 100644 index 0000000000..b5314b258a --- /dev/null +++ b/target/linux/realtek/patches-6.12/005-04-v6.17-i2c-rtl9300-Add-missing-count-byte-for-SMBus-Block-O.patch @@ -0,0 +1,53 @@ +From 82b350dd8185ce790e61555c436f90b6501af23c Mon Sep 17 00:00:00 2001 +From: Sven Eckelmann +Date: Sun, 10 Aug 2025 20:05:16 +0200 +Subject: [PATCH] i2c: rtl9300: Add missing count byte for SMBus Block Ops + +The expected on-wire format of an SMBus Block Write is + + S Addr Wr [A] Comm [A] Count [A] Data [A] Data [A] ... [A] Data [A] P + +Everything starting from the Count byte is provided by the I2C subsystem in +the array data->block. But the driver was skipping the Count byte +(data->block[0]) when sending it to the RTL93xx I2C controller. + +Only the actual data could be seen on the wire: + + S Addr Wr [A] Comm [A] Data [A] Data [A] ... [A] Data [A] P + +This wire format is not SMBus Block Write compatible but matches the format +of an I2C Block Write. Simply adding the count byte to the buffer for the +I2C controller is enough to fix the transmission. + +This also affects read because the I2C controller must receive the count +byte + $count * data bytes. + +Fixes: c366be720235 ("i2c: Add driver for the RTL9300 I2C controller") +Signed-off-by: Sven Eckelmann +Cc: # v6.13+ +Reviewed-by: Chris Packham +Tested-by: Chris Packham +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250810-i2c-rtl9300-multi-byte-v5-4-cd9dca0db722@narfation.org + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -285,15 +285,15 @@ static int rtl9300_i2c_smbus_xfer(struct + ret = -EINVAL; + goto out_unlock; + } +- ret = rtl9300_i2c_config_xfer(i2c, chan, addr, data->block[0]); ++ ret = rtl9300_i2c_config_xfer(i2c, chan, addr, data->block[0] + 1); + if (ret) + goto out_unlock; + if (read_write == I2C_SMBUS_WRITE) { +- ret = rtl9300_i2c_write(i2c, &data->block[1], data->block[0]); ++ ret = rtl9300_i2c_write(i2c, &data->block[0], data->block[0] + 1); + if (ret) + goto out_unlock; + } +- len = data->block[0]; ++ len = data->block[0] + 1; + break; + + default: diff --git a/target/linux/realtek/patches-6.12/006-01-v6.17-i2c-rtl9300-fix-channel-number-bound-check.patch b/target/linux/realtek/patches-6.12/006-01-v6.17-i2c-rtl9300-fix-channel-number-bound-check.patch new file mode 100644 index 0000000000..2076a0ad68 --- /dev/null +++ b/target/linux/realtek/patches-6.12/006-01-v6.17-i2c-rtl9300-fix-channel-number-bound-check.patch @@ -0,0 +1,40 @@ +From cd6c956fbc13156bcbcca084b46a8380caebc2a8 Mon Sep 17 00:00:00 2001 +From: Jonas Jelonek +Date: Sun, 31 Aug 2025 10:04:46 +0000 +Subject: [PATCH] i2c: rtl9300: fix channel number bound check + +Fix the current check for number of channels (child nodes in the device +tree). Before, this was: + +if (device_get_child_node_count(dev) >= RTL9300_I2C_MUX_NCHAN) + +RTL9300_I2C_MUX_NCHAN gives the maximum number of channels so checking +with '>=' isn't correct because it doesn't allow the last channel +number. Thus, fix it to: + +if (device_get_child_node_count(dev) > RTL9300_I2C_MUX_NCHAN) + +Issue occured on a TP-Link TL-ST1008F v2.0 device (8 SFP+ ports) and fix +is tested there. + +Fixes: c366be720235 ("i2c: Add driver for the RTL9300 I2C controller") +Cc: stable@vger.kernel.org # v6.13+ +Signed-off-by: Jonas Jelonek +Tested-by: Sven Eckelmann +Reviewed-by: Chris Packham +Tested-by: Chris Packham # On RTL9302C based board +Tested-by: Markus Stockhausen +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250831100457.3114-2-jelonek.jonas@gmail.com + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -353,7 +353,7 @@ static int rtl9300_i2c_probe(struct plat + + platform_set_drvdata(pdev, i2c); + +- if (device_get_child_node_count(dev) >= RTL9300_I2C_MUX_NCHAN) ++ if (device_get_child_node_count(dev) > RTL9300_I2C_MUX_NCHAN) + return dev_err_probe(dev, -EINVAL, "Too many channels\n"); + + device_for_each_child_node(dev, child) { diff --git a/target/linux/realtek/patches-6.12/006-02-v6.17-i2c-rtl9300-ensure-data-length-is-within-supported-r.patch b/target/linux/realtek/patches-6.12/006-02-v6.17-i2c-rtl9300-ensure-data-length-is-within-supported-r.patch new file mode 100644 index 0000000000..382c47a882 --- /dev/null +++ b/target/linux/realtek/patches-6.12/006-02-v6.17-i2c-rtl9300-ensure-data-length-is-within-supported-r.patch @@ -0,0 +1,61 @@ +From 06418cb5a1a542a003fdb4ad8e76ea542d57cfba Mon Sep 17 00:00:00 2001 +From: Jonas Jelonek +Date: Sun, 31 Aug 2025 10:04:47 +0000 +Subject: [PATCH] i2c: rtl9300: ensure data length is within supported range + +Add an explicit check for the xfer length to 'rtl9300_i2c_config_xfer' +to ensure the data length isn't within the supported range. In +particular a data length of 0 is not supported by the hardware and +causes unintended or destructive behaviour. + +This limitation becomes obvious when looking at the register +documentation [1]. 4 bits are reserved for DATA_WIDTH and the value +of these 4 bits is used as N + 1, allowing a data length range of +1 <= len <= 16. + +Affected by this is the SMBus Quick Operation which works with a data +length of 0. Passing 0 as the length causes an underflow of the value +due to: + +(len - 1) & 0xf + +and effectively specifying a transfer length of 16 via the registers. +This causes a 16-byte write operation instead of a Quick Write. For +example, on SFP modules without write-protected EEPROM this soft-bricks +them by overwriting some initial bytes. + +For completeness, also add a quirk for the zero length. + +[1] https://svanheule.net/realtek/longan/register/i2c_mst1_ctrl2 + +Fixes: c366be720235 ("i2c: Add driver for the RTL9300 I2C controller") +Cc: stable@vger.kernel.org # v6.13+ +Signed-off-by: Jonas Jelonek +Tested-by: Sven Eckelmann +Reviewed-by: Chris Packham +Tested-by: Chris Packham # On RTL9302C based board +Tested-by: Markus Stockhausen +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250831100457.3114-3-jelonek.jonas@gmail.com + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -99,6 +99,9 @@ static int rtl9300_i2c_config_xfer(struc + { + u32 val, mask; + ++ if (len < 1 || len > 16) ++ return -EINVAL; ++ + val = chan->bus_freq << RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS; + mask = RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK; + +@@ -323,7 +326,7 @@ static const struct i2c_algorithm rtl930 + }; + + static struct i2c_adapter_quirks rtl9300_i2c_quirks = { +- .flags = I2C_AQ_NO_CLK_STRETCH, ++ .flags = I2C_AQ_NO_CLK_STRETCH | I2C_AQ_NO_ZERO_LEN, + .max_read_len = 16, + .max_write_len = 16, + }; diff --git a/target/linux/realtek/patches-6.12/006-03-v6.17-i2c-rtl9300-remove-broken-SMBus-Quick-operation-supp.patch b/target/linux/realtek/patches-6.12/006-03-v6.17-i2c-rtl9300-remove-broken-SMBus-Quick-operation-supp.patch new file mode 100644 index 0000000000..6de11af54f --- /dev/null +++ b/target/linux/realtek/patches-6.12/006-03-v6.17-i2c-rtl9300-remove-broken-SMBus-Quick-operation-supp.patch @@ -0,0 +1,77 @@ +From ede965fd555ac2536cf651893a998dbfd8e57b86 Mon Sep 17 00:00:00 2001 +From: Jonas Jelonek +Date: Sun, 31 Aug 2025 10:04:48 +0000 +Subject: [PATCH] i2c: rtl9300: remove broken SMBus Quick operation support + +Remove the SMBus Quick operation from this driver because it is not +natively supported by the hardware and is wrongly implemented in the +driver. + +The I2C controllers in Realtek RTL9300 and RTL9310 are SMBus-compliant +but there doesn't seem to be native support for the SMBus Quick +operation. It is not explicitly mentioned in the documentation but +looking at the registers which configure an SMBus transaction, one can +see that the data length cannot be set to 0. This suggests that the +hardware doesn't allow any SMBus message without data bytes (except for +those it does on it's own, see SMBus Block Read). + +The current implementation of SMBus Quick operation passes a length of +0 (which is actually invalid). Before the fix of a bug in a previous +commit, this led to a read operation of 16 bytes from any register (the +one of a former transaction or any other value. + +This caused issues like soft-bricked SFP modules after a simple probe +with i2cdetect which uses Quick by default. Running this with SFP +modules whose EEPROM isn't write-protected, some of the initial bytes +are overwritten because a 16-byte write operation is executed instead of +a Quick Write. (This temporarily soft-bricked one of my DAC cables.) + +Because SMBus Quick operation is obviously not supported on these +controllers (because a length of 0 cannot be set, even when no register +address is set), remove that instead of claiming there is support. There +also shouldn't be any kind of emulated 'Quick' which just does another +kind of operation in the background. Otherwise, specific issues occur +in case of a 'Quick' Write which actually writes unknown data to an +unknown register. + +Fixes: c366be720235 ("i2c: Add driver for the RTL9300 I2C controller") +Cc: stable@vger.kernel.org # v6.13+ +Signed-off-by: Jonas Jelonek +Tested-by: Sven Eckelmann +Reviewed-by: Chris Packham +Tested-by: Chris Packham # On RTL9302C based board +Tested-by: Markus Stockhausen +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250831100457.3114-4-jelonek.jonas@gmail.com + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -225,15 +225,6 @@ static int rtl9300_i2c_smbus_xfer(struct + } + + switch (size) { +- case I2C_SMBUS_QUICK: +- ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 0); +- if (ret) +- goto out_unlock; +- ret = rtl9300_i2c_reg_addr_set(i2c, 0, 0); +- if (ret) +- goto out_unlock; +- break; +- + case I2C_SMBUS_BYTE: + if (read_write == I2C_SMBUS_WRITE) { + ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 0); +@@ -315,9 +306,9 @@ out_unlock: + + static u32 rtl9300_i2c_func(struct i2c_adapter *a) + { +- return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | +- I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | +- I2C_FUNC_SMBUS_BLOCK_DATA; ++ return I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | ++ I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA | ++ I2C_FUNC_SMBUS_I2C_BLOCK; + } + + static const struct i2c_algorithm rtl9300_i2c_algo = { diff --git a/target/linux/realtek/patches-6.12/007-01-v6.17-i2c-rtl9300-Drop-unsupported-I2C_FUNC_SMBUS_I2C_BLOC.patch b/target/linux/realtek/patches-6.12/007-01-v6.17-i2c-rtl9300-Drop-unsupported-I2C_FUNC_SMBUS_I2C_BLOC.patch new file mode 100644 index 0000000000..901c48abdc --- /dev/null +++ b/target/linux/realtek/patches-6.12/007-01-v6.17-i2c-rtl9300-Drop-unsupported-I2C_FUNC_SMBUS_I2C_BLOC.patch @@ -0,0 +1,26 @@ +From 095530512152e6811278de9c30f170f0ac9705eb Mon Sep 17 00:00:00 2001 +From: Sven Eckelmann +Date: Sat, 27 Sep 2025 11:52:16 +0200 +Subject: [PATCH] i2c: rtl9300: Drop unsupported I2C_FUNC_SMBUS_I2C_BLOCK + +While applying the patch for commit ede965fd555a ("i2c: rtl9300: remove +broken SMBus Quick operation support"), a conflict was incorrectly solved +by adding the I2C_FUNC_SMBUS_I2C_BLOCK feature flag. But the code to handle +I2C_SMBUS_I2C_BLOCK_DATA requests will be added by a separate commit. + +Fixes: ede965fd555a ("i2c: rtl9300: remove broken SMBus Quick operation support") +Signed-off-by: Sven Eckelmann +Signed-off-by: Wolfram Sang + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -307,8 +307,7 @@ out_unlock: + static u32 rtl9300_i2c_func(struct i2c_adapter *a) + { + return I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | +- I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA | +- I2C_FUNC_SMBUS_I2C_BLOCK; ++ I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA; + } + + static const struct i2c_algorithm rtl9300_i2c_algo = { diff --git a/target/linux/realtek/patches-6.12/007-02-v6.18-i2c-rtl9300-Implement-I2C-block-read-and-write.patch b/target/linux/realtek/patches-6.12/007-02-v6.18-i2c-rtl9300-Implement-I2C-block-read-and-write.patch new file mode 100644 index 0000000000..d97b76993b --- /dev/null +++ b/target/linux/realtek/patches-6.12/007-02-v6.18-i2c-rtl9300-Implement-I2C-block-read-and-write.patch @@ -0,0 +1,119 @@ +From 415216ae3196e67bdb9515519f219d553bd38d3a Mon Sep 17 00:00:00 2001 +From: Harshal Gohel +Date: Sat, 27 Sep 2025 11:52:17 +0200 +Subject: [PATCH] i2c: rtl9300: Implement I2C block read and write + +It was noticed that the original implementation of SMBus Block Write in the +driver was actually an I2C Block Write. Both differ only in the Count byte +before the actual data: + + S Addr Wr [A] Comm [A] Count [A] Data [A] Data [A] ... [A] Data [A] P + +The I2C Block Write is just skipping this Count byte and starts directly +with the data: + + S Addr Wr [A] Comm [A] Data [A] Data [A] ... [A] Data [A] P + +The I2C controller of RTL93xx doesn't handle this Count byte special and it +is simply another one of (16 possible) data bytes. Adding support for the +I2C Block Write therefore only requires skipping the count byte (0) in +data->block. + +It is similar for reads. The SMBUS Block read is having a Count byte before +the data: + + S Addr Wr [A] Comm [A] + Sr Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P + +And the I2C Block Read is directly starting with the actual data: + + S Addr Wr [A] Comm [A] + Sr Addr Rd [A] [Data] A [Data] A ... A [Data] NA P + +The I2C controller is also not handling this byte in a special way. It +simply provides every byte after the Rd marker + Ack as part of the 16 byte +receive buffer (registers). The content of this buffer just has to be +copied to the right position in the receive data->block. + +Signed-off-by: Harshal Gohel +Co-developed-by: Sven Eckelmann +Signed-off-by: Sven Eckelmann +Reviewed-by: Chris Packham +Tested-by: Chris Packham +Reviewed-by: Jonas Jelonek +Tested-by: Jonas Jelonek + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -186,22 +186,32 @@ static int rtl9300_i2c_execute_xfer(stru + return -EIO; + + if (read_write == I2C_SMBUS_READ) { +- if (size == I2C_SMBUS_BYTE || size == I2C_SMBUS_BYTE_DATA) { ++ switch (size) { ++ case I2C_SMBUS_BYTE: ++ case I2C_SMBUS_BYTE_DATA: + ret = regmap_read(i2c->regmap, + i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val); + if (ret) + return ret; + data->byte = val & 0xff; +- } else if (size == I2C_SMBUS_WORD_DATA) { ++ break; ++ case I2C_SMBUS_WORD_DATA: + ret = regmap_read(i2c->regmap, + i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val); + if (ret) + return ret; + data->word = val & 0xffff; +- } else { ++ break; ++ case I2C_SMBUS_I2C_BLOCK_DATA: ++ ret = rtl9300_i2c_read(i2c, &data->block[1], len); ++ if (ret) ++ return ret; ++ break; ++ default: + ret = rtl9300_i2c_read(i2c, &data->block[0], len); + if (ret) + return ret; ++ break; + } + } + +@@ -290,6 +300,25 @@ static int rtl9300_i2c_smbus_xfer(struct + len = data->block[0] + 1; + break; + ++ case I2C_SMBUS_I2C_BLOCK_DATA: ++ ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); ++ if (ret) ++ goto out_unlock; ++ if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) { ++ ret = -EINVAL; ++ goto out_unlock; ++ } ++ ret = rtl9300_i2c_config_xfer(i2c, chan, addr, data->block[0]); ++ if (ret) ++ goto out_unlock; ++ if (read_write == I2C_SMBUS_WRITE) { ++ ret = rtl9300_i2c_write(i2c, &data->block[1], data->block[0]); ++ if (ret) ++ goto out_unlock; ++ } ++ len = data->block[0]; ++ break; ++ + default: + dev_err(&adap->dev, "Unsupported transaction %d\n", size); + ret = -EOPNOTSUPP; +@@ -307,7 +336,8 @@ out_unlock: + static u32 rtl9300_i2c_func(struct i2c_adapter *a) + { + return I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | +- I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA; ++ I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA | ++ I2C_FUNC_SMBUS_I2C_BLOCK; + } + + static const struct i2c_algorithm rtl9300_i2c_algo = { diff --git a/target/linux/realtek/patches-6.12/008-01-v6.18-i2c-rtl9300-use-regmap-fields-and-API-for-registers.patch b/target/linux/realtek/patches-6.12/008-01-v6.18-i2c-rtl9300-use-regmap-fields-and-API-for-registers.patch new file mode 100644 index 0000000000..30bd16ee69 --- /dev/null +++ b/target/linux/realtek/patches-6.12/008-01-v6.18-i2c-rtl9300-use-regmap-fields-and-API-for-registers.patch @@ -0,0 +1,354 @@ +From 5a6ecb27435ef7a67d7bec4543f0c6303f34e8a6 Mon Sep 17 00:00:00 2001 +From: Jonas Jelonek +Date: Sat, 27 Sep 2025 10:19:23 +0000 +Subject: [PATCH] i2c: rtl9300: use regmap fields and API for registers + +Adapt the RTL9300 I2C controller driver to use more of the regmap +API, especially make use of reg_field and regmap_field instead of macros +to represent registers. Most register operations are performed through +regmap_field_* API then. + +Handle SCL selection using separate chip-specific functions since this +is already known to differ between the Realtek SoC families in such a +way that this cannot be properly handled using just a different +reg_field. + +This makes it easier to add support for newer generations or to handle +differences between specific revisions within a series. Just by +defining a separate driver data structure with the corresponding +register field definitions and linking it to a new compatible. + +Signed-off-by: Jonas Jelonek +Tested-by: Sven Eckelmann +Reviewed-by: Chris Packham +Tested-by: Chris Packham # On RTL9302C based board +Tested-by: Markus Stockhausen +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250927101931.71575-2-jelonek.jonas@gmail.com + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -23,97 +23,117 @@ struct rtl9300_i2c_chan { + u8 sda_pin; + }; + ++enum rtl9300_i2c_reg_scope { ++ REG_SCOPE_GLOBAL, ++ REG_SCOPE_MASTER, ++}; ++ ++struct rtl9300_i2c_reg_field { ++ struct reg_field field; ++ enum rtl9300_i2c_reg_scope scope; ++}; ++ ++enum rtl9300_i2c_reg_fields { ++ F_DATA_WIDTH = 0, ++ F_DEV_ADDR, ++ F_I2C_FAIL, ++ F_I2C_TRIG, ++ F_MEM_ADDR, ++ F_MEM_ADDR_WIDTH, ++ F_RD_MODE, ++ F_RWOP, ++ F_SCL_FREQ, ++ F_SCL_SEL, ++ F_SDA_OUT_SEL, ++ F_SDA_SEL, ++ ++ /* keep last */ ++ F_NUM_FIELDS ++}; ++ ++struct rtl9300_i2c_drv_data { ++ struct rtl9300_i2c_reg_field field_desc[F_NUM_FIELDS]; ++ int (*select_scl)(struct rtl9300_i2c *i2c, u8 scl); ++ u32 data_reg; ++ u8 max_nchan; ++}; ++ + #define RTL9300_I2C_MUX_NCHAN 8 + + struct rtl9300_i2c { + struct regmap *regmap; + struct device *dev; + struct rtl9300_i2c_chan chans[RTL9300_I2C_MUX_NCHAN]; ++ struct regmap_field *fields[F_NUM_FIELDS]; + u32 reg_base; ++ u32 data_reg; + u8 sda_pin; + struct mutex lock; + }; + + #define RTL9300_I2C_MST_CTRL1 0x0 +-#define RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS 8 +-#define RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK GENMASK(31, 8) +-#define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS 4 +-#define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK GENMASK(6, 4) +-#define RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL BIT(3) +-#define RTL9300_I2C_MST_CTRL1_RWOP BIT(2) +-#define RTL9300_I2C_MST_CTRL1_I2C_FAIL BIT(1) +-#define RTL9300_I2C_MST_CTRL1_I2C_TRIG BIT(0) + #define RTL9300_I2C_MST_CTRL2 0x4 +-#define RTL9300_I2C_MST_CTRL2_RD_MODE BIT(15) +-#define RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS 8 +-#define RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK GENMASK(14, 8) +-#define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS 4 +-#define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK GENMASK(7, 4) +-#define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS 2 +-#define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK GENMASK(3, 2) +-#define RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS 0 +-#define RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK GENMASK(1, 0) + #define RTL9300_I2C_MST_DATA_WORD0 0x8 + #define RTL9300_I2C_MST_DATA_WORD1 0xc + #define RTL9300_I2C_MST_DATA_WORD2 0x10 + #define RTL9300_I2C_MST_DATA_WORD3 0x14 +- + #define RTL9300_I2C_MST_GLB_CTRL 0x384 + + static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len) + { +- u32 val, mask; + int ret; + +- val = len << RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS; +- mask = RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK; +- +- ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val); ++ ret = regmap_field_write(i2c->fields[F_MEM_ADDR_WIDTH], len); + if (ret) + return ret; + +- val = reg << RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS; +- mask = RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK; ++ return regmap_field_write(i2c->fields[F_MEM_ADDR], reg); ++} + +- return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val); ++static int rtl9300_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl) ++{ ++ return regmap_field_write(i2c->fields[F_SCL_SEL], 1); + } + + static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, u8 sda_pin) + { ++ struct rtl9300_i2c_drv_data *drv_data; + int ret; +- u32 val, mask; + +- ret = regmap_update_bits(i2c->regmap, RTL9300_I2C_MST_GLB_CTRL, BIT(sda_pin), BIT(sda_pin)); ++ drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev); ++ ++ ret = regmap_field_update_bits(i2c->fields[F_SDA_SEL], BIT(sda_pin), BIT(sda_pin)); + if (ret) + return ret; + +- val = (sda_pin << RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS) | +- RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL; +- mask = RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK | RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL; ++ ret = regmap_field_write(i2c->fields[F_SDA_OUT_SEL], sda_pin); ++ if (ret) ++ return ret; + +- return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val); ++ return drv_data->select_scl(i2c, 0); + } + + static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan, + u16 addr, u16 len) + { +- u32 val, mask; ++ int ret; + + if (len < 1 || len > 16) + return -EINVAL; + +- val = chan->bus_freq << RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS; +- mask = RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK; +- +- val |= addr << RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS; +- mask |= RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK; ++ ret = regmap_field_write(i2c->fields[F_SCL_FREQ], chan->bus_freq); ++ if (ret) ++ return ret; + +- val |= ((len - 1) & 0xf) << RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS; +- mask |= RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK; ++ ret = regmap_field_write(i2c->fields[F_DEV_ADDR], addr); ++ if (ret) ++ return ret; + +- mask |= RTL9300_I2C_MST_CTRL2_RD_MODE; ++ ret = regmap_field_write(i2c->fields[F_DATA_WIDTH], (len - 1) & 0xf); ++ if (ret) ++ return ret; + +- return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val); ++ return regmap_field_write(i2c->fields[F_RD_MODE], 0); + } + + static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len) +@@ -124,8 +144,7 @@ static int rtl9300_i2c_read(struct rtl93 + if (len > 16) + return -EIO; + +- ret = regmap_bulk_read(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, +- vals, ARRAY_SIZE(vals)); ++ ret = regmap_bulk_read(i2c->regmap, i2c->data_reg, vals, ARRAY_SIZE(vals)); + if (ret) + return ret; + +@@ -152,52 +171,49 @@ static int rtl9300_i2c_write(struct rtl9 + vals[reg] |= buf[i] << shift; + } + +- return regmap_bulk_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, +- vals, ARRAY_SIZE(vals)); ++ return regmap_bulk_write(i2c->regmap, i2c->data_reg, vals, ARRAY_SIZE(vals)); + } + + static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data) + { +- return regmap_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, data); ++ return regmap_write(i2c->regmap, i2c->data_reg, data); + } + + static int rtl9300_i2c_execute_xfer(struct rtl9300_i2c *i2c, char read_write, + int size, union i2c_smbus_data *data, int len) + { +- u32 val, mask; ++ u32 val; + int ret; + +- val = read_write == I2C_SMBUS_WRITE ? RTL9300_I2C_MST_CTRL1_RWOP : 0; +- mask = RTL9300_I2C_MST_CTRL1_RWOP; +- +- val |= RTL9300_I2C_MST_CTRL1_I2C_TRIG; +- mask |= RTL9300_I2C_MST_CTRL1_I2C_TRIG; ++ ret = regmap_field_write(i2c->fields[F_RWOP], read_write == I2C_SMBUS_WRITE); ++ if (ret) ++ return ret; + +- ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val); ++ ret = regmap_field_write(i2c->fields[F_I2C_TRIG], 1); + if (ret) + return ret; + +- ret = regmap_read_poll_timeout(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, +- val, !(val & RTL9300_I2C_MST_CTRL1_I2C_TRIG), 100, 100000); ++ ret = regmap_field_read_poll_timeout(i2c->fields[F_I2C_TRIG], val, !val, 100, 100000); + if (ret) + return ret; + +- if (val & RTL9300_I2C_MST_CTRL1_I2C_FAIL) ++ ret = regmap_field_read(i2c->fields[F_I2C_FAIL], &val); ++ if (ret) ++ return ret; ++ if (val) + return -EIO; + + if (read_write == I2C_SMBUS_READ) { + switch (size) { + case I2C_SMBUS_BYTE: + case I2C_SMBUS_BYTE_DATA: +- ret = regmap_read(i2c->regmap, +- i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val); ++ ret = regmap_read(i2c->regmap, i2c->data_reg, &val); + if (ret) + return ret; + data->byte = val & 0xff; + break; + case I2C_SMBUS_WORD_DATA: +- ret = regmap_read(i2c->regmap, +- i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val); ++ ret = regmap_read(i2c->regmap, i2c->data_reg, &val); + if (ret) + return ret; + data->word = val & 0xffff; +@@ -355,9 +371,11 @@ static int rtl9300_i2c_probe(struct plat + { + struct device *dev = &pdev->dev; + struct rtl9300_i2c *i2c; ++ struct fwnode_handle *child; ++ struct rtl9300_i2c_drv_data *drv_data; ++ struct reg_field fields[F_NUM_FIELDS]; + u32 clock_freq, sda_pin; + int ret, i = 0; +- struct fwnode_handle *child; + + i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); + if (!i2c) +@@ -376,9 +394,22 @@ static int rtl9300_i2c_probe(struct plat + + platform_set_drvdata(pdev, i2c); + +- if (device_get_child_node_count(dev) > RTL9300_I2C_MUX_NCHAN) ++ drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev); ++ if (device_get_child_node_count(dev) > drv_data->max_nchan) + return dev_err_probe(dev, -EINVAL, "Too many channels\n"); + ++ i2c->data_reg = i2c->reg_base + drv_data->data_reg; ++ for (i = 0; i < F_NUM_FIELDS; i++) { ++ fields[i] = drv_data->field_desc[i].field; ++ if (drv_data->field_desc[i].scope == REG_SCOPE_MASTER) ++ fields[i].reg += i2c->reg_base; ++ } ++ ret = devm_regmap_field_bulk_alloc(dev, i2c->regmap, i2c->fields, ++ fields, F_NUM_FIELDS); ++ if (ret) ++ return ret; ++ ++ i = 0; + device_for_each_child_node(dev, child) { + struct rtl9300_i2c_chan *chan = &i2c->chans[i]; + struct i2c_adapter *adap = &chan->adap; +@@ -395,7 +426,6 @@ static int rtl9300_i2c_probe(struct plat + case I2C_MAX_STANDARD_MODE_FREQ: + chan->bus_freq = RTL9300_I2C_STD_FREQ; + break; +- + case I2C_MAX_FAST_MODE_FREQ: + chan->bus_freq = RTL9300_I2C_FAST_FREQ; + break; +@@ -427,11 +457,37 @@ static int rtl9300_i2c_probe(struct plat + return 0; + } + ++#define GLB_REG_FIELD(reg, msb, lsb) \ ++ { .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_GLOBAL } ++#define MST_REG_FIELD(reg, msb, lsb) \ ++ { .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_MASTER } ++ ++static const struct rtl9300_i2c_drv_data rtl9300_i2c_drv_data = { ++ .field_desc = { ++ [F_MEM_ADDR] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 8, 31), ++ [F_SDA_OUT_SEL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 4, 6), ++ [F_SCL_SEL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 3, 3), ++ [F_RWOP] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 2, 2), ++ [F_I2C_FAIL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 1, 1), ++ [F_I2C_TRIG] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 0, 0), ++ [F_RD_MODE] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 15, 15), ++ [F_DEV_ADDR] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 8, 14), ++ [F_DATA_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 4, 7), ++ [F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 2, 3), ++ [F_SCL_FREQ] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 0, 1), ++ [F_SDA_SEL] = GLB_REG_FIELD(RTL9300_I2C_MST_GLB_CTRL, 0, 7), ++ }, ++ .select_scl = rtl9300_i2c_select_scl, ++ .data_reg = RTL9300_I2C_MST_DATA_WORD0, ++ .max_nchan = RTL9300_I2C_MUX_NCHAN, ++}; ++ ++ + static const struct of_device_id i2c_rtl9300_dt_ids[] = { +- { .compatible = "realtek,rtl9301-i2c" }, +- { .compatible = "realtek,rtl9302b-i2c" }, +- { .compatible = "realtek,rtl9302c-i2c" }, +- { .compatible = "realtek,rtl9303-i2c" }, ++ { .compatible = "realtek,rtl9301-i2c", .data = (void *) &rtl9300_i2c_drv_data }, ++ { .compatible = "realtek,rtl9302b-i2c", .data = (void *) &rtl9300_i2c_drv_data }, ++ { .compatible = "realtek,rtl9302c-i2c", .data = (void *) &rtl9300_i2c_drv_data }, ++ { .compatible = "realtek,rtl9303-i2c", .data = (void *) &rtl9300_i2c_drv_data }, + {} + }; + MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids); diff --git a/target/linux/realtek/patches-6.12/008-02-v6.18-dt-bindings-i2c-realtek-rtl9301-i2c-fix-wording-and-.patch b/target/linux/realtek/patches-6.12/008-02-v6.18-dt-bindings-i2c-realtek-rtl9301-i2c-fix-wording-and-.patch new file mode 100644 index 0000000000..1eefe48af0 --- /dev/null +++ b/target/linux/realtek/patches-6.12/008-02-v6.18-dt-bindings-i2c-realtek-rtl9301-i2c-fix-wording-and-.patch @@ -0,0 +1,51 @@ +From 80f3e37d5e734bbfe891592bb669ceb5e8b314dc Mon Sep 17 00:00:00 2001 +From: Jonas Jelonek +Date: Sat, 27 Sep 2025 10:19:24 +0000 +Subject: [PATCH] dt-bindings: i2c: realtek,rtl9301-i2c: fix wording and typos + +Fix wording of binding description to use plural because there is not +only a single RTL9300 SoC. RTL9300 describes a whole family of Realtek +SoCs. + +Add missing word 'of' in description of reg property. + +Change 'SDA pin' to 'SDA line number' because the property must contain +the SDA (channel) number ranging from 0-7 instead of a real pin number. + +Signed-off-by: Jonas Jelonek +Reviewed-by: Rob Herring (Arm) +Reviewed-by: Chris Packham +Tested-by: Chris Packham # On RTL9302C based board +Tested-by: Markus Stockhausen +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250927101931.71575-3-jelonek.jonas@gmail.com + +--- a/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml ++++ b/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml +@@ -10,7 +10,7 @@ maintainers: + - Chris Packham + + description: +- The RTL9300 SoC has two I2C controllers. Each of these has an SCL line (which ++ RTL9300 SoCs have two I2C controllers. Each of these has an SCL line (which + if not-used for SCL can be a GPIO). There are 8 common SDA lines that can be + assigned to either I2C controller. + +@@ -27,7 +27,7 @@ properties: + + reg: + items: +- - description: Register offset and size this I2C controller. ++ - description: Register offset and size of this I2C controller. + + "#address-cells": + const: 1 +@@ -42,7 +42,7 @@ patternProperties: + + properties: + reg: +- description: The SDA pin associated with the I2C bus. ++ description: The SDA line number associated with the I2C bus. + maxItems: 1 + + required: diff --git a/target/linux/realtek/patches-6.12/008-03-v6.18-i2c-rtl9300-rename-internal-sda_pin-to-sda_num.patch b/target/linux/realtek/patches-6.12/008-03-v6.18-i2c-rtl9300-rename-internal-sda_pin-to-sda_num.patch new file mode 100644 index 0000000000..37f09766ff --- /dev/null +++ b/target/linux/realtek/patches-6.12/008-03-v6.18-i2c-rtl9300-rename-internal-sda_pin-to-sda_num.patch @@ -0,0 +1,118 @@ +From 8ff3819d7edcd56e4c533b9391a156cd607048fa Mon Sep 17 00:00:00 2001 +From: Jonas Jelonek +Date: Sat, 27 Sep 2025 10:19:25 +0000 +Subject: [PATCH] i2c: rtl9300: rename internal sda_pin to sda_num + +Rename the internally used 'sda_pin' to 'sda_num' to make it clear that +this is NOT the actual pin number of the GPIO pin but rather the logical +SDA channel number. Although the alternate function SDA_Y is sometimes +given with the GPIO number, this is not always the case. Thus, avoid any +confusion or misconfiguration by giving the variable the correct name. + +This follows the description change in the devicetree bindings. + +Signed-off-by: Jonas Jelonek +Tested-by: Sven Eckelmann +Reviewed-by: Chris Packham +Tested-by: Chris Packham # On RTL9302C based board +Tested-by: Markus Stockhausen +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250927101931.71575-4-jelonek.jonas@gmail.com + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -20,7 +20,7 @@ struct rtl9300_i2c_chan { + struct i2c_adapter adap; + struct rtl9300_i2c *i2c; + enum rtl9300_bus_freq bus_freq; +- u8 sda_pin; ++ u8 sda_num; + }; + + enum rtl9300_i2c_reg_scope { +@@ -67,7 +67,7 @@ struct rtl9300_i2c { + struct regmap_field *fields[F_NUM_FIELDS]; + u32 reg_base; + u32 data_reg; +- u8 sda_pin; ++ u8 sda_num; + struct mutex lock; + }; + +@@ -102,11 +102,11 @@ static int rtl9300_i2c_config_io(struct + + drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev); + +- ret = regmap_field_update_bits(i2c->fields[F_SDA_SEL], BIT(sda_pin), BIT(sda_pin)); ++ ret = regmap_field_update_bits(i2c->fields[F_SDA_SEL], BIT(sda_num), BIT(sda_num)); + if (ret) + return ret; + +- ret = regmap_field_write(i2c->fields[F_SDA_OUT_SEL], sda_pin); ++ ret = regmap_field_write(i2c->fields[F_SDA_OUT_SEL], sda_num); + if (ret) + return ret; + +@@ -243,11 +243,11 @@ static int rtl9300_i2c_smbus_xfer(struct + int len = 0, ret; + + mutex_lock(&i2c->lock); +- if (chan->sda_pin != i2c->sda_pin) { ++ if (chan->sda_num != i2c->sda_num) { + ret = rtl9300_i2c_config_io(i2c, chan->sda_pin); + if (ret) + goto out_unlock; +- i2c->sda_pin = chan->sda_pin; ++ i2c->sda_num = chan->sda_num; + } + + switch (size) { +@@ -374,7 +374,7 @@ static int rtl9300_i2c_probe(struct plat + struct fwnode_handle *child; + struct rtl9300_i2c_drv_data *drv_data; + struct reg_field fields[F_NUM_FIELDS]; +- u32 clock_freq, sda_pin; ++ u32 clock_freq, sda_num; + int ret, i = 0; + + i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); +@@ -414,7 +414,7 @@ static int rtl9300_i2c_probe(struct plat + struct rtl9300_i2c_chan *chan = &i2c->chans[i]; + struct i2c_adapter *adap = &chan->adap; + +- ret = fwnode_property_read_u32(child, "reg", &sda_pin); ++ ret = fwnode_property_read_u32(child, "reg", &sda_num); + if (ret) + return ret; + +@@ -431,11 +431,11 @@ static int rtl9300_i2c_probe(struct plat + break; + default: + dev_warn(i2c->dev, "SDA%d clock-frequency %d not supported using default\n", +- sda_pin, clock_freq); ++ sda_num, clock_freq); + break; + } + +- chan->sda_pin = sda_pin; ++ chan->sda_num = sda_num; + chan->i2c = i2c; + adap = &i2c->chans[i].adap; + adap->owner = THIS_MODULE; +@@ -445,14 +445,14 @@ static int rtl9300_i2c_probe(struct plat + adap->dev.parent = dev; + i2c_set_adapdata(adap, chan); + adap->dev.of_node = to_of_node(child); +- snprintf(adap->name, sizeof(adap->name), "%s SDA%d\n", dev_name(dev), sda_pin); ++ snprintf(adap->name, sizeof(adap->name), "%s SDA%d\n", dev_name(dev), sda_num); + i++; + + ret = devm_i2c_add_adapter(dev, adap); + if (ret) + return ret; + } +- i2c->sda_pin = 0xff; ++ i2c->sda_num = 0xff; + + return 0; + } diff --git a/target/linux/realtek/patches-6.12/008-04-v6.18-i2c-rtl9300-move-setting-SCL-frequency-to-config_io.patch b/target/linux/realtek/patches-6.12/008-04-v6.18-i2c-rtl9300-move-setting-SCL-frequency-to-config_io.patch new file mode 100644 index 0000000000..8620ce9fe0 --- /dev/null +++ b/target/linux/realtek/patches-6.12/008-04-v6.18-i2c-rtl9300-move-setting-SCL-frequency-to-config_io.patch @@ -0,0 +1,67 @@ +From 6b0549abc8582a81425f89a436def8e28d8d7dce Mon Sep 17 00:00:00 2001 +From: Jonas Jelonek +Date: Sat, 27 Sep 2025 10:19:26 +0000 +Subject: [PATCH] i2c: rtl9300: move setting SCL frequency to config_io + +Move the register operation to set the SCL frequency to the +rtl9300_i2c_config_io function instead of the rtl9300_i2c_config_xfer +function. This rather belongs there next to selecting the current SDA +output line. + +Signed-off-by: Jonas Jelonek +Tested-by: Sven Eckelmann +Reviewed-by: Chris Packham +Tested-by: Chris Packham # On RTL9302C based board +Tested-by: Markus Stockhausen +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250927101931.71575-5-jelonek.jonas@gmail.com + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -95,18 +95,23 @@ static int rtl9300_i2c_select_scl(struct + return regmap_field_write(i2c->fields[F_SCL_SEL], 1); + } + +-static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, u8 sda_pin) ++static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan) + { + struct rtl9300_i2c_drv_data *drv_data; + int ret; + + drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev); + +- ret = regmap_field_update_bits(i2c->fields[F_SDA_SEL], BIT(sda_num), BIT(sda_num)); ++ ret = regmap_field_update_bits(i2c->fields[F_SDA_SEL], BIT(chan->sda_num), ++ BIT(chan->sda_num)); + if (ret) + return ret; + +- ret = regmap_field_write(i2c->fields[F_SDA_OUT_SEL], sda_num); ++ ret = regmap_field_write(i2c->fields[F_SDA_OUT_SEL], chan->sda_num); ++ if (ret) ++ return ret; ++ ++ ret = regmap_field_write(i2c->fields[F_SCL_FREQ], chan->bus_freq); + if (ret) + return ret; + +@@ -121,10 +126,6 @@ static int rtl9300_i2c_config_xfer(struc + if (len < 1 || len > 16) + return -EINVAL; + +- ret = regmap_field_write(i2c->fields[F_SCL_FREQ], chan->bus_freq); +- if (ret) +- return ret; +- + ret = regmap_field_write(i2c->fields[F_DEV_ADDR], addr); + if (ret) + return ret; +@@ -244,7 +245,7 @@ static int rtl9300_i2c_smbus_xfer(struct + + mutex_lock(&i2c->lock); + if (chan->sda_num != i2c->sda_num) { +- ret = rtl9300_i2c_config_io(i2c, chan->sda_pin); ++ ret = rtl9300_i2c_config_io(i2c, chan); + if (ret) + goto out_unlock; + i2c->sda_num = chan->sda_num; diff --git a/target/linux/realtek/patches-6.12/008-05-v6.18-i2c-rtl9300-do-not-set-read-mode-on-every-transfer.patch b/target/linux/realtek/patches-6.12/008-05-v6.18-i2c-rtl9300-do-not-set-read-mode-on-every-transfer.patch new file mode 100644 index 0000000000..5dc6878e5b --- /dev/null +++ b/target/linux/realtek/patches-6.12/008-05-v6.18-i2c-rtl9300-do-not-set-read-mode-on-every-transfer.patch @@ -0,0 +1,49 @@ +From 0cb24186d0ebd7dd12c070fed9d782bf7c6dfb1e Mon Sep 17 00:00:00 2001 +From: Jonas Jelonek +Date: Sat, 27 Sep 2025 10:19:27 +0000 +Subject: [PATCH] i2c: rtl9300: do not set read mode on every transfer + +Move the operation to set the read mode from config_xfer to probe. + +The I2C controller of RTL9300 and RTL9310 support a legacy message mode +for READs with 'Read Address Data' instead of the standard format 'Write +Address ; Read Data'. There is no way to pass that via smbus_xfer, thus +there is no point in supported this in the driver and moreover no point +in setting this on every transaction. Setting this once in the probe +call is sufficient. + +Signed-off-by: Jonas Jelonek +Tested-by: Sven Eckelmann +Reviewed-by: Chris Packham +Tested-by: Chris Packham # On RTL9302C based board +Tested-by: Markus Stockhausen +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250927101931.71575-6-jelonek.jonas@gmail.com + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -130,11 +130,7 @@ static int rtl9300_i2c_config_xfer(struc + if (ret) + return ret; + +- ret = regmap_field_write(i2c->fields[F_DATA_WIDTH], (len - 1) & 0xf); +- if (ret) +- return ret; +- +- return regmap_field_write(i2c->fields[F_RD_MODE], 0); ++ return regmap_field_write(i2c->fields[F_DATA_WIDTH], (len - 1) & 0xf); + } + + static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len) +@@ -455,6 +451,11 @@ static int rtl9300_i2c_probe(struct plat + } + i2c->sda_num = 0xff; + ++ /* only use standard read format */ ++ ret = regmap_field_write(i2c->fields[F_RD_MODE], 0); ++ if (ret) ++ return ret; ++ + return 0; + } + diff --git a/target/linux/realtek/patches-6.12/008-06-v6.18-i2c-rtl9300-separate-xfer-configuration-and-executio.patch b/target/linux/realtek/patches-6.12/008-06-v6.18-i2c-rtl9300-separate-xfer-configuration-and-executio.patch new file mode 100644 index 0000000000..2d329fdb4c --- /dev/null +++ b/target/linux/realtek/patches-6.12/008-06-v6.18-i2c-rtl9300-separate-xfer-configuration-and-executio.patch @@ -0,0 +1,382 @@ +From 447dd46f95014eb4ea94f6164963bf23ce05b927 Mon Sep 17 00:00:00 2001 +From: Jonas Jelonek +Date: Sat, 27 Sep 2025 10:19:28 +0000 +Subject: [PATCH] i2c: rtl9300: separate xfer configuration and execution + +So far, the rtl9300_i2c_smbus_xfer code is quite a mess with function +calls distributed over the whole function setting different values in +different cases. Calls to rtl9300_i2c_config_xfer and +rtl9300_i2c_reg_addr_set are used in every case-block with varying +values whose meaning is not instantly obvious. In some cases, there are +additional calls within these case-blocks doing more things. + +This is in general a bad design and especially really bad for +readability and maintainability because it distributes changes or +issues to multiple locations due to the same function being called with +different hardcoded values in different places. + +To have a good structure, setting different parameters based on the +desired operation should not be interleaved with applying these +parameters to the hardware registers. Or in different words, the +parameter site should be mixed with the call site. + +Thus, separate configuration and execution of an SMBus xfer within +rtl9300_i2c_smbus_xfer to improve readability and maintainability. Add a +new 'struct rtl9300_i2c_xfer' to carry the required parameters for an +xfer which are configured based on the input parameters within a single +switch-case block, without having any function calls within this block. + +The function calls to actually apply these values to the hardware +registers then appear below in a single place and just operate on the +passed instance of 'struct rtl9300_i2c_xfer'. These are +'rtl9300_i2c_prepare_xfer' which combines applying all parameters of the +xfer to the corresponding register, and 'rtl9300_i2c_do_xfer' which +actually executes the xfer and does post-processing if needed. + +Signed-off-by: Jonas Jelonek +Tested-by: Sven Eckelmann +Reviewed-by: Chris Packham +Tested-by: Chris Packham # On RTL9302C based board +Tested-by: Markus Stockhausen +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250927101931.71575-7-jelonek.jonas@gmail.com + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + + enum rtl9300_bus_freq { + RTL9300_I2C_STD_FREQ, +@@ -71,6 +72,22 @@ struct rtl9300_i2c { + struct mutex lock; + }; + ++enum rtl9300_i2c_xfer_type { ++ RTL9300_I2C_XFER_BYTE, ++ RTL9300_I2C_XFER_WORD, ++ RTL9300_I2C_XFER_BLOCK, ++}; ++ ++struct rtl9300_i2c_xfer { ++ enum rtl9300_i2c_xfer_type type; ++ u16 dev_addr; ++ u8 reg_addr; ++ u8 reg_addr_len; ++ u8 *data; ++ u8 data_len; ++ bool write; ++}; ++ + #define RTL9300_I2C_MST_CTRL1 0x0 + #define RTL9300_I2C_MST_CTRL2 0x4 + #define RTL9300_I2C_MST_DATA_WORD0 0x8 +@@ -95,45 +112,37 @@ static int rtl9300_i2c_select_scl(struct + return regmap_field_write(i2c->fields[F_SCL_SEL], 1); + } + +-static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan) ++static int rtl9300_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan) + { + struct rtl9300_i2c_drv_data *drv_data; + int ret; + +- drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev); ++ if (i2c->sda_num == chan->sda_num) ++ return 0; + +- ret = regmap_field_update_bits(i2c->fields[F_SDA_SEL], BIT(chan->sda_num), +- BIT(chan->sda_num)); ++ ret = regmap_field_write(i2c->fields[F_SCL_FREQ], chan->bus_freq); + if (ret) + return ret; + +- ret = regmap_field_write(i2c->fields[F_SDA_OUT_SEL], chan->sda_num); ++ drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev); ++ ret = drv_data->select_scl(i2c, 0); + if (ret) + return ret; + +- ret = regmap_field_write(i2c->fields[F_SCL_FREQ], chan->bus_freq); ++ ret = regmap_field_update_bits(i2c->fields[F_SDA_SEL], BIT(chan->sda_num), ++ BIT(chan->sda_num)); + if (ret) + return ret; + +- return drv_data->select_scl(i2c, 0); +-} +- +-static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan, +- u16 addr, u16 len) +-{ +- int ret; +- +- if (len < 1 || len > 16) +- return -EINVAL; +- +- ret = regmap_field_write(i2c->fields[F_DEV_ADDR], addr); ++ ret = regmap_field_write(i2c->fields[F_SDA_OUT_SEL], chan->sda_num); + if (ret) + return ret; + +- return regmap_field_write(i2c->fields[F_DATA_WIDTH], (len - 1) & 0xf); ++ i2c->sda_num = chan->sda_num; ++ return 0; + } + +-static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len) ++static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, u8 len) + { + u32 vals[4] = {}; + int i, ret; +@@ -153,7 +162,7 @@ static int rtl9300_i2c_read(struct rtl93 + return 0; + } + +-static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len) ++static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, u8 len) + { + u32 vals[4] = {}; + int i; +@@ -176,16 +185,51 @@ static int rtl9300_i2c_writel(struct rtl + return regmap_write(i2c->regmap, i2c->data_reg, data); + } + +-static int rtl9300_i2c_execute_xfer(struct rtl9300_i2c *i2c, char read_write, +- int size, union i2c_smbus_data *data, int len) ++static int rtl9300_i2c_prepare_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_xfer *xfer) + { +- u32 val; + int ret; + +- ret = regmap_field_write(i2c->fields[F_RWOP], read_write == I2C_SMBUS_WRITE); ++ if (xfer->data_len < 1 || xfer->data_len > 16) ++ return -EINVAL; ++ ++ ret = regmap_field_write(i2c->fields[F_DEV_ADDR], xfer->dev_addr); + if (ret) + return ret; + ++ ret = rtl9300_i2c_reg_addr_set(i2c, xfer->reg_addr, xfer->reg_addr_len); ++ if (ret) ++ return ret; ++ ++ ret = regmap_field_write(i2c->fields[F_RWOP], xfer->write); ++ if (ret) ++ return ret; ++ ++ ret = regmap_field_write(i2c->fields[F_DATA_WIDTH], (xfer->data_len - 1) & 0xf); ++ if (ret) ++ return ret; ++ ++ if (xfer->write) { ++ switch (xfer->type) { ++ case RTL9300_I2C_XFER_BYTE: ++ ret = rtl9300_i2c_writel(i2c, *xfer->data); ++ break; ++ case RTL9300_I2C_XFER_WORD: ++ ret = rtl9300_i2c_writel(i2c, get_unaligned((const u16 *)xfer->data)); ++ break; ++ default: ++ ret = rtl9300_i2c_write(i2c, xfer->data, xfer->data_len); ++ break; ++ } ++ } ++ ++ return ret; ++} ++ ++static int rtl9300_i2c_do_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_xfer *xfer) ++{ ++ u32 val; ++ int ret; ++ + ret = regmap_field_write(i2c->fields[F_I2C_TRIG], 1); + if (ret) + return ret; +@@ -200,28 +244,24 @@ static int rtl9300_i2c_execute_xfer(stru + if (val) + return -EIO; + +- if (read_write == I2C_SMBUS_READ) { +- switch (size) { +- case I2C_SMBUS_BYTE: +- case I2C_SMBUS_BYTE_DATA: ++ if (!xfer->write) { ++ switch (xfer->type) { ++ case RTL9300_I2C_XFER_BYTE: + ret = regmap_read(i2c->regmap, i2c->data_reg, &val); + if (ret) + return ret; +- data->byte = val & 0xff; ++ ++ *xfer->data = val & 0xff; + break; +- case I2C_SMBUS_WORD_DATA: ++ case RTL9300_I2C_XFER_WORD: + ret = regmap_read(i2c->regmap, i2c->data_reg, &val); + if (ret) + return ret; +- data->word = val & 0xffff; +- break; +- case I2C_SMBUS_I2C_BLOCK_DATA: +- ret = rtl9300_i2c_read(i2c, &data->block[1], len); +- if (ret) +- return ret; ++ ++ put_unaligned(val & 0xffff, (u16*)xfer->data); + break; + default: +- ret = rtl9300_i2c_read(i2c, &data->block[0], len); ++ ret = rtl9300_i2c_read(i2c, xfer->data, xfer->data_len); + if (ret) + return ret; + break; +@@ -237,108 +277,62 @@ static int rtl9300_i2c_smbus_xfer(struct + { + struct rtl9300_i2c_chan *chan = i2c_get_adapdata(adap); + struct rtl9300_i2c *i2c = chan->i2c; +- int len = 0, ret; ++ struct rtl9300_i2c_xfer xfer = {0}; ++ int ret; ++ ++ if (addr > 0x7f) ++ return -EINVAL; + + mutex_lock(&i2c->lock); +- if (chan->sda_num != i2c->sda_num) { +- ret = rtl9300_i2c_config_io(i2c, chan); +- if (ret) +- goto out_unlock; +- i2c->sda_num = chan->sda_num; +- } ++ ++ ret = rtl9300_i2c_config_chan(i2c, chan); ++ if (ret) ++ goto out_unlock; ++ ++ xfer.dev_addr = addr & 0x7f; ++ xfer.write = (read_write == I2C_SMBUS_WRITE); ++ xfer.reg_addr = command; ++ xfer.reg_addr_len = 1; + + switch (size) { + case I2C_SMBUS_BYTE: +- if (read_write == I2C_SMBUS_WRITE) { +- ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 0); +- if (ret) +- goto out_unlock; +- ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); +- if (ret) +- goto out_unlock; +- } else { +- ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 1); +- if (ret) +- goto out_unlock; +- ret = rtl9300_i2c_reg_addr_set(i2c, 0, 0); +- if (ret) +- goto out_unlock; +- } ++ xfer.data = (read_write == I2C_SMBUS_READ) ? &data->byte : &command; ++ xfer.data_len = 1; ++ xfer.reg_addr = 0; ++ xfer.reg_addr_len = 0; ++ xfer.type = RTL9300_I2C_XFER_BYTE; + break; +- + case I2C_SMBUS_BYTE_DATA: +- ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); +- if (ret) +- goto out_unlock; +- ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 1); +- if (ret) +- goto out_unlock; +- if (read_write == I2C_SMBUS_WRITE) { +- ret = rtl9300_i2c_writel(i2c, data->byte); +- if (ret) +- goto out_unlock; +- } ++ xfer.data = &data->byte; ++ xfer.data_len = 1; ++ xfer.type = RTL9300_I2C_XFER_BYTE; + break; +- + case I2C_SMBUS_WORD_DATA: +- ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); +- if (ret) +- goto out_unlock; +- ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 2); +- if (ret) +- goto out_unlock; +- if (read_write == I2C_SMBUS_WRITE) { +- ret = rtl9300_i2c_writel(i2c, data->word); +- if (ret) +- goto out_unlock; +- } ++ xfer.data = (u8 *)&data->word; ++ xfer.data_len = 2; ++ xfer.type = RTL9300_I2C_XFER_WORD; + break; +- + case I2C_SMBUS_BLOCK_DATA: +- ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); +- if (ret) +- goto out_unlock; +- if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) { +- ret = -EINVAL; +- goto out_unlock; +- } +- ret = rtl9300_i2c_config_xfer(i2c, chan, addr, data->block[0] + 1); +- if (ret) +- goto out_unlock; +- if (read_write == I2C_SMBUS_WRITE) { +- ret = rtl9300_i2c_write(i2c, &data->block[0], data->block[0] + 1); +- if (ret) +- goto out_unlock; +- } +- len = data->block[0] + 1; ++ xfer.data = &data->block[0]; ++ xfer.data_len = data->block[0] + 1; ++ xfer.type = RTL9300_I2C_XFER_BLOCK; + break; +- + case I2C_SMBUS_I2C_BLOCK_DATA: +- ret = rtl9300_i2c_reg_addr_set(i2c, command, 1); +- if (ret) +- goto out_unlock; +- if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) { +- ret = -EINVAL; +- goto out_unlock; +- } +- ret = rtl9300_i2c_config_xfer(i2c, chan, addr, data->block[0]); +- if (ret) +- goto out_unlock; +- if (read_write == I2C_SMBUS_WRITE) { +- ret = rtl9300_i2c_write(i2c, &data->block[1], data->block[0]); +- if (ret) +- goto out_unlock; +- } +- len = data->block[0]; ++ xfer.data = &data->block[1]; ++ xfer.data_len = data->block[0]; ++ xfer.type = RTL9300_I2C_XFER_BLOCK; + break; +- + default: + dev_err(&adap->dev, "Unsupported transaction %d\n", size); + ret = -EOPNOTSUPP; + goto out_unlock; + } + +- ret = rtl9300_i2c_execute_xfer(i2c, read_write, size, data, len); ++ ret = rtl9300_i2c_prepare_xfer(i2c, &xfer); ++ if (ret) ++ goto out_unlock; ++ ++ ret = rtl9300_i2c_do_xfer(i2c, &xfer); + + out_unlock: + mutex_unlock(&i2c->lock); diff --git a/target/linux/realtek/patches-6.12/008-07-v6.18-i2c-rtl9300-use-scoped-guard-instead-of-explicit-loc.patch b/target/linux/realtek/patches-6.12/008-07-v6.18-i2c-rtl9300-use-scoped-guard-instead-of-explicit-loc.patch new file mode 100644 index 0000000000..58552ca210 --- /dev/null +++ b/target/linux/realtek/patches-6.12/008-07-v6.18-i2c-rtl9300-use-scoped-guard-instead-of-explicit-loc.patch @@ -0,0 +1,68 @@ +From bcd5f0da57e6c47a884dcad94ad6b0e32cce8705 Mon Sep 17 00:00:00 2001 +From: Jonas Jelonek +Date: Sat, 27 Sep 2025 10:19:29 +0000 +Subject: [PATCH] i2c: rtl9300: use scoped guard instead of explicit + lock/unlock + +Use the scoped guard infrastructure which unlocks a mutex automatically +when the guard goes out of scope, instead of explicit lock and unlock. +This simplifies the code and control flow in rtl9300_i2c_smbus_xfer and +removes the need of using goto in error cases to unlock before +returning. + +Signed-off-by: Jonas Jelonek +Reviewed-by: Chris Packham +Tested-by: Chris Packham # On RTL9302C based board +Tested-by: Markus Stockhausen +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250927101931.71575-8-jelonek.jonas@gmail.com + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -72,6 +72,8 @@ struct rtl9300_i2c { + struct mutex lock; + }; + ++DEFINE_GUARD(rtl9300_i2c, struct rtl9300_i2c *, mutex_lock(&_T->lock), mutex_unlock(&_T->lock)) ++ + enum rtl9300_i2c_xfer_type { + RTL9300_I2C_XFER_BYTE, + RTL9300_I2C_XFER_WORD, +@@ -283,11 +285,11 @@ static int rtl9300_i2c_smbus_xfer(struct + if (addr > 0x7f) + return -EINVAL; + +- mutex_lock(&i2c->lock); ++ guard(rtl9300_i2c)(i2c); + + ret = rtl9300_i2c_config_chan(i2c, chan); + if (ret) +- goto out_unlock; ++ return ret; + + xfer.dev_addr = addr & 0x7f; + xfer.write = (read_write == I2C_SMBUS_WRITE); +@@ -324,20 +326,14 @@ static int rtl9300_i2c_smbus_xfer(struct + break; + default: + dev_err(&adap->dev, "Unsupported transaction %d\n", size); +- ret = -EOPNOTSUPP; +- goto out_unlock; ++ return -EOPNOTSUPP; + } + + ret = rtl9300_i2c_prepare_xfer(i2c, &xfer); + if (ret) +- goto out_unlock; +- +- ret = rtl9300_i2c_do_xfer(i2c, &xfer); +- +-out_unlock: +- mutex_unlock(&i2c->lock); ++ return ret; + +- return ret; ++ return rtl9300_i2c_do_xfer(i2c, &xfer); + } + + static u32 rtl9300_i2c_func(struct i2c_adapter *a) diff --git a/target/linux/realtek/patches-6.12/008-08-v6.18-dt-bindings-i2c-realtek-rtl9301-i2c-extend-for-RTL93.patch b/target/linux/realtek/patches-6.12/008-08-v6.18-dt-bindings-i2c-realtek-rtl9301-i2c-extend-for-RTL93.patch new file mode 100644 index 0000000000..9bc6851e70 --- /dev/null +++ b/target/linux/realtek/patches-6.12/008-08-v6.18-dt-bindings-i2c-realtek-rtl9301-i2c-extend-for-RTL93.patch @@ -0,0 +1,94 @@ +From 17689aafb793599a862617a127429dd3d6f675c9 Mon Sep 17 00:00:00 2001 +From: Jonas Jelonek +Date: Sat, 27 Sep 2025 10:19:30 +0000 +Subject: [PATCH] dt-bindings: i2c: realtek,rtl9301-i2c: extend for RTL9310 + support + +Adjust the regex for child-node address to account for the fact that +RTL9310 supports 12 instead of only 8 SDA lines. Also, narrow this per +variant. + +Add a vendor-specific property to explicitly specify the SCL line number +of the defined I2C controller/master. This is required, in particular +for RTL9310, to operate on the correct SCL for each controller. Require +this property to be specified for RTL9310. + +Add compatibles for known SoC variants RTL9311, RTL9312 and RTL9313. + +Signed-off-by: Jonas Jelonek +Reviewed-by: Rob Herring (Arm) +Reviewed-by: Chris Packham +Tested-by: Markus Stockhausen +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250927101931.71575-9-jelonek.jonas@gmail.com + +--- a/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml ++++ b/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml +@@ -13,6 +13,8 @@ description: + RTL9300 SoCs have two I2C controllers. Each of these has an SCL line (which + if not-used for SCL can be a GPIO). There are 8 common SDA lines that can be + assigned to either I2C controller. ++ RTL9310 SoCs have equal capabilities but support 12 common SDA lines which ++ can be assigned to either I2C controller. + + properties: + compatible: +@@ -23,7 +25,15 @@ properties: + - realtek,rtl9302c-i2c + - realtek,rtl9303-i2c + - const: realtek,rtl9301-i2c +- - const: realtek,rtl9301-i2c ++ - items: ++ - enum: ++ - realtek,rtl9311-i2c ++ - realtek,rtl9312-i2c ++ - realtek,rtl9313-i2c ++ - const: realtek,rtl9310-i2c ++ - enum: ++ - realtek,rtl9301-i2c ++ - realtek,rtl9310-i2c + + reg: + items: +@@ -35,8 +45,14 @@ properties: + "#size-cells": + const: 0 + ++ realtek,scl: ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ description: ++ The SCL line number of this I2C controller. ++ enum: [ 0, 1 ] ++ + patternProperties: +- '^i2c@[0-7]$': ++ '^i2c@[0-9ab]$': + $ref: /schemas/i2c/i2c-controller.yaml + unevaluatedProperties: false + +@@ -48,6 +64,25 @@ patternProperties: + required: + - reg + ++ ++allOf: ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: realtek,rtl9310-i2c ++ then: ++ required: ++ - realtek,scl ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: realtek,rtl9301-i2c ++ then: ++ patternProperties: ++ '^i2c@[89ab]$': false ++ + required: + - compatible + - reg diff --git a/target/linux/realtek/patches-6.12/008-09-v6.18-i2c-rtl9300-add-support-for-RTL9310-I2C-controller.patch b/target/linux/realtek/patches-6.12/008-09-v6.18-i2c-rtl9300-add-support-for-RTL9310-I2C-controller.patch new file mode 100644 index 0000000000..6d5a23c0e8 --- /dev/null +++ b/target/linux/realtek/patches-6.12/008-09-v6.18-i2c-rtl9300-add-support-for-RTL9310-I2C-controller.patch @@ -0,0 +1,134 @@ +From 8d43287120ce6437e7a77e735d99137f3fdb3ae9 Mon Sep 17 00:00:00 2001 +From: Jonas Jelonek +Date: Sat, 27 Sep 2025 10:19:31 +0000 +Subject: [PATCH] i2c: rtl9300: add support for RTL9310 I2C controller + +Add support for the internal I2C controllers of RTL9310 series based +SoCs to the driver for RTL9300. Add register definitions, chip-specific +functions and compatible strings for known RTL9310-based SoCs RTL9311, +RTL9312 and RTL9313. + +Make use of a new device tree property 'realtek,scl' which needs to be +specified in case both or only the second master is used. This is +required due how the register layout changed in contrast to RTL9300, +which has SCL selection in a global register instead of a +master-specific one. + +Signed-off-by: Jonas Jelonek +Tested-by: Sven Eckelmann +Reviewed-by: Chris Packham +Tested-by: Markus Stockhausen +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20250927101931.71575-10-jelonek.jonas@gmail.com + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -60,14 +60,16 @@ struct rtl9300_i2c_drv_data { + }; + + #define RTL9300_I2C_MUX_NCHAN 8 ++#define RTL9310_I2C_MUX_NCHAN 12 + + struct rtl9300_i2c { + struct regmap *regmap; + struct device *dev; +- struct rtl9300_i2c_chan chans[RTL9300_I2C_MUX_NCHAN]; ++ struct rtl9300_i2c_chan chans[RTL9310_I2C_MUX_NCHAN]; + struct regmap_field *fields[F_NUM_FIELDS]; + u32 reg_base; + u32 data_reg; ++ u8 scl_num; + u8 sda_num; + struct mutex lock; + }; +@@ -98,6 +100,12 @@ struct rtl9300_i2c_xfer { + #define RTL9300_I2C_MST_DATA_WORD3 0x14 + #define RTL9300_I2C_MST_GLB_CTRL 0x384 + ++#define RTL9310_I2C_MST_IF_CTRL 0x1004 ++#define RTL9310_I2C_MST_IF_SEL 0x1008 ++#define RTL9310_I2C_MST_CTRL 0x0 ++#define RTL9310_I2C_MST_MEMADDR_CTRL 0x4 ++#define RTL9310_I2C_MST_DATA_CTRL 0x8 ++ + static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len) + { + int ret; +@@ -114,6 +122,11 @@ static int rtl9300_i2c_select_scl(struct + return regmap_field_write(i2c->fields[F_SCL_SEL], 1); + } + ++static int rtl9310_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl) ++{ ++ return regmap_field_update_bits(i2c->fields[F_SCL_SEL], BIT(scl), BIT(scl)); ++} ++ + static int rtl9300_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan) + { + struct rtl9300_i2c_drv_data *drv_data; +@@ -127,7 +140,7 @@ static int rtl9300_i2c_config_chan(struc + return ret; + + drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev); +- ret = drv_data->select_scl(i2c, 0); ++ ret = drv_data->select_scl(i2c, i2c->scl_num); + if (ret) + return ret; + +@@ -361,7 +374,7 @@ static int rtl9300_i2c_probe(struct plat + struct fwnode_handle *child; + struct rtl9300_i2c_drv_data *drv_data; + struct reg_field fields[F_NUM_FIELDS]; +- u32 clock_freq, sda_num; ++ u32 clock_freq, scl_num, sda_num; + int ret, i = 0; + + i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); +@@ -379,6 +392,11 @@ static int rtl9300_i2c_probe(struct plat + if (ret) + return ret; + ++ ret = device_property_read_u32(dev, "realtek,scl", &scl_num); ++ if (ret || scl_num != 1) ++ scl_num = 0; ++ i2c->scl_num = (u8)scl_num; ++ + platform_set_drvdata(pdev, i2c); + + drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev); +@@ -474,12 +492,35 @@ static const struct rtl9300_i2c_drv_data + .max_nchan = RTL9300_I2C_MUX_NCHAN, + }; + ++static const struct rtl9300_i2c_drv_data rtl9310_i2c_drv_data = { ++ .field_desc = { ++ [F_SCL_SEL] = GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 12, 13), ++ [F_SDA_SEL] = GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 0, 11), ++ [F_SCL_FREQ] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 30, 31), ++ [F_DEV_ADDR] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 11, 17), ++ [F_SDA_OUT_SEL] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 18, 21), ++ [F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 9, 10), ++ [F_DATA_WIDTH] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 5, 8), ++ [F_RD_MODE] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 4, 4), ++ [F_RWOP] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 2, 2), ++ [F_I2C_FAIL] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 1, 1), ++ [F_I2C_TRIG] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 0, 0), ++ [F_MEM_ADDR] = MST_REG_FIELD(RTL9310_I2C_MST_MEMADDR_CTRL, 0, 23), ++ }, ++ .select_scl = rtl9310_i2c_select_scl, ++ .data_reg = RTL9310_I2C_MST_DATA_CTRL, ++ .max_nchan = RTL9310_I2C_MUX_NCHAN, ++}; + + static const struct of_device_id i2c_rtl9300_dt_ids[] = { + { .compatible = "realtek,rtl9301-i2c", .data = (void *) &rtl9300_i2c_drv_data }, + { .compatible = "realtek,rtl9302b-i2c", .data = (void *) &rtl9300_i2c_drv_data }, + { .compatible = "realtek,rtl9302c-i2c", .data = (void *) &rtl9300_i2c_drv_data }, + { .compatible = "realtek,rtl9303-i2c", .data = (void *) &rtl9300_i2c_drv_data }, ++ { .compatible = "realtek,rtl9310-i2c", .data = (void *) &rtl9310_i2c_drv_data }, ++ { .compatible = "realtek,rtl9311-i2c", .data = (void *) &rtl9310_i2c_drv_data }, ++ { .compatible = "realtek,rtl9312-i2c", .data = (void *) &rtl9310_i2c_drv_data }, ++ { .compatible = "realtek,rtl9313-i2c", .data = (void *) &rtl9310_i2c_drv_data }, + {} + }; + MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids); diff --git a/target/linux/realtek/patches-6.12/020-02-v6.18-timer-rtl-otto-drop-set-counter-function.patch b/target/linux/realtek/patches-6.12/020-02-v6.18-timer-rtl-otto-drop-set-counter-function.patch new file mode 100644 index 0000000000..5ee2f07f27 --- /dev/null +++ b/target/linux/realtek/patches-6.12/020-02-v6.18-timer-rtl-otto-drop-set-counter-function.patch @@ -0,0 +1,51 @@ +From 85e27f218121bdaa8e8afd68674262aa154d2cb4 Mon Sep 17 00:00:00 2001 +From: Markus Stockhausen +Date: Mon, 4 Aug 2025 04:03:26 -0400 +Subject: clocksource/drivers/timer-rtl-otto: Drop set_counter function +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The current counter value is a read only register. It will be +reset when writing a new target timer value with rttm_set_period(). +rttm_set_counter() is essentially a noop. Drop it. + +While this makes rttm_start_timer() and rttm_enable_timer() the +same functions keep both to make the established abstraction layers +for register and control functions active. + +Downstream has already tested and confirmed a patch. See +https://github.com/openwrt/openwrt/pull/19468 +https://forum.openwrt.org/t/support-for-rtl838x-based-managed-switches/57875/3788 + +Tested-by: Stephen Howell +Tested-by: Bjørn Mork +Signed-off-by: Markus Stockhausen +Link: https://lore.kernel.org/r/20250804080328.2609287-3-markus.stockhausen@gmx.de +Signed-off-by: Daniel Lezcano +--- + drivers/clocksource/timer-rtl-otto.c | 6 ------ + 1 file changed, 6 deletions(-) + +--- a/drivers/clocksource/timer-rtl-otto.c ++++ b/drivers/clocksource/timer-rtl-otto.c +@@ -56,11 +56,6 @@ struct rttm_cs { + }; + + /* Simple internal register functions */ +-static inline void rttm_set_counter(void __iomem *base, unsigned int counter) +-{ +- iowrite32(counter, base + RTTM_CNT); +-} +- + static inline unsigned int rttm_get_counter(void __iomem *base) + { + return ioread32(base + RTTM_CNT); +@@ -137,7 +132,6 @@ static void rttm_stop_timer(void __iomem + + static void rttm_start_timer(struct timer_of *to, u32 mode) + { +- rttm_set_counter(to->of_base.base, 0); + rttm_enable_timer(to->of_base.base, mode, to->of_clk.rate / RTTM_TICKS_PER_SEC); + } + diff --git a/target/linux/realtek/patches-6.12/021-v6.18-mtd-nand-add-realtek-ecc-engine.patch b/target/linux/realtek/patches-6.12/021-v6.18-mtd-nand-add-realtek-ecc-engine.patch new file mode 100644 index 0000000000..7c7811e707 --- /dev/null +++ b/target/linux/realtek/patches-6.12/021-v6.18-mtd-nand-add-realtek-ecc-engine.patch @@ -0,0 +1,521 @@ +From 3148d0e5b1c5733d69ec51b70c8280e46488750a Mon Sep 17 00:00:00 2001 +From: Markus Stockhausen +Date: Fri, 19 Sep 2025 03:52:01 -0400 +Subject: mtd: nand: realtek-ecc: Add Realtek external ECC engine support + +The Realtek RTl93xx switch SoC series has a built in ECC controller +that can provide BCH6 or BCH12 over 512 data and 6 tag bytes. It +generates 10 (BCH6) or 20 (BCH12) bytes of parity. + +This engine will most likely work in conjunction with the Realtek +spi-mem based NAND controller but can work on its own. Therefore +the initial implementation will be of type external. + +Remark! The engine can support any data blocks that are multiples +of 512 bytes. For now limit it to data+oob layouts that have been +analyzed from existing devices. This way it keeps compatibility +and pre-existing vendor data can be read. + +Signed-off-by: Markus Stockhausen +Signed-off-by: Miquel Raynal +--- + drivers/mtd/nand/Kconfig | 8 + + drivers/mtd/nand/Makefile | 1 + + drivers/mtd/nand/ecc-realtek.c | 464 +++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 473 insertions(+) + create mode 100644 drivers/mtd/nand/ecc-realtek.c + +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -65,6 +65,14 @@ config MTD_NAND_ECC_MEDIATEK + help + This enables support for the hardware ECC engine from Mediatek. + ++config MTD_NAND_ECC_REALTEK ++ tristate "Realtek RTL93xx hardware ECC engine" ++ depends on HAS_IOMEM ++ depends on MACH_REALTEK_RTL || COMPILE_TEST ++ select MTD_NAND_ECC ++ help ++ This enables support for the hardware ECC engine from Realtek. ++ + endmenu + + endmenu +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -2,6 +2,7 @@ + + nandcore-objs := core.o bbt.o + obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o ++obj-$(CONFIG_MTD_NAND_ECC_REALTEK) += ecc-realtek.o + obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o + obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o + obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o +--- /dev/null ++++ b/drivers/mtd/nand/ecc-realtek.c +@@ -0,0 +1,464 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Support for Realtek hardware ECC engine in RTL93xx SoCs ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * The Realtek ECC engine has two operation modes. ++ * ++ * - BCH6 : Generate 10 ECC bytes from 512 data bytes plus 6 free bytes ++ * - BCH12 : Generate 20 ECC bytes from 512 data bytes plus 6 free bytes ++ * ++ * It can run for arbitrary NAND flash chips with different block and OOB sizes. Currently there ++ * are only two known devices in the wild that have NAND flash and make use of this ECC engine ++ * (Linksys LGS328C & LGS352C). To keep compatibility with vendor firmware, new modes can only ++ * be added when new data layouts have been analyzed. For now allow BCH6 on flash with 2048 byte ++ * blocks and 64 bytes oob. ++ * ++ * This driver aligns with kernel ECC naming conventions. Neverthless a short notice on the ++ * Realtek naming conventions for the different structures in the OOB area. ++ * ++ * - BBI : Bad block indicator. The first two bytes of OOB. Protected by ECC! ++ * - tag : 6 User/free bytes. First tag "contains" 2 bytes BBI. Protected by ECC! ++ * - syndrome : ECC/parity bytes ++ * ++ * Altogether this gives currently the following block layout. ++ * ++ * +------+------+------+------+-----+------+------+------+------+-----+-----+-----+-----+ ++ * | 512 | 512 | 512 | 512 | 2 | 4 | 6 | 6 | 6 | 10 | 10 | 10 | 10 | ++ * +------+------+------+------+-----+------+------+------+------+-----+-----+-----+-----+ ++ * | data | data | data | data | BBI | free | free | free | free | ECC | ECC | ECC | ECC | ++ * +------+------+------+------+-----+------+------+------+------+-----+-----+-----+-----+ ++ */ ++ ++#define RTL_ECC_ALLOWED_PAGE_SIZE 2048 ++#define RTL_ECC_ALLOWED_OOB_SIZE 64 ++#define RTL_ECC_ALLOWED_STRENGTH 6 ++ ++#define RTL_ECC_BLOCK_SIZE 512 ++#define RTL_ECC_FREE_SIZE 6 ++#define RTL_ECC_PARITY_SIZE_BCH6 10 ++#define RTL_ECC_PARITY_SIZE_BCH12 20 ++ ++/* ++ * The engine is fed with two DMA regions. One for data (always 512 bytes) and one for free bytes ++ * and parity (either 16 bytes for BCH6 or 26 bytes for BCH12). Start and length of each must be ++ * aligned to a multiple of 4. ++ */ ++ ++#define RTL_ECC_DMA_FREE_PARITY_SIZE ALIGN(RTL_ECC_FREE_SIZE + RTL_ECC_PARITY_SIZE_BCH12, 4) ++#define RTL_ECC_DMA_SIZE (RTL_ECC_BLOCK_SIZE + RTL_ECC_DMA_FREE_PARITY_SIZE) ++ ++#define RTL_ECC_CFG 0x00 ++#define RTL_ECC_BCH6 0 ++#define RTL_ECC_BCH12 BIT(28) ++#define RTL_ECC_DMA_PRECISE BIT(12) ++#define RTL_ECC_BURST_128 GENMASK(1, 0) ++#define RTL_ECC_DMA_TRIGGER 0x08 ++#define RTL_ECC_OP_DECODE 0 ++#define RTL_ECC_OP_ENCODE BIT(0) ++#define RTL_ECC_DMA_START 0x0c ++#define RTL_ECC_DMA_TAG 0x10 ++#define RTL_ECC_STATUS 0x14 ++#define RTL_ECC_CORR_COUNT GENMASK(19, 12) ++#define RTL_ECC_RESULT BIT(8) ++#define RTL_ECC_ALL_ONE BIT(4) ++#define RTL_ECC_OP_STATUS BIT(0) ++ ++struct rtl_ecc_engine { ++ struct device *dev; ++ struct nand_ecc_engine engine; ++ struct mutex lock; ++ char *buf; ++ dma_addr_t buf_dma; ++ struct regmap *regmap; ++}; ++ ++struct rtl_ecc_ctx { ++ struct rtl_ecc_engine * rtlc; ++ struct nand_ecc_req_tweak_ctx req_ctx; ++ int steps; ++ int bch_mode; ++ int strength; ++ int parity_size; ++}; ++ ++static const struct regmap_config rtl_ecc_regmap_config = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = 4, ++}; ++ ++static inline void *nand_to_ctx(struct nand_device *nand) ++{ ++ return nand->ecc.ctx.priv; ++} ++ ++static inline struct rtl_ecc_engine *nand_to_rtlc(struct nand_device *nand) ++{ ++ struct nand_ecc_engine *eng = nand->ecc.engine; ++ ++ return container_of(eng, struct rtl_ecc_engine, engine); ++} ++ ++static int rtl_ecc_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobregion) ++{ ++ struct nand_device *nand = mtd_to_nanddev(mtd); ++ struct rtl_ecc_ctx *ctx = nand_to_ctx(nand); ++ ++ if (section < 0 || section >= ctx->steps) ++ return -ERANGE; ++ ++ oobregion->offset = ctx->steps * RTL_ECC_FREE_SIZE + section * ctx->parity_size; ++ oobregion->length = ctx->parity_size; ++ ++ return 0; ++} ++ ++static int rtl_ecc_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobregion) ++{ ++ struct nand_device *nand = mtd_to_nanddev(mtd); ++ struct rtl_ecc_ctx *ctx = nand_to_ctx(nand); ++ int bbm; ++ ++ if (section < 0 || section >= ctx->steps) ++ return -ERANGE; ++ ++ /* reserve 2 BBM bytes in first block */ ++ bbm = section ? 0 : 2; ++ oobregion->offset = section * RTL_ECC_FREE_SIZE + bbm; ++ oobregion->length = RTL_ECC_FREE_SIZE - bbm; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops rtl_ecc_ooblayout_ops = { ++ .ecc = rtl_ecc_ooblayout_ecc, ++ .free = rtl_ecc_ooblayout_free, ++}; ++ ++static void rtl_ecc_kick_engine(struct rtl_ecc_ctx *ctx, int operation) ++{ ++ struct rtl_ecc_engine *rtlc = ctx->rtlc; ++ ++ regmap_write(rtlc->regmap, RTL_ECC_CFG, ++ ctx->bch_mode | RTL_ECC_BURST_128 | RTL_ECC_DMA_PRECISE); ++ ++ regmap_write(rtlc->regmap, RTL_ECC_DMA_START, rtlc->buf_dma); ++ regmap_write(rtlc->regmap, RTL_ECC_DMA_TAG, rtlc->buf_dma + RTL_ECC_BLOCK_SIZE); ++ regmap_write(rtlc->regmap, RTL_ECC_DMA_TRIGGER, operation); ++} ++ ++static int rtl_ecc_wait_for_engine(struct rtl_ecc_ctx *ctx) ++{ ++ struct rtl_ecc_engine *rtlc = ctx->rtlc; ++ int ret, status, bitflips; ++ bool all_one; ++ ++ /* ++ * The ECC engine needs 6-8 us to encode/decode a BCH6 syndrome for 512 bytes of data ++ * and 6 free bytes. In case the NAND area has been erased and all data and oob is ++ * set to 0xff, decoding takes 30us (reason unknown). Although the engine can trigger ++ * interrupts when finished, use active polling for now. 12 us maximum wait time has ++ * proven to be a good tradeoff between performance and overhead. ++ */ ++ ++ ret = regmap_read_poll_timeout(rtlc->regmap, RTL_ECC_STATUS, status, ++ !(status & RTL_ECC_OP_STATUS), 12, 1000000); ++ if (ret) ++ return ret; ++ ++ ret = FIELD_GET(RTL_ECC_RESULT, status); ++ all_one = FIELD_GET(RTL_ECC_ALL_ONE, status); ++ bitflips = FIELD_GET(RTL_ECC_CORR_COUNT, status); ++ ++ /* For erased blocks (all bits one) error status can be ignored */ ++ if (all_one) ++ ret = 0; ++ ++ return ret ? -EBADMSG : bitflips; ++} ++ ++static int rtl_ecc_run_engine(struct rtl_ecc_ctx *ctx, char *data, char *free, ++ char *parity, int operation) ++{ ++ struct rtl_ecc_engine *rtlc = ctx->rtlc; ++ char *buf_parity = rtlc->buf + RTL_ECC_BLOCK_SIZE + RTL_ECC_FREE_SIZE; ++ char *buf_free = rtlc->buf + RTL_ECC_BLOCK_SIZE; ++ char *buf_data = rtlc->buf; ++ int ret; ++ ++ mutex_lock(&rtlc->lock); ++ ++ memcpy(buf_data, data, RTL_ECC_BLOCK_SIZE); ++ memcpy(buf_free, free, RTL_ECC_FREE_SIZE); ++ memcpy(buf_parity, parity, ctx->parity_size); ++ ++ dma_sync_single_for_device(rtlc->dev, rtlc->buf_dma, RTL_ECC_DMA_SIZE, DMA_TO_DEVICE); ++ rtl_ecc_kick_engine(ctx, operation); ++ ret = rtl_ecc_wait_for_engine(ctx); ++ dma_sync_single_for_cpu(rtlc->dev, rtlc->buf_dma, RTL_ECC_DMA_SIZE, DMA_FROM_DEVICE); ++ ++ if (ret >= 0) { ++ memcpy(data, buf_data, RTL_ECC_BLOCK_SIZE); ++ memcpy(free, buf_free, RTL_ECC_FREE_SIZE); ++ memcpy(parity, buf_parity, ctx->parity_size); ++ } ++ ++ mutex_unlock(&rtlc->lock); ++ ++ return ret; ++} ++ ++static int rtl_ecc_prepare_io_req(struct nand_device *nand, struct nand_page_io_req *req) ++{ ++ struct rtl_ecc_engine *rtlc = nand_to_rtlc(nand); ++ struct rtl_ecc_ctx *ctx = nand_to_ctx(nand); ++ char *data, *free, *parity; ++ int ret = 0; ++ ++ if (req->mode == MTD_OPS_RAW) ++ return 0; ++ ++ nand_ecc_tweak_req(&ctx->req_ctx, req); ++ ++ if (req->type == NAND_PAGE_READ) ++ return 0; ++ ++ free = req->oobbuf.in; ++ data = req->databuf.in; ++ parity = req->oobbuf.in + ctx->steps * RTL_ECC_FREE_SIZE; ++ ++ for (int i = 0; i < ctx->steps; i++) { ++ ret |= rtl_ecc_run_engine(ctx, data, free, parity, RTL_ECC_OP_ENCODE); ++ ++ free += RTL_ECC_FREE_SIZE; ++ data += RTL_ECC_BLOCK_SIZE; ++ parity += ctx->parity_size; ++ } ++ ++ if (unlikely(ret)) ++ dev_dbg(rtlc->dev, "ECC calculation failed\n"); ++ ++ return ret ? -EBADMSG : 0; ++} ++ ++static int rtl_ecc_finish_io_req(struct nand_device *nand, struct nand_page_io_req *req) ++{ ++ struct rtl_ecc_engine *rtlc = nand_to_rtlc(nand); ++ struct rtl_ecc_ctx *ctx = nand_to_ctx(nand); ++ struct mtd_info *mtd = nanddev_to_mtd(nand); ++ char *data, *free, *parity; ++ bool failure = false; ++ int bitflips = 0; ++ ++ if (req->mode == MTD_OPS_RAW) ++ return 0; ++ ++ if (req->type == NAND_PAGE_WRITE) { ++ nand_ecc_restore_req(&ctx->req_ctx, req); ++ return 0; ++ } ++ ++ free = req->oobbuf.in; ++ data = req->databuf.in; ++ parity = req->oobbuf.in + ctx->steps * RTL_ECC_FREE_SIZE; ++ ++ for (int i = 0 ; i < ctx->steps; i++) { ++ int ret = rtl_ecc_run_engine(ctx, data, free, parity, RTL_ECC_OP_DECODE); ++ ++ if (unlikely(ret < 0)) ++ /* ECC totally fails for bitflips in erased blocks */ ++ ret = nand_check_erased_ecc_chunk(data, RTL_ECC_BLOCK_SIZE, ++ parity, ctx->parity_size, ++ free, RTL_ECC_FREE_SIZE, ++ ctx->strength); ++ if (unlikely(ret < 0)) { ++ failure = true; ++ mtd->ecc_stats.failed++; ++ } else { ++ mtd->ecc_stats.corrected += ret; ++ bitflips = max_t(unsigned int, bitflips, ret); ++ } ++ ++ free += RTL_ECC_FREE_SIZE; ++ data += RTL_ECC_BLOCK_SIZE; ++ parity += ctx->parity_size; ++ } ++ ++ nand_ecc_restore_req(&ctx->req_ctx, req); ++ ++ if (unlikely(failure)) ++ dev_dbg(rtlc->dev, "ECC correction failed\n"); ++ else if (unlikely(bitflips > 2)) ++ dev_dbg(rtlc->dev, "%d bitflips detected\n", bitflips); ++ ++ return failure ? -EBADMSG : bitflips; ++} ++ ++static int rtl_ecc_check_support(struct nand_device *nand) ++{ ++ struct mtd_info *mtd = nanddev_to_mtd(nand); ++ struct device *dev = nand->ecc.engine->dev; ++ ++ if (mtd->oobsize != RTL_ECC_ALLOWED_OOB_SIZE || ++ mtd->writesize != RTL_ECC_ALLOWED_PAGE_SIZE) { ++ dev_err(dev, "only flash geometry data=%d, oob=%d supported\n", ++ RTL_ECC_ALLOWED_PAGE_SIZE, RTL_ECC_ALLOWED_OOB_SIZE); ++ return -EINVAL; ++ } ++ ++ if (nand->ecc.user_conf.algo != NAND_ECC_ALGO_BCH || ++ nand->ecc.user_conf.strength != RTL_ECC_ALLOWED_STRENGTH || ++ nand->ecc.user_conf.placement != NAND_ECC_PLACEMENT_OOB || ++ nand->ecc.user_conf.step_size != RTL_ECC_BLOCK_SIZE) { ++ dev_err(dev, "only algo=bch, strength=%d, placement=oob, step=%d supported\n", ++ RTL_ECC_ALLOWED_STRENGTH, RTL_ECC_BLOCK_SIZE); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int rtl_ecc_init_ctx(struct nand_device *nand) ++{ ++ struct nand_ecc_props *conf = &nand->ecc.ctx.conf; ++ struct rtl_ecc_engine *rtlc = nand_to_rtlc(nand); ++ struct mtd_info *mtd = nanddev_to_mtd(nand); ++ int strength = nand->ecc.user_conf.strength; ++ struct device *dev = nand->ecc.engine->dev; ++ struct rtl_ecc_ctx *ctx; ++ int ret; ++ ++ ret = rtl_ecc_check_support(nand); ++ if (ret) ++ return ret; ++ ++ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); ++ if (!ctx) ++ return -ENOMEM; ++ ++ nand->ecc.ctx.priv = ctx; ++ mtd_set_ooblayout(mtd, &rtl_ecc_ooblayout_ops); ++ ++ conf->algo = NAND_ECC_ALGO_BCH; ++ conf->strength = strength; ++ conf->step_size = RTL_ECC_BLOCK_SIZE; ++ conf->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; ++ ++ ctx->rtlc = rtlc; ++ ctx->steps = mtd->writesize / RTL_ECC_BLOCK_SIZE; ++ ctx->strength = strength; ++ ctx->bch_mode = strength == 6 ? RTL_ECC_BCH6 : RTL_ECC_BCH12; ++ ctx->parity_size = strength == 6 ? RTL_ECC_PARITY_SIZE_BCH6 : RTL_ECC_PARITY_SIZE_BCH12; ++ ++ ret = nand_ecc_init_req_tweaking(&ctx->req_ctx, nand); ++ if (ret) ++ return ret; ++ ++ dev_dbg(dev, "using bch%d with geometry data=%dx%d, free=%dx6, parity=%dx%d", ++ conf->strength, ctx->steps, conf->step_size, ++ ctx->steps, ctx->steps, ctx->parity_size); ++ ++ return 0; ++} ++ ++static void rtl_ecc_cleanup_ctx(struct nand_device *nand) ++{ ++ struct rtl_ecc_ctx *ctx = nand_to_ctx(nand); ++ ++ if (ctx) ++ nand_ecc_cleanup_req_tweaking(&ctx->req_ctx); ++} ++ ++static struct nand_ecc_engine_ops rtl_ecc_engine_ops = { ++ .init_ctx = rtl_ecc_init_ctx, ++ .cleanup_ctx = rtl_ecc_cleanup_ctx, ++ .prepare_io_req = rtl_ecc_prepare_io_req, ++ .finish_io_req = rtl_ecc_finish_io_req, ++}; ++ ++static int rtl_ecc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct rtl_ecc_engine *rtlc; ++ void __iomem *base; ++ int ret; ++ ++ rtlc = devm_kzalloc(dev, sizeof(*rtlc), GFP_KERNEL); ++ if (!rtlc) ++ return -ENOMEM; ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ ret = devm_mutex_init(dev, &rtlc->lock); ++ if (ret) ++ return ret; ++ ++ rtlc->regmap = devm_regmap_init_mmio(dev, base, &rtl_ecc_regmap_config); ++ if (IS_ERR(rtlc->regmap)) ++ return PTR_ERR(rtlc->regmap); ++ ++ /* ++ * Focus on simplicity and use a preallocated DMA buffer for data exchange with the ++ * engine. For now make it a noncoherent memory model as invalidating/flushing caches ++ * is faster than reading/writing uncached memory on the known architectures. ++ */ ++ ++ rtlc->buf = dma_alloc_noncoherent(dev, RTL_ECC_DMA_SIZE, &rtlc->buf_dma, ++ DMA_BIDIRECTIONAL, GFP_KERNEL); ++ if (IS_ERR(rtlc->buf)) ++ return PTR_ERR(rtlc->buf); ++ ++ rtlc->dev = dev; ++ rtlc->engine.dev = dev; ++ rtlc->engine.ops = &rtl_ecc_engine_ops; ++ rtlc->engine.integration = NAND_ECC_ENGINE_INTEGRATION_EXTERNAL; ++ ++ nand_ecc_register_on_host_hw_engine(&rtlc->engine); ++ ++ platform_set_drvdata(pdev, rtlc); ++ ++ return 0; ++} ++ ++static void rtl_ecc_remove(struct platform_device *pdev) ++{ ++ struct rtl_ecc_engine *rtlc = platform_get_drvdata(pdev); ++ ++ nand_ecc_unregister_on_host_hw_engine(&rtlc->engine); ++ dma_free_noncoherent(rtlc->dev, RTL_ECC_DMA_SIZE, rtlc->buf, rtlc->buf_dma, ++ DMA_BIDIRECTIONAL); ++} ++ ++static const struct of_device_id rtl_ecc_of_ids[] = { ++ { ++ .compatible = "realtek,rtl9301-ecc", ++ }, ++ { /* sentinel */ }, ++}; ++ ++static struct platform_driver rtl_ecc_driver = { ++ .driver = { ++ .name = "rtl-nand-ecc-engine", ++ .of_match_table = rtl_ecc_of_ids, ++ }, ++ .probe = rtl_ecc_probe, ++ .remove = rtl_ecc_remove, ++}; ++module_platform_driver(rtl_ecc_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Markus Stockhausen "); ++MODULE_DESCRIPTION("Realtek NAND hardware ECC controller"); diff --git a/target/linux/realtek/patches-6.12/022-v7.0-mtd-nand-realtek-ecc-relax-OOB-size-check-to-minimum.patch b/target/linux/realtek/patches-6.12/022-v7.0-mtd-nand-realtek-ecc-relax-OOB-size-check-to-minimum.patch new file mode 100644 index 0000000000..8155c78dcf --- /dev/null +++ b/target/linux/realtek/patches-6.12/022-v7.0-mtd-nand-realtek-ecc-relax-OOB-size-check-to-minimum.patch @@ -0,0 +1,67 @@ +From 0c741b8b6963e584b41c284cd743c545636edb04 Mon Sep 17 00:00:00 2001 +From: Ahmed Naseef +Date: Sat, 7 Feb 2026 11:02:43 +0400 +Subject: mtd: nand: realtek-ecc: relax OOB size check to minimum + +The ECC engine strictly validates that flash OOB size equals exactly +64 bytes. However, some NAND chips have a larger physical OOB while +vendor firmware only uses the first 64 bytes for the ECC layout. For +example the Macronix MX35LF1G24AD found in the Netlink HG323DAC has +128 byte physical OOB but vendor firmware only uses the first 64 +bytes (24 bytes free + 40 bytes BCH6 parity), leaving bytes 64-127 +unused. + +Since the engine only operates on the first 64 bytes of OOB +regardless of the physical size, change the check from exact match +to minimum size. Flash with OOB >= 64 bytes works correctly with +the engine's 64-byte layout. + +Suggested-by: Markus Stockhausen +Signed-off-by: Ahmed Naseef +Signed-off-by: Miquel Raynal +--- + drivers/mtd/nand/ecc-realtek.c | 18 ++++++++++-------- + 1 file changed, 10 insertions(+), 8 deletions(-) + +--- a/drivers/mtd/nand/ecc-realtek.c ++++ b/drivers/mtd/nand/ecc-realtek.c +@@ -17,10 +17,12 @@ + * - BCH12 : Generate 20 ECC bytes from 512 data bytes plus 6 free bytes + * + * It can run for arbitrary NAND flash chips with different block and OOB sizes. Currently there +- * are only two known devices in the wild that have NAND flash and make use of this ECC engine +- * (Linksys LGS328C & LGS352C). To keep compatibility with vendor firmware, new modes can only +- * be added when new data layouts have been analyzed. For now allow BCH6 on flash with 2048 byte +- * blocks and 64 bytes oob. ++ * are a few known devices in the wild that make use of this ECC engine ++ * (Linksys LGS328C, LGS352C & Netlink HG323DAC). To keep compatibility with vendor firmware, ++ * new modes can only be added when new data layouts have been analyzed. For now allow BCH6 on ++ * flash with 2048 byte blocks and at least 64 bytes oob. Some vendors make use of ++ * 128 bytes OOB NAND chips (e.g. Macronix MX35LF1G24AD) but only use BCH6 and thus the first ++ * 64 bytes of the OOB area. In this case the engine leaves any extra bytes unused. + * + * This driver aligns with kernel ECC naming conventions. Neverthless a short notice on the + * Realtek naming conventions for the different structures in the OOB area. +@@ -39,7 +41,7 @@ + */ + + #define RTL_ECC_ALLOWED_PAGE_SIZE 2048 +-#define RTL_ECC_ALLOWED_OOB_SIZE 64 ++#define RTL_ECC_ALLOWED_MIN_OOB_SIZE 64 + #define RTL_ECC_ALLOWED_STRENGTH 6 + + #define RTL_ECC_BLOCK_SIZE 512 +@@ -310,10 +312,10 @@ static int rtl_ecc_check_support(struct + struct mtd_info *mtd = nanddev_to_mtd(nand); + struct device *dev = nand->ecc.engine->dev; + +- if (mtd->oobsize != RTL_ECC_ALLOWED_OOB_SIZE || ++ if (mtd->oobsize < RTL_ECC_ALLOWED_MIN_OOB_SIZE || + mtd->writesize != RTL_ECC_ALLOWED_PAGE_SIZE) { +- dev_err(dev, "only flash geometry data=%d, oob=%d supported\n", +- RTL_ECC_ALLOWED_PAGE_SIZE, RTL_ECC_ALLOWED_OOB_SIZE); ++ dev_err(dev, "only flash geometry data=%d, oob>=%d supported\n", ++ RTL_ECC_ALLOWED_PAGE_SIZE, RTL_ECC_ALLOWED_MIN_OOB_SIZE); + return -EINVAL; + } + diff --git a/target/linux/realtek/patches-6.12/023-01-v7.0-dt-bindings-gpio-realtek-otto-add-rtl9607-compatible.patch b/target/linux/realtek/patches-6.12/023-01-v7.0-dt-bindings-gpio-realtek-otto-add-rtl9607-compatible.patch new file mode 100644 index 0000000000..bfaf092872 --- /dev/null +++ b/target/linux/realtek/patches-6.12/023-01-v7.0-dt-bindings-gpio-realtek-otto-add-rtl9607-compatible.patch @@ -0,0 +1,27 @@ +From 49944d6ab7eb951f2aefee69341c623e13434863 Mon Sep 17 00:00:00 2001 +From: Rustam Adilov +Date: Thu, 5 Mar 2026 21:11:05 +0500 +Subject: dt-bindings: gpio: realtek-otto: add rtl9607 compatible + +Add the "realtek,rtl9607-gpio" compatible for GPIO nodes +on the RTL9607C SoC series. + +Signed-off-by: Rustam Adilov +Reviewed-by: Linus Walleij +Reviewed-by: Sander Vanheule +Link: https://patch.msgid.link/20260305161106.15999-2-adilov@disroot.org +Signed-off-by: Bartosz Golaszewski +--- + Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml | 1 + + 1 file changed, 1 insertion(+) + +--- a/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml ++++ b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml +@@ -30,6 +30,7 @@ properties: + - realtek,rtl8390-gpio + - realtek,rtl9300-gpio + - realtek,rtl9310-gpio ++ - realtek,rtl9607-gpio + - const: realtek,otto-gpio + + reg: true diff --git a/target/linux/realtek/patches-6.12/023-02-v7.0-gpio-realtek-otto-add-rtl9607-support.patch b/target/linux/realtek/patches-6.12/023-02-v7.0-gpio-realtek-otto-add-rtl9607-support.patch new file mode 100644 index 0000000000..bc60d881a7 --- /dev/null +++ b/target/linux/realtek/patches-6.12/023-02-v7.0-gpio-realtek-otto-add-rtl9607-support.patch @@ -0,0 +1,29 @@ +From 8f0aecf2957e7dba78603544368846133bf6d22e Mon Sep 17 00:00:00 2001 +From: Rustam Adilov +Date: Thu, 5 Mar 2026 21:11:06 +0500 +Subject: gpio: realtek-otto: add rtl9607 support + +The RTL9607C SoC has support for 3 GPIO banks with 32 GPIOs each and +the port order is reversed just like in RTL930x. + +Signed-off-by: Rustam Adilov +Reviewed-by: Sander Vanheule +Link: https://patch.msgid.link/20260305161106.15999-3-adilov@disroot.org +Signed-off-by: Bartosz Golaszewski +--- + drivers/gpio/gpio-realtek-otto.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/gpio/gpio-realtek-otto.c ++++ b/drivers/gpio/gpio-realtek-otto.c +@@ -350,6 +350,10 @@ static const struct of_device_id realtek + { + .compatible = "realtek,rtl9310-gpio", + }, ++ { ++ .compatible = "realtek,rtl9607-gpio", ++ .data = (void *)GPIO_PORTS_REVERSED, ++ }, + {} + }; + MODULE_DEVICE_TABLE(of, realtek_gpio_of_match); diff --git a/target/linux/realtek/patches-6.12/024-01-v7.1-dt-bindings-net-ethernet-phy-add-property-enet-phy-p.patch b/target/linux/realtek/patches-6.12/024-01-v7.1-dt-bindings-net-ethernet-phy-add-property-enet-phy-p.patch new file mode 100644 index 0000000000..fd0235c53f --- /dev/null +++ b/target/linux/realtek/patches-6.12/024-01-v7.1-dt-bindings-net-ethernet-phy-add-property-enet-phy-p.patch @@ -0,0 +1,37 @@ +From c1887257a81bf62f48178d3b9d31e23520d67b2c Mon Sep 17 00:00:00 2001 +From: Damien Dejean +Date: Wed, 18 Mar 2026 22:54:58 +0100 +Subject: [PATCH 1/4] dt-bindings: net: ethernet-phy: add property + enet-phy-pair-order + +Add property enet-phy-pair-order to the device tree bindings to define +the pair order of the PHY. To simplify PCB design some manufacturers +allow to wire the pairs in a reverse order, and change the order in +software. + +The property can be set to 0 to force the normal pair order (ABCD), or 1 +to force the reverse pair order (DCBA). + +Signed-off-by: Damien Dejean +Reviewed-by: Rob Herring (Arm) +Link: https://patch.msgid.link/20260318215502.106528-2-dam.dejean@gmail.com +Signed-off-by: Jakub Kicinski +--- + Documentation/devicetree/bindings/net/ethernet-phy.yaml | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml ++++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml +@@ -122,6 +122,12 @@ properties: + e.g. wrong bootstrap configuration caused by issues in PCB + layout design. + ++ enet-phy-pair-order: ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ enum: [0, 1] ++ description: ++ For normal (0) or reverse (1) order of the pairs (ABCD -> DCBA). ++ + eee-broken-100tx: + $ref: /schemas/types.yaml#/definitions/flag + description: diff --git a/target/linux/realtek/patches-6.12/024-02-v7.1-net-phy-realtek-add-RTL8224-pair-order-support.patch b/target/linux/realtek/patches-6.12/024-02-v7.1-net-phy-realtek-add-RTL8224-pair-order-support.patch new file mode 100644 index 0000000000..63e8512b16 --- /dev/null +++ b/target/linux/realtek/patches-6.12/024-02-v7.1-net-phy-realtek-add-RTL8224-pair-order-support.patch @@ -0,0 +1,124 @@ +From 330296ea9e158758aa65631f5ec64aa74806b7e2 Mon Sep 17 00:00:00 2001 +From: Damien Dejean +Date: Wed, 18 Mar 2026 22:54:59 +0100 +Subject: [PATCH 2/4] net: phy: realtek: add RTL8224 pair order support + +The RTL8224 has a register to configure a pair swap (from ABCD order to +DCBA) providing PCB designers more flexbility when wiring the chip. The +swap parameter has to be set correctly for each of the 4 ports before +the chip can detect a link. + +After a reset, this register is (unfortunately) left in a random state, +thus it has to be initialized. On most of the devices the bootloader +does it once for all and we can rely on the value set, on some other it +is not and the kernel has to do it. + +The MDI pair swap can be set in the device tree using the property +enet-phy-pair-order. The property is set to 0 to keep the default order +(ABCD), or 1 to reverse the pairs (DCBA). + +Signed-off-by: Damien Dejean +Link: https://patch.msgid.link/20260318215502.106528-3-dam.dejean@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/realtek/Kconfig | 1 + + drivers/net/phy/realtek/realtek_main.c | 64 ++++++++++++++++++++++++++ + 2 files changed, 65 insertions(+) + +--- a/drivers/net/phy/realtek/Kconfig ++++ b/drivers/net/phy/realtek/Kconfig +@@ -1,6 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0-only + config REALTEK_PHY + tristate "Realtek PHYs" ++ select PHY_PACKAGE + help + Currently supports RTL821x/RTL822x and fast ethernet PHYs + +--- a/drivers/net/phy/realtek/realtek_main.c ++++ b/drivers/net/phy/realtek/realtek_main.c +@@ -175,6 +175,8 @@ + #define RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN BIT(12) + #define RTL8221B_PHYCR1_PHYAD_0_EN BIT(13) + ++#define RTL8224_VND1_MDI_PAIR_SWAP 0xa90 ++ + #define RTL8366RB_POWER_SAVE 0x15 + #define RTL8366RB_POWER_SAVE_ON BIT(12) + +@@ -1865,6 +1867,66 @@ static int rtl8224_cable_test_get_status + return rtl8224_cable_test_report(phydev, finished); + } + ++static int rtl8224_package_modify_mmd(struct phy_device *phydev, int devad, ++ u32 regnum, u16 mask, u16 set) ++{ ++ int val, ret; ++ ++ phy_lock_mdio_bus(phydev); ++ ++ val = __phy_package_read_mmd(phydev, 0, devad, regnum); ++ if (val < 0) { ++ ret = val; ++ goto exit; ++ } ++ ++ val &= ~mask; ++ val |= set; ++ ++ ret = __phy_package_write_mmd(phydev, 0, devad, regnum, val); ++ ++exit: ++ phy_unlock_mdio_bus(phydev); ++ return ret; ++} ++ ++static int rtl8224_mdi_config_order(struct phy_device *phydev) ++{ ++ struct device_node *np = phydev->mdio.dev.of_node; ++ u8 port_offset = phydev->mdio.addr & 3; ++ u32 order = 0; ++ int ret; ++ ++ ret = of_property_read_u32(np, "enet-phy-pair-order", &order); ++ ++ /* Do nothing in case the property is not present */ ++ if (ret == -EINVAL || ret == -ENOSYS) ++ return 0; ++ ++ if (ret) ++ return ret; ++ ++ if (order & ~1) ++ return -EINVAL; ++ ++ return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1, ++ RTL8224_VND1_MDI_PAIR_SWAP, ++ BIT(port_offset), ++ order ? BIT(port_offset) : 0); ++} ++ ++static int rtl8224_config_init(struct phy_device *phydev) ++{ ++ return rtl8224_mdi_config_order(phydev); ++} ++ ++static int rtl8224_probe(struct phy_device *phydev) ++{ ++ /* Chip exposes 4 ports, join all of them in the same package */ ++ return devm_phy_package_join(&phydev->mdio.dev, phydev, ++ phydev->mdio.addr & ~3, 0); ++} ++ + static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) + { + int val; +@@ -2466,6 +2528,8 @@ static struct phy_driver realtek_drvs[] + PHY_ID_MATCH_EXACT(0x001ccad0), + .name = "RTL8224 2.5Gbps PHY", + .flags = PHY_POLL_CABLE_TEST, ++ .probe = rtl8224_probe, ++ .config_init = rtl8224_config_init, + .get_features = rtl822x_c45_get_features, + .config_aneg = rtl822x_c45_config_aneg, + .read_status = rtl822x_c45_read_status, diff --git a/target/linux/realtek/patches-6.12/024-03-v7.1-dt-bindings-net-ethernet-phy-add-property-enet-phy-p.patch b/target/linux/realtek/patches-6.12/024-03-v7.1-dt-bindings-net-ethernet-phy-add-property-enet-phy-p.patch new file mode 100644 index 0000000000..a6a215fb03 --- /dev/null +++ b/target/linux/realtek/patches-6.12/024-03-v7.1-dt-bindings-net-ethernet-phy-add-property-enet-phy-p.patch @@ -0,0 +1,39 @@ +From 58ffb5910f32e5b387d4af31ee21851c40eb31b5 Mon Sep 17 00:00:00 2001 +From: Damien Dejean +Date: Wed, 18 Mar 2026 22:55:00 +0100 +Subject: [PATCH 3/4] dt-bindings: net: ethernet-phy: add property + enet-phy-pair-polarity + +Add the property enet-phy-pair-polarity to describe the polarity of the +PHY pairs. To ease PCB designs some manufacturers allow to wire the +pairs with a reverse polarity and provide a way to configure it. + +The property 'enet-phy-pair-polarity' sets the polarity of each pair. +Bit 0 to 3 configure the polarity or pairs A to D, if set to 1 the +polarity is reversed for this pair. + +Signed-off-by: Damien Dejean +Reviewed-by: Rob Herring (Arm) +Link: https://patch.msgid.link/20260318215502.106528-4-dam.dejean@gmail.com +Signed-off-by: Jakub Kicinski +--- + Documentation/devicetree/bindings/net/ethernet-phy.yaml | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml ++++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml +@@ -128,6 +128,14 @@ properties: + description: + For normal (0) or reverse (1) order of the pairs (ABCD -> DCBA). + ++ enet-phy-pair-polarity: ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ maximum: 0xf ++ description: ++ A bitmap to describe pair polarity swap. Bit 0 to swap polarity of pair A, ++ bit 1 to swap polarity of pair B, bit 2 to swap polarity of pair C and bit ++ 3 to swap polarity of pair D. ++ + eee-broken-100tx: + $ref: /schemas/types.yaml#/definitions/flag + description: diff --git a/target/linux/realtek/patches-6.12/024-04-v7.1-net-phy-realtek-add-RTL8224-polarity-support.patch b/target/linux/realtek/patches-6.12/024-04-v7.1-net-phy-realtek-add-RTL8224-polarity-support.patch new file mode 100644 index 0000000000..df69c6515d --- /dev/null +++ b/target/linux/realtek/patches-6.12/024-04-v7.1-net-phy-realtek-add-RTL8224-polarity-support.patch @@ -0,0 +1,76 @@ +From beed9c0e9b53c98bc66d28d46fbe38c347e9aa74 Mon Sep 17 00:00:00 2001 +From: Damien Dejean +Date: Wed, 18 Mar 2026 22:55:01 +0100 +Subject: [PATCH 4/4] net: phy: realtek: add RTL8224 polarity support + +The RTL8224 has a register to configure the polarity of every pair of +each port. It provides device designers more flexbility when wiring the +chip. + +Unfortunately, the register is left in an unknown state after a reset. +Thus on devices where the bootloader don't initialize it, the driver has +to do it to detect and use a link. + +The MDI polarity swap can be set in the device tree using the property +enet-phy-pair-polarity. The u32 value is a bitfield where bit[0..3] +control the polarity of pairs A..D. + +Signed-off-by: Damien Dejean +Link: https://patch.msgid.link/20260318215502.106528-5-dam.dejean@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/realtek/realtek_main.c | 34 +++++++++++++++++++++++++- + 1 file changed, 33 insertions(+), 1 deletion(-) + +--- a/drivers/net/phy/realtek/realtek_main.c ++++ b/drivers/net/phy/realtek/realtek_main.c +@@ -176,6 +176,7 @@ + #define RTL8221B_PHYCR1_PHYAD_0_EN BIT(13) + + #define RTL8224_VND1_MDI_PAIR_SWAP 0xa90 ++#define RTL8224_VND1_MDI_POLARITY_SWAP 0xa94 + + #define RTL8366RB_POWER_SAVE 0x15 + #define RTL8366RB_POWER_SAVE_ON BIT(12) +@@ -1915,9 +1916,40 @@ static int rtl8224_mdi_config_order(stru + order ? BIT(port_offset) : 0); + } + ++static int rtl8224_mdi_config_polarity(struct phy_device *phydev) ++{ ++ struct device_node *np = phydev->mdio.dev.of_node; ++ u8 offset = (phydev->mdio.addr & 3) * 4; ++ u32 polarity = 0; ++ int ret; ++ ++ ret = of_property_read_u32(np, "enet-phy-pair-polarity", &polarity); ++ ++ /* Do nothing if the property is not present */ ++ if (ret == -EINVAL || ret == -ENOSYS) ++ return 0; ++ ++ if (ret) ++ return ret; ++ ++ if (polarity & ~0xf) ++ return -EINVAL; ++ ++ return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1, ++ RTL8224_VND1_MDI_POLARITY_SWAP, ++ 0xf << offset, ++ polarity << offset); ++} ++ + static int rtl8224_config_init(struct phy_device *phydev) + { +- return rtl8224_mdi_config_order(phydev); ++ int ret; ++ ++ ret = rtl8224_mdi_config_order(phydev); ++ if (ret) ++ return ret; ++ ++ return rtl8224_mdi_config_polarity(phydev); + } + + static int rtl8224_probe(struct phy_device *phydev) diff --git a/target/linux/realtek/patches-6.12/100-rtl9300-i2c-add-more-speeds.patch b/target/linux/realtek/patches-6.12/100-rtl9300-i2c-add-more-speeds.patch new file mode 100644 index 0000000000..1879c8f5ee --- /dev/null +++ b/target/linux/realtek/patches-6.12/100-rtl9300-i2c-add-more-speeds.patch @@ -0,0 +1,52 @@ +From linux-i2c Fri Feb 27 11:11:34 2026 +From: Jan Kantert +Date: Fri, 27 Feb 2026 11:11:34 +0000 +To: linux-i2c +Subject: [PATCH] i2c: rtl9300: add support for 50 kHz and 2.5 MHz bus speeds +Message-Id: <20260227111134.2163701-1-jan-kernel () kantert ! net> +X-MARC-Message: https://marc.info/?l=linux-i2c&m=177219358420283 + +Some SFP modules on certain switches (for example the ONTi ONT-S508CL-8S and +XikeStor SKS8300-8X) exhibit unreliable I2C communication at the currently +supported speeds. Add support for 50 kHz and 2.5 MHz I2C bus modes on the +RTL9300 to improve compatibility with these devices. + +Signed-off-by: Jan Kantert +--- + drivers/i2c/busses/i2c-rtl9300.c | 16 ++++++++++++++-- + 1 file changed, 14 insertions(+), 2 deletions(-) + +--- a/drivers/i2c/busses/i2c-rtl9300.c ++++ b/drivers/i2c/busses/i2c-rtl9300.c +@@ -11,10 +11,16 @@ + #include + + enum rtl9300_bus_freq { +- RTL9300_I2C_STD_FREQ, +- RTL9300_I2C_FAST_FREQ, ++ RTL9300_I2C_STD_FREQ, // 100kHz ++ RTL9300_I2C_FAST_FREQ, // 400kHz ++ RTL9300_I2C_SUPER_FAST_FREQ, // 2.5MHz ++ RTL9300_I2C_SLOW_FREQ, // 50kHz + }; + ++#define RTL9300_I2C_MAX_SUPER_FAST_FREQ 2500000 ++#define RTL9300_I2C_MAX_SLOW_FREQ 50000 ++ ++ + struct rtl9300_i2c; + + struct rtl9300_i2c_chan { +@@ -434,6 +440,12 @@ static int rtl9300_i2c_probe(struct plat + case I2C_MAX_FAST_MODE_FREQ: + chan->bus_freq = RTL9300_I2C_FAST_FREQ; + break; ++ case RTL9300_I2C_MAX_SUPER_FAST_FREQ: ++ chan->bus_freq = RTL9300_I2C_SUPER_FAST_FREQ; ++ break; ++ case RTL9300_I2C_MAX_SLOW_FREQ: ++ chan->bus_freq = RTL9300_I2C_SLOW_FREQ; ++ break; + default: + dev_warn(i2c->dev, "SDA%d clock-frequency %d not supported using default\n", + sda_num, clock_freq); diff --git a/target/linux/realtek/patches-6.12/300-mips-add-rtl838x-platform.patch b/target/linux/realtek/patches-6.12/300-mips-add-rtl838x-platform.patch new file mode 100644 index 0000000000..c0ebb3184f --- /dev/null +++ b/target/linux/realtek/patches-6.12/300-mips-add-rtl838x-platform.patch @@ -0,0 +1,91 @@ +From fce11f68491b46b93df69de0630cd9edb90bc772 Mon Sep 17 00:00:00 2001 +From: Birger Koblitz +Date: Wed, 29 Dec 2021 21:54:21 +0100 +Subject: [PATCH] realtek: Create 4 different Realtek Platforms + +Creates RTL83XX as a basic kernel config parameter for the +RTL838X, RTL839x, RTL930X and RTL931X platforms with respective +configurations for the SoCs, which are introduced in addition. + +Submitted-by: Birger Koblitz +--- +--- a/arch/mips/Kbuild.platforms ++++ b/arch/mips/Kbuild.platforms +@@ -22,6 +22,7 @@ platform-$(CONFIG_MACH_NINTENDO64) += n6 + platform-$(CONFIG_PIC32MZDA) += pic32/ + platform-$(CONFIG_RALINK) += ralink/ + platform-$(CONFIG_MIKROTIK_RB532) += rb532/ ++platform-$(CONFIG_MACH_REALTEK_RTL) += rtl-otto/ + platform-$(CONFIG_SGI_IP22) += sgi-ip22/ + platform-$(CONFIG_SGI_IP27) += sgi-ip27/ + platform-$(CONFIG_SGI_IP28) += sgi-ip22/ +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -651,23 +651,24 @@ config RALINK + + config MACH_REALTEK_RTL + bool "Realtek RTL838x/RTL839x based machines" +- select MIPS_GENERIC +- select MACH_GENERIC_CORE + select DMA_NONCOHERENT + select IRQ_MIPS_CPU +- select CSRC_R4K +- select CEVT_R4K + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_MIPS16 +- select SYS_SUPPORTS_MULTITHREADING +- select SYS_SUPPORTS_VPE_LOADER + select BOOT_RAW + select PINCTRL + select USE_OF + select REALTEK_OTTO_TIMER ++ select NO_EXCEPT_FILL ++ select SYS_SUPPORTS_HIGHMEM ++ select SYS_HAS_EARLY_PRINTK ++ select SYS_HAS_EARLY_PRINTK_8250 ++ select USE_GENERIC_EARLY_PRINTK_8250 ++ select ARCH_HAS_RESET_CONTROLLER ++ select RESET_CONTROLLER + + config SGI_IP22 + bool "SGI IP22 (Indy/Indigo2)" +@@ -1011,6 +1012,36 @@ config FIT_IMAGE_FDT_EPM5 + from Mobileye in the FIT kernel image. + This requires u-boot on the platform. + ++config RTL838X ++ bool "Realtek RTL838X based platforms" ++ depends on MACH_REALTEK_RTL ++ select CPU_SUPPORTS_CPUFREQ ++ select MIPS_EXTERNAL_TIMER ++ ++config RTL839X ++ bool "Realtek RTL839X based platforms" ++ depends on MACH_REALTEK_RTL ++ select CPU_SUPPORTS_CPUFREQ ++ select MIPS_EXTERNAL_TIMER ++ select SYS_SUPPORTS_MULTITHREADING ++ ++config RTL930X ++ bool "Realtek RTL930X based platforms" ++ depends on MACH_REALTEK_RTL ++ select MIPS_CPU_SCACHE ++ select MIPS_EXTERNAL_TIMER ++ select SYS_SUPPORTS_MULTITHREADING ++ ++config RTL931X ++ bool "Realtek RTL931X based platforms" ++ depends on RTL930X ++ select MIPS_GIC ++ select COMMON_CLK ++ select CLKSRC_MIPS_GIC ++ select SYS_SUPPORTS_VPE_LOADER ++ select SYS_SUPPORTS_SMP ++ select SYS_SUPPORTS_MIPS_CPS ++ + source "arch/mips/alchemy/Kconfig" + source "arch/mips/ath25/Kconfig" + source "arch/mips/ath79/Kconfig" diff --git a/target/linux/realtek/patches-6.12/302-6.17-irqchip-mips-gic-forced-affinity.patch b/target/linux/realtek/patches-6.12/302-6.17-irqchip-mips-gic-forced-affinity.patch new file mode 100644 index 0000000000..cf04d60703 --- /dev/null +++ b/target/linux/realtek/patches-6.12/302-6.17-irqchip-mips-gic-forced-affinity.patch @@ -0,0 +1,47 @@ +From 2250db8628a0d8293ad2e0671138b848a185fba1 Mon Sep 17 00:00:00 2001 +From: Markus Stockhausen +Date: Sat, 21 Jun 2025 01:49:51 -0400 +Subject: irqchip/mips-gic: Allow forced affinity + +Devices of the Realtek MIPS Otto platform use the official rtl-otto-timer +as clock event generator and CPU clocksource. It is registered for each CPU +startup via cpuhp_setup_state() and forces the affinity of the clockevent +interrupts to the appropriate CPU via irq_force_affinity(). + +On the "smaller" devices with a vendor specific interrupt controller +(supported by irq-realtek-rtl) the registration works fine. The "larger" +RTL931x series is based on a MIPS interAptiv dual core with a MIPS GIC +controller. Interrupt routing setup is cancelled because gic_set_affinity() +does not accept the current (not yet online) CPU as a target. + +Relax the checks by evaluating the force parameter that is provided for +exactly this purpose like in other drivers. With this the affinity can be +set as follows: + + - force = false: allow to set affinity to any online cpu + - force = true: allow to set affinity to any cpu + +Co-developed-by: Sebastian Gottschall +Signed-off-by: Sebastian Gottschall +Signed-off-by: Markus Stockhausen +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/all/20250621054952.380374-1-markus.stockhausen@gmx.de +--- + drivers/irqchip/irq-mips-gic.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +--- a/drivers/irqchip/irq-mips-gic.c ++++ b/drivers/irqchip/irq-mips-gic.c +@@ -263,7 +263,11 @@ static int gic_set_affinity(struct irq_d + unsigned long flags; + unsigned int cpu; + +- cpu = cpumask_first_and(cpumask, cpu_online_mask); ++ if (force) ++ cpu = cpumask_first(cpumask); ++ else ++ cpu = cpumask_first_and(cpumask, cpu_online_mask); ++ + if (cpu >= NR_CPUS) + return -EINVAL; + diff --git a/target/linux/realtek/patches-6.12/306-disable-upstream-realtek-board.patch b/target/linux/realtek/patches-6.12/306-disable-upstream-realtek-board.patch new file mode 100644 index 0000000000..62dd64223e --- /dev/null +++ b/target/linux/realtek/patches-6.12/306-disable-upstream-realtek-board.patch @@ -0,0 +1,16 @@ +From: Markus Stockhausen +Subject: [PATCH] realtek: disable upstream Realtek board + +Upstream now has integrated the Realtek target into the generic +MIPS initialization. For now disable the board compilation. + +Submitted-by: Markus Stockhausen +--- +--- a/arch/mips/generic/Makefile ++++ b/arch/mips/generic/Makefile +@@ -13,4 +13,4 @@ obj-$(CONFIG_LEGACY_BOARD_SEAD3) += boar + obj-$(CONFIG_LEGACY_BOARD_OCELOT) += board-ocelot.o + obj-$(CONFIG_MACH_INGENIC) += board-ingenic.o + obj-$(CONFIG_VIRT_BOARD_RANCHU) += board-ranchu.o +-obj-$(CONFIG_MACH_REALTEK_RTL) += board-realtek.o ++# obj-$(CONFIG_MACH_REALTEK_RTL) += board-realtek.o diff --git a/target/linux/realtek/patches-6.12/308-tune-switch-4kec.patch b/target/linux/realtek/patches-6.12/308-tune-switch-4kec.patch new file mode 100644 index 0000000000..87cd76d462 --- /dev/null +++ b/target/linux/realtek/patches-6.12/308-tune-switch-4kec.patch @@ -0,0 +1,24 @@ +From: Markus Stockhausen +Date: Fri, 13 Jun 2025 20:25:37 +0100 +Subject: [PATCH] realtek: set mtune 4kec for RTL838x targets + +Generic patches will always force the gcc kernel tuning to 34kc. With RTL838x +being only 4kec this does not harm but is not right. Match the tuning properly. + +Signed-off-by: Markus Stockhausen +--- + +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -164,6 +164,11 @@ cflags-$(CONFIG_CPU_R4X00) += $(call cc- + cflags-$(CONFIG_CPU_TX49XX) += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap + cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap + cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -mtune=34kc -Wa,--trap ++ ++#ifdef CONFIG_RTL838X ++cflags-$(CONFIG_CPU_MIPS32_R2) := $(subst 34kc,4kec,$(cflags-$(CONFIG_CPU_MIPS32_R2))) ++#endif ++ + cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg + cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap -modd-spreg + cflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,--trap diff --git a/target/linux/realtek/patches-6.12/314-irqchip-irq-realtek-rtl-add-VPE-support.patch b/target/linux/realtek/patches-6.12/314-irqchip-irq-realtek-rtl-add-VPE-support.patch new file mode 100644 index 0000000000..4610ca8c19 --- /dev/null +++ b/target/linux/realtek/patches-6.12/314-irqchip-irq-realtek-rtl-add-VPE-support.patch @@ -0,0 +1,427 @@ +From 6c18e9c491959ac0674ebe36b09f9ddc3f2c9bce Mon Sep 17 00:00:00 2001 +From: Birger Koblitz +Date: Fri, 31 Dec 2021 11:56:49 +0100 +Subject: [PATCH] realtek: Add VPE support for the IRQ driver + +In order to support VSMP, enable support for both VPEs of the RTL839X +and RTL930X SoCs in the irq-realtek-rtl driver. Add support for IRQ +affinity setting. + +Up to kernel 5.15 this patch was divided into two parts + +315-irqchip-irq-realtek-rtl-add-VPE-support.patch +319-irqchip-irq-realtek-rtl-fix-VPE-affinity.patch + +As both parts will only work in combination they have been merged into +one patch. + +Submitted-by: Birger Koblitz +Submitted-by: INAGAKI Hiroshi +Signed-off-by: Markus Stockhausen +--- + drivers/irqchip/irq-realtek-rtl.c | 296 +++++++++++++++++++++++++----- + 1 file changed, 249 insertions(+), 47 deletions(-) + +--- a/drivers/irqchip/irq-realtek-rtl.c ++++ b/drivers/irqchip/irq-realtek-rtl.c +@@ -22,22 +22,58 @@ + #define RTL_ICTL_IRR3 0x14 + + #define RTL_ICTL_NUM_INPUTS 32 +- +-#define REG(x) (realtek_ictl_base + x) ++#define RTL_ICTL_NUM_OUTPUTS 15 + + static DEFINE_RAW_SPINLOCK(irq_lock); +-static void __iomem *realtek_ictl_base; ++ ++#define REG(offset, cpu) (realtek_ictl_base[cpu] + offset) ++ ++static u32 realtek_ictl_unmask[NR_CPUS]; ++static void __iomem *realtek_ictl_base[NR_CPUS]; ++static cpumask_t realtek_ictl_cpu_configurable; ++ ++struct realtek_ictl_output { ++ /* IRQ controller data */ ++ struct fwnode_handle *fwnode; ++ /* Output specific data */ ++ unsigned int output_index; ++ struct irq_domain *domain; ++ u32 child_mask; ++}; + + /* +- * IRR0-IRR3 store 4 bits per interrupt, but Realtek uses inverted numbering, +- * placing IRQ 31 in the first four bits. A routing value of '0' means the +- * interrupt is left disconnected. Routing values {1..15} connect to output +- * lines {0..14}. ++ * Per CPU we have a set of 5 registers that determine interrupt handling for ++ * 32 external interrupts. GIMR (enable/disable interrupt) plus IRR0-IRR3 that ++ * contain "routing" or "priority" values. GIMR uses one bit for each interrupt ++ * and IRRx store 4 bits per interrupt. Realtek uses inverted numbering, ++ * placing IRQ 31 in the first four bits. The register combinations give the ++ * following results for a single interrupt in the wild: ++ * ++ * a) GIMR = 0 / IRRx > 0 -> no interrupts ++ * b) GIMR = 0 / IRRx = 0 -> no interrupts ++ * c) GIMR = 1 / IRRx > 0 -> interrupts ++ * d) GIMR = 1 / IRRx = 0 -> rare interrupts in SMP environment ++ * ++ * Combination d) seems to trigger interrupts only on a VPE if the other VPE ++ * has GIMR = 0 and IRRx > 0. E.g. busy without interrupts allowed. To provide ++ * IRQ balancing features in SMP this driver will handle the registers as ++ * follows: ++ * ++ * 1) set IRRx > 0 for VPE where the interrupt is desired ++ * 2) set IRRx = 0 for VPE where the interrupt is not desired ++ * 3) set both GIMR = 0 to mask (disabled) interrupt ++ * 4) set GIMR = 1 to unmask (enable) interrupt but only for VPE where IRRx > 0 + */ ++ + #define IRR_OFFSET(idx) (4 * (3 - (idx * 4) / 32)) + #define IRR_SHIFT(idx) ((idx * 4) % 32) + +-static void write_irr(void __iomem *irr0, int idx, u32 value) ++static inline u32 read_irr(void __iomem *irr0, int idx) ++{ ++ return (readl(irr0 + IRR_OFFSET(idx)) >> IRR_SHIFT(idx)) & 0xf; ++} ++ ++static inline void write_irr(void __iomem *irr0, int idx, u32 value) + { + unsigned int offset = IRR_OFFSET(idx); + unsigned int shift = IRR_SHIFT(idx); +@@ -48,16 +84,33 @@ static void write_irr(void __iomem *irr0 + writel(irr, irr0 + offset); + } + ++static inline void enable_gimr(int hwirq, int cpu) ++{ ++ u32 value; ++ ++ value = readl(REG(RTL_ICTL_GIMR, cpu)); ++ value |= (BIT(hwirq) & realtek_ictl_unmask[cpu]); ++ writel(value, REG(RTL_ICTL_GIMR, cpu)); ++} ++ ++static inline void disable_gimr(int hwirq, int cpu) ++{ ++ u32 value; ++ ++ value = readl(REG(RTL_ICTL_GIMR, cpu)); ++ value &= ~BIT(hwirq); ++ writel(value, REG(RTL_ICTL_GIMR, cpu)); ++} ++ + static void realtek_ictl_unmask_irq(struct irq_data *i) + { + unsigned long flags; +- u32 value; ++ int cpu; + + raw_spin_lock_irqsave(&irq_lock, flags); + +- value = readl(REG(RTL_ICTL_GIMR)); +- value |= BIT(i->hwirq); +- writel(value, REG(RTL_ICTL_GIMR)); ++ for_each_cpu(cpu, &realtek_ictl_cpu_configurable) ++ enable_gimr(i->hwirq, cpu); + + raw_spin_unlock_irqrestore(&irq_lock, flags); + } +@@ -65,110 +118,259 @@ static void realtek_ictl_unmask_irq(stru + static void realtek_ictl_mask_irq(struct irq_data *i) + { + unsigned long flags; +- u32 value; ++ int cpu; + + raw_spin_lock_irqsave(&irq_lock, flags); + +- value = readl(REG(RTL_ICTL_GIMR)); +- value &= ~BIT(i->hwirq); +- writel(value, REG(RTL_ICTL_GIMR)); ++ for_each_cpu(cpu, &realtek_ictl_cpu_configurable) ++ disable_gimr(i->hwirq, cpu); + + raw_spin_unlock_irqrestore(&irq_lock, flags); + } + ++static int __maybe_unused realtek_ictl_irq_affinity(struct irq_data *i, ++ const struct cpumask *dest, bool force) ++{ ++ struct realtek_ictl_output *output = i->domain->host_data; ++ cpumask_t cpu_configure; ++ cpumask_t cpu_disable; ++ cpumask_t cpu_enable; ++ unsigned long flags; ++ int cpu; ++ ++ raw_spin_lock_irqsave(&irq_lock, flags); ++ ++ cpumask_and(&cpu_configure, cpu_present_mask, &realtek_ictl_cpu_configurable); ++ ++ cpumask_and(&cpu_enable, &cpu_configure, dest); ++ cpumask_andnot(&cpu_disable, &cpu_configure, dest); ++ ++ for_each_cpu(cpu, &cpu_disable) { ++ write_irr(REG(RTL_ICTL_IRR0, cpu), i->hwirq, 0); ++ realtek_ictl_unmask[cpu] &= ~BIT(i->hwirq); ++ disable_gimr(i->hwirq, cpu); ++ } ++ ++ for_each_cpu(cpu, &cpu_enable) { ++ write_irr(REG(RTL_ICTL_IRR0, cpu), i->hwirq, output->output_index + 1); ++ realtek_ictl_unmask[cpu] |= BIT(i->hwirq); ++ enable_gimr(i->hwirq, cpu); ++ } ++ ++ irq_data_update_effective_affinity(i, &cpu_enable); ++ ++ raw_spin_unlock_irqrestore(&irq_lock, flags); ++ ++ return IRQ_SET_MASK_OK; ++} ++ + static struct irq_chip realtek_ictl_irq = { + .name = "realtek-rtl-intc", + .irq_mask = realtek_ictl_mask_irq, + .irq_unmask = realtek_ictl_unmask_irq, ++#ifdef CONFIG_SMP ++ .irq_set_affinity = realtek_ictl_irq_affinity, ++#endif + }; + + static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) + { ++ struct realtek_ictl_output *output = d->host_data; + unsigned long flags; + + irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq); + + raw_spin_lock_irqsave(&irq_lock, flags); +- write_irr(REG(RTL_ICTL_IRR0), hw, 1); ++ ++ output->child_mask |= BIT(hw); ++ write_irr(REG(RTL_ICTL_IRR0, 0), hw, output->output_index + 1); ++ realtek_ictl_unmask[0] |= BIT(hw); ++ + raw_spin_unlock_irqrestore(&irq_lock, flags); + + return 0; + } + ++static int intc_select(struct irq_domain *d, struct irq_fwspec *fwspec, ++ enum irq_domain_bus_token bus_token) ++{ ++ struct realtek_ictl_output *output = d->host_data; ++ bool routed_elsewhere; ++ unsigned long flags; ++ u32 routing_old; ++ int cpu; ++ ++ if (fwspec->fwnode != output->fwnode) ++ return false; ++ ++ /* Original specifiers had only one parameter */ ++ if (fwspec->param_count < 2) ++ return true; ++ ++ raw_spin_lock_irqsave(&irq_lock, flags); ++ ++ /* ++ * Inputs can only be routed to one output, so they shouldn't be ++ * allowed to end up in multiple domains. ++ */ ++ for_each_cpu(cpu, &realtek_ictl_cpu_configurable) { ++ routing_old = read_irr(REG(RTL_ICTL_IRR0, cpu), fwspec->param[0]); ++ routed_elsewhere = routing_old && fwspec->param[1] != routing_old - 1; ++ if (routed_elsewhere) { ++ pr_warn("soc int %d already routed to output %d\n", ++ fwspec->param[0], routing_old - 1); ++ break; ++ } ++ } ++ ++ raw_spin_unlock_irqrestore(&irq_lock, flags); ++ ++ return !routed_elsewhere && fwspec->param[1] == output->output_index; ++} ++ + static const struct irq_domain_ops irq_domain_ops = { + .map = intc_map, ++ .select = intc_select, + .xlate = irq_domain_xlate_onecell, + }; + + static void realtek_irq_dispatch(struct irq_desc *desc) + { ++ struct realtek_ictl_output *output = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); +- struct irq_domain *domain; ++ int cpu = smp_processor_id(); + unsigned long pending; + unsigned int soc_int; + + chained_irq_enter(chip, desc); +- pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR)); ++ pending = readl(REG(RTL_ICTL_GIMR, cpu)) & readl(REG(RTL_ICTL_GISR, cpu)) ++ & output->child_mask; + + if (unlikely(!pending)) { + spurious_interrupt(); + goto out; + } + +- domain = irq_desc_get_handler_data(desc); +- for_each_set_bit(soc_int, &pending, 32) +- generic_handle_domain_irq(domain, soc_int); ++ for_each_set_bit(soc_int, &pending, RTL_ICTL_NUM_INPUTS) ++ generic_handle_domain_irq(output->domain, soc_int); + + out: + chained_irq_exit(chip, desc); + } + ++/* ++ * SoC interrupts are cascaded to MIPS CPU interrupts according to the ++ * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for ++ * the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts ++ * thus go into 4 IRRs. A routing value of '0' means the interrupt is left ++ * disconnected. Routing values {1..15} connect to output lines {0..14}. ++ */ ++static int __init setup_parent_interrupts(struct device_node *node, int *parents, ++ unsigned int num_parents) ++{ ++ struct realtek_ictl_output *outputs; ++ struct realtek_ictl_output *output; ++ struct irq_domain *domain; ++ unsigned int p; ++ ++ outputs = kcalloc(num_parents, sizeof(*outputs), GFP_KERNEL); ++ if (!outputs) ++ return -ENOMEM; ++ ++ for (p = 0; p < num_parents; p++) { ++ output = outputs + p; ++ ++ domain = irq_domain_add_linear(node, RTL_ICTL_NUM_INPUTS, &irq_domain_ops, output); ++ if (!domain) ++ goto domain_err; ++ ++ output->fwnode = of_node_to_fwnode(node); ++ output->output_index = p; ++ output->domain = domain; ++ ++ irq_set_chained_handler_and_data(parents[p], realtek_irq_dispatch, output); ++ } ++ ++ return 0; ++ ++domain_err: ++ while (p--) { ++ irq_set_chained_handler_and_data(parents[p], NULL, NULL); ++ irq_domain_remove(outputs[p].domain); ++ } ++ ++ kfree(outputs); ++ ++ return -ENOMEM; ++} ++ + static int __init realtek_rtl_of_init(struct device_node *node, struct device_node *parent) + { ++ int parent_irqs[RTL_ICTL_NUM_OUTPUTS]; + struct of_phandle_args oirq; +- struct irq_domain *domain; ++ unsigned int num_parents; + unsigned int soc_irq; +- int parent_irq; ++ unsigned int p; ++ int cpu; ++ ++ cpumask_clear(&realtek_ictl_cpu_configurable); + +- realtek_ictl_base = of_iomap(node, 0); +- if (!realtek_ictl_base) ++ for (cpu = 0; cpu < NR_CPUS; cpu++) { ++ realtek_ictl_base[cpu] = of_iomap(node, cpu); ++ if (realtek_ictl_base[cpu]) { ++ cpumask_set_cpu(cpu, &realtek_ictl_cpu_configurable); ++ ++ /* Disable all cascaded interrupts and clear routing */ ++ for (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) { ++ write_irr(REG(RTL_ICTL_IRR0, cpu), soc_irq, 0); ++ realtek_ictl_unmask[cpu] &= ~BIT(soc_irq); ++ disable_gimr(soc_irq, cpu); ++ } ++ } ++ } ++ ++ if (cpumask_empty(&realtek_ictl_cpu_configurable)) + return -ENXIO; + +- /* Disable all cascaded interrupts and clear routing */ +- writel(0, REG(RTL_ICTL_GIMR)); +- for (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) +- write_irr(REG(RTL_ICTL_IRR0), soc_irq, 0); ++ num_parents = of_irq_count(node); ++ if (num_parents > RTL_ICTL_NUM_OUTPUTS) { ++ pr_err("too many parent interrupts\n"); ++ return -EINVAL; ++ } + +- if (WARN_ON(!of_irq_count(node))) { ++ for (p = 0; p < num_parents; p++) ++ parent_irqs[p] = of_irq_get(node, p); ++ ++ if (WARN_ON(!num_parents)) { + /* + * If DT contains no parent interrupts, assume MIPS CPU IRQ 2 + * (HW0) is connected to the first output. This is the case for + * all known hardware anyway. "interrupt-map" is deprecated, so + * don't bother trying to parse that. ++ * Since this is to account for old devicetrees with one-cell ++ * interrupt specifiers, only one output domain is needed. + */ + oirq.np = of_find_compatible_node(NULL, NULL, "mti,cpu-interrupt-controller"); +- oirq.args_count = 1; +- oirq.args[0] = 2; +- +- parent_irq = irq_create_of_mapping(&oirq); ++ if (oirq.np) { ++ oirq.args_count = 1; ++ oirq.args[0] = 2; ++ ++ parent_irqs[0] = irq_create_of_mapping(&oirq); ++ num_parents = 1; ++ } + + of_node_put(oirq.np); +- } else { +- parent_irq = of_irq_get(node, 0); + } + +- if (parent_irq < 0) +- return parent_irq; +- else if (!parent_irq) +- return -ENODEV; +- +- domain = irq_domain_add_linear(node, RTL_ICTL_NUM_INPUTS, &irq_domain_ops, NULL); +- if (!domain) +- return -ENOMEM; +- +- irq_set_chained_handler_and_data(parent_irq, realtek_irq_dispatch, domain); ++ /* Ensure we haven't collected any errors before proceeding */ ++ for (p = 0; p < num_parents; p++) { ++ if (parent_irqs[p] < 0) ++ return parent_irqs[p]; ++ if (!parent_irqs[p]) ++ return -ENODEV; ++ } + +- return 0; ++ return setup_parent_interrupts(node, &parent_irqs[0], num_parents); + } + + IRQCHIP_DECLARE(realtek_rtl_intc, "realtek,rtl-intc", realtek_rtl_of_init); diff --git a/target/linux/realtek/patches-6.12/318-add-rtl83xx-clk-support.patch b/target/linux/realtek/patches-6.12/318-add-rtl83xx-clk-support.patch new file mode 100644 index 0000000000..2a580e670c --- /dev/null +++ b/target/linux/realtek/patches-6.12/318-add-rtl83xx-clk-support.patch @@ -0,0 +1,33 @@ +From 800d5fb3c6a16661932c932bacd660e38d06b727 Mon Sep 17 00:00:00 2001 +From: Markus Stockhausen +Date: Thu, 25 Aug 2022 08:22:36 +0200 +Subject: [PATCH] realtek: add patch to enable new clock driver in kernel + +Allow building the clock driver with kernel config options. + +Submitted-by: Markus Stockhausen +--- + drivers/clk/Kconfig | 1 + + drivers/clk/Makefile | 1 + + 2 files changed, 2 insertions(+) + +--- a/drivers/clk/Kconfig ++++ b/drivers/clk/Kconfig +@@ -491,6 +491,7 @@ source "drivers/clk/mvebu/Kconfig" + source "drivers/clk/nuvoton/Kconfig" + source "drivers/clk/pistachio/Kconfig" + source "drivers/clk/qcom/Kconfig" ++source "drivers/clk/realtek/Kconfig" + source "drivers/clk/ralink/Kconfig" + source "drivers/clk/renesas/Kconfig" + source "drivers/clk/rockchip/Kconfig" +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -122,6 +122,7 @@ obj-$(CONFIG_COMMON_CLK_PISTACHIO) += pi + obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ + obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ + obj-y += ralink/ ++obj-$(CONFIG_COMMON_CLK_REALTEK) += realtek/ + obj-y += renesas/ + obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ + obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ diff --git a/target/linux/realtek/patches-6.12/330-add-realtek-thernal-driver.patch b/target/linux/realtek/patches-6.12/330-add-realtek-thernal-driver.patch new file mode 100644 index 0000000000..ab466ba6d2 --- /dev/null +++ b/target/linux/realtek/patches-6.12/330-add-realtek-thernal-driver.patch @@ -0,0 +1,22 @@ +--- a/drivers/thermal/Kconfig ++++ b/drivers/thermal/Kconfig +@@ -499,4 +499,11 @@ config LOONGSON2_THERMAL + is higher than the high temperature threshold or lower than the low + temperature threshold, the interrupt will occur. + ++config REALTEK_THERMAL ++ tristate "Realtek RTL838x and RTL930x thermal sensor support" ++ depends on RTL838X || RTL839X || RTL930X || RTL960X || COMPILE_TEST ++ depends on THERMAL_OF ++ help ++ Support thermal sensor in Realtek RTL838x, RTL839x, RTL930x and RTL960x SoCs ++ + endif +--- a/drivers/thermal/Makefile ++++ b/drivers/thermal/Makefile +@@ -63,4 +63,5 @@ obj-$(CONFIG_AMLOGIC_THERMAL) += aml + obj-$(CONFIG_SPRD_THERMAL) += sprd_thermal.o + obj-$(CONFIG_KHADAS_MCU_FAN_THERMAL) += khadas_mcu_fan.o + obj-$(CONFIG_LOONGSON2_THERMAL) += loongson2_thermal.o ++obj-$(CONFIG_REALTEK_THERMAL) += realtek-thermal.o + obj-$(CONFIG_THERMAL_CORE_TESTING) += testing/ diff --git a/target/linux/realtek/patches-6.12/700-dsa-mdio-increase-max-ports-for-rtl839x-rtl931x.patch b/target/linux/realtek/patches-6.12/700-dsa-mdio-increase-max-ports-for-rtl839x-rtl931x.patch new file mode 100644 index 0000000000..5f7e96358a --- /dev/null +++ b/target/linux/realtek/patches-6.12/700-dsa-mdio-increase-max-ports-for-rtl839x-rtl931x.patch @@ -0,0 +1,152 @@ +From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 26 Nov 2020 12:02:21 +0100 +Subject: realtek dsa/phy: Increase max ports for RTL839X/RTL931X + +Linux standard can only support up to 32 devices per mdio bus and up to +12 ports per DSA switch. This is not enough for the large RTL839X and +RTL931X devices. Increase the max values accordingly. Additionally take +care about the functions that work on bit masks. + +Submitted-by: Bert Vermeulen +Submitted-by: Birger Koblitz +Submitted-by: Sander Vanheule +Submitted-by: Bjørn Mork +Submitted-by: John Crispin +Signed-off-by: Markus Stockhausen +--- + drivers/net/mdio/fwnode_mdio.c | 2 +- + include/linux/phy.h | 6 +++--- + include/linux/platform_data/dsa.h | 2 +- + include/net/dsa.h | 14 +++++++------- + net/dsa/slave.c | 4 ++-- + 5 files changed, 14 insertions(+), 14 deletions(-) + +--- a/drivers/net/mdio/fwnode_mdio.c ++++ b/drivers/net/mdio/fwnode_mdio.c +@@ -90,7 +90,7 @@ int fwnode_mdiobus_phy_device_register(s + } + + if (fwnode_property_read_bool(child, "broken-turn-around")) +- mdio->phy_ignore_ta_mask |= 1 << addr; ++ mdio->phy_ignore_ta_mask |= BIT_ULL(addr); + + fwnode_property_read_u32(child, "reset-assert-us", + &phy->mdio.reset_assert_delay); +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -311,7 +311,7 @@ static inline const char *phy_modes(phy_ + #define PHY_INIT_TIMEOUT 100000 + #define PHY_FORCE_TIMEOUT 10 + +-#define PHY_MAX_ADDR 32 ++#define PHY_MAX_ADDR 64 + + /* Used when trying to connect to a specific phy (mii bus id:phy device id) */ + #define PHY_ID_FMT "%s:%02x" +@@ -431,10 +431,10 @@ struct mii_bus { + struct mdio_device *mdio_map[PHY_MAX_ADDR]; + + /** @phy_mask: PHY addresses to be ignored when probing */ +- u32 phy_mask; ++ u64 phy_mask; + + /** @phy_ignore_ta_mask: PHY addresses to ignore the TA/read failure */ +- u32 phy_ignore_ta_mask; ++ u64 phy_ignore_ta_mask; + + /** + * @irq: An array of interrupts, each PHY's interrupt at the index +--- a/include/linux/platform_data/dsa.h ++++ b/include/linux/platform_data/dsa.h +@@ -6,7 +6,7 @@ struct device; + struct net_device; + + #define DSA_MAX_SWITCHES 4 +-#define DSA_MAX_PORTS 12 ++#define DSA_MAX_PORTS 54 + #define DSA_RTABLE_NONE -1 + + struct dsa_chip_data { +--- a/include/net/dsa.h ++++ b/include/net/dsa.h +@@ -480,7 +480,7 @@ struct dsa_switch { + /* + * User mii_bus and devices for the individual ports. + */ +- u32 phys_mii_mask; ++ u64 phys_mii_mask; + struct mii_bus *user_mii_bus; + + /* Ageing Time limits in msecs */ +@@ -616,24 +616,24 @@ static inline bool dsa_is_user_port(stru + dsa_switch_for_each_port_continue_reverse((_dp), (_ds)) \ + if (dsa_port_is_cpu((_dp))) + +-static inline u32 dsa_user_ports(struct dsa_switch *ds) ++static inline u64 dsa_user_ports(struct dsa_switch *ds) + { + struct dsa_port *dp; +- u32 mask = 0; ++ u64 mask = 0; + + dsa_switch_for_each_user_port(dp, ds) +- mask |= BIT(dp->index); ++ mask |= BIT_ULL(dp->index); + + return mask; + } + +-static inline u32 dsa_cpu_ports(struct dsa_switch *ds) ++static inline u64 dsa_cpu_ports(struct dsa_switch *ds) + { + struct dsa_port *cpu_dp; +- u32 mask = 0; ++ u64 mask = 0; + + dsa_switch_for_each_cpu_port(cpu_dp, ds) +- mask |= BIT(cpu_dp->index); ++ mask |= BIT_ULL(cpu_dp->index); + + return mask; + } +--- a/net/dsa/user.c ++++ b/net/dsa/user.c +@@ -320,7 +320,7 @@ static int dsa_user_phy_read(struct mii_ + { + struct dsa_switch *ds = bus->priv; + +- if (ds->phys_mii_mask & (1 << addr)) ++ if (ds->phys_mii_mask & BIT_ULL(addr)) + return ds->ops->phy_read(ds, addr, reg); + + return 0xffff; +@@ -330,7 +330,7 @@ static int dsa_user_phy_write(struct mii + { + struct dsa_switch *ds = bus->priv; + +- if (ds->phys_mii_mask & (1 << addr)) ++ if (ds->phys_mii_mask & BIT_ULL(addr)) + return ds->ops->phy_write(ds, addr, reg, val); + + return 0; +--- a/drivers/net/phy/mdio_bus.c ++++ b/drivers/net/phy/mdio_bus.c +@@ -615,7 +615,7 @@ static int mdiobus_scan_bus_c22(struct m + int i; + + for (i = 0; i < PHY_MAX_ADDR; i++) { +- if ((bus->phy_mask & BIT(i)) == 0) { ++ if ((bus->phy_mask & BIT_ULL(i)) == 0ULL) { + struct phy_device *phydev; + + phydev = mdiobus_scan_c22(bus, i); +@@ -631,7 +631,7 @@ static int mdiobus_scan_bus_c45(struct m + int i; + + for (i = 0; i < PHY_MAX_ADDR; i++) { +- if ((bus->phy_mask & BIT(i)) == 0) { ++ if ((bus->phy_mask & BIT_ULL(i)) == 0ULL) { + struct phy_device *phydev; + + /* Don't scan C45 if we already have a C22 device */ diff --git a/target/linux/realtek/patches-6.12/712-net-phy-add-an-MDIO-SMBus-library.patch b/target/linux/realtek/patches-6.12/712-net-phy-add-an-MDIO-SMBus-library.patch new file mode 100644 index 0000000000..aede3cf638 --- /dev/null +++ b/target/linux/realtek/patches-6.12/712-net-phy-add-an-MDIO-SMBus-library.patch @@ -0,0 +1,428 @@ +From d585c55b9f70cf9e8c66820d7efe7130c683f19e Mon Sep 17 00:00:00 2001 +From: Antoine Tenart +Date: Fri, 21 Feb 2020 11:51:27 +0100 +Subject: [PATCH 2/3] net: phy: add an MDIO SMBus library + +Signed-off-by: Antoine Tenart +--- + drivers/net/mdio/Kconfig | 11 +++++++ + drivers/net/mdio/Makefile | 1 + + drivers/net/mdio/mdio-smbus.c | 62 +++++++++++++++++++++++++++++++++++ + drivers/net/phy/Kconfig | 1 + + include/linux/mdio/mdio-i2c.h | 16 +++++++++ + 5 files changed, 91 insertions(+) + create mode 100644 drivers/net/mdio/mdio-smbus.c + +--- a/drivers/net/mdio/Kconfig ++++ b/drivers/net/mdio/Kconfig +@@ -54,6 +54,17 @@ config MDIO_SUN4I + interface units of the Allwinner SoC that have an EMAC (A10, + A12, A10s, etc.) + ++config MDIO_SMBUS ++ tristate ++ depends on I2C_SMBUS ++ help ++ Support SMBus based PHYs. This provides a MDIO bus bridged ++ to SMBus to allow PHYs connected in SMBus mode to be accessed ++ using the existing infrastructure. ++ ++ This is library mode. ++ ++ + config MDIO_XGENE + tristate "APM X-Gene SoC MDIO bus controller" + depends on ARCH_XGENE || COMPILE_TEST +--- a/drivers/net/mdio/Makefile ++++ b/drivers/net/mdio/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-ms + obj-$(CONFIG_MDIO_MVUSB) += mdio-mvusb.o + obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o + obj-$(CONFIG_MDIO_REGMAP) += mdio-regmap.o ++obj-$(CONFIG_MDIO_SMBUS) += mdio-smbus.o + obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o + obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o + obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o +--- /dev/null ++++ b/drivers/net/mdio/mdio-smbus.c +@@ -0,0 +1,341 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * MDIO SMBus bridge ++ * ++ * Copyright (C) 2020 Antoine Tenart ++ * Copyright (C) 2025 Bjørn Mork ++ * ++ * Network PHYs can appear on SMBus when they are part of SFP modules. ++ */ ++#include ++#include ++#include ++#include ++ ++static int smbus_mii_read_c45(struct mii_bus *mii, int phy_id, int devad, int reg) ++{ ++ u16 bus_addr = i2c_mii_phy_addr(phy_id); ++ struct i2c_adapter *i2c = mii->priv; ++ union i2c_smbus_data data; ++ size_t addrlen; ++ u8 buf[5], *p; ++ int i, ret; ++ ++ if (!i2c_mii_valid_phy_id(phy_id)) ++ return 0xffff; ++ ++ p = buf; ++ if (devad >= 0) { ++ *p++ = 0x20 | devad; ++ *p++ = reg >> 8; ++ } ++ *p++ = reg; ++ addrlen = p - buf; ++ ++ i2c_lock_bus(i2c, I2C_LOCK_SEGMENT); ++ if (addrlen > 1) { ++ for (i = 1; i < addrlen; i++) { ++ data.byte = buf[i]; ++ ret = __i2c_smbus_xfer(i2c, bus_addr, 0, I2C_SMBUS_WRITE, buf[0], I2C_SMBUS_BYTE_DATA, &data); ++ if (ret < 0) ++ goto unlock; ++ } ++ } ++ ++ for (i = addrlen; i < addrlen + 2; i++) { ++ ret = __i2c_smbus_xfer(i2c, bus_addr, 0, I2C_SMBUS_READ, buf[0], I2C_SMBUS_BYTE_DATA, &data); ++ if (ret < 0) ++ goto unlock; ++ buf[i] = data.byte; ++ } ++ ++unlock: ++ i2c_unlock_bus(i2c, I2C_LOCK_SEGMENT); ++ if (ret < 0) ++ return 0xffff; ++ return buf[addrlen] << 8 | buf[addrlen + 1]; ++} ++ ++static int smbus_mii_write_c45(struct mii_bus *mii, int phy_id, int devad, int reg, u16 val) ++{ ++ u16 bus_addr = i2c_mii_phy_addr(phy_id); ++ struct i2c_adapter *i2c = mii->priv; ++ union i2c_smbus_data data; ++ size_t buflen; ++ u8 buf[5], *p; ++ int i, ret; ++ ++ if (!i2c_mii_valid_phy_id(phy_id)) ++ return 0; ++ ++ p = buf; ++ if (devad >= 0) { ++ *p++ = devad; ++ *p++ = reg >> 8; ++ } ++ *p++ = reg; ++ *p++ = val >> 8; ++ *p++ = val; ++ buflen = p - buf; ++ ++ i2c_lock_bus(i2c, I2C_LOCK_SEGMENT); ++ for (i = 1; i < buflen; i++) { ++ data.byte = buf[i]; ++ ret = __i2c_smbus_xfer(i2c, bus_addr, 0, I2C_SMBUS_WRITE, buf[0], I2C_SMBUS_BYTE_DATA, &data); ++ if (ret < 0) ++ goto unlock; ++ } ++unlock: ++ i2c_unlock_bus(i2c, I2C_LOCK_SEGMENT); ++ return ret < 0 ? ret : 0; ++} ++ ++static int smbus_mii_read_c22(struct mii_bus *bus, int phy_id, int reg) ++{ ++ return smbus_mii_read_c45(bus, phy_id, -1, reg); ++} ++ ++static int smbus_mii_write_c22(struct mii_bus *bus, int phy_id, int reg, u16 val) ++{ ++ return smbus_mii_write_c45(bus, phy_id, -1, reg, val); ++} ++ ++/* From mdio-i2c.c: ++ * ++ * RollBall SFPs do not access internal PHY via I2C address 0x56, but ++ * instead via address 0x51, when SFP page is set to 0x03 and password to ++ * 0xffffffff. ++ * ++ * address size contents description ++ * ------- ---- -------- ----------- ++ * 0x80 1 CMD 0x01/0x02/0x04 for write/read/done ++ * 0x81 1 DEV Clause 45 device ++ * 0x82 2 REG Clause 45 register ++ * 0x84 2 VAL Register value ++ */ ++#define ROLLBALL_PHY_I2C_ADDR 0x51 ++ ++#define ROLLBALL_PASSWORD (SFP_VSL + 3) ++ ++#define ROLLBALL_CMD_ADDR 0x80 ++#define ROLLBALL_DATA_ADDR 0x81 ++ ++#define ROLLBALL_CMD_WRITE 0x01 ++#define ROLLBALL_CMD_READ 0x02 ++#define ROLLBALL_CMD_DONE 0x04 ++ ++#define SFP_PAGE_ROLLBALL_MDIO 3 ++ ++static int smbus_set_sfp_page_lock(struct i2c_adapter *i2c, int bus_addr, u8 page) ++{ ++ union i2c_smbus_data data; ++ u8 oldpage; ++ int ret; ++ ++ i2c_lock_bus(i2c, I2C_LOCK_SEGMENT); ++ ++ /* read current page */ ++ ret = __i2c_smbus_xfer(i2c, bus_addr, 0, I2C_SMBUS_READ, SFP_PAGE, I2C_SMBUS_BYTE_DATA, &data); ++ if (ret < 0) ++ goto unlock; ++ ++ oldpage = data.byte; ++ data.byte = page; ++ ret = __i2c_smbus_xfer(i2c, bus_addr, 0, I2C_SMBUS_WRITE, SFP_PAGE, I2C_SMBUS_BYTE_DATA, &data); ++ if (ret == 0) ++ return oldpage; ++ ++unlock: ++ i2c_unlock_bus(i2c, I2C_LOCK_SEGMENT); ++ ++ return ret; ++} ++ ++static int __smbus_set_sfp_page_unlock(struct i2c_adapter *i2c, int bus_addr, u8 page) ++{ ++ union i2c_smbus_data data; ++ int ret; ++ ++ data.byte = page; ++ ret = __i2c_smbus_xfer(i2c, bus_addr, 0, I2C_SMBUS_WRITE, SFP_PAGE, I2C_SMBUS_BYTE_DATA, &data); ++ i2c_unlock_bus(i2c, I2C_LOCK_SEGMENT); ++ ++ return ret; ++} ++ ++/* Wait for the ROLLBALL_CMD_ADDR register to read ROLLBALL_CMD_DONE, ++ * indicating that the previous command has completed. ++ * ++ * Quoting from the mdio-i2c.c implementation: ++ * ++ * By experiment it takes up to 70 ms to access a register for these ++ * SFPs. Sleep 20ms between iterations and try 10 times. ++ */ ++static int __smbus_rollball_mii_poll(struct i2c_adapter *i2c , int bus_addr) ++{ ++ union i2c_smbus_data data; ++ int i, ret; ++ ++ i = 10; ++ do { ++ msleep(20); ++ ++ ret = __i2c_smbus_xfer(i2c, bus_addr, 0, I2C_SMBUS_READ, ROLLBALL_CMD_ADDR, I2C_SMBUS_BYTE_DATA, &data); ++ if (ret < 0) ++ return ret; ++ ++ if (data.byte == ROLLBALL_CMD_DONE) ++ return 0; ++ } while (i-- > 0); ++ dev_dbg(&i2c->dev, "poll timed out\n"); ++ return -ETIMEDOUT; ++} ++ ++static int smbus_mii_read_rollball(struct mii_bus *bus, int phy_id, int devad, int reg) ++{ ++ struct i2c_adapter *i2c = bus->priv; ++ union i2c_smbus_data data; ++ int i, bus_addr, old, ret; ++ u8 buf[6]; ++ ++ bus_addr = i2c_mii_phy_addr(phy_id); ++ if (bus_addr != ROLLBALL_PHY_I2C_ADDR) ++ return 0xffff; ++ ++ old = smbus_set_sfp_page_lock(i2c, bus_addr, SFP_PAGE_ROLLBALL_MDIO); ++ if (old < 0) ++ return 0xffff; ++ ++ /* set address */ ++ buf[0] = ROLLBALL_CMD_READ; ++ buf[1] = devad; ++ buf[2] = reg >> 8; ++ buf[3] = reg & 0xff; ++ ++ /* send address */ ++ for (i = 0; i < 4; i++) { ++ data.byte = buf[i]; ++ ret = __i2c_smbus_xfer(i2c, bus_addr, 0, I2C_SMBUS_WRITE, ROLLBALL_CMD_ADDR + i, I2C_SMBUS_BYTE_DATA, &data); ++ if (ret < 0) ++ goto unlock; ++ } ++ ++ /* wait for command to complete */ ++ ret = __smbus_rollball_mii_poll(i2c, bus_addr); ++ if (ret) ++ goto unlock; ++ ++ /* read result */ ++ for (i = 4; i < 6; i++) { ++ ret = __i2c_smbus_xfer(i2c, bus_addr, 0, I2C_SMBUS_READ, ROLLBALL_CMD_ADDR + i, I2C_SMBUS_BYTE_DATA, &data); ++ if (ret < 0) ++ goto unlock; ++ buf[i] = data.byte; ++ } ++ ++unlock: ++ __smbus_set_sfp_page_unlock(i2c, bus_addr, old); ++ if (ret < 0) ++ return 0xffff; ++ return buf[4] << 8 | buf[5]; ++} ++ ++static int smbus_mii_write_rollball(struct mii_bus *bus, int phy_id, int devad, int reg, u16 val) ++{ ++ struct i2c_adapter *i2c = bus->priv; ++ union i2c_smbus_data data; ++ int i, bus_addr, old, ret; ++ u8 buf[6]; ++ ++ bus_addr = i2c_mii_phy_addr(phy_id); ++ if (bus_addr != ROLLBALL_PHY_I2C_ADDR) ++ return 0; ++ ++ old = smbus_set_sfp_page_lock(i2c, bus_addr, SFP_PAGE_ROLLBALL_MDIO); ++ if (old < 0) ++ return old; ++ ++ /* set address */ ++ buf[0] = ROLLBALL_CMD_WRITE; ++ buf[1] = devad; ++ buf[2] = reg >> 8; ++ buf[3] = reg & 0xff; ++ buf[4] = val >> 8; ++ buf[5] = val & 0xff; ++ ++ /* send address and value */ ++ for (i = 0; i < 6; i++) { ++ data.byte = buf[i]; ++ ret = __i2c_smbus_xfer(i2c, bus_addr, 0, I2C_SMBUS_WRITE, ROLLBALL_CMD_ADDR + i, I2C_SMBUS_BYTE_DATA, &data); ++ if (ret < 0) ++ goto unlock; ++ } ++ ++ /* wait for command to complete */ ++ ret = __smbus_rollball_mii_poll(i2c, bus_addr); ++ ++unlock: ++ __smbus_set_sfp_page_unlock(i2c, bus_addr, old); ++ return ret; ++} ++ ++/* write "password" - four 0xff bytes - to the ROLLBALL_PASSWORD register */ ++static int smbus_mii_init_rollball(struct i2c_adapter *i2c) ++{ ++ union i2c_smbus_data data; ++ int i, ret; ++ ++ data.byte = 0xff; ++ for (i = 0; i < 4; i++) { ++ ret = i2c_smbus_xfer(i2c, ROLLBALL_PHY_I2C_ADDR, 0, I2C_SMBUS_WRITE, ROLLBALL_PASSWORD + i, I2C_SMBUS_BYTE_DATA, &data); ++ if (ret < 0) ++ return ret; ++ } ++ return 0; ++} ++ ++struct mii_bus *mdio_smbus_alloc(struct device *parent, struct i2c_adapter *i2c, ++ enum mdio_i2c_proto protocol) ++{ ++ struct mii_bus *mii; ++ int ret; ++ ++ if (!i2c_check_functionality(i2c, I2C_FUNC_SMBUS_BYTE_DATA)) ++ return ERR_PTR(-EINVAL); ++ ++ mii = mdiobus_alloc(); ++ if (!mii) ++ return ERR_PTR(-ENOMEM); ++ ++ snprintf(mii->id, MII_BUS_ID_SIZE, "smbus:%s", dev_name(parent)); ++ mii->parent = parent; ++ mii->priv = i2c; ++ ++ switch (protocol) { ++ case MDIO_I2C_ROLLBALL: ++ ret = smbus_mii_init_rollball(i2c); ++ if (ret < 0) { ++ dev_err(parent, ++ "Cannot initialize RollBall MDIO protocol on SMBus: %d\n", ++ ret); ++ mdiobus_free(mii); ++ return ERR_PTR(ret); ++ } ++ ++ mii->read_c45 = smbus_mii_read_rollball; ++ mii->write_c45 = smbus_mii_write_rollball; ++ break; ++ default: ++ mii->read = smbus_mii_read_c22; ++ mii->write = smbus_mii_write_c22; ++ mii->read_c45 = smbus_mii_read_c45; ++ mii->write_c45 = smbus_mii_write_c45; ++ break; ++ } ++ ++ return mii; ++} ++ ++MODULE_AUTHOR("Antoine Tenart"); ++MODULE_DESCRIPTION("MDIO SMBus bridge library"); ++MODULE_LICENSE("GPL"); +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -76,6 +76,7 @@ config SFP + depends on I2C && PHYLINK + depends on HWMON || HWMON=n + select MDIO_I2C ++ select MDIO_SMBUS + + comment "Switch configuration API + drivers" + +--- a/include/linux/mdio/mdio-i2c.h ++++ b/include/linux/mdio/mdio-i2c.h +@@ -20,5 +20,9 @@ enum mdio_i2c_proto { + + struct mii_bus *mdio_i2c_alloc(struct device *parent, struct i2c_adapter *i2c, + enum mdio_i2c_proto protocol); ++struct mii_bus *mdio_smbus_alloc(struct device *parent, struct i2c_adapter *i2c, ++ enum mdio_i2c_proto protocol); ++bool i2c_mii_valid_phy_id(int phy_id); ++unsigned int i2c_mii_phy_addr(int phy_id); + + #endif +--- a/drivers/net/mdio/mdio-i2c.c ++++ b/drivers/net/mdio/mdio-i2c.c +@@ -20,12 +20,12 @@ + * specified to be present in SFP modules. These correspond with PHY + * addresses 16 and 17. Disallow access to these "phy" addresses. + */ +-static bool i2c_mii_valid_phy_id(int phy_id) ++bool i2c_mii_valid_phy_id(int phy_id) + { + return phy_id != 0x10 && phy_id != 0x11; + } + +-static unsigned int i2c_mii_phy_addr(int phy_id) ++unsigned int i2c_mii_phy_addr(int phy_id) + { + return phy_id + 0x40; + } diff --git a/target/linux/realtek/patches-6.12/714-net-phy-sfp-add-support-for-SMBus.patch b/target/linux/realtek/patches-6.12/714-net-phy-sfp-add-support-for-SMBus.patch new file mode 100644 index 0000000000..b6c56b300a --- /dev/null +++ b/target/linux/realtek/patches-6.12/714-net-phy-sfp-add-support-for-SMBus.patch @@ -0,0 +1,126 @@ +From 3cb0bde365d913c484d20224367a54a0eac780a7 Mon Sep 17 00:00:00 2001 +From: Antoine Tenart +Date: Fri, 21 Feb 2020 11:55:29 +0100 +Subject: [PATCH 3/3] net: phy: sfp: add support for SMBus + +Signed-off-by: Antoine Tenart +--- + drivers/net/phy/sfp.c | 92 +++++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 88 insertions(+), 4 deletions(-) + +--- a/drivers/net/phy/sfp.c ++++ b/drivers/net/phy/sfp.c +@@ -729,10 +729,64 @@ static int sfp_i2c_write(struct sfp *sfp + return ret == ARRAY_SIZE(msgs) ? len : 0; + } + ++static int sfp_smbus_read(struct sfp *sfp, bool a2, u8 dev_addr, void *buf, ++ size_t len) ++{ ++ u8 bus_addr = a2 ? 0x51 : 0x50, *val = buf; ++ union i2c_smbus_data data; ++ int ret; ++ ++ bus_addr -= 0x40; ++ ++ while (len > 0) { ++ ret = i2c_smbus_xfer(sfp->i2c, i2c_mii_phy_addr(bus_addr), 0, ++ I2C_SMBUS_READ, dev_addr, ++ I2C_SMBUS_BYTE_DATA, &data); ++ if (ret) ++ return ret; ++ *val++ = data.byte; ++ dev_addr++; ++ len--; ++ } ++ ++ return val - (u8 *)buf; ++} ++ ++static int sfp_smbus_write(struct sfp *sfp, bool a2, u8 dev_addr, void *buf, ++ size_t len) ++{ ++ u8 bus_addr = a2 ? 0x51 : 0x50, *val = buf; ++ union i2c_smbus_data data; ++ int ret; ++ ++ bus_addr -= 0x40; ++ ++ while (len > 0) { ++ data.byte = *val++; ++ ret = i2c_smbus_xfer(sfp->i2c, i2c_mii_phy_addr(bus_addr), 0, ++ I2C_SMBUS_WRITE, dev_addr, ++ I2C_SMBUS_BYTE_DATA, &data); ++ if (ret) ++ return ret; ++ dev_addr++; ++ len--; ++ } ++ ++ return val - (u8 *)buf; ++} ++ + static int sfp_i2c_configure(struct sfp *sfp, struct i2c_adapter *i2c) + { +- if (!i2c_check_functionality(i2c, I2C_FUNC_I2C)) +- return -EINVAL; ++ if (!i2c_check_functionality(i2c, I2C_FUNC_I2C)) { ++ if (i2c_check_functionality(i2c, I2C_FUNC_SMBUS_BYTE_DATA)) { ++ sfp->i2c = i2c; ++ sfp->read = sfp_smbus_read; ++ sfp->write = sfp_smbus_write; ++ ++ return 0; ++ } else ++ return -EINVAL; ++ } + + sfp->i2c = i2c; + sfp->read = sfp_i2c_read; +@@ -764,6 +818,29 @@ static int sfp_i2c_mdiobus_create(struct + return 0; + } + ++static int sfp_sm_mdiobus_create(struct sfp *sfp) ++{ ++ struct mii_bus *sm_mii; ++ int ret; ++ ++ sm_mii = mdio_smbus_alloc(sfp->dev, sfp->i2c, sfp->mdio_protocol); ++ if (IS_ERR(sm_mii)) ++ return PTR_ERR(sm_mii); ++ ++ sm_mii->name = "SFP SMBus"; ++ sm_mii->phy_mask = ~0; ++ ++ ret = mdiobus_register(sm_mii); ++ if (ret < 0) { ++ mdiobus_free(sm_mii); ++ return ret; ++ } ++ ++ sfp->i2c_mii = sm_mii; ++ ++ return 0; ++} ++ + static void sfp_i2c_mdiobus_destroy(struct sfp *sfp) + { + mdiobus_unregister(sfp->i2c_mii); +@@ -1938,9 +2015,15 @@ static void sfp_sm_fault(struct sfp *sfp + + static int sfp_sm_add_mdio_bus(struct sfp *sfp) + { +- if (sfp->mdio_protocol != MDIO_I2C_NONE) ++ if (sfp->mdio_protocol == MDIO_I2C_NONE) ++ return 0; ++ ++ if (i2c_check_functionality(sfp->i2c, I2C_FUNC_I2C)) + return sfp_i2c_mdiobus_create(sfp); + ++ if (i2c_check_functionality(sfp->i2c, I2C_FUNC_SMBUS_BYTE_DATA)) ++ return sfp_sm_mdiobus_create(sfp); ++ + return 0; + } + diff --git a/target/linux/realtek/patches-6.12/716-net-ethernet-add-support-for-rtl838x-ethernet.patch b/target/linux/realtek/patches-6.12/716-net-ethernet-add-support-for-rtl838x-ethernet.patch new file mode 100644 index 0000000000..3d7529074d --- /dev/null +++ b/target/linux/realtek/patches-6.12/716-net-ethernet-add-support-for-rtl838x-ethernet.patch @@ -0,0 +1,48 @@ +From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 26 Nov 2020 12:02:21 +0100 +Subject: net: ethernet: Add support for RTL838x ethernet + +* rename the target to realtek +* add refactored DSA driver +* add latest gpio driver +* lots of arch cleanups +* new irq driver +* additional boards + +Submitted-by: Bert Vermeulen +Submitted-by: Birger Koblitz +Submitted-by: Sander Vanheule +Submitted-by: Bjørn Mork +Submitted-by: John Crispin +--- + drivers/net/ethernet/Kconfig | 7 +- + drivers/net/ethernet/Makefile | 1 + + 2 files changed, 8 insertions(+) + +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -179,6 +179,13 @@ source "drivers/net/ethernet/rdc/Kconfig + source "drivers/net/ethernet/realtek/Kconfig" + source "drivers/net/ethernet/renesas/Kconfig" + source "drivers/net/ethernet/rocker/Kconfig" ++ ++config NET_RTL838X ++ tristate "Realtek rtl838x Ethernet MAC support" ++ depends on MACH_REALTEK_RTL ++ help ++ Say Y here if you want to use the Realtek rtl838x Gbps Ethernet MAC. ++ + source "drivers/net/ethernet/samsung/Kconfig" + source "drivers/net/ethernet/seeq/Kconfig" + source "drivers/net/ethernet/sgi/Kconfig" +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -82,6 +82,7 @@ obj-$(CONFIG_NET_VENDOR_REALTEK) += real + obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/ + obj-$(CONFIG_NET_VENDOR_RDC) += rdc/ + obj-$(CONFIG_NET_VENDOR_ROCKER) += rocker/ ++obj-$(CONFIG_NET_RTL838X) += rtl838x_eth.o + obj-$(CONFIG_NET_VENDOR_SAMSUNG) += samsung/ + obj-$(CONFIG_NET_VENDOR_SEEQ) += seeq/ + obj-$(CONFIG_NET_VENDOR_SILAN) += silan/ diff --git a/target/linux/realtek/patches-6.12/718-net-dsa-add-support-for-rtl838x-switch.patch b/target/linux/realtek/patches-6.12/718-net-dsa-add-support-for-rtl838x-switch.patch new file mode 100644 index 0000000000..dc261efe36 --- /dev/null +++ b/target/linux/realtek/patches-6.12/718-net-dsa-add-support-for-rtl838x-switch.patch @@ -0,0 +1,42 @@ +From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 26 Nov 2020 12:02:21 +0100 +Subject: net: dsa: Add support for rtl838x switch + +* rename the target to realtek +* add refactored DSA driver +* add latest gpio driver +* lots of arch cleanups +* new irq driver +* additional boards + +Submitted-by: Bert Vermeulen +Submitted-by: Birger Koblitz +Submitted-by: Sander Vanheule +Submitted-by: Bjørn Mork +Submitted-by: John Crispin +--- + drivers/net/dsa/rtl83xx/Kconfig | 2 ++ + drivers/net/dsa/rtl83xx/Makefile | 1 + + 2 files changed, 3 insertions(+) + +--- a/drivers/net/dsa/Kconfig ++++ b/drivers/net/dsa/Kconfig +@@ -91,6 +91,8 @@ source "drivers/net/dsa/xrs700x/Kconfig" + + source "drivers/net/dsa/realtek/Kconfig" + ++source "drivers/net/dsa/rtl83xx/Kconfig" ++ + config NET_DSA_RZN1_A5PSW + tristate "Renesas RZ/N1 A5PSW Ethernet switch support" + depends on OF && ARCH_RZN1 +--- a/drivers/net/dsa/Makefile ++++ b/drivers/net/dsa/Makefile +@@ -26,5 +26,6 @@ obj-y += mxl862xx/ + obj-y += ocelot/ + obj-y += qca/ + obj-y += realtek/ ++obj-y += rtl83xx/ + obj-y += sja1105/ + obj-y += xrs700x/ diff --git a/target/linux/realtek/patches-6.12/720-add-rtl-phy.patch b/target/linux/realtek/patches-6.12/720-add-rtl-phy.patch new file mode 100644 index 0000000000..d82bb64e9a --- /dev/null +++ b/target/linux/realtek/patches-6.12/720-add-rtl-phy.patch @@ -0,0 +1,41 @@ +From 89f71ebb355c624320c2b0ace8ae9488ff53cbeb Mon Sep 17 00:00:00 2001 +From: Birger Koblitz +Date: Tue, 5 Jan 2021 20:40:52 +0100 +Subject: PHY: Add realtek PHY + +This fixes the build problems for the REALTEK target by adding a proper +configuration option for the phy module. + +Submitted-by: Birger Koblitz +--- a/drivers/net/phy/realtek/Makefile ++++ b/drivers/net/phy/realtek/Makefile +@@ -2,3 +2,4 @@ + realtek-y += realtek_main.o + realtek-$(CONFIG_REALTEK_PHY_HWMON) += realtek_hwmon.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o ++obj-$(CONFIG_REALTEK_PHY_MULTIPORT) += realtek_multiport.o +--- a/drivers/net/phy/realtek/Kconfig ++++ b/drivers/net/phy/realtek/Kconfig +@@ -5,6 +5,11 @@ config REALTEK_PHY + help + Currently supports RTL821x/RTL822x and fast ethernet PHYs + ++config REALTEK_PHY_MULTIPORT ++ tristate "Realtek multiport PHYs" ++ help ++ Currently supports RTL8214x/RTL8218x gigabit multiport PHYs ++ + if REALTEK_PHY + + config REALTEK_PHY_HWMON +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -109,7 +109,7 @@ obj-$(CONFIG_NXP_CBTX_PHY) += nxp-cbtx.o + obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o + obj-y += qcom/ + obj-$(CONFIG_QSEMI_PHY) += qsemi.o +-obj-$(CONFIG_REALTEK_PHY) += realtek/ ++obj-y += realtek/ + obj-y += rtl8261n/ + obj-$(CONFIG_RENESAS_PHY) += uPD60620.o + obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o diff --git a/target/linux/realtek/patches-6.12/721-net-dsa-add-support-for-tag-rtl-otto.patch b/target/linux/realtek/patches-6.12/721-net-dsa-add-support-for-tag-rtl-otto.patch new file mode 100644 index 0000000000..d82a05edc2 --- /dev/null +++ b/target/linux/realtek/patches-6.12/721-net-dsa-add-support-for-tag-rtl-otto.patch @@ -0,0 +1,51 @@ +From: Markus Stockhausen +Date: Sun, 1 Feb 2026 10:40:52 +0100 +Subject: realtek: net: dsa: add suport for tag rtl-otto + +This adds the rtl-otto tag feature for Realtek switches. + +Signed-off-by: Markus Stockhausen + +--- a/net/dsa/Makefile ++++ b/net/dsa/Makefile +@@ -37,6 +37,7 @@ obj-$(CONFIG_NET_DSA_TAG_QCA) += tag_qca + obj-$(CONFIG_NET_DSA_TAG_RTL4_A) += tag_rtl4_a.o + obj-$(CONFIG_NET_DSA_TAG_RTL8_4) += tag_rtl8_4.o + obj-$(CONFIG_NET_DSA_TAG_RZN1_A5PSW) += tag_rzn1_a5psw.o ++obj-$(CONFIG_NET_DSA_TAG_RTL_OTTO) += tag_rtl_otto.o + obj-$(CONFIG_NET_DSA_TAG_SJA1105) += tag_sja1105.o + obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag_trailer.o + obj-$(CONFIG_NET_DSA_TAG_VSC73XX_8021Q) += tag_vsc73xx_8021q.o +--- a/net/dsa/Kconfig ++++ b/net/dsa/Kconfig +@@ -177,6 +177,12 @@ config NET_DSA_TAG_LAN9303 + Say Y or M if you want to enable support for tagging frames for the + SMSC/Microchip LAN9303 family of switches. + ++config NET_DSA_TAG_RTL_OTTO ++ tristate "Tag driver for Realtek Otto switches (RTL83xx/RTL93xx)" ++ help ++ Say Y or M if you want to enable support for tagging frames for the ++ Realtek Otto family of switches. ++ + config NET_DSA_TAG_SJA1105 + tristate "Tag driver for NXP SJA1105 switches" + select PACKING +--- a/include/net/dsa.h ++++ b/include/net/dsa.h +@@ -57,6 +57,7 @@ struct tc_action; + #define DSA_TAG_PROTO_BRCM_LEGACY_FCS_VALUE 29 + #define DSA_TAG_PROTO_MXL862_VALUE 30 + #define DSA_TAG_PROTO_MXL862_8021Q_VALUE 31 ++#define DSA_TAG_PROTO_RTL_OTTO_VALUE 32 + + + enum dsa_tag_protocol { +@@ -92,6 +93,7 @@ enum dsa_tag_protocol { + DSA_TAG_PROTO_VSC73XX_8021Q = DSA_TAG_PROTO_VSC73XX_8021Q_VALUE, + DSA_TAG_PROTO_MXL862 = DSA_TAG_PROTO_MXL862_VALUE, + DSA_TAG_PROTO_MXL862_8021Q = DSA_TAG_PROTO_MXL862_8021Q_VALUE, ++ DSA_TAG_PROTO_RTL_OTTO = DSA_TAG_PROTO_RTL_OTTO_VALUE, + }; + + struct dsa_switch; diff --git a/target/linux/realtek/patches-6.12/723-net-mdio-Add-Realtek-Otto-auxiliary-controller.patch b/target/linux/realtek/patches-6.12/723-net-mdio-Add-Realtek-Otto-auxiliary-controller.patch new file mode 100644 index 0000000000..ac6cb1bc20 --- /dev/null +++ b/target/linux/realtek/patches-6.12/723-net-mdio-Add-Realtek-Otto-auxiliary-controller.patch @@ -0,0 +1,239 @@ +From ffb7da9aa25765b2115e7ff3ee4f6dafa60f5421 Mon Sep 17 00:00:00 2001 +From: Sander Vanheule +Date: Fri, 27 Dec 2024 14:55:31 +0100 +Subject: [PATCH] net: mdio: Add Realtek Otto auxiliary controller + +SoCs in Realtek's Otto platform such as the RTL8380, RTL8391, and +RTL9302 have a simple auxiliary MDIO controller that is commonly used to +manage RTL8231 GPIO expanders on switch devices. + +Add a new MDIO controller driver supporting the RTL838x (maple), RTL839x +(cypress), and RTL930x (longan) SoCs. + +Signed-off-by: Sander Vanheule +--- + drivers/net/mdio/Kconfig | 10 ++ + drivers/net/mdio/Makefile | 1 + + drivers/net/mdio/mdio-realtek-otto-aux.c | 175 +++++++++++++++++++++++ + 3 files changed, 186 insertions(+) + create mode 100644 drivers/net/mdio/mdio-realtek-otto-aux.c + +--- a/drivers/net/mdio/Kconfig ++++ b/drivers/net/mdio/Kconfig +@@ -207,6 +207,16 @@ config MDIO_REGMAP + regmap. Users willing to use this driver must explicitly select + REGMAP. + ++config MDIO_REALTEK_OTTO_AUX ++ tristate "Realtek Otto auxiliary MDIO interface support" ++ default MACH_REALTEK_RTL ++ depends on MACH_REALTEK_RTL ++ depends on MFD_SYSCON ++ select MDIO_DEVRES ++ help ++ This driver supports the auxilairy MDIO bus on RTL838x SoCs. This bus ++ is typically used to attach RTL8231 GPIO extenders. ++ + config MDIO_THUNDER + tristate "ThunderX SOCs MDIO buses" + depends on 64BIT +--- a/drivers/net/mdio/Makefile ++++ b/drivers/net/mdio/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-ms + obj-$(CONFIG_MDIO_MVUSB) += mdio-mvusb.o + obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o + obj-$(CONFIG_MDIO_REGMAP) += mdio-regmap.o ++obj-$(CONFIG_MDIO_REALTEK_OTTO_AUX) += mdio-realtek-otto-aux.o + obj-$(CONFIG_MDIO_SMBUS) += mdio-smbus.o + obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o + obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o +--- /dev/null ++++ b/drivers/net/mdio/mdio-realtek-otto-aux.c +@@ -0,0 +1,187 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RTL8380_EXT_GPIO_INDIRECT_ACCESS 0xA09C ++#define RTL8390_EXT_GPIO_INDIRECT_ACCESS 0x0224 ++#define RTL9300_EXT_GPIO_INDIRECT_ACCESS 0xC620 ++#define RTL9310_EXT_GPIO_INDIRECT_ACCESS 0x07F4 ++ ++#define RTL83XX_AUX_MDIO_DATA_OFFSET 16 ++#define RTL83XX_AUX_MDIO_RCMD_FAIL 0 ++ ++#define RTL93XX_AUX_MDIO_DATA_OFFSET 12 ++#define RTL93XX_AUX_MDIO_RCMD_FAIL BIT(28) ++ ++#define REALTEK_AUX_MDIO_REG GENMASK(11, 7) ++#define REALTEK_AUX_MDIO_PHY_ADDR GENMASK(6, 2) ++#define REALTEK_AUX_MDIO_WRITE BIT(1) ++#define REALTEK_AUX_MDIO_READ 0 ++#define REALTEK_AUX_MDIO_EXEC BIT(0) ++ ++struct realtek_aux_mdio_info { ++ unsigned int cmd_reg; ++ unsigned int data_offset; ++ unsigned int rcmd_fail_mask; ++ unsigned int timeout_us; ++}; ++ ++static const struct realtek_aux_mdio_info info_rtl838x = { ++ .cmd_reg = RTL8380_EXT_GPIO_INDIRECT_ACCESS, ++ .data_offset = RTL83XX_AUX_MDIO_DATA_OFFSET, ++ .rcmd_fail_mask = RTL83XX_AUX_MDIO_RCMD_FAIL, ++ .timeout_us = 1700, ++}; ++ ++static const struct realtek_aux_mdio_info info_rtl839x = { ++ .cmd_reg = RTL8390_EXT_GPIO_INDIRECT_ACCESS, ++ .data_offset = RTL83XX_AUX_MDIO_DATA_OFFSET, ++ .rcmd_fail_mask = RTL83XX_AUX_MDIO_RCMD_FAIL, ++ .timeout_us = 4120, ++}; ++ ++static const struct realtek_aux_mdio_info info_rtl930x = { ++ .cmd_reg = RTL9300_EXT_GPIO_INDIRECT_ACCESS, ++ .data_offset = RTL93XX_AUX_MDIO_DATA_OFFSET, ++ .rcmd_fail_mask = RTL93XX_AUX_MDIO_RCMD_FAIL, ++ .timeout_us = 19000, ++}; ++ ++static const struct realtek_aux_mdio_info info_rtl931x = { ++ .cmd_reg = RTL9310_EXT_GPIO_INDIRECT_ACCESS, ++ .data_offset = RTL93XX_AUX_MDIO_DATA_OFFSET, ++ .rcmd_fail_mask = RTL93XX_AUX_MDIO_RCMD_FAIL, ++ .timeout_us = 19000, ++}; ++ ++struct realtek_aux_mdio_ctrl { ++ struct device *dev; ++ struct regmap *map; ++ const struct realtek_aux_mdio_info *info; ++}; ++ ++#define mii_bus_to_ctrl(bus) ((struct realtek_aux_mdio_ctrl *) bus->priv) ++ ++static int realtek_aux_mdio_cmd(struct realtek_aux_mdio_ctrl *ctrl, int addr, int regnum, ++ u32 rw_bit, u16 *data) ++{ ++ unsigned int cmd; ++ int err; ++ ++ cmd = rw_bit | REALTEK_AUX_MDIO_EXEC; ++ cmd |= FIELD_PREP(REALTEK_AUX_MDIO_PHY_ADDR, addr); ++ cmd |= FIELD_PREP(REALTEK_AUX_MDIO_REG, regnum); ++ ++ if (rw_bit == REALTEK_AUX_MDIO_WRITE) ++ cmd |= *data << ctrl->info->data_offset; ++ ++ err = regmap_write(ctrl->map, ctrl->info->cmd_reg, cmd); ++ if (err) ++ return err; ++ ++ err = regmap_read_poll_timeout_atomic(ctrl->map, ctrl->info->cmd_reg, cmd, ++ !(cmd & REALTEK_AUX_MDIO_EXEC), 3, ctrl->info->timeout_us); ++ if (err) ++ return err; ++ ++ if (rw_bit == REALTEK_AUX_MDIO_READ) { ++ if (cmd & ctrl->info->rcmd_fail_mask) ++ return -EIO; ++ ++ *data = (cmd >> ctrl->info->data_offset) & GENMASK(15, 0); ++ } ++ ++ return 0; ++} ++ ++static int realtek_aux_mdio_read(struct mii_bus *bus, int addr, int regnum) ++{ ++ struct realtek_aux_mdio_ctrl *ctrl = mii_bus_to_ctrl(bus); ++ u16 data; ++ int err; ++ ++ err = realtek_aux_mdio_cmd(ctrl, addr, regnum, REALTEK_AUX_MDIO_READ, &data); ++ ++ if (err) ++ return err; ++ else ++ return data; ++} ++ ++static int realtek_aux_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) ++{ ++ struct realtek_aux_mdio_ctrl *ctrl = mii_bus_to_ctrl(bus); ++ ++ return realtek_aux_mdio_cmd(ctrl, addr, regnum, REALTEK_AUX_MDIO_WRITE, &val); ++} ++ ++static int realtek_aux_mdio_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct realtek_aux_mdio_ctrl *ctrl; ++ struct mii_bus *bus; ++ ++ bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*ctrl)); ++ if (!bus) ++ return -ENOMEM; ++ ++ ctrl = bus->priv; ++ ctrl->dev = &pdev->dev; ++ ctrl->info = (const struct realtek_aux_mdio_info *) device_get_match_data(ctrl->dev); ++ ctrl->map = syscon_node_to_regmap(np->parent); ++ if (IS_ERR(ctrl->map)) ++ return PTR_ERR(ctrl->map); ++ ++ bus->name = "Realtek auxiliary MDIO bus"; ++ snprintf(bus->id, MII_BUS_ID_SIZE, "realtek-aux-mdio") ; ++ bus->parent = ctrl->dev; ++ bus->read = realtek_aux_mdio_read; ++ bus->write = realtek_aux_mdio_write; ++ /* Don't have interrupts */ ++ for (unsigned int i = 0; i < PHY_MAX_ADDR; i++) ++ bus->irq[i] = PHY_POLL; ++ ++ return devm_of_mdiobus_register(ctrl->dev, bus, np); ++} ++ ++static const struct of_device_id realtek_aux_mdio_of_match[] = { ++ { ++ .compatible = "realtek,rtl8380-aux-mdio", ++ .data = &info_rtl838x, ++ }, ++ { ++ .compatible = "realtek,rtl8390-aux-mdio", ++ .data = &info_rtl839x, ++ }, ++ { ++ .compatible = "realtek,rtl9300-aux-mdio", ++ .data = &info_rtl930x, ++ }, ++ { ++ .compatible = "realtek,rtl9310-aux-mdio", ++ .data = &info_rtl931x, ++ }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, realtek_aux_mdio_of_match); ++ ++static struct platform_driver realtek_aux_mdio_driver = { ++ .driver = { ++ .name = "realtek-otto-aux-mdio", ++ .of_match_table = realtek_aux_mdio_of_match ++ }, ++ .probe = realtek_aux_mdio_probe, ++}; ++module_platform_driver(realtek_aux_mdio_driver); ++ ++MODULE_AUTHOR("Sander Vanheule "); ++MODULE_DESCRIPTION("Realtek otto auxiliary MDIO bus"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/realtek/patches-6.12/730-add-pcs-rtl-otto.patch b/target/linux/realtek/patches-6.12/730-add-pcs-rtl-otto.patch new file mode 100644 index 0000000000..27927bd891 --- /dev/null +++ b/target/linux/realtek/patches-6.12/730-add-pcs-rtl-otto.patch @@ -0,0 +1,37 @@ +From ad75da9aaa8765b2115e7b40ee4f6dbcd60c3321 Mon Sep 17 00:00:00 2001 +From: Markus Stockhausen +Date: Weg, 17 Sep 2025 20:23:31 +0200 +Subject: [PATCH] net: pcs: Add Realtek Otto SerDes controller + +SoCs in Realtek's Otto platform such as the RTL83xx and RTL93xx +have multiple SerDes to drive the PHYs. Provide a PCS driver +to configure them. + +Signed-off-by: Markus Stockhausen +--- +--- a/drivers/net/pcs/Kconfig ++++ b/drivers/net/pcs/Kconfig +@@ -36,6 +36,14 @@ config PCS_MTK_USXGMII + 1000Base-X, 2500Base-X and Cisco SGMII are supported on the same + differential pairs via an embedded LynxI PHY. + ++config PCS_RTL_OTTO ++ tristate "Realtek Otto SerDes PCS" ++ depends on MACH_REALTEK_RTL || COMPILE_TEST ++ select PHYLINK ++ select REGMAP ++ help ++ This module provides a driver for the Realtek SerDes PCS ++ + config PCS_RZN1_MIIC + tristate "Renesas RZ/N1 MII converter" + depends on OF && (ARCH_RZN1 || COMPILE_TEST) +--- a/drivers/net/pcs/Makefile ++++ b/drivers/net/pcs/Makefile +@@ -7,5 +7,6 @@ pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs. + obj-$(CONFIG_PCS_XPCS) += pcs_xpcs.o + obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o + obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o ++obj-$(CONFIG_PCS_RTL_OTTO) += pcs-rtl-otto.o + obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o + obj-$(CONFIG_PCS_MTK_USXGMII) += pcs-mtk-usxgmii.o diff --git a/target/linux/realtek/patches-6.12/740-net-phy-realtek-support-MDI-swapping-for-RTL8226.patch b/target/linux/realtek/patches-6.12/740-net-phy-realtek-support-MDI-swapping-for-RTL8226.patch new file mode 100644 index 0000000000..63540be15a --- /dev/null +++ b/target/linux/realtek/patches-6.12/740-net-phy-realtek-support-MDI-swapping-for-RTL8226.patch @@ -0,0 +1,190 @@ +From 672a9bfb2e01ecaf40e5b92e9cc564589ffc251d Mon Sep 17 00:00:00 2001 +From: Jan Hoffmann +Date: Tue, 23 Dec 2025 20:07:53 +0100 +Subject: [PATCH] net: phy: realtek: support MDI swapping for RTL8226 + +Add support for configuring swapping of MDI pairs (ABCD->DCBA) when the +property "enet-phy-pair-order" is specified. + +Unfortunately, no documentation about this feature is available, so the +configuration involves magic values. Only enabling MDI swapping is +supported, as it is unknown whether the patching step can be safely +reversed. + +For now, only implement it for RTL8226, where it is needed to make the +PHYs in Zyxel XGS1010-12 rev A1 work. However, parts of this code might +also be useful for other PHYs in the future: + +RTL8221B also allows to configure MDI swapping via the same register, +but does not need the additional patching step. Since it also supports +configuration via strapping pins, there might not be any need for driver +support on that PHY, though. + +The patching step itself seems to be the same which is also used by the +integrated PHY of some Realtek PCIe/USB NICs. + +Signed-off-by: Jan Hoffmann +--- + drivers/net/phy/realtek/realtek_main.c | 159 ++++++++++++++++++++++++- + 1 file changed, 158 insertions(+), 1 deletion(-) + +--- a/drivers/net/phy/realtek/realtek_main.c ++++ b/drivers/net/phy/realtek/realtek_main.c +@@ -1489,6 +1489,148 @@ static unsigned int rtl822x_inband_caps( + } + } + ++static int rtl8226_set_mdi_swap(struct phy_device *phydev, bool swap_enable) ++{ ++ u16 val = swap_enable ? BIT(5) : 0; ++ ++ return phy_modify_mmd(phydev, MDIO_MMD_VEND1, 0x6a21, BIT(5), val); ++} ++ ++static int rtl8226_patch_mdi_swap(struct phy_device *phydev) ++{ ++ int ret; ++ u16 vals[4]; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xd068); ++ if (ret < 0) ++ return ret; ++ ++ if (!(ret & BIT(1))) { ++ /* already swapped */ ++ return 0; ++ } ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xd068, 0x7, 0x1); ++ if (ret < 0) ++ return ret; ++ ++ /* swap adccal_offset */ ++ ++ for (int i = 0; i < 4; i++) { ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xd068, 0x3 << 3, i << 3); ++ if (ret < 0) ++ return ret; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xd06a); ++ if (ret < 0) ++ return ret; ++ ++ vals[i] = ret; ++ } ++ ++ for (int i = 0; i < 4; i++) { ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xd068, 0x3 << 3, i << 3); ++ if (ret < 0) ++ return ret; ++ ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xd06a, vals[3 - i]); ++ if (ret < 0) ++ return ret; ++ } ++ ++ /* swap rg_lpf_cap_xg */ ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xbd5a); ++ if (ret < 0) ++ return ret; ++ ++ vals[0] = ret & 0x1f; ++ vals[1] = (ret >> 8) & 0x1f; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xbd5c); ++ if (ret < 0) ++ return ret; ++ ++ vals[2] = ret & 0x1f; ++ vals[3] = (ret >> 8) & 0x1f; ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xbd5a, 0x1f1f, ++ vals[3] | (vals[2] << 8)); ++ if (ret < 0) ++ return ret; ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xbd5c, 0x1f1f, ++ vals[1] | (vals[0] << 8)); ++ if (ret < 0) ++ return ret; ++ ++ /* swap rg_lpf_cap */ ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xbc18); ++ if (ret < 0) ++ return ret; ++ ++ vals[0] = ret & 0x1f; ++ vals[1] = (ret >> 8) & 0x1f; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xbc1a); ++ if (ret < 0) ++ return ret; ++ ++ vals[2] = ret & 0x1f; ++ vals[3] = (ret >> 8) & 0x1f; ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xbc18, 0x1f1f, ++ vals[3] | (vals[2] << 8)); ++ if (ret < 0) ++ return ret; ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xbc1a, 0x1f1f, ++ vals[1] | (vals[0] << 8)); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++static int rtl8226_config_mdi_order(struct phy_device *phydev) ++{ ++ u32 order; ++ int ret; ++ ++ ret = of_property_read_u32(phydev->mdio.dev.of_node, "enet-phy-pair-order", &order); ++ ++ /* Property not present, nothing to do */ ++ if (ret == -EINVAL) ++ return 0; ++ ++ if (ret) ++ return ret; ++ ++ /* Only enabling MDI swapping is supported */ ++ if (order != 1) ++ return -EINVAL; ++ ++ ret = rtl8226_set_mdi_swap(phydev, true); ++ if (ret) ++ return ret; ++ ++ ret = rtl8226_patch_mdi_swap(phydev); ++ return ret; ++} ++ ++static int rtl8226_config_init(struct phy_device *phydev) ++{ ++ int ret; ++ ++ ret = rtl8226_config_mdi_order(phydev); ++ if (ret) ++ return ret; ++ ++ return rtl822x_config_init(phydev); ++} ++ ++ + static int rtl822xb_get_rate_matching(struct phy_device *phydev, + phy_interface_t iface) + { +@@ -2452,7 +2594,7 @@ static struct phy_driver realtek_drvs[] + .soft_reset = rtl822x_c45_soft_reset, + .get_features = rtl822x_c45_get_features, + .config_aneg = rtl822x_c45_config_aneg, +- .config_init = rtl822x_config_init, ++ .config_init = rtl8226_config_init, + .inband_caps = rtl822x_inband_caps, + .config_inband = rtl822x_config_inband, + .read_status = rtl822xb_c45_read_status, diff --git a/target/linux/realtek/patches-6.12/800-gpio-regmap-Bypass-cache-for-shadowed-outputs.patch b/target/linux/realtek/patches-6.12/800-gpio-regmap-Bypass-cache-for-shadowed-outputs.patch new file mode 100644 index 0000000000..fd73b162f8 --- /dev/null +++ b/target/linux/realtek/patches-6.12/800-gpio-regmap-Bypass-cache-for-shadowed-outputs.patch @@ -0,0 +1,56 @@ +From b3f79468c90d8770f007d628a1e32b2d5d44a5c2 Mon Sep 17 00:00:00 2001 +From: Sander Vanheule +Date: Sat, 15 May 2021 11:57:32 +0200 +Subject: [PATCH] gpio: regmap: Bypass cache for shadowed outputs + +Some chips have the read-only input and write-only output data registers +aliased to the same offset, but do not perform direction multiplexing on +writes. Upon writing the register, this then always updates the output +value, even when the pin is configured as input. As a result it is not +safe to perform read-modify-writes on output pins, when other pins are +still configured as input. + +For example, on a bit-banged I2C bus, where the lines are switched +between out-low and in (with external pull-up) + + OUT(L) IN OUT(H) +SCK ....../''''''|'''''' + +SDA '''''''''\.......... + ^ ^- SCK switches to direction to OUT, but now has a high + | value, breaking the clock. + | + \- Perform RMW to update SDA. This reads the current input + value for SCK, updates the SDA value and writes back a 1 + for SCK as well. + +If a register is used for both the data input and data output (and is +not marked as volatile) the driver should ensure the cache is not +updated on register reads. This ensures proper functioning of writing +the output register with regmap_update_bits(), which will then use and +update the cache only on register writes. + +Signed-off-by: Sander Vanheule +--- + drivers/gpio/gpio-regmap.c | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +--- a/drivers/gpio/gpio-regmap.c ++++ b/drivers/gpio/gpio-regmap.c +@@ -80,7 +80,15 @@ static int gpio_regmap_get(struct gpio_c + if (ret) + return ret; + +- ret = regmap_read(gpio->regmap, reg, &val); ++ /* ++ * Ensure we don't spoil the register cache with pin input values and ++ * perform a bypassed read. This way the cache (if any) is only used and ++ * updated on register writes. ++ */ ++ if (gpio->reg_dat_base == gpio->reg_set_base) ++ ret = regmap_read_bypassed(gpio->regmap, reg, &val); ++ else ++ ret = regmap_read(gpio->regmap, reg, &val); + if (ret) + return ret; + diff --git a/target/linux/realtek/patches-6.12/802-mfd-Add-RTL8231-core-device.patch b/target/linux/realtek/patches-6.12/802-mfd-Add-RTL8231-core-device.patch new file mode 100644 index 0000000000..2a6be8e456 --- /dev/null +++ b/target/linux/realtek/patches-6.12/802-mfd-Add-RTL8231-core-device.patch @@ -0,0 +1,330 @@ +From 4e3455e058d40eb2a7326016494e3c81dc506c33 Mon Sep 17 00:00:00 2001 +From: Sander Vanheule +Date: Mon, 10 May 2021 18:33:01 +0200 +Subject: [PATCH] mfd: Add RTL8231 core device + +The RTL8231 is implemented as an MDIO device, and provides a regmap +interface for register access by the core and child devices. + +The chip can also be a device on an SMI bus, an I2C-like bus by Realtek. +Since kernel support for SMI is limited, and no real-world SMI +implementations have been encountered for this device, this is currently +unimplemented. The use of the regmap interface should make any future +support relatively straightforward. + +After reset, all pins are muxed to GPIO inputs before the pin drivers +are enabled. This is done to prevent accidental system resets, when a +pin is connected to the parent SoC's reset line. + +To provide different read and write semantics for the GPIO data +registers, a secondary virtual register range is used to enable separate +caching properties of pin input and output values. + +Signed-off-by: Sander Vanheule +--- + drivers/mfd/Kconfig | 9 ++ + drivers/mfd/Makefile | 1 + + drivers/mfd/rtl8231.c | 193 ++++++++++++++++++++++++++++++++++++ + include/linux/mfd/rtl8231.h | 71 +++++++++++++ + 4 files changed, 274 insertions(+) + create mode 100644 drivers/mfd/rtl8231.c + create mode 100644 include/linux/mfd/rtl8231.h + +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -1219,6 +1219,15 @@ config MFD_RDC321X + southbridge which provides access to GPIOs and Watchdog using the + southbridge PCI device configuration space. + ++config MFD_RTL8231 ++ tristate "Realtek RTL8231 GPIO and LED expander" ++ select MFD_CORE ++ select REGMAP_MDIO ++ help ++ Support for the Realtek RTL8231 GPIO and LED expander. ++ Provides up to 37 GPIOs, 88 LEDs, and one PWM output. ++ When built as a module, this module will be named rtl8231. ++ + config MFD_RT4831 + tristate "Richtek RT4831 four channel WLED and Display Bias Voltage" + depends on I2C +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -246,6 +246,7 @@ obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421- + obj-$(CONFIG_MFD_HI6421_SPMI) += hi6421-spmi-pmic.o + obj-$(CONFIG_MFD_HI655X_PMIC) += hi655x-pmic.o + obj-$(CONFIG_MFD_DLN2) += dln2.o ++obj-$(CONFIG_MFD_RTL8231) += rtl8231.o + obj-$(CONFIG_MFD_RT4831) += rt4831.o + obj-$(CONFIG_MFD_RT5033) += rt5033.o + obj-$(CONFIG_MFD_RT5120) += rt5120.o +--- /dev/null ++++ b/drivers/mfd/rtl8231.c +@@ -0,0 +1,193 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++static bool rtl8231_volatile_reg(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ /* ++ * Registers with self-clearing bits, strapping pin values. ++ * Don't mark the data registers as volatile, since we need ++ * caching for the output values. ++ */ ++ case RTL8231_REG_FUNC0: ++ case RTL8231_REG_FUNC1: ++ case RTL8231_REG_PIN_HI_CFG: ++ case RTL8231_REG_LED_END: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++static const struct reg_field RTL8231_FIELD_LED_START = REG_FIELD(RTL8231_REG_FUNC0, 1, 1); ++ ++static const struct mfd_cell rtl8231_cells[] = { ++ { ++ .name = "rtl8231-pinctrl", ++ }, ++ { ++ .name = "rtl8231-leds", ++ .of_compatible = "realtek,rtl8231-leds", ++ }, ++}; ++ ++static int rtl8231_soft_reset(struct regmap *map) ++{ ++ const unsigned int all_pins_mask = GENMASK(RTL8231_BITS_VAL - 1, 0); ++ unsigned int val; ++ int err; ++ ++ /* SOFT_RESET bit self-clears when done */ ++ regmap_write_bits(map, RTL8231_REG_PIN_HI_CFG, ++ RTL8231_PIN_HI_CFG_SOFT_RESET, RTL8231_PIN_HI_CFG_SOFT_RESET); ++ err = regmap_read_poll_timeout(map, RTL8231_REG_PIN_HI_CFG, val, ++ !(val & RTL8231_PIN_HI_CFG_SOFT_RESET), 50, 1000); ++ if (err) ++ return err; ++ ++ regcache_mark_dirty(map); ++ ++ /* ++ * Chip reset results in a pin configuration that is a mix of LED and GPIO outputs. ++ * Select GPI functionality for all pins before enabling pin outputs. ++ */ ++ regmap_write(map, RTL8231_REG_PIN_MODE0, all_pins_mask); ++ regmap_write(map, RTL8231_REG_GPIO_DIR0, all_pins_mask); ++ regmap_write(map, RTL8231_REG_PIN_MODE1, all_pins_mask); ++ regmap_write(map, RTL8231_REG_GPIO_DIR1, all_pins_mask); ++ regmap_write(map, RTL8231_REG_PIN_HI_CFG, ++ RTL8231_PIN_HI_CFG_MODE_MASK | RTL8231_PIN_HI_CFG_DIR_MASK); ++ ++ return 0; ++} ++ ++static int rtl8231_init(struct device *dev, struct regmap *map) ++{ ++ struct regmap_field *led_start; ++ unsigned int started; ++ unsigned int val; ++ int err; ++ ++ err = regmap_read(map, RTL8231_REG_FUNC1, &val); ++ if (err) { ++ dev_err(dev, "failed to read READY_CODE\n"); ++ return err; ++ } ++ ++ val = FIELD_GET(RTL8231_FUNC1_READY_CODE_MASK, val); ++ if (val != RTL8231_FUNC1_READY_CODE_VALUE) { ++ dev_err(dev, "RTL8231 not present or ready 0x%x != 0x%x\n", ++ val, RTL8231_FUNC1_READY_CODE_VALUE); ++ return -ENODEV; ++ } ++ ++ led_start = dev_get_drvdata(dev); ++ err = regmap_field_read(led_start, &started); ++ if (err) ++ return err; ++ ++ if (!started) { ++ err = rtl8231_soft_reset(map); ++ if (err) ++ return err; ++ /* LED_START enables power to output pins, and starts the LED engine */ ++ err = regmap_field_force_write(led_start, 1); ++ } ++ ++ return err; ++} ++ ++static const struct regmap_config rtl8231_mdio_regmap_config = { ++ .val_bits = RTL8231_BITS_VAL, ++ .reg_bits = RTL8231_BITS_REG, ++ .volatile_reg = rtl8231_volatile_reg, ++ .max_register = RTL8231_REG_COUNT - 1, ++ .use_single_read = true, ++ .use_single_write = true, ++ .reg_format_endian = REGMAP_ENDIAN_BIG, ++ .val_format_endian = REGMAP_ENDIAN_BIG, ++ /* Cannot use REGCACHE_FLAT because it's not smart enough about cache invalidation */ ++ .cache_type = REGCACHE_RBTREE, ++}; ++ ++static int rtl8231_mdio_probe(struct mdio_device *mdiodev) ++{ ++ struct device *dev = &mdiodev->dev; ++ struct regmap_field *led_start; ++ struct regmap *map; ++ int err; ++ ++ map = devm_regmap_init_mdio(mdiodev, &rtl8231_mdio_regmap_config); ++ if (IS_ERR(map)) { ++ dev_err(dev, "failed to init regmap\n"); ++ return PTR_ERR(map); ++ } ++ ++ led_start = devm_regmap_field_alloc(dev, map, RTL8231_FIELD_LED_START); ++ if (IS_ERR(led_start)) ++ return PTR_ERR(led_start); ++ ++ dev_set_drvdata(dev, led_start); ++ ++ mdiodev->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); ++ if (IS_ERR(mdiodev->reset_gpio)) ++ return PTR_ERR(mdiodev->reset_gpio); ++ ++ device_property_read_u32(dev, "reset-assert-delay", &mdiodev->reset_assert_delay); ++ device_property_read_u32(dev, "reset-deassert-delay", &mdiodev->reset_deassert_delay); ++ ++ err = rtl8231_init(dev, map); ++ if (err) ++ return err; ++ ++ return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, rtl8231_cells, ++ ARRAY_SIZE(rtl8231_cells), NULL, 0, NULL); ++} ++ ++__maybe_unused static int rtl8231_suspend(struct device *dev) ++{ ++ struct regmap_field *led_start = dev_get_drvdata(dev); ++ ++ return regmap_field_force_write(led_start, 0); ++} ++ ++__maybe_unused static int rtl8231_resume(struct device *dev) ++{ ++ struct regmap_field *led_start = dev_get_drvdata(dev); ++ ++ return regmap_field_force_write(led_start, 1); ++} ++ ++static SIMPLE_DEV_PM_OPS(rtl8231_pm_ops, rtl8231_suspend, rtl8231_resume); ++ ++static const struct of_device_id rtl8231_of_match[] = { ++ { .compatible = "realtek,rtl8231" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, rtl8231_of_match); ++ ++static struct mdio_driver rtl8231_mdio_driver = { ++ .mdiodrv.driver = { ++ .name = "rtl8231-expander", ++ .of_match_table = rtl8231_of_match, ++ .pm = pm_ptr(&rtl8231_pm_ops), ++ }, ++ .probe = rtl8231_mdio_probe, ++}; ++mdio_module_driver(rtl8231_mdio_driver); ++ ++MODULE_AUTHOR("Sander Vanheule "); ++MODULE_DESCRIPTION("Realtek RTL8231 GPIO and LED expander"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/include/linux/mfd/rtl8231.h +@@ -0,0 +1,71 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++/* ++ * Register definitions the RTL8231 GPIO and LED expander chip ++ */ ++ ++#ifndef __LINUX_MFD_RTL8231_H ++#define __LINUX_MFD_RTL8231_H ++ ++#include ++ ++/* ++ * Registers addresses are 5 bit, values are 16 bit ++ * Also define a duplicated range of virtual addresses, to enable ++ * different read/write behaviour on the GPIO data registers ++ */ ++#define RTL8231_BITS_VAL 16 ++#define RTL8231_BITS_REG 5 ++ ++/* Chip control */ ++#define RTL8231_REG_FUNC0 0x00 ++#define RTL8231_FUNC0_SCAN_MODE BIT(0) ++#define RTL8231_FUNC0_SCAN_SINGLE 0 ++#define RTL8231_FUNC0_SCAN_BICOLOR BIT(0) ++ ++#define RTL8231_REG_FUNC1 0x01 ++#define RTL8231_FUNC1_READY_CODE_VALUE 0x37 ++#define RTL8231_FUNC1_READY_CODE_MASK GENMASK(9, 4) ++#define RTL8231_FUNC1_DEBOUNCE_MASK GENMASK(15, 10) ++ ++/* Pin control */ ++#define RTL8231_REG_PIN_MODE0 0x02 ++#define RTL8231_REG_PIN_MODE1 0x03 ++ ++#define RTL8231_PIN_MODE_LED 0 ++#define RTL8231_PIN_MODE_GPIO 1 ++ ++/* Pin high config: pin and GPIO control for pins 32-26 */ ++#define RTL8231_REG_PIN_HI_CFG 0x04 ++#define RTL8231_PIN_HI_CFG_MODE_MASK GENMASK(4, 0) ++#define RTL8231_PIN_HI_CFG_DIR_MASK GENMASK(9, 5) ++#define RTL8231_PIN_HI_CFG_INV_MASK GENMASK(14, 10) ++#define RTL8231_PIN_HI_CFG_SOFT_RESET BIT(15) ++ ++/* GPIO control registers */ ++#define RTL8231_REG_GPIO_DIR0 0x05 ++#define RTL8231_REG_GPIO_DIR1 0x06 ++#define RTL8231_REG_GPIO_INVERT0 0x07 ++#define RTL8231_REG_GPIO_INVERT1 0x08 ++ ++#define RTL8231_GPIO_DIR_IN 1 ++#define RTL8231_GPIO_DIR_OUT 0 ++ ++/* ++ * GPIO data registers ++ * Only the output data can be written to these registers, and only the input ++ * data can be read. ++ */ ++#define RTL8231_REG_GPIO_DATA0 0x1c ++#define RTL8231_REG_GPIO_DATA1 0x1d ++#define RTL8231_REG_GPIO_DATA2 0x1e ++#define RTL8231_PIN_HI_DATA_MASK GENMASK(4, 0) ++ ++/* LED control base registers */ ++#define RTL8231_REG_LED0_BASE 0x09 ++#define RTL8231_REG_LED1_BASE 0x10 ++#define RTL8231_REG_LED2_BASE 0x17 ++#define RTL8231_REG_LED_END 0x1b ++ ++#define RTL8231_REG_COUNT 0x1f ++ ++#endif /* __LINUX_MFD_RTL8231_H */ diff --git a/target/linux/realtek/patches-6.12/803-pinctrl-Add-RTL8231-pin-control-and-GPIO-support.patch b/target/linux/realtek/patches-6.12/803-pinctrl-Add-RTL8231-pin-control-and-GPIO-support.patch new file mode 100644 index 0000000000..1b88dcd55c --- /dev/null +++ b/target/linux/realtek/patches-6.12/803-pinctrl-Add-RTL8231-pin-control-and-GPIO-support.patch @@ -0,0 +1,581 @@ +From 098324288a63a6dcc44e96cc381aef3d5c48d89e Mon Sep 17 00:00:00 2001 +From: Sander Vanheule +Date: Mon, 10 May 2021 22:15:31 +0200 +Subject: [PATCH] pinctrl: Add RTL8231 pin control and GPIO support + +This driver implements the GPIO and pin muxing features provided by the +RTL8231. The device should be instantiated as an MFD child, where the +parent device has already configured the regmap used for register +access. + +Debouncing is only available for the six highest GPIOs, and must be +emulated when other pins are used for (button) inputs. Although +described in the bindings, drive strength selection is currently not +implemented. + +Signed-off-by: Sander Vanheule +--- + drivers/pinctrl/Kconfig | 11 + + drivers/pinctrl/Makefile | 1 + + drivers/pinctrl/pinctrl-rtl8231.c | 521 ++++++++++++++++++++++++++++++ + 3 files changed, 533 insertions(+) + create mode 100644 drivers/pinctrl/pinctrl-rtl8231.c + +--- a/drivers/pinctrl/Kconfig ++++ b/drivers/pinctrl/Kconfig +@@ -483,6 +483,17 @@ config PINCTRL_SCMI + It uses SCMI Message Protocol to interact with the + firmware providing all the pinctrl controls. + ++config PINCTRL_RTL8231 ++ tristate "Realtek RTL8231 GPIO expander's pin controller" ++ depends on MFD_RTL8231 ++ default MFD_RTL8231 ++ select GPIO_REGMAP ++ select GENERIC_PINCONF ++ select GENERIC_PINMUX_FUNCTIONS ++ help ++ Support for RTL8231 expander's GPIOs and pin controller. ++ When built as a module, the module will be called pinctrl-rtl8231. ++ + config PINCTRL_SINGLE + tristate "One-register-per-pin type device tree based pinctrl driver" + depends on OF +--- a/drivers/pinctrl/Makefile ++++ b/drivers/pinctrl/Makefile +@@ -47,6 +47,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-p + obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o + obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o + obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o ++obj-$(CONFIG_PINCTRL_RTL8231) += pinctrl-rtl8231.o + obj-$(CONFIG_PINCTRL_SCMI) += pinctrl-scmi.o + obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o + obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o +--- /dev/null ++++ b/drivers/pinctrl/pinctrl-rtl8231.c +@@ -0,0 +1,525 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "core.h" ++#include "pinmux.h" ++#include ++ ++#define RTL8231_NUM_GPIOS 37 ++#define RTL8231_DEBOUNCE_USEC 100000 ++#define RTL8231_DEBOUNCE_MIN_OFFSET 31 ++ ++struct rtl8231_pin_ctrl { ++ struct pinctrl_desc pctl_desc; ++ struct regmap *map; ++}; ++ ++/* ++ * Pin controller functionality ++ */ ++static const char * const rtl8231_pin_function_names[] = { ++ "gpio", ++ "led", ++ "pwm", ++}; ++ ++enum rtl8231_pin_function { ++ RTL8231_PIN_FUNCTION_GPIO = BIT(0), ++ RTL8231_PIN_FUNCTION_LED = BIT(1), ++ RTL8231_PIN_FUNCTION_PWM = BIT(2), ++}; ++ ++struct rtl8231_pin_desc { ++ const enum rtl8231_pin_function functions; ++ const u8 reg; ++ const u8 offset; ++ const u8 gpio_function_value; ++}; ++ ++#define RTL8231_PIN_DESC(_num, _func, _reg, _fld, _val) \ ++ [_num] = { \ ++ .functions = RTL8231_PIN_FUNCTION_GPIO | _func, \ ++ .reg = _reg, \ ++ .offset = _fld, \ ++ .gpio_function_value = _val, \ ++ } ++#define RTL8231_GPIO_PIN_DESC(_num, _reg, _fld) \ ++ RTL8231_PIN_DESC(_num, 0, _reg, _fld, RTL8231_PIN_MODE_GPIO) ++#define RTL8231_LED_PIN_DESC(_num, _reg, _fld) \ ++ RTL8231_PIN_DESC(_num, RTL8231_PIN_FUNCTION_LED, _reg, _fld, RTL8231_PIN_MODE_GPIO) ++#define RTL8231_PWM_PIN_DESC(_num, _reg, _fld) \ ++ RTL8231_PIN_DESC(_num, RTL8231_PIN_FUNCTION_PWM, _reg, _fld, 0) ++ ++/* ++ * All pins have a GPIO/LED mux bit, but the bits for pins 35/36 are read-only. Use this bit ++ * for the GPIO-only pin instead of a placeholder, so the rest of the logic can stay generic. ++ */ ++static struct rtl8231_pin_desc rtl8231_pin_data[RTL8231_NUM_GPIOS] = { ++ RTL8231_LED_PIN_DESC(0, RTL8231_REG_PIN_MODE0, 0), ++ RTL8231_LED_PIN_DESC(1, RTL8231_REG_PIN_MODE0, 1), ++ RTL8231_LED_PIN_DESC(2, RTL8231_REG_PIN_MODE0, 2), ++ RTL8231_LED_PIN_DESC(3, RTL8231_REG_PIN_MODE0, 3), ++ RTL8231_LED_PIN_DESC(4, RTL8231_REG_PIN_MODE0, 4), ++ RTL8231_LED_PIN_DESC(5, RTL8231_REG_PIN_MODE0, 5), ++ RTL8231_LED_PIN_DESC(6, RTL8231_REG_PIN_MODE0, 6), ++ RTL8231_LED_PIN_DESC(7, RTL8231_REG_PIN_MODE0, 7), ++ RTL8231_LED_PIN_DESC(8, RTL8231_REG_PIN_MODE0, 8), ++ RTL8231_LED_PIN_DESC(9, RTL8231_REG_PIN_MODE0, 9), ++ RTL8231_LED_PIN_DESC(10, RTL8231_REG_PIN_MODE0, 10), ++ RTL8231_LED_PIN_DESC(11, RTL8231_REG_PIN_MODE0, 11), ++ RTL8231_LED_PIN_DESC(12, RTL8231_REG_PIN_MODE0, 12), ++ RTL8231_LED_PIN_DESC(13, RTL8231_REG_PIN_MODE0, 13), ++ RTL8231_LED_PIN_DESC(14, RTL8231_REG_PIN_MODE0, 14), ++ RTL8231_LED_PIN_DESC(15, RTL8231_REG_PIN_MODE0, 15), ++ RTL8231_LED_PIN_DESC(16, RTL8231_REG_PIN_MODE1, 0), ++ RTL8231_LED_PIN_DESC(17, RTL8231_REG_PIN_MODE1, 1), ++ RTL8231_LED_PIN_DESC(18, RTL8231_REG_PIN_MODE1, 2), ++ RTL8231_LED_PIN_DESC(19, RTL8231_REG_PIN_MODE1, 3), ++ RTL8231_LED_PIN_DESC(20, RTL8231_REG_PIN_MODE1, 4), ++ RTL8231_LED_PIN_DESC(21, RTL8231_REG_PIN_MODE1, 5), ++ RTL8231_LED_PIN_DESC(22, RTL8231_REG_PIN_MODE1, 6), ++ RTL8231_LED_PIN_DESC(23, RTL8231_REG_PIN_MODE1, 7), ++ RTL8231_LED_PIN_DESC(24, RTL8231_REG_PIN_MODE1, 8), ++ RTL8231_LED_PIN_DESC(25, RTL8231_REG_PIN_MODE1, 9), ++ RTL8231_LED_PIN_DESC(26, RTL8231_REG_PIN_MODE1, 10), ++ RTL8231_LED_PIN_DESC(27, RTL8231_REG_PIN_MODE1, 11), ++ RTL8231_LED_PIN_DESC(28, RTL8231_REG_PIN_MODE1, 12), ++ RTL8231_LED_PIN_DESC(29, RTL8231_REG_PIN_MODE1, 13), ++ RTL8231_LED_PIN_DESC(30, RTL8231_REG_PIN_MODE1, 14), ++ RTL8231_LED_PIN_DESC(31, RTL8231_REG_PIN_MODE1, 15), ++ RTL8231_LED_PIN_DESC(32, RTL8231_REG_PIN_HI_CFG, 0), ++ RTL8231_LED_PIN_DESC(33, RTL8231_REG_PIN_HI_CFG, 1), ++ RTL8231_LED_PIN_DESC(34, RTL8231_REG_PIN_HI_CFG, 2), ++ RTL8231_PWM_PIN_DESC(35, RTL8231_REG_FUNC1, 3), ++ RTL8231_GPIO_PIN_DESC(36, RTL8231_REG_PIN_HI_CFG, 4), ++}; ++ ++#define RTL8231_PIN(_num) \ ++ { \ ++ .number = _num, \ ++ .name = "gpio" #_num, \ ++ .drv_data = &rtl8231_pin_data[_num] \ ++ } ++ ++static const struct pinctrl_pin_desc rtl8231_pins[RTL8231_NUM_GPIOS] = { ++ RTL8231_PIN(0), ++ RTL8231_PIN(1), ++ RTL8231_PIN(2), ++ RTL8231_PIN(3), ++ RTL8231_PIN(4), ++ RTL8231_PIN(5), ++ RTL8231_PIN(6), ++ RTL8231_PIN(7), ++ RTL8231_PIN(8), ++ RTL8231_PIN(9), ++ RTL8231_PIN(10), ++ RTL8231_PIN(11), ++ RTL8231_PIN(12), ++ RTL8231_PIN(13), ++ RTL8231_PIN(14), ++ RTL8231_PIN(15), ++ RTL8231_PIN(16), ++ RTL8231_PIN(17), ++ RTL8231_PIN(18), ++ RTL8231_PIN(19), ++ RTL8231_PIN(20), ++ RTL8231_PIN(21), ++ RTL8231_PIN(22), ++ RTL8231_PIN(23), ++ RTL8231_PIN(24), ++ RTL8231_PIN(25), ++ RTL8231_PIN(26), ++ RTL8231_PIN(27), ++ RTL8231_PIN(28), ++ RTL8231_PIN(29), ++ RTL8231_PIN(30), ++ RTL8231_PIN(31), ++ RTL8231_PIN(32), ++ RTL8231_PIN(33), ++ RTL8231_PIN(34), ++ RTL8231_PIN(35), ++ RTL8231_PIN(36), ++}; ++ ++static int rtl8231_get_groups_count(struct pinctrl_dev *pctldev) ++{ ++ return ARRAY_SIZE(rtl8231_pins); ++} ++ ++static const char *rtl8231_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector) ++{ ++ return rtl8231_pins[selector].name; ++} ++ ++static int rtl8231_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, ++ const unsigned int **pins, unsigned int *num_pins) ++{ ++ if (selector >= ARRAY_SIZE(rtl8231_pins)) ++ return -EINVAL; ++ ++ *pins = &rtl8231_pins[selector].number; ++ *num_pins = 1; ++ ++ return 0; ++} ++ ++static const struct pinctrl_ops rtl8231_pinctrl_ops = { ++ .get_groups_count = rtl8231_get_groups_count, ++ .get_group_name = rtl8231_get_group_name, ++ .get_group_pins = rtl8231_get_group_pins, ++ .dt_node_to_map = pinconf_generic_dt_node_to_map_all, ++ .dt_free_map = pinconf_generic_dt_free_map, ++}; ++ ++static int rtl8231_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, ++ unsigned int group_selector) ++{ ++ const struct function_desc *func = pinmux_generic_get_function(pctldev, func_selector); ++ const struct rtl8231_pin_desc *desc = rtl8231_pins[group_selector].drv_data; ++ const struct rtl8231_pin_ctrl *ctrl = pinctrl_dev_get_drvdata(pctldev); ++ unsigned int func_flag = (uintptr_t) func->data; ++ unsigned int function_mask; ++ unsigned int gpio_function; ++ ++ if (!(desc->functions & func_flag)) ++ return -EINVAL; ++ ++ function_mask = BIT(desc->offset); ++ gpio_function = desc->gpio_function_value << desc->offset; ++ ++ if (func_flag == RTL8231_PIN_FUNCTION_GPIO) ++ return regmap_update_bits(ctrl->map, desc->reg, function_mask, gpio_function); ++ else ++ return regmap_update_bits(ctrl->map, desc->reg, function_mask, ~gpio_function); ++} ++ ++static int rtl8231_gpio_request_enable(struct pinctrl_dev *pctldev, ++ struct pinctrl_gpio_range *range, unsigned int offset) ++{ ++ const struct rtl8231_pin_desc *desc = rtl8231_pins[offset].drv_data; ++ struct rtl8231_pin_ctrl *ctrl = pinctrl_dev_get_drvdata(pctldev); ++ unsigned int function_mask; ++ unsigned int gpio_function; ++ ++ function_mask = BIT(desc->offset); ++ gpio_function = desc->gpio_function_value << desc->offset; ++ ++ return regmap_update_bits(ctrl->map, desc->reg, function_mask, gpio_function); ++} ++ ++static const struct pinmux_ops rtl8231_pinmux_ops = { ++ .get_functions_count = pinmux_generic_get_function_count, ++ .get_function_name = pinmux_generic_get_function_name, ++ .get_function_groups = pinmux_generic_get_function_groups, ++ .set_mux = rtl8231_set_mux, ++ .gpio_request_enable = rtl8231_gpio_request_enable, ++ .strict = true, ++}; ++ ++static int rtl8231_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset, ++ unsigned long *config) ++{ ++ struct rtl8231_pin_ctrl *ctrl = pinctrl_dev_get_drvdata(pctldev); ++ unsigned int param = pinconf_to_config_param(*config); ++ unsigned int arg; ++ int err; ++ int v; ++ ++ switch (param) { ++ case PIN_CONFIG_INPUT_DEBOUNCE: ++ if (offset < RTL8231_DEBOUNCE_MIN_OFFSET) ++ return -EINVAL; ++ ++ err = regmap_read(ctrl->map, RTL8231_REG_FUNC1, &v); ++ if (err) ++ return err; ++ ++ v = FIELD_GET(RTL8231_FUNC1_DEBOUNCE_MASK, v); ++ if (v & BIT(offset - RTL8231_DEBOUNCE_MIN_OFFSET)) ++ arg = RTL8231_DEBOUNCE_USEC; ++ else ++ arg = 0; ++ break; ++ default: ++ return -ENOTSUPP; ++ } ++ ++ *config = pinconf_to_config_packed(param, arg); ++ ++ return 0; ++} ++ ++static int rtl8231_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset, ++ unsigned long *configs, unsigned int num_configs) ++{ ++ struct rtl8231_pin_ctrl *ctrl = pinctrl_dev_get_drvdata(pctldev); ++ unsigned int param, arg; ++ unsigned int pin_mask; ++ int err; ++ int i; ++ ++ for (i = 0; i < num_configs; i++) { ++ param = pinconf_to_config_param(configs[i]); ++ arg = pinconf_to_config_argument(configs[i]); ++ ++ switch (param) { ++ case PIN_CONFIG_INPUT_DEBOUNCE: ++ if (offset < RTL8231_DEBOUNCE_MIN_OFFSET) ++ return -EINVAL; ++ ++ pin_mask = FIELD_PREP(RTL8231_FUNC1_DEBOUNCE_MASK, ++ BIT(offset - RTL8231_DEBOUNCE_MIN_OFFSET)); ++ ++ switch (arg) { ++ case 0: ++ err = regmap_update_bits(ctrl->map, RTL8231_REG_FUNC1, ++ pin_mask, 0); ++ break; ++ case RTL8231_DEBOUNCE_USEC: ++ err = regmap_update_bits(ctrl->map, RTL8231_REG_FUNC1, ++ pin_mask, pin_mask); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ break; ++ default: ++ return -ENOTSUPP; ++ } ++ } ++ ++ return err; ++} ++ ++static const struct pinconf_ops rtl8231_pinconf_ops = { ++ .is_generic = true, ++ .pin_config_get = rtl8231_pin_config_get, ++ .pin_config_set = rtl8231_pin_config_set, ++}; ++ ++static int rtl8231_pinctrl_init_functions(struct pinctrl_dev *pctl, struct rtl8231_pin_ctrl *ctrl) ++{ ++ const char *function_name; ++ const char **groups; ++ unsigned int f_idx; ++ unsigned int pin; ++ int num_groups; ++ int err; ++ ++ for (f_idx = 0; f_idx < ARRAY_SIZE(rtl8231_pin_function_names); f_idx++) { ++ function_name = rtl8231_pin_function_names[f_idx]; ++ ++ for (pin = 0, num_groups = 0; pin < ctrl->pctl_desc.npins; pin++) ++ if (rtl8231_pin_data[pin].functions & BIT(f_idx)) ++ num_groups++; ++ ++ groups = devm_kcalloc(pctl->dev, num_groups, sizeof(*groups), GFP_KERNEL); ++ if (!groups) ++ return -ENOMEM; ++ ++ for (pin = 0, num_groups = 0; pin < ctrl->pctl_desc.npins; pin++) ++ if (rtl8231_pin_data[pin].functions & BIT(f_idx)) ++ groups[num_groups++] = rtl8231_pins[pin].name; ++ ++ err = pinmux_generic_add_function(pctl, function_name, groups, num_groups, ++ (void *) BIT(f_idx)); ++ if (err < 0) ++ return err; ++ } ++ ++ return 0; ++} ++ ++struct pin_field_info { ++ const struct reg_field gpio_data; ++ const struct reg_field gpio_dir; ++ const struct reg_field mode; ++}; ++ ++static const struct pin_field_info pin_fields[] = { ++ { ++ .gpio_data = REG_FIELD(RTL8231_REG_GPIO_DATA0, 0, 15), ++ .gpio_dir = REG_FIELD(RTL8231_REG_GPIO_DIR0, 0, 15), ++ .mode = REG_FIELD(RTL8231_REG_PIN_MODE0, 0, 15), ++ }, ++ { ++ .gpio_data = REG_FIELD(RTL8231_REG_GPIO_DATA1, 0, 15), ++ .gpio_dir = REG_FIELD(RTL8231_REG_GPIO_DIR1, 0, 15), ++ .mode = REG_FIELD(RTL8231_REG_PIN_MODE1, 0, 15), ++ }, ++ { ++ .gpio_data = REG_FIELD(RTL8231_REG_GPIO_DATA2, 0, 4), ++ .gpio_dir = REG_FIELD(RTL8231_REG_PIN_HI_CFG, 5, 9), ++ .mode = REG_FIELD(RTL8231_REG_PIN_HI_CFG, 0, 4), ++ }, ++}; ++ ++static int rtl8231_configure_safe(struct device *dev, struct regmap *map) ++{ ++ struct regmap_field *field_data; ++ struct regmap_field *field_mode; ++ struct regmap_field *field_dir; ++ unsigned int is_output; ++ unsigned int is_gpio; ++ unsigned int data; ++ unsigned int mode; ++ unsigned int dir; ++ int err; ++ ++ for (unsigned int i = 0; i < ARRAY_SIZE(pin_fields); i++) { ++ field_data = devm_regmap_field_alloc(dev, map, pin_fields[i].gpio_data); ++ if (IS_ERR(field_data)) ++ return PTR_ERR(field_data); ++ ++ field_dir = devm_regmap_field_alloc(dev, map, pin_fields[i].gpio_dir); ++ if (IS_ERR(field_dir)) ++ return PTR_ERR(field_dir); ++ ++ field_mode = devm_regmap_field_alloc(dev, map, pin_fields[i].mode); ++ if (IS_ERR(field_mode)) ++ return PTR_ERR(field_mode); ++ ++ /* The register cache is invalid at start-up, so this should read from HW */ ++ err = regmap_field_read(field_data, &data); ++ if (err) ++ return err; ++ ++ err = regmap_field_read(field_dir, &dir); ++ if (err) ++ return err; ++ ++ err = regmap_field_read(field_mode, &mode); ++ if (err) ++ return err; ++ ++ /* Write back only the GPIO-out values to fix the cache */ ++ data &= ~dir; ++ regmap_field_write(field_data, data); ++ ++ /* ++ * Set every pin that is configured as gpio-output but muxed for the alternative ++ * (LED) function to gpio-in. That way the pin will be high impedance when it is ++ * muxed to GPIO, preventing unwanted glitches. ++ * The pin muxes are left as-is, so there are no signal changes. ++ */ ++ is_gpio = mode; ++ is_output = ~dir; ++ regmap_field_write(field_dir, dir | (~is_gpio & is_output)); ++ ++ devm_regmap_field_free(dev, field_data); ++ devm_regmap_field_free(dev, field_dir); ++ devm_regmap_field_free(dev, field_mode); ++ } ++ ++ return 0; ++} ++ ++static int rtl8231_pinctrl_init(struct device *dev, struct rtl8231_pin_ctrl *ctrl) ++{ ++ struct pinctrl_dev *pctldev; ++ int err; ++ ++ ctrl->pctl_desc.name = "rtl8231-pinctrl"; ++ ctrl->pctl_desc.owner = THIS_MODULE; ++ ctrl->pctl_desc.confops = &rtl8231_pinconf_ops; ++ ctrl->pctl_desc.pctlops = &rtl8231_pinctrl_ops; ++ ctrl->pctl_desc.pmxops = &rtl8231_pinmux_ops; ++ ctrl->pctl_desc.npins = ARRAY_SIZE(rtl8231_pins); ++ ctrl->pctl_desc.pins = rtl8231_pins; ++ ++ err = devm_pinctrl_register_and_init(dev->parent, &ctrl->pctl_desc, ctrl, &pctldev); ++ if (err) { ++ dev_err(dev, "failed to register pin controller\n"); ++ return err; ++ } ++ ++ err = rtl8231_pinctrl_init_functions(pctldev, ctrl); ++ if (err) ++ return err; ++ ++ err = pinctrl_enable(pctldev); ++ if (err) ++ dev_err(dev, "failed to enable pin controller\n"); ++ ++ return err; ++} ++ ++/* ++ * GPIO controller functionality ++ */ ++static int rtl8231_gpio_reg_mask_xlate(struct gpio_regmap *gpio, unsigned int base, ++ unsigned int offset, unsigned int *reg, unsigned int *mask) ++{ ++ unsigned int pin_mask = BIT(offset % RTL8231_BITS_VAL); ++ ++ if (base == RTL8231_REG_GPIO_DATA0 || offset < 32) { ++ *reg = base + offset / RTL8231_BITS_VAL; ++ *mask = pin_mask; ++ } else if (base == RTL8231_REG_GPIO_DIR0) { ++ *reg = RTL8231_REG_PIN_HI_CFG; ++ *mask = FIELD_PREP(RTL8231_PIN_HI_CFG_DIR_MASK, pin_mask); ++ } else { ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int rtl8231_pinctrl_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct rtl8231_pin_ctrl *ctrl; ++ struct gpio_regmap_config gpio_cfg = {}; ++ int err; ++ ++ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); ++ if (!ctrl) ++ return -ENOMEM; ++ ++ ctrl->map = dev_get_regmap(dev->parent, NULL); ++ if (!ctrl->map) ++ return -ENODEV; ++ ++ err = rtl8231_configure_safe(dev, ctrl->map); ++ if (err) ++ return err; ++ ++ err = rtl8231_pinctrl_init(dev, ctrl); ++ if (err) ++ return err; ++ ++ gpio_cfg.regmap = ctrl->map; ++ gpio_cfg.parent = dev->parent; ++ gpio_cfg.ngpio = RTL8231_NUM_GPIOS; ++ gpio_cfg.ngpio_per_reg = RTL8231_BITS_VAL; ++ ++ gpio_cfg.reg_dat_base = GPIO_REGMAP_ADDR(RTL8231_REG_GPIO_DATA0); ++ gpio_cfg.reg_set_base = GPIO_REGMAP_ADDR(RTL8231_REG_GPIO_DATA0); ++ gpio_cfg.reg_dir_in_base = GPIO_REGMAP_ADDR(RTL8231_REG_GPIO_DIR0); ++ ++ gpio_cfg.reg_mask_xlate = rtl8231_gpio_reg_mask_xlate; ++ ++ return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_cfg)); ++} ++ ++static struct platform_driver rtl8231_pinctrl_driver = { ++ .driver = { ++ .name = "rtl8231-pinctrl", ++ }, ++ .probe = rtl8231_pinctrl_probe, ++}; ++module_platform_driver(rtl8231_pinctrl_driver); ++ ++MODULE_AUTHOR("Sander Vanheule "); ++MODULE_DESCRIPTION("Realtek RTL8231 pin control and GPIO support"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/realtek/patches-6.12/804-leds-Add-support-for-RTL8231-LED-scan-matrix.patch b/target/linux/realtek/patches-6.12/804-leds-Add-support-for-RTL8231-LED-scan-matrix.patch new file mode 100644 index 0000000000..324b556998 --- /dev/null +++ b/target/linux/realtek/patches-6.12/804-leds-Add-support-for-RTL8231-LED-scan-matrix.patch @@ -0,0 +1,338 @@ +From 6b797a97c007e46d6081fc6f4b41ce8407078605 Mon Sep 17 00:00:00 2001 +From: Sander Vanheule +Date: Mon, 10 May 2021 22:16:11 +0200 +Subject: [PATCH] leds: Add support for RTL8231 LED scan matrix + +Both single and bi-color scanning modes are supported. The driver will +verify that the addresses are valid for the current mode, before +registering the LEDs. LEDs can be turned on, off, or toggled at one of +six predefined rates from 40ms to 1280ms. + +Implements a platform device for use as a child device with RTL8231 MFD, +and uses the parent regmap to access the required registers. + +Signed-off-by: Sander Vanheule +--- + drivers/leds/Kconfig | 10 ++ + drivers/leds/Makefile | 1 + + drivers/leds/leds-rtl8231.c | 291 ++++++++++++++++++++++++++++++++++++ + 3 files changed, 302 insertions(+) + create mode 100644 drivers/leds/leds-rtl8231.c + +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -634,6 +634,16 @@ config LEDS_REGULATOR + help + This option enables support for regulator driven LEDs. + ++config LEDS_RTL8231 ++ tristate "RTL8231 LED matrix support" ++ depends on LEDS_CLASS ++ depends on MFD_RTL8231 ++ default MFD_RTL8231 ++ help ++ This option enables support for using the LED scanning matrix output ++ of the RTL8231 GPIO and LED expander chip. ++ When built as a module, this module will be named leds-rtl8231. ++ + config LEDS_BD2606MVV + tristate "LED driver for BD2606MVV" + depends on LEDS_CLASS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -80,6 +80,7 @@ obj-$(CONFIG_LEDS_PM8058) += leds-pm805 + obj-$(CONFIG_LEDS_POWERNV) += leds-powernv.o + obj-$(CONFIG_LEDS_PWM) += leds-pwm.o + obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o ++obj-$(CONFIG_LEDS_RTL8231) += leds-rtl8231.o + obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o + obj-$(CONFIG_LEDS_ST1202) += leds-st1202.o + obj-$(CONFIG_LEDS_SUN50I_A100) += leds-sun50i-a100.o +--- /dev/null ++++ b/drivers/leds/leds-rtl8231.c +@@ -0,0 +1,285 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++/** ++ * struct led_toggle_rate - description of an LED blinking mode ++ * @interval_ms: LED toggle rate in milliseconds ++ * @mode: Register field value used to activate this mode ++ * ++ * For LED hardware accelerated blinking, with equal on and off delay. ++ * Both delays are given by @interval, so the interval at which the LED blinks ++ * (i.e. turn on and off once) is double this value. ++ */ ++struct led_toggle_rate { ++ u16 interval_ms; ++ u8 mode; ++}; ++ ++/** ++ * struct led_modes - description of all LED modes ++ * @toggle_rates: Array of led_toggle_rate values, sorted by ascending interval ++ * @num_toggle_rates: Number of elements in @led_toggle_rate ++ * @off: Register field value to turn LED off ++ * @on: Register field value to turn LED on ++ */ ++struct led_modes { ++ const struct led_toggle_rate *toggle_rates; ++ unsigned int num_toggle_rates; ++ u8 off; ++ u8 on; ++}; ++ ++struct rtl8231_led { ++ struct led_classdev led; ++ const struct led_modes *modes; ++ struct regmap_field *reg_field; ++}; ++#define to_rtl8231_led(_cdev) container_of(_cdev, struct rtl8231_led, led) ++ ++#define RTL8231_NUM_LEDS 3 ++#define RTL8231_LED_PER_REG 5 ++#define RTL8231_BITS_PER_LED 3 ++ ++static const unsigned int rtl8231_led_port_counts_single[RTL8231_NUM_LEDS] = {32, 32, 24}; ++static const unsigned int rtl8231_led_port_counts_bicolor[RTL8231_NUM_LEDS] = {24, 24, 24}; ++ ++static const unsigned int rtl8231_led_base[RTL8231_NUM_LEDS] = { ++ RTL8231_REG_LED0_BASE, ++ RTL8231_REG_LED1_BASE, ++ RTL8231_REG_LED2_BASE, ++}; ++ ++#define RTL8231_DEFAULT_TOGGLE_INTERVAL_MS 500 ++ ++static const struct led_toggle_rate rtl8231_toggle_rates[] = { ++ { 40, 1}, ++ { 80, 2}, ++ { 160, 3}, ++ { 320, 4}, ++ { 640, 5}, ++ {1280, 6}, ++}; ++ ++static const struct led_modes rtl8231_led_modes = { ++ .off = 0, ++ .on = 7, ++ .num_toggle_rates = ARRAY_SIZE(rtl8231_toggle_rates), ++ .toggle_rates = rtl8231_toggle_rates, ++}; ++ ++static void rtl8231_led_brightness_set(struct led_classdev *led_cdev, ++ enum led_brightness brightness) ++{ ++ struct rtl8231_led *pled = to_rtl8231_led(led_cdev); ++ ++ if (brightness) ++ regmap_field_write(pled->reg_field, pled->modes->on); ++ else ++ regmap_field_write(pled->reg_field, pled->modes->off); ++} ++ ++static enum led_brightness rtl8231_led_brightness_get(struct led_classdev *led_cdev) ++{ ++ struct rtl8231_led *pled = to_rtl8231_led(led_cdev); ++ u32 current_mode = pled->modes->off; ++ ++ regmap_field_read(pled->reg_field, ¤t_mode); ++ ++ if (current_mode == pled->modes->off) ++ return LED_OFF; ++ else ++ return LED_ON; ++} ++ ++static unsigned int rtl8231_led_current_interval(struct rtl8231_led *pled) ++{ ++ unsigned int mode; ++ unsigned int i; ++ ++ if (regmap_field_read(pled->reg_field, &mode)) ++ return 0; ++ ++ for (i = 0; i < pled->modes->num_toggle_rates; i++) ++ if (mode == pled->modes->toggle_rates[i].mode) ++ return pled->modes->toggle_rates[i].interval_ms; ++ ++ return 0; ++} ++ ++static int rtl8231_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on, ++ unsigned long *delay_off) ++{ ++ struct rtl8231_led *pled = to_rtl8231_led(led_cdev); ++ const struct led_toggle_rate *rates = pled->modes->toggle_rates; ++ unsigned int num_rates = pled->modes->num_toggle_rates; ++ unsigned int interval_ms; ++ unsigned int i; ++ int err; ++ ++ if (*delay_on == 0 && *delay_off == 0) { ++ interval_ms = RTL8231_DEFAULT_TOGGLE_INTERVAL_MS; ++ } else { ++ /* ++ * If the current mode is blinking, choose the delay that (likely) changed. ++ * Otherwise, choose the interval that would have the same total delay. ++ */ ++ interval_ms = rtl8231_led_current_interval(pled); ++ if (interval_ms > 0 && interval_ms == *delay_off) ++ interval_ms = *delay_on; ++ else if (interval_ms > 0 && interval_ms == *delay_on) ++ interval_ms = *delay_off; ++ else ++ interval_ms = (*delay_on + *delay_off) / 2; ++ } ++ ++ /* Find clamped toggle interval */ ++ for (i = 0; i < (num_rates - 1); i++) ++ if (interval_ms > rates[i].interval_ms) ++ break; ++ ++ interval_ms = rates[i].interval_ms; ++ ++ err = regmap_field_write(pled->reg_field, rates[i].mode); ++ if (err) ++ return err; ++ ++ *delay_on = interval_ms; ++ *delay_off = interval_ms; ++ ++ return 0; ++} ++ ++static int rtl8231_led_read_address(struct fwnode_handle *fwnode, unsigned int *addr_port, ++ unsigned int *addr_led) ++{ ++ u32 addr[2]; ++ int err; ++ ++ err = fwnode_property_count_u32(fwnode, "reg"); ++ if (err < 0) ++ return err; ++ if (err != ARRAY_SIZE(addr)) ++ return -EINVAL; ++ ++ err = fwnode_property_read_u32_array(fwnode, "reg", addr, ARRAY_SIZE(addr)); ++ if (err) ++ return err; ++ ++ *addr_port = addr[0]; ++ *addr_led = addr[1]; ++ ++ return 0; ++} ++ ++static const struct regmap_field *rtl8231_led_get_field(struct device *dev, struct regmap *map, ++ unsigned int port_index, unsigned int led_index) ++{ ++ unsigned int offset = port_index / RTL8231_LED_PER_REG; ++ unsigned int shift = (port_index % RTL8231_LED_PER_REG) * RTL8231_BITS_PER_LED; ++ const struct reg_field field = REG_FIELD(rtl8231_led_base[led_index] + offset, shift, ++ shift + RTL8231_BITS_PER_LED - 1); ++ ++ return devm_regmap_field_alloc(dev, map, field); ++} ++ ++static int rtl8231_led_probe_single(struct device *dev, struct regmap *map, ++ const unsigned int *port_counts, struct fwnode_handle *fwnode) ++{ ++ struct led_init_data init_data = {}; ++ struct rtl8231_led *pled; ++ unsigned int port_index; ++ unsigned int led_index; ++ int err; ++ ++ pled = devm_kzalloc(dev, sizeof(*pled), GFP_KERNEL); ++ if (!pled) ++ return -ENOMEM; ++ ++ err = rtl8231_led_read_address(fwnode, &port_index, &led_index); ++ if (err) { ++ dev_err(dev, "LED address invalid"); ++ return err; ++ } ++ ++ if (led_index >= RTL8231_NUM_LEDS || port_index >= port_counts[led_index]) { ++ dev_err(dev, "LED address (%d.%d) invalid", port_index, led_index); ++ return -EINVAL; ++ } ++ ++ pled->reg_field = rtl8231_led_get_field(dev, map, port_index, led_index); ++ if (IS_ERR(pled->reg_field)) ++ return PTR_ERR(pled->reg_field); ++ ++ pled->modes = &rtl8231_led_modes; ++ ++ pled->led.max_brightness = 1; ++ pled->led.brightness_get = rtl8231_led_brightness_get; ++ pled->led.brightness_set = rtl8231_led_brightness_set; ++ pled->led.blink_set = rtl8231_led_blink_set; ++ ++ init_data.fwnode = fwnode; ++ ++ return devm_led_classdev_register_ext(dev, &pled->led, &init_data); ++} ++ ++static int rtl8231_led_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ const unsigned int *port_counts; ++ struct fwnode_handle *child; ++ struct regmap *map; ++ int err; ++ ++ map = dev_get_regmap(dev->parent, NULL); ++ if (!map) ++ return -ENODEV; ++ ++ if (device_property_match_string(dev, "realtek,led-scan-mode", "single-color") >= 0) { ++ port_counts = rtl8231_led_port_counts_single; ++ regmap_update_bits(map, RTL8231_REG_FUNC0, ++ RTL8231_FUNC0_SCAN_MODE, RTL8231_FUNC0_SCAN_SINGLE); ++ } else if (device_property_match_string(dev, "realtek,led-scan-mode", "bi-color") >= 0) { ++ port_counts = rtl8231_led_port_counts_bicolor; ++ regmap_update_bits(map, RTL8231_REG_FUNC0, ++ RTL8231_FUNC0_SCAN_MODE, RTL8231_FUNC0_SCAN_BICOLOR); ++ } else { ++ dev_err(dev, "scan mode missing or invalid"); ++ return -EINVAL; ++ } ++ ++ fwnode_for_each_available_child_node(dev->fwnode, child) { ++ err = rtl8231_led_probe_single(dev, map, port_counts, child); ++ if (err) ++ dev_warn(dev, "failed to register LED %pfwP", child); ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id of_rtl8231_led_match[] = { ++ { .compatible = "realtek,rtl8231-leds" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, of_rtl8231_led_match); ++ ++static struct platform_driver rtl8231_led_driver = { ++ .driver = { ++ .name = "rtl8231-leds", ++ .of_match_table = of_rtl8231_led_match, ++ }, ++ .probe = rtl8231_led_probe, ++}; ++module_platform_driver(rtl8231_led_driver); ++ ++MODULE_AUTHOR("Sander Vanheule "); ++MODULE_DESCRIPTION("Realtek RTL8231 LED support"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/realtek/patches-6.12/805-add-i2c-gpio-shared-driver.patch b/target/linux/realtek/patches-6.12/805-add-i2c-gpio-shared-driver.patch new file mode 100644 index 0000000000..e50ee312dd --- /dev/null +++ b/target/linux/realtek/patches-6.12/805-add-i2c-gpio-shared-driver.patch @@ -0,0 +1,41 @@ +From 9d2327c5f1ac63cb14af088a95eba110ab0c473e Mon Sep 17 00:00:00 2001 +From: Markus Stockhausen +Date: Wed, 7 May 2025 09:47:24 -0400 +Subject: [PATCH] realtek: add i2c-gpio-shared driver + +Adds the Kconfig and Makefile settings to make the new driver available. + +Signed-off-by: Markus Stockhausen +--- + drivers/i2c/busses/Kconfig | 9 +++++++++ + drivers/i2c/busses/Makefile | 1 + + 2 files changed, 10 insertions(+) + +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -683,6 +683,15 @@ config I2C_GPIO + This is a very simple bitbanging I2C driver utilizing the + arch-neutral GPIO API to control the SCL and SDA lines. + ++config I2C_GPIO_SHARED ++ tristate "multiple GPIO-based bitbanging I2C with shared SCL" ++ depends on GPIOLIB || COMPILE_TEST ++ select I2C_ALGOBIT ++ help ++ This is an alternative of the I2C GPIO driver for devices with only ++ few GPIO pins where multiple busses with dedicated SDA lines share ++ a single SCL line. ++ + config I2C_GPIO_FAULT_INJECTOR + bool "GPIO-based fault injector" + depends on I2C_GPIO +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -67,6 +67,7 @@ obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o + obj-$(CONFIG_I2C_EMEV2) += i2c-emev2.o + obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o + obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o ++obj-$(CONFIG_I2C_GPIO_SHARED) += i2c-gpio-shared.o + obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o + obj-$(CONFIG_I2C_HISI) += i2c-hisi.o + obj-$(CONFIG_I2C_HIX5HD2) += i2c-hix5hd2.o diff --git a/target/linux/realtek/patches-6.12/806-add-mdio-driver.patch b/target/linux/realtek/patches-6.12/806-add-mdio-driver.patch new file mode 100644 index 0000000000..17461f0e4b --- /dev/null +++ b/target/linux/realtek/patches-6.12/806-add-mdio-driver.patch @@ -0,0 +1,34 @@ +From 5b38f63ee59afd95c1d265b7e2097a0958db8a61 Mon Sep 01 00:00:00 2025 +From: Markus Stockhausen +Date: Mon, 01 Sep 2025 20:13:21 +0200 +Subject: realtek: add support for mdio controller + +Signed-off-by: Markus Stockhausen +--- + +--- a/drivers/net/mdio/Makefile ++++ b/drivers/net/mdio/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-ms + obj-$(CONFIG_MDIO_MVUSB) += mdio-mvusb.o + obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o + obj-$(CONFIG_MDIO_REGMAP) += mdio-regmap.o ++obj-$(CONFIG_MDIO_REALTEK_OTTO) += mdio-realtek-otto.o + obj-$(CONFIG_MDIO_REALTEK_OTTO_AUX) += mdio-realtek-otto-aux.o + obj-$(CONFIG_MDIO_SMBUS) += mdio-smbus.o + obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o +--- a/drivers/net/mdio/Kconfig ++++ b/drivers/net/mdio/Kconfig +@@ -207,6 +207,13 @@ config MDIO_REGMAP + regmap. Users willing to use this driver must explicitly select + REGMAP. + ++config MDIO_REALTEK_OTTO ++ tristate "Realtek Otto MDIO interface support" ++ default MACH_REALTEK_RTL ++ depends on MACH_REALTEK_RTL || COMPILE_TEST ++ help ++ This driver supports the MDIO bus on RTL83xx/RTL93xx SoCs. ++ + config MDIO_REALTEK_OTTO_AUX + tristate "Realtek Otto auxiliary MDIO interface support" + default MACH_REALTEK_RTL diff --git a/target/linux/realtek/patches-6.12/808-add-serdes-mdio-driver.patch b/target/linux/realtek/patches-6.12/808-add-serdes-mdio-driver.patch new file mode 100644 index 0000000000..292683f846 --- /dev/null +++ b/target/linux/realtek/patches-6.12/808-add-serdes-mdio-driver.patch @@ -0,0 +1,37 @@ +From fc3eda9aa25765b2115e7427ee4f6dbcd60f8721 Mon Sep 17 00:00:00 2001 +From: Markus Stockhausen +Date: Mon, 15 Sep 2025 17:23:31 +0200 +Subject: [PATCH] net: mdio: Add Realtek Otto SerDes controller + +SoCs in Realtek's Otto platform such as the RTL83xx and RTL93xx +have multiple SerDes to drive the PHYs. Provide a mdio interface +to access their registers. + +Signed-off-by: Markus Stockhausen +--- +--- a/drivers/net/mdio/Makefile ++++ b/drivers/net/mdio/Makefile +@@ -22,6 +22,7 @@ obj-$(CONFIG_MDIO_OCTEON) += mdio-octeo + obj-$(CONFIG_MDIO_REGMAP) += mdio-regmap.o + obj-$(CONFIG_MDIO_REALTEK_OTTO) += mdio-realtek-otto.o + obj-$(CONFIG_MDIO_REALTEK_OTTO_AUX) += mdio-realtek-otto-aux.o ++obj-$(CONFIG_MDIO_REALTEK_OTTO_SERDES) += mdio-realtek-otto-serdes.o + obj-$(CONFIG_MDIO_SMBUS) += mdio-smbus.o + obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o + obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o +--- a/drivers/net/mdio/Kconfig ++++ b/drivers/net/mdio/Kconfig +@@ -224,6 +224,13 @@ config MDIO_REALTEK_OTTO_AUX + This driver supports the auxilairy MDIO bus on RTL838x SoCs. This bus + is typically used to attach RTL8231 GPIO extenders. + ++config MDIO_REALTEK_OTTO_SERDES ++ tristate "Realtek Otto MDIO SerDes interface support" ++ default MACH_REALTEK_RTL ++ depends on MACH_REALTEK_RTL || COMPILE_TEST ++ help ++ This driver provides MDIO access to the RTL83xx/RTL93xx SerDes. ++ + config MDIO_THUNDER + tristate "ThunderX SOCs MDIO buses" + depends on 64BIT diff --git a/target/linux/realtek/patches-6.12/809-add-hasivo-stc8-mfd.patch b/target/linux/realtek/patches-6.12/809-add-hasivo-stc8-mfd.patch new file mode 100644 index 0000000000..7c865eb4d1 --- /dev/null +++ b/target/linux/realtek/patches-6.12/809-add-hasivo-stc8-mfd.patch @@ -0,0 +1,332 @@ +From 7e59fb5d3f2d8b4280ed0bc408c73c0aa9cd8934 Mon Sep 17 00:00:00 2001 +From: Bevan Weiss +Date: Mon, 9 Feb 2026 18:31:46 +1100 +Subject: mfd: Add Hasivo STC8 mfd + +This STC8 microcontroller is used on a range of Hasivo managed switches. +It typically performs some fan/thermal control, and also has some +discrete IO hanging off of it. +The fan/thermal control is still somewhat unknown at this stage, but the +LED / gpio control has been determined as being two I2C registers which +need to be written to with a 'typical' Hasivo 0x40 execute mask set, to +change values. + +Rather than having this expose the LED functionality / thermal control +directly, just represent it as an mfd, with some configurable OR'ing of +an execute-bit to certain registers (execute-bit-regs). This way different +STC8 arrangements can hopefully be handled by devicetree configs rather +than needing new driver code. + + +Signed-off-by: Bevan Weiss +--- + .../bindings/mfd/hasivo,stc8-mfd.yaml | 99 ++++++++++ + drivers/mfd/Kconfig | 11 ++ + drivers/mfd/Makefile | 2 + + drivers/mfd/hasivo-stc8-mfd.c | 182 ++++++++++++++++++ + 4 files changed, 294 insertions(+) + create mode 100644 Documentation/devicetree/bindings/mfd/hasivo,stc8-mfd.yaml + create mode 100644 drivers/mfd/hasivo-stc8-mfd.c + +--- /dev/null ++++ b/Documentation/devicetree/bindings/mfd/hasivo,stc8-mfd.yaml +@@ -0,0 +1,99 @@ ++# SPDX-License-Identifier: GPL-2.0 ++# STC8 MFD binding for Hasivo STC8 microcontroller used in managed switches ++ ++title: "STC8 multi-function device" ++description: | ++ This binding describes the Hasivo STC8 multi-function device. ++ This is an STC8 microcontroller with custom firmware used by Hasivo to ++ provide various functions on their managed switch products. ++ The main known functionality currently is to allow for discrete GPIO control ++ which turns on/off LEDs and controls PWM for fan speed. ++ It is known that for the discrete IO however, the host must send an execute ++ flag (0x40) along with the register write to have the STC8 apply the change. ++ This binding allows for specifying which registers require this execute flag ++ to be set automatically by the MFD driver. ++ ++maintainers: ++ - bevan.weiss@gmail.com ++ ++properties: ++ compatible: ++ description: > ++ Must be "hasivo,stc8-mfd" for the MFD driver to bind. ++ Child devices will require that this also expose the "syscon" binding, ++ such that registers can be mapped through this MFD. ++ type: string ++ required: true ++ ++ reg: ++ description: > ++ I2C address of the STC8 device on the bus. ++ type: integer ++ required: true ++ ++ hasivo,execute-bit: ++ description: > ++ The mask that will be automatically ORd on writes to the registers ++ specified in hasivo,execute-bit-regs. This mask is used to signal to ++ the STC8 that the write should be executed. ++ If not specified, defaults to 0x40. ++ type: unsigned integer ++ defaults: 0x40 ++ required: false ++ ++ hasivo,execute-bit-registers: ++ description: > ++ Array of registers for which the execute-bit mask should be ++ applied. Writes to other registers will not have the execute-bit mask ++ applied. ++ If not specified, no registers will have the execute-bit mask applied. ++ type: array of unsigned integers ++ required: false ++ ++required: ++ - compatible ++ - reg ++ ++children: ++ ++examples: ++ - | ++ &i2c0 { ++ status = "okay"; ++ ++ stc8: stc8-mfd@0x4d { ++ compatible = "hasivo,stc8-mfd", "syscon"; ++ reg = <0x4d>; ++ hasivo,execute-bit = <0x40>; ++ hasivo,execute-bit-regs = <0x01 0x02>; ++ ++ poe_led_lan1: led@1,1 { ++ compatible = "register-bit-led"; ++ offset = <0x01>; ++ mask = <0x01>; ++ label = "orange:poe_led_lan1"; ++ default-state = "off"; ++ }; ++ poe_led_lan2: led@1,2 { ++ compatible = "register-bit-led"; ++ offset = <0x01>; ++ mask = <0x02>; ++ label = "orange:poe_led_lan2"; ++ default-state = "off"; ++ }; ++ poe_led_lan3: led@1,3 { ++ compatible = "register-bit-led"; ++ offset = <0x01>; ++ mask = <0x04>; ++ label = "orange:poe_led_lan3"; ++ default-state = "off"; ++ }; ++ poe_led_lan4: led@1,4 { ++ compatible = "register-bit-led"; ++ offset = <0x01>; ++ mask = <0x08>; ++ label = "orange:poe_led_lan4"; ++ default-state = "off"; ++ }; ++ }; ++ }; +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -557,6 +557,17 @@ config MFD_MX25_TSADC + i.MX25 processors. They consist of a conversion queue for general + purpose ADC and a queue for Touchscreens. + ++config MFD_HASIVO_STC8 ++ tristate "Hasivo STC8 Multifunction Device" ++ select MFD_CORE ++ select REGMAP_I2C ++ depends on I2C ++ help ++ Support for the Hasivo STC8 multifunction device over I2C. ++ This driver provides common support for accessing the device, ++ additional drivers must be enabled in order to use the ++ functionality of the device. ++ + config MFD_HI6421_PMIC + tristate "HiSilicon Hi6421 PMU/Codec IC" + depends on OF +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -290,3 +290,5 @@ obj-$(CONFIG_MFD_ATC260X_I2C) += atc260x + + obj-$(CONFIG_MFD_RSMU_I2C) += rsmu_i2c.o rsmu_core.o + obj-$(CONFIG_MFD_RSMU_SPI) += rsmu_spi.o rsmu_core.o ++ ++obj-$(CONFIG_MFD_HASIVO_STC8) += hasivo-stc8-mfd.o +--- /dev/null ++++ b/drivers/mfd/hasivo-stc8-mfd.c +@@ -0,0 +1,169 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Hasivo STC8 MFD driver with configurable write ORing for execute bit ++ * I2C implementation ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct stc8_mfd { ++ struct device *dev; ++ struct regmap *parent_regmap; ++ struct regmap *child_regmap; ++ u32 exec_bit; ++ size_t num_exec_regs; ++ u32 exec_regs[] __counted_by(num_exec_regs); ++}; ++ ++/* Check if register requires execute bit */ ++static bool is_exec_reg(struct stc8_mfd *mfd, unsigned int reg) ++{ ++ for (size_t i = 0; i < mfd->num_exec_regs; i++) { ++ if (mfd->exec_regs[i] == reg) ++ return true; ++ } ++ return false; ++} ++ ++/* Custom regmap write wrapper */ ++static int stc8_child_reg_write(void *context, unsigned int reg, unsigned int val) ++{ ++ struct stc8_mfd *mfd = context; ++ const unsigned int orig_val = val; ++ ++ /* Apply execute bit if this register is in the list */ ++ if (is_exec_reg(mfd, reg)) { ++ val |= mfd->exec_bit; ++ dev_dbg(mfd->dev, "Applying exec bit to reg 0x%02x, orig_val=0x%02x, new_val=0x%02x\n", reg, orig_val, val); ++ } ++ ++ /* Forward to parent regmap (I2C bus) */ ++ return regmap_write(mfd->parent_regmap, reg, val); ++} ++ ++/* Custom regmap read - transparent passthrough */ ++static int stc8_child_reg_read(void *context, unsigned int reg, unsigned int *val) ++{ ++ struct stc8_mfd *mfd = context; ++ ++ return regmap_read(mfd->parent_regmap, reg, val); ++} ++ ++static const struct regmap_config stc8_parent_regmap_config = { ++ .name = "stc8-mfd-parent", ++ .reg_bits = 8, ++ .val_bits = 8, ++}; ++ ++static const struct regmap_config stc8_child_regmap_config = { ++ .name = "stc8-mfd-child", ++ .reg_bits = 8, ++ .val_bits = 8, ++ .reg_read = stc8_child_reg_read, ++ .reg_write = stc8_child_reg_write, ++}; ++ ++static int stc8_i2c_probe(struct i2c_client *client) ++{ ++ struct device_node *np = client->dev.of_node; ++ struct stc8_mfd *mfd; ++ u32 exec_bit; ++ int count; ++ int ret; ++ ++ /* Get execute bit value (default 0x40) */ ++ if (of_property_read_u32(np, "hasivo,execute-bit", &exec_bit)) ++ exec_bit = 0x40; ++ ++ /* Get count of execute registers */ ++ count = of_property_count_u32_elems(np, "hasivo,execute-bit-registers"); ++ if (count < 0) ++ count = 0; ++ ++ mfd = devm_kzalloc(&client->dev, struct_size(mfd, exec_regs, count), GFP_KERNEL); ++ if (!mfd) ++ return -ENOMEM; ++ ++ mfd->num_exec_regs = count; ++ mfd->dev = &client->dev; ++ if (count > 0) { ++ ret = of_property_read_u32_array(np, "hasivo,execute-bit-registers", ++ mfd->exec_regs, count); ++ if (ret) { ++ dev_err(mfd->dev, "Failed to read execute-bit-registers: %d\n", ret); ++ return ret; ++ } ++ } ++ ++ mfd->exec_bit = exec_bit; ++ dev_info(mfd->dev, "execute-bit=0x%02x, %zu execute-bit-registers\n", ++ mfd->exec_bit, mfd->num_exec_regs); ++ ++ dev_dbg(mfd->dev, "Hasivo STC8 MFD driver probed started\n"); ++ ++ i2c_set_clientdata(client, mfd); ++ ++ /* Create parent regmap for direct I2C access */ ++ mfd->parent_regmap = devm_regmap_init_i2c(client, ++ &stc8_parent_regmap_config); ++ if (IS_ERR(mfd->parent_regmap)) { ++ dev_err(&client->dev, "Failed to init parent regmap\n"); ++ return PTR_ERR(mfd->parent_regmap); ++ } ++ ++ /* Create child regmap with custom read/write for masking */ ++ mfd->child_regmap = devm_regmap_init(&client->dev, NULL, mfd, ++ &stc8_child_regmap_config); ++ if (IS_ERR(mfd->child_regmap)) { ++ dev_err(&client->dev, "Failed to init child regmap\n"); ++ return PTR_ERR(mfd->child_regmap); ++ } ++ /* Set the child regmap as the syscon regmap */ ++ ret = of_syscon_register_regmap(mfd->dev->of_node, mfd->child_regmap); ++ if (ret) ++ return ret; ++ ++ /* Automatically populate child devices from device tree */ ++ ret = of_platform_populate(client->dev.of_node, NULL, NULL, ++ &client->dev); ++ if (ret) { ++ dev_err(&client->dev, "Failed to add child devices: %d\n", ret); ++ return ret; ++ } ++ ++ dev_dbg(&client->dev, "Hasivo STC8 MFD driver probed successfully\n"); ++ ++ return 0; ++} ++ ++static void stc8_i2c_remove(struct i2c_client *client) ++{ ++ of_platform_depopulate(&client->dev); ++ dev_dbg(&client->dev, "Hasivo STC8 MFD driver removed\n"); ++} ++ ++static const struct of_device_id stc8_of_match[] = { ++ { .compatible = "hasivo,stc8-mfd" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, stc8_of_match); ++ ++static struct i2c_driver stc8_i2c_driver = { ++ .driver = { ++ .name = "hasivo-stc8-mfd", ++ .of_match_table = stc8_of_match, ++ }, ++ .probe = stc8_i2c_probe, ++ .remove = stc8_i2c_remove, ++}; ++module_i2c_driver(stc8_i2c_driver); ++ ++MODULE_AUTHOR("Bevan Weiss "); ++MODULE_DESCRIPTION("Hasivo STC8 MFD driver with configurable write masking"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/realtek/patches-6.12/810-lm75-alert-polarity-swap.patch b/target/linux/realtek/patches-6.12/810-lm75-alert-polarity-swap.patch new file mode 100644 index 0000000000..694640af5d --- /dev/null +++ b/target/linux/realtek/patches-6.12/810-lm75-alert-polarity-swap.patch @@ -0,0 +1,59 @@ +From 92ea53e058d40ebda7326016494e3c21dc536c53 Mon Sep 17 00:00:00 2001 +From: Markus Stockhausen +Date: Mon, 23 Mar 2026 22:12:01 +0200 +Subject: [PATCH] hwmon: lm75 alert polarity swap + +The LM75 can steer the alert polarity. In default mode the alert +output pin is active-low. This can not be configured with the +existing LM75 driver. + +There are hardware designs that use this alert output for an automatic +fan speed control. E.g. the D-Link DGS-1250. This works as follows + +- temperature below Tmax threshold -> alert pin low -> fan slow speed +- temperature above Tmax threshold -> alert pin high -> fan high speed + +As one can see the hardware design requires the alert pin to be +configured in mode active-high to work as described. Add a LM75 DTS +property "alert-polarity-active-high" that allows to swap the alert +pin behaviour during initialization to active-high. + +Signed-off-by: Markus Stockhausen + +--- a/drivers/hwmon/lm75.c ++++ b/drivers/hwmon/lm75.c +@@ -121,7 +121,8 @@ struct lm75_data { + + static const u8 lm75_sample_set_masks[] = { 0 << 5, 1 << 5, 2 << 5, 3 << 5 }; + +-#define LM75_SAMPLE_CLEAR_MASK (3 << 5) ++#define LM75_SAMPLE_CLEAR_MASK (3 << 5) ++#define LM75_ALERT_POLARITY_HIGH BIT(2) + + /* The structure below stores the configuration values of the supported devices. + * In case of being supported multiple configurations, the default one must +@@ -631,6 +632,7 @@ static int lm75_probe(struct i2c_client + struct device *hwmon_dev; + struct lm75_data *data; + int status, err; ++ u16 set_mask; + + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA)) +@@ -680,9 +682,14 @@ static int lm75_probe(struct i2c_client + } + data->orig_conf = status; + data->current_conf = status; ++ ++ set_mask = data->params->set_mask; ++ if (of_property_read_bool(dev->of_node, "alert-polarity-active-high")) { ++ pr_info("set lm75 alert to active high\n"); ++ set_mask |= LM75_ALERT_POLARITY_HIGH; ++ } + +- err = lm75_write_config(data, data->params->set_mask, +- data->params->clr_mask); ++ err = lm75_write_config(data, set_mask, data->params->clr_mask); + if (err) + return err; + diff --git a/target/linux/realtek/rtl838x/config-6.12 b/target/linux/realtek/rtl838x/config-6.12 new file mode 100644 index 0000000000..4f098a75d9 --- /dev/null +++ b/target/linux/realtek/rtl838x/config-6.12 @@ -0,0 +1,264 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BMIPS_CPUFREQ is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_REALTEK=y +CONFIG_COMMON_CLK_RTL83XX=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_CPUFREQ=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_EARLY_PRINTK_8250=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FIXED_PHY=y +CONFIG_FORCE_NR_CPUS=y +CONFIG_FS_IOMAP=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_REALTEK_OTTO=y +CONFIG_GPIO_REGMAP=y +CONFIG_GPIO_WATCHDOG=y +# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set +CONFIG_GRO_CELLS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HWMON=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_GPIO_SHARED=y +CONFIG_I2C_MUX=y +# CONFIG_I2C_MUX_RTL9300 is not set +# CONFIG_I2C_RTL9300 is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_JFFS2_ZLIB=y +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_RTL8231 is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MACH_REALTEK_RTL=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_GPIO=y +CONFIG_MDIO_I2C=y +CONFIG_MDIO_REALTEK_OTTO=y +CONFIG_MDIO_REALTEK_OTTO_AUX=y +CONFIG_MDIO_REALTEK_OTTO_SERDES=y +CONFIG_MDIO_SMBUS=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_HASIVO_STC8 is not set +CONFIG_MFD_RTL8231=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_MIPS_CMDLINE_FROM_DTB=y +CONFIG_MIPS_EXTERNAL_TIMER=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_MIPS_SPRAM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +# CONFIG_MTD_NAND_ECC_REALTEK is not set +# CONFIG_MTD_SPI_NAND is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_BRNIMAGE_FW=y +CONFIG_MTD_SPLIT_EVA_FW=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_H3C_VFS=y +CONFIG_MTD_SPLIT_TPLINK_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_MTD_VIRT_CONCAT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_RTL83XX=y +# CONFIG_NET_DSA_RTL83XX_RTL930X_L3_OFFLOAD is not set +CONFIG_NET_DSA_TAG_RTL_OTTO=y +CONFIG_NET_EGRESS=y +CONFIG_NET_INGRESS=y +CONFIG_NET_RTL838X=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NO_EXCEPT_FILL=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PCS_RTL_OTTO=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_RTL8231=y +CONFIG_PM_OPP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REALTEK_OTTO_TIMER=y +CONFIG_REALTEK_OTTO_WDT=y +CONFIG_REALTEK_PHY=y +CONFIG_REALTEK_PHY_HWMON=y +CONFIG_REALTEK_PHY_MULTIPORT=y +CONFIG_REALTEK_THERMAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MDIO=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RTL838X=y +# CONFIG_RTL839X is not set +# CONFIG_RTL930X is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SFP=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_REALTEK_SNAND is not set +CONFIG_SRAM=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_THERMAL=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y +CONFIG_USE_OF=y +CONFIG_WATCHDOG_CORE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/realtek/rtl839x/config-6.12 b/target/linux/realtek/rtl839x/config-6.12 new file mode 100644 index 0000000000..c515afbf8a --- /dev/null +++ b/target/linux/realtek/rtl839x/config-6.12 @@ -0,0 +1,286 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BMIPS_CPUFREQ is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_REALTEK=y +CONFIG_COMMON_CLK_RTL83XX=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_CPUFREQ=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_EARLY_PRINTK_8250=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FIXED_PHY=y +CONFIG_FS_IOMAP=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_REALTEK_OTTO=y +CONFIG_GPIO_REGMAP=y +CONFIG_GPIO_WATCHDOG=y +# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set +CONFIG_GRO_CELLS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HWMON=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_GPIO_SHARED=y +# CONFIG_I2C_MUX_RTL9300 is not set +# CONFIG_I2C_RTL9300 is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_JFFS2_ZLIB=y +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_RTL8231 is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MACH_REALTEK_RTL=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_I2C=y +CONFIG_MDIO_REALTEK_OTTO=y +CONFIG_MDIO_REALTEK_OTTO_AUX=y +CONFIG_MDIO_REALTEK_OTTO_SERDES=y +CONFIG_MDIO_SMBUS=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_HASIVO_STC8 is not set +CONFIG_MFD_RTL8231=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_MIPS_CMDLINE_FROM_DTB=y +CONFIG_MIPS_EXTERNAL_TIMER=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_MT=y +# CONFIG_MIPS_MT_FPAFF is not set +CONFIG_MIPS_MT_SMP=y +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_NR_CPU_NR_MAP=2 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_MIPS_SPRAM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +# CONFIG_MTD_NAND_ECC_REALTEK is not set +# CONFIG_MTD_SPI_NAND is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_BRNIMAGE_FW=y +CONFIG_MTD_SPLIT_EVA_FW=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_H3C_VFS=y +CONFIG_MTD_SPLIT_TPLINK_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_MTD_VIRT_CONCAT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SRCU_NMI_SAFE=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_RTL83XX=y +# CONFIG_NET_DSA_RTL83XX_RTL930X_L3_OFFLOAD is not set +CONFIG_NET_DSA_TAG_RTL_OTTO=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_RTL838X=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NO_EXCEPT_FILL=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NR_CPUS=2 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PCS_RTL_OTTO=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_RTL8231=y +CONFIG_PM_OPP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REALTEK_OTTO_TIMER=y +CONFIG_REALTEK_OTTO_WDT=y +CONFIG_REALTEK_PHY=y +CONFIG_REALTEK_PHY_HWMON=y +CONFIG_REALTEK_PHY_MULTIPORT=y +CONFIG_REALTEK_THERMAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MDIO=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +# CONFIG_RTL838X is not set +CONFIG_RTL839X=y +# CONFIG_RTL930X is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SFP=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_REALTEK_SNAND is not set +CONFIG_SRAM=y +CONFIG_SWPHY=y +CONFIG_SYNC_R4K=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_THERMAL=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y +CONFIG_USE_OF=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/realtek/rtl930x/config-6.12 b/target/linux/realtek/rtl930x/config-6.12 new file mode 100644 index 0000000000..2170e72ee0 --- /dev/null +++ b/target/linux/realtek/rtl930x/config-6.12 @@ -0,0 +1,264 @@ +CONFIG_AQUANTIA_PHY=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BOARD_SCACHE=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_REALTEK is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRC_CCITT=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_EARLY_PRINTK_8250=y +CONFIG_EEPROM_AT24=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FIXED_PHY=y +CONFIG_FORCE_NR_CPUS=y +CONFIG_FS_IOMAP=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_REALTEK_OTTO=y +CONFIG_GRO_CELLS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HIGHMEM=y +CONFIG_HWMON=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_GPIO_SHARED=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_RTL9300=y +CONFIG_I2C_RTL9300=y +CONFIG_I2C_SMBUS=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_JFFS2_ZLIB=y +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_RTL8231 is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MACH_REALTEK_RTL=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_I2C=y +CONFIG_MDIO_REALTEK_OTTO=y +CONFIG_MDIO_REALTEK_OTTO_AUX=y +CONFIG_MDIO_REALTEK_OTTO_SERDES=y +CONFIG_MDIO_SMBUS=y +# CONFIG_MFD_HASIVO_STC8 is not set +CONFIG_MFD_RTL8231=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_MIPS_CMDLINE_FROM_DTB=y +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_MIPS_EXTERNAL_TIMER=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_MT=y +# CONFIG_MIPS_MT_FPAFF is not set +CONFIG_MIPS_MT_SMP=y +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_NR_CPU_NR_MAP=2 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_MIPS_SPRAM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +# CONFIG_MTD_NAND_ECC_REALTEK is not set +# CONFIG_MTD_SPI_NAND is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_BRNIMAGE_FW=y +CONFIG_MTD_SPLIT_EVA_FW=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_TPLINK_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_MTD_VIRT_CONCAT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_RTL83XX=y +# CONFIG_NET_DSA_RTL83XX_RTL930X_L3_OFFLOAD is not set +CONFIG_NET_DSA_TAG_RTL_OTTO=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_RTL838X=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NO_EXCEPT_FILL=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NR_CPUS=2 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PCS_RTL_OTTO=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_RTL8231=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REALTEK_OTTO_TIMER=y +CONFIG_REALTEK_OTTO_WDT=y +CONFIG_REALTEK_PHY=y +CONFIG_REALTEK_PHY_HWMON=y +CONFIG_REALTEK_PHY_MULTIPORT=y +CONFIG_REALTEK_THERMAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MDIO=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTL8261N_PHY=y +# CONFIG_RTL838X is not set +# CONFIG_RTL839X is not set +CONFIG_RTL930X=y +# CONFIG_RTL931X is not set +CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SFP=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_REALTEK_SNAND is not set +CONFIG_SWPHY=y +CONFIG_SYNC_R4K=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_THERMAL=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y +CONFIG_USE_OF=y +CONFIG_WATCHDOG_CORE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/realtek/rtl930x_nand/config-6.12 b/target/linux/realtek/rtl930x_nand/config-6.12 new file mode 100644 index 0000000000..473fa91b30 --- /dev/null +++ b/target/linux/realtek/rtl930x_nand/config-6.12 @@ -0,0 +1,269 @@ +CONFIG_AQUANTIA_PHY=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BOARD_SCACHE=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_REALTEK is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRC_CCITT=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_EARLY_PRINTK_8250=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FIXED_PHY=y +CONFIG_FORCE_NR_CPUS=y +CONFIG_FS_IOMAP=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_REALTEK_OTTO=y +CONFIG_GRO_CELLS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HIGHMEM=y +CONFIG_HWMON=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +# CONFIG_I2C_GPIO_SHARED is not set +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_RTL9300=y +CONFIG_I2C_RTL9300=y +CONFIG_I2C_SMBUS=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_JFFS2_ZLIB=y +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_RTL8231 is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MACH_REALTEK_RTL=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_I2C=y +CONFIG_MDIO_REALTEK_OTTO=y +CONFIG_MDIO_REALTEK_OTTO_AUX=y +CONFIG_MDIO_REALTEK_OTTO_SERDES=y +CONFIG_MDIO_SMBUS=y +# CONFIG_MFD_HASIVO_STC8 is not set +CONFIG_MFD_RTL8231=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_MIPS_CMDLINE_FROM_DTB=y +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_MIPS_EXTERNAL_TIMER=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_MT=y +# CONFIG_MIPS_MT_FPAFF is not set +CONFIG_MIPS_MT_SMP=y +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_NR_CPU_NR_MAP=2 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_MIPS_SPRAM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_REALTEK=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_BRNIMAGE_FW=y +CONFIG_MTD_SPLIT_EVA_FW=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_TPLINK_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_VIRT_CONCAT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_RTL83XX=y +# CONFIG_NET_DSA_RTL83XX_RTL930X_L3_OFFLOAD is not set +CONFIG_NET_DSA_TAG_RTL_OTTO=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_RTL838X=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NO_EXCEPT_FILL=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NR_CPUS=2 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PCS_RTL_OTTO=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_RTL8231=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REALTEK_OTTO_TIMER=y +CONFIG_REALTEK_OTTO_WDT=y +CONFIG_REALTEK_PHY=y +CONFIG_REALTEK_PHY_HWMON=y +CONFIG_REALTEK_PHY_MULTIPORT=y +CONFIG_REALTEK_THERMAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MDIO=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTL8261N_PHY=y +# CONFIG_RTL838X is not set +# CONFIG_RTL839X is not set +CONFIG_RTL930X=y +# CONFIG_RTL931X is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SFP=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_REALTEK_SNAND=y +CONFIG_SWPHY=y +CONFIG_SYNC_R4K=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_THERMAL=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y +CONFIG_USE_OF=y +CONFIG_WATCHDOG_CORE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/realtek/rtl931x/config-6.12 b/target/linux/realtek/rtl931x/config-6.12 new file mode 100644 index 0000000000..b5c2ba630d --- /dev/null +++ b/target/linux/realtek/rtl931x/config-6.12 @@ -0,0 +1,272 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BOARD_SCACHE=y +CONFIG_CLKSRC_MIPS_GIC=y +CONFIG_CLOCKSOURCE_WATCHDOG=y +CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=125 +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_REALTEK is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_EARLY_PRINTK_8250=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FIXED_PHY=y +CONFIG_FS_IOMAP=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_REALTEK_OTTO=y +CONFIG_GRO_CELLS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HIGHMEM=y +CONFIG_HWMON=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +# CONFIG_I2C_GPIO_SHARED is not set +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_RTL9300=y +CONFIG_I2C_RTL9300=y +CONFIG_I2C_SMBUS=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_JFFS2_ZLIB=y +CONFIG_KMAP_LOCAL=y +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_RTL8231 is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MACH_REALTEK_RTL=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_I2C=y +CONFIG_MDIO_REALTEK_OTTO=y +CONFIG_MDIO_REALTEK_OTTO_AUX=y +CONFIG_MDIO_REALTEK_OTTO_SERDES=y +CONFIG_MDIO_SMBUS=y +# CONFIG_MFD_HASIVO_STC8 is not set +CONFIG_MFD_RTL8231=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_CLOCK_VSYSCALL=y +CONFIG_MIPS_CM=y +# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_MIPS_CMDLINE_FROM_DTB=y +CONFIG_MIPS_CPC=y +CONFIG_MIPS_CPS=y +# CONFIG_MIPS_CPS_NS16550_BOOL is not set +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_MIPS_EXTERNAL_TIMER=y +CONFIG_MIPS_GIC=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_MT=y +CONFIG_MIPS_MT_FPAFF=y +CONFIG_MIPS_MT_SMP=y +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_NR_CPU_NR_MAP=2 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_MIPS_SPRAM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +# CONFIG_MTD_NAND_ECC_REALTEK is not set +# CONFIG_MTD_SPI_NAND is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_BRNIMAGE_FW=y +CONFIG_MTD_SPLIT_EVA_FW=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_TPLINK_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SRCU_NMI_SAFE=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_RTL83XX=y +# CONFIG_NET_DSA_RTL83XX_RTL930X_L3_OFFLOAD is not set +CONFIG_NET_DSA_TAG_RTL_OTTO=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_RTL838X=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NO_EXCEPT_FILL=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NR_CPUS=4 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PCS_RTL_OTTO=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_RTL8231=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REALTEK_OTTO_TIMER=y +CONFIG_REALTEK_OTTO_WDT=y +CONFIG_REALTEK_PHY=y +CONFIG_REALTEK_PHY_HWMON=y +CONFIG_REALTEK_PHY_MULTIPORT=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +# CONFIG_RTL838X is not set +# CONFIG_RTL839X is not set +CONFIG_RTL930X=y +CONFIG_RTL931X=y +CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_LM75=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SFP=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_REALTEK_SNAND is not set +CONFIG_SWPHY=y +CONFIG_SYNC_R4K=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MIPS_CPS=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_SYS_SUPPORTS_VPE_LOADER=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y +CONFIG_USE_OF=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WEAK_ORDERING=y +CONFIG_XPS=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/realtek/rtl931x_nand/config-6.12 b/target/linux/realtek/rtl931x_nand/config-6.12 new file mode 100644 index 0000000000..1642286ca7 --- /dev/null +++ b/target/linux/realtek/rtl931x_nand/config-6.12 @@ -0,0 +1,278 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BOARD_SCACHE=y +CONFIG_CLKSRC_MIPS_GIC=y +CONFIG_CLOCKSOURCE_WATCHDOG=y +CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=125 +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_REALTEK is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_EARLY_PRINTK_8250=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FIXED_PHY=y +CONFIG_FS_IOMAP=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_REALTEK_OTTO=y +CONFIG_GRO_CELLS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HIGHMEM=y +CONFIG_HWMON=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +# CONFIG_I2C_GPIO_SHARED is not set +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_RTL9300=y +CONFIG_I2C_RTL9300=y +CONFIG_I2C_SMBUS=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_JFFS2_ZLIB=y +CONFIG_KMAP_LOCAL=y +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_RTL8231 is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MACH_REALTEK_RTL=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_I2C=y +CONFIG_MDIO_REALTEK_OTTO=y +CONFIG_MDIO_REALTEK_OTTO_AUX=y +CONFIG_MDIO_REALTEK_OTTO_SERDES=y +CONFIG_MDIO_SMBUS=y +# CONFIG_MFD_HASIVO_STC8 is not set +CONFIG_MFD_RTL8231=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_CLOCK_VSYSCALL=y +CONFIG_MIPS_CM=y +# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_MIPS_CMDLINE_FROM_DTB=y +CONFIG_MIPS_CPC=y +CONFIG_MIPS_CPS=y +# CONFIG_MIPS_CPS_NS16550_BOOL is not set +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_MIPS_EXTERNAL_TIMER=y +CONFIG_MIPS_GIC=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_MT=y +CONFIG_MIPS_MT_FPAFF=y +CONFIG_MIPS_MT_SMP=y +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_NR_CPU_NR_MAP=2 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_MIPS_SPRAM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_REALTEK=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_BRNIMAGE_FW=y +CONFIG_MTD_SPLIT_EVA_FW=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_TPLINK_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_VIRT_CONCAT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SRCU_NMI_SAFE=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_RTL83XX=y +# CONFIG_NET_DSA_RTL83XX_RTL930X_L3_OFFLOAD is not set +CONFIG_NET_DSA_TAG_RTL_OTTO=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_RTL838X=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NO_EXCEPT_FILL=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NR_CPUS=4 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PCS_RTL_OTTO=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_RTL8231=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REALTEK_OTTO_TIMER=y +CONFIG_REALTEK_OTTO_WDT=y +CONFIG_REALTEK_PHY_MULTIPORT=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +# CONFIG_RTL838X is not set +# CONFIG_RTL839X is not set +CONFIG_RTL930X=y +CONFIG_RTL931X=y +CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_LM75=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SFP=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_REALTEK_SNAND=y +CONFIG_SWPHY=y +CONFIG_SYNC_R4K=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MIPS_CPS=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_SYS_SUPPORTS_VPE_LOADER=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y +CONFIG_USE_OF=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WEAK_ORDERING=y +CONFIG_XPS=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y