qualcommax: ipq60xx: add CMN PLL clock controller support

Add IPQ6018 support to the upstream CMN PLL driver. The CMN PLL at
0x9b000 generates the 12 GHz base clock feeding the networking
subsystem. Its output clocks (bias_pll_cc_clk at 300 MHz and
bias_pll_nss_noc_clk at 416.5 MHz) replace the previous fixed-clock
stubs and are found by GCC via global clock name lookup.

Signed-off-by: John Crispin <john@phrozen.org>

target/linux/qualcommax/ipq60xx/config-default

@@ -1,3 +1,4 @@
+CONFIG_IPQ_CMN_PLL=y
 CONFIG_IPQ_GCC_6018=y
 CONFIG_MTD_SPLIT_FIT_FW=y
 CONFIG_PINCTRL_IPQ6018=y

target/linux/qualcommax/patches-6.12/0913-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ6018.patch

@@ -0,0 +1,33 @@
+From: John Crispin <john@phrozen.org>
+Date: Wed, 05 Mar 2026 12:00:00 +0100
+Subject: dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018
+
+The CMN PLL block in the IPQ6018 SoC takes 48 MHz as the reference
+input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
+bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
+subsystem.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+ create mode 100644 include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h
+
+--- /dev/null
++++ b/include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
++ */
++
++#ifndef _DT_BINDINGS_CLK_QCOM_IPQ6018_CMN_PLL_H
++#define _DT_BINDINGS_CLK_QCOM_IPQ6018_CMN_PLL_H
++
++/* CMN PLL core clock. */
++#define IPQ6018_CMN_PLL_CLK			0
++
++/* The output clocks from CMN PLL of IPQ6018. */
++#define IPQ6018_BIAS_PLL_CC_CLK			1
++#define IPQ6018_BIAS_PLL_NSS_NOC_CLK		2
++#endif

target/linux/qualcommax/patches-6.12/0914-clk-qcom-ipq-cmn-pll-Add-IPQ6018-SoC-support.patch

@@ -0,0 +1,44 @@
+From: John Crispin <john@phrozen.org>
+Date: Wed, 05 Mar 2026 12:00:00 +0100
+Subject: clk: qcom: ipq-cmn-pll: Add IPQ6018 SoC support
+
+The CMN PLL in IPQ6018 SoC supplies fixed clocks to the networking
+subsystem: bias_pll_cc_clk at 300 MHz and bias_pll_nss_noc_clk at
+416.5 MHz.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/clk/qcom/ipq-cmn-pll.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/clk/qcom/ipq-cmn-pll.c
++++ b/drivers/clk/qcom/ipq-cmn-pll.c
+@@ -52,6 +52,7 @@
+ #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
+ #include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h>
+ #include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
++#include <dt-bindings/clock/qcom,ipq6018-cmn-pll.h>
+ 
+ #define CMN_PLL_REFCLK_SRC_SELECTION		0x28
+ #define CMN_PLL_REFCLK_SRC_DIV			GENMASK(9, 8)
+@@ -118,6 +119,12 @@ static const struct cmn_pll_fixed_output
+ 	{ /* Sentinel */ }
+ };
+ 
++static const struct cmn_pll_fixed_output_clk ipq6018_output_clks[] = {
++	CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_CC_CLK, "bias_pll_cc_clk", 300000000UL),
++	CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_NSS_NOC_CLK, "bias_pll_nss_noc_clk", 416500000UL),
++	{ /* Sentinel */ }
++};
++
+ static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = {
+ 	CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
+ 	CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
+@@ -456,6 +463,7 @@ static const struct dev_pm_ops ipq_cmn_p
+ static const struct of_device_id ipq_cmn_pll_clk_ids[] = {
+ 	{ .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks },
+ 	{ .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks },
++	{ .compatible = "qcom,ipq6018-cmn-pll", .data = &ipq6018_output_clks },
+ 	{ .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks },
+ 	{ }
+ };