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d1: refresh config for 6.18
Refresh config for 6.18. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
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@ -1,4 +1,5 @@
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CONFIG_64BIT=y
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# CONFIG_ACLINT_SSWI is not set
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# CONFIG_ACPI is not set
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# CONFIG_ARCH_CANAAN is not set
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CONFIG_ARCH_DMA_ADDR_T_64BIT=y
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@ -264,6 +265,7 @@ CONFIG_PAGE_POOL=y
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CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
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CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
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CONFIG_PANIC_TIMEOUT=0
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# CONFIG_PCIE_DW_DEBUGFS is not set
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CONFIG_PCS_XPCS=y
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CONFIG_PER_VMA_LOCK=y
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CONFIG_PGTABLE_LEVELS=5
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@ -342,30 +344,41 @@ CONFIG_RISCV_ALTERNATIVE_EARLY=y
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CONFIG_RISCV_APLIC=y
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CONFIG_RISCV_APLIC_MSI=y
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CONFIG_RISCV_BOOT_SPINWAIT=y
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CONFIG_RISCV_COMBO_SPINLOCKS=y
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CONFIG_RISCV_DMA_NONCOHERENT=y
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# CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS is not set
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CONFIG_RISCV_IMSIC=y
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CONFIG_RISCV_INTC=y
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# CONFIG_RISCV_IOMMU is not set
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CONFIG_RISCV_ISA_C=y
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CONFIG_RISCV_ISA_FALLBACK=y
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CONFIG_RISCV_ISA_SUPM=y
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CONFIG_RISCV_ISA_SVNAPOT=y
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CONFIG_RISCV_ISA_SVPBMT=y
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CONFIG_RISCV_ISA_V=y
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CONFIG_RISCV_ISA_VENDOR_EXT=y
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CONFIG_RISCV_ISA_VENDOR_EXT_ANDES=y
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# CONFIG_RISCV_ISA_VENDOR_EXT_MIPS is not set
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CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE=y
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# CONFIG_RISCV_ISA_VENDOR_EXT_THEAD is not set
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CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y
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CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD=768
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# CONFIG_RISCV_ISA_XTHEADVECTOR is not set
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CONFIG_RISCV_ISA_ZACAS=y
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CONFIG_RISCV_ISA_ZAWRS=y
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CONFIG_RISCV_ISA_ZBA=y
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CONFIG_RISCV_ISA_ZBB=y
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CONFIG_RISCV_ISA_ZBC=y
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CONFIG_RISCV_ISA_ZBKB=y
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CONFIG_RISCV_ISA_ZICBOM=y
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CONFIG_RISCV_ISA_ZICBOP=y
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CONFIG_RISCV_ISA_ZICBOZ=y
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CONFIG_RISCV_MISALIGNED=y
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CONFIG_RISCV_NONSTANDARD_CACHE_OPS=y
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CONFIG_RISCV_PROBE_UNALIGNED_ACCESS=y
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CONFIG_RISCV_SBI=y
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CONFIG_RISCV_SBI_V01=y
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# CONFIG_RISCV_TICKET_SPINLOCKS is not set
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CONFIG_RISCV_TIMER=y
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CONFIG_RISCV_USE_LINKER_RELAXATION=y
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# CONFIG_RPS is not set
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