diff --git a/target/linux/ramips/patches-6.18/831-03-mmc-mtk-sd-use-default-PATCH_BIT1-2-values-for-mt762.patch b/target/linux/ramips/patches-6.18/831-03-mmc-mtk-sd-use-default-PATCH_BIT1-2-values-for-mt762.patch
index 3142870aee..be705aeb93 100644
--- a/target/linux/ramips/patches-6.18/831-03-mmc-mtk-sd-use-default-PATCH_BIT1-2-values-for-mt762.patch
+++ b/target/linux/ramips/patches-6.18/831-03-mmc-mtk-sd-use-default-PATCH_BIT1-2-values-for-mt762.patch
@@ -1,30 +1,38 @@
 From: Shiji Yang <yangshiji66@outlook.com>
-Date: Sat, 24 May 2025 15:53:26 +0800
+Date: Wed, 18 Jun 2025 22:35:12 +0800
 Subject: [PATCH 3/3] mmc: mtk-sd: use default PATCH_BIT1/2 values for mt7620
 
-The definitions of these two registers seem to be slightly different
-from other variants. Use their default values to follow the vendor
-SDK driver behaviors.
+The register map definitions of these PATCH_BIT registers seem to be
+slightly different from other variants. Use their default values to
+respect the vendor SDK driver behaviors.
 
 Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
 ---
- drivers/mmc/host/mtk-sd.c | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
+ drivers/mmc/host/mtk-sd.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
 
 --- a/drivers/mmc/host/mtk-sd.c
 +++ b/drivers/mmc/host/mtk-sd.c
-@@ -1804,9 +1804,11 @@ static void msdc_init_hw(struct msdc_hos
- 	}
- 	writel(0, host->base + MSDC_IOCON);
- 	sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
--	writel(0x403c0046, host->base + MSDC_PATCH_BIT);
--	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
--	writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
+@@ -1955,7 +1955,8 @@ static void msdc_init_hw(struct msdc_hos
+ 	val |= FIELD_PREP(MSDC_CKGEN_MSDC_DLY_SEL, 1);
+ 
+ 	/* First MSDC_PATCH_BIT setup is done: pull the trigger! */
+-	writel(val, host->base + MSDC_PATCH_BIT);
++	if (!host->dev_comp->mips_mt762x)
++		writel(val, host->base + MSDC_PATCH_BIT);
+ 
+ 	/* Set wr data, crc status, cmd response turnaround period for UHS104 */
+ 	pb1_val = FIELD_PREP(MSDC_PB1_WRDAT_CRC_TACNTR, 1);
+@@ -2018,8 +2019,10 @@ static void msdc_init_hw(struct msdc_hos
+ 		pb2_val |= MSDC_PB2_SUPPORT_64G;
+ 
+ 	/* Patch Bit 1/2 setup is done: pull the trigger! */
+-	writel(pb1_val, host->base + MSDC_PATCH_BIT1);
+-	writel(pb2_val, host->base + MSDC_PATCH_BIT2);
 +	if (!host->dev_comp->mips_mt762x) {
-+		writel(0x403c0046, host->base + MSDC_PATCH_BIT);
-+		sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
-+		writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
++		writel(pb1_val, host->base + MSDC_PATCH_BIT1);
++		writel(pb2_val, host->base + MSDC_PATCH_BIT2);
 +	}
  	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
  
- 	if (host->dev_comp->stop_clk_fix) {
+ 	if (host->dev_comp->data_tune) {