realtek: dsa: remove ops structures from family check

dsa_switch_ops and phylink_mac_ops do not need to be assigned
by a family check. Instead they can be directly linked in the
configuration structure.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22749
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Markus Stockhausen 2026-04-03 09:10:59 +02:00 committed by Hauke Mehrtens
parent acf9796d7d
commit a3442aa95c
6 changed files with 16 additions and 11 deletions

View File

@ -1584,14 +1584,18 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
if (!priv)
return -ENOMEM;
priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
priv->r = device_get_match_data(&pdev->dev);
priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
if (!priv->ds)
return -ENOMEM;
priv->ds->dev = dev;
priv->ds->priv = priv;
priv->ds->ops = &rtldsa_83xx_switch_ops;
priv->ds->needs_standalone_vlan_filtering = true;
priv->ds->ops = priv->r->switch_ops;
priv->ds->phylink_mac_ops = priv->r->phylink_mac_ops;
priv->dev = dev;
dev_set_drvdata(dev, priv);
@ -1603,35 +1607,26 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
if (err)
return err;
priv->r = device_get_match_data(&pdev->dev);
priv->family_id = soc_info.family;
priv->id = soc_info.id;
switch (soc_info.family) {
case RTL8380_FAMILY_ID:
priv->ds->ops = &rtldsa_83xx_switch_ops;
priv->ds->phylink_mac_ops = &rtldsa_83xx_phylink_mac_ops;
priv->ds->num_lag_ids = 8;
priv->l2_bucket_size = 4;
priv->n_mst = 64;
break;
case RTL8390_FAMILY_ID:
priv->ds->ops = &rtldsa_83xx_switch_ops;
priv->ds->phylink_mac_ops = &rtldsa_83xx_phylink_mac_ops;
priv->ds->num_lag_ids = 16;
priv->l2_bucket_size = 4;
priv->n_mst = 256;
break;
case RTL9300_FAMILY_ID:
priv->ds->ops = &rtldsa_93xx_switch_ops;
priv->ds->phylink_mac_ops = &rtldsa_93xx_phylink_mac_ops;
priv->ds->num_lag_ids = 16;
sw_w32(0, RTL930X_ST_CTRL);
priv->l2_bucket_size = 8;
priv->n_mst = 64;
break;
case RTL9310_FAMILY_ID:
priv->ds->ops = &rtldsa_93xx_switch_ops;
priv->ds->phylink_mac_ops = &rtldsa_93xx_phylink_mac_ops;
priv->ds->num_lag_ids = 16;
sw_w32(0, RTL931x_ST_CTRL);
priv->l2_bucket_size = 8;

View File

@ -1807,6 +1807,8 @@ int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group,
struct netdev_lag_upper_info *info);
const struct rtldsa_config rtldsa_838x_cfg = {
.switch_ops = &rtldsa_83xx_switch_ops,
.phylink_mac_ops = &rtldsa_83xx_phylink_mac_ops,
.cpu_port = RTL838X_CPU_PORT,
.fib_entries = 8192,
.mask_port_reg_be = rtl838x_mask_port_reg,

View File

@ -1368,6 +1368,8 @@ struct rtldsa_mirror_config {
};
struct rtldsa_config {
const struct dsa_switch_ops *switch_ops;
const struct phylink_mac_ops *phylink_mac_ops;
void (*mask_port_reg_be)(u64 clear, u64 set, int reg);
void (*set_port_reg_be)(u64 set, int reg);
u64 (*get_port_reg_be)(int reg);

View File

@ -1722,6 +1722,8 @@ int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group,
struct netdev_lag_upper_info *info);
const struct rtldsa_config rtldsa_839x_cfg = {
.switch_ops = &rtldsa_83xx_switch_ops,
.phylink_mac_ops = &rtldsa_83xx_phylink_mac_ops,
.cpu_port = RTL839X_CPU_PORT,
.fib_entries = 16384,
.mask_port_reg_be = rtl839x_mask_port_reg_be,

View File

@ -2793,6 +2793,8 @@ static void rtldsa_930x_qos_init(struct rtl838x_switch_priv *priv)
}
const struct rtldsa_config rtldsa_930x_cfg = {
.switch_ops = &rtldsa_93xx_switch_ops,
.phylink_mac_ops = &rtldsa_93xx_phylink_mac_ops,
.cpu_port = RTL930X_CPU_PORT,
.fib_entries = 16384,
.mask_port_reg_be = rtl838x_mask_port_reg,

View File

@ -1934,6 +1934,8 @@ static void rtldsa_931x_qos_init(struct rtl838x_switch_priv *priv)
}
const struct rtldsa_config rtldsa_931x_cfg = {
.switch_ops = &rtldsa_93xx_switch_ops,
.phylink_mac_ops = &rtldsa_93xx_phylink_mac_ops,
.cpu_port = RTL931X_CPU_PORT,
.fib_entries = 16384, /* TODO: has 32K but code cannot handle that */
.mask_port_reg_be = rtl839x_mask_port_reg_be,