diff --git a/target/linux/ramips/dts/mt7628an.dtsi b/target/linux/ramips/dts/mt7628an.dtsi
index 7c37b952f3..bf39ec307b 100644
--- a/target/linux/ramips/dts/mt7628an.dtsi
+++ b/target/linux/ramips/dts/mt7628an.dtsi
@@ -232,6 +232,15 @@
 			reg = <0x5000 0x1000>;
 			#pwm-cells = <2>;
 
+			clocks = <&sysc MT76X8_CLK_PWM_TOP>,
+				 <&sysc MT76X8_CLK_PWM_MAIN>,
+				 <&sysc MT76X8_CLK_PWM_CH1>,
+				 <&sysc MT76X8_CLK_PWM_CH2>,
+				 <&sysc MT76X8_CLK_PWM_CH3>,
+				 <&sysc MT76X8_CLK_PWM_CH4>;
+			clock-names = "top", "main",
+				      "pwm1", "pwm2", "pwm3", "pwm4";
+
 			pinctrl-names = "default";
 			pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
 
diff --git a/target/linux/ramips/patches-6.12/101-clk-ralink-mtmips-add-pwm-clocks-for-mt76x8.patch b/target/linux/ramips/patches-6.12/101-clk-ralink-mtmips-add-pwm-clocks-for-mt76x8.patch
new file mode 100644
index 0000000000..94880f7e07
--- /dev/null
+++ b/target/linux/ramips/patches-6.12/101-clk-ralink-mtmips-add-pwm-clocks-for-mt76x8.patch
@@ -0,0 +1,42 @@
+From f0300b3fc74a71742eee50ac596166b5780e0df6 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Tue, 24 Feb 2026 19:19:14 +0800
+Subject: [PATCH] clk: ralink: mtmips: add pwm clocks for mt76x8
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/clk/ralink/clk-mtmips.c                  | 8 +++++++-
+ include/dt-bindings/clock/mediatek,mtmips-sysc.h | 6 ++++++
+ 2 files changed, 13 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/ralink/clk-mtmips.c
++++ b/drivers/clk/ralink/clk-mtmips.c
+@@ -222,7 +222,13 @@ static struct mtmips_clk mt76x8_pherip_c
+ 	{ CLK_PERIPH("10000d00.uart1", "periph") },
+ 	{ CLK_PERIPH("10000e00.uart2", "periph") },
+ 	{ CLK_PERIPH("10130000.mmc", "sdhc") },
+-	{ CLK_PERIPH("10300000.wmac", "xtal") }
++	{ CLK_PERIPH("10300000.wmac", "xtal") },
++	{ CLK_PERIPH("10005000.pwm-top", "periph") },
++	{ CLK_PERIPH("10005000.pwm-main", "periph") },
++	{ CLK_PERIPH("10005000.pwm-ch1", "periph") },
++	{ CLK_PERIPH("10005000.pwm-ch2", "periph") },
++	{ CLK_PERIPH("10005000.pwm-ch3", "periph") },
++	{ CLK_PERIPH("10005000.pwm-ch4", "periph") }
+ };
+ 
+ static int mtmips_register_pherip_clocks(struct device_node *np,
+--- a/include/dt-bindings/clock/mediatek,mtmips-sysc.h
++++ b/include/dt-bindings/clock/mediatek,mtmips-sysc.h
+@@ -126,5 +126,11 @@
+ #define MT76X8_CLK_UART2	15
+ #define MT76X8_CLK_MMC		16
+ #define MT76X8_CLK_WMAC		17
++#define MT76X8_CLK_PWM_TOP	18
++#define MT76X8_CLK_PWM_MAIN	19
++#define MT76X8_CLK_PWM_CH1	20
++#define MT76X8_CLK_PWM_CH2	21
++#define MT76X8_CLK_PWM_CH3	22
++#define MT76X8_CLK_PWM_CH4	23
+ 
+ #endif /* _DT_BINDINGS_CLK_MTMIPS_H */