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realtek: dsa: common MSTI initialization

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The dsa probing currently disable multiple spanning tree for RTL93xx
and keeps the bootloader setup for RTL83xx untouched. Additionally it
does this by checking for the family id. Refactor this to a common
"disable msti" setup.

To make it clear: From now on RTL83xx will also run in MSTI disabled
state. Tested on Linksys LGS310C.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22749
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Markus Stockhausen 2026-04-03 09:45:11 +02:00 committed by Hauke Mehrtens
parent e745ee3f13
commit 8ea46952d6
6 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c
View File

@ -1596,6 +1596,7 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
priv->ds->ops = priv->r->switch_ops;
priv->ds->phylink_mac_ops = priv->r->phylink_mac_ops;
priv->ds->num_lag_ids = priv->r->num_lag_ids;
priv->ds->num_ports = priv->r->cpu_port + 1;
priv->dev = dev;
dev_set_drvdata(dev, priv);
@ -1610,15 +1611,7 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
priv->family_id = soc_info.family;
priv->id = soc_info.id;
switch (soc_info.family) {
case RTL9300_FAMILY_ID:
sw_w32(0, RTL930X_ST_CTRL);
break;
case RTL9310_FAMILY_ID:
sw_w32(0, RTL931x_ST_CTRL);
break;
}
priv->ds->num_ports = priv->r->cpu_port + 1;
sw_w32(0, priv->r->spanning_tree_ctrl);
priv->irq_mask = GENMASK_ULL(priv->r->cpu_port - 1, 0);
err = rtl83xx_mdio_probe(priv);

1
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.c
View File

@ -1809,6 +1809,7 @@ int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group,
const struct rtldsa_config rtldsa_838x_cfg = {
.switch_ops = &rtldsa_83xx_switch_ops,
.phylink_mac_ops = &rtldsa_83xx_phylink_mac_ops,
.spanning_tree_ctrl = RTL838X_VLAN_STP_CTRL,
.l2_bucket_size = 4,
.n_mst = 64,
.num_lag_ids = 8,

5
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.h
View File

@ -292,8 +292,10 @@
#define MV_ACT_TRAP2CPU 2
#define MV_ACT_COPY2CPU 3
#define RTL838X_VLAN_STP_CTRL (0x3b20)
#define RTL839X_ST_CTRL (0x27e4)
#define RTL930X_ST_CTRL (0x8798)
#define RTL931x_ST_CTRL (0x8000)
#define RTL931X_ST_CTRL (0x8000)
#define RTL930X_L2_PORT_SABLK_CTRL (0x905c)
#define RTL930X_L2_PORT_DABLK_CTRL (0x9060)
@ -1422,6 +1424,7 @@ struct rtldsa_config {
u32 fib_entries;
int trk_ctrl;
int trk_hash_ctrl;
int spanning_tree_ctrl;
void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
void (*vlan_set_tagged)(u32 vlan, struct rtl838x_vlan_info *info);
void (*vlan_set_untagged)(u32 vlan, u64 portmask);

1
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl839x.c
View File

@ -1724,6 +1724,7 @@ int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group,
const struct rtldsa_config rtldsa_839x_cfg = {
.switch_ops = &rtldsa_83xx_switch_ops,
.phylink_mac_ops = &rtldsa_83xx_phylink_mac_ops,
.spanning_tree_ctrl = RTL839X_ST_CTRL,
.l2_bucket_size = 4,
.n_mst = 256,
.num_lag_ids = 16,

1
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c
View File

@ -2795,6 +2795,7 @@ static void rtldsa_930x_qos_init(struct rtl838x_switch_priv *priv)
const struct rtldsa_config rtldsa_930x_cfg = {
.switch_ops = &rtldsa_93xx_switch_ops,
.phylink_mac_ops = &rtldsa_93xx_phylink_mac_ops,
.spanning_tree_ctrl = RTL930X_ST_CTRL,
.l2_bucket_size = 8,
.n_mst = 64,
.num_lag_ids = 16,

1
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c
View File

@ -1936,6 +1936,7 @@ static void rtldsa_931x_qos_init(struct rtl838x_switch_priv *priv)
const struct rtldsa_config rtldsa_931x_cfg = {
.switch_ops = &rtldsa_93xx_switch_ops,
.phylink_mac_ops = &rtldsa_93xx_phylink_mac_ops,
.spanning_tree_ctrl = RTL931X_ST_CTRL,
.l2_bucket_size = 8,
.n_mst = 128,
.num_lag_ids = 16,