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kernel/ixp4xx: bump patches for v6.18
A bunch of the patches are now upstream, remove them, rename the remaining patch and refresh. Link: https://github.com/openwrt/openwrt/pull/22896 Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Linus Walleij
parent
c5f9a5e61c
commit
677c2fb19d
@ -1,41 +0,0 @@
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From eff2700d2ec99aac06fff0ad35cbc594bd3e04a8 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Mon, 10 Feb 2025 10:31:16 +0100
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Subject: [PATCH 1/2] ARM: dts: ixp4xx: Fix up PCI on WG302
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Looking at the board file for WG302 v2 was not a good idea
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because the GPIO IRQ for slot 2 differs, and v1 uses GPIO
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10 instead of GPIO 9. Fix it up.
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Link: https://lore.kernel.org/20250210-ixp4xx-dts-v1-2-6b752d745e04@linaro.org
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---
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.../dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts
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+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts
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@@ -57,7 +57,7 @@
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status = "okay";
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/*
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- * Taken from WG302 v2 PCI boardfile (wg302v2-pci.c)
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+ * Taken from WG302 v1 PCI boardfile (wg302v1-pci.c)
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* We have slots (IDSEL) 1 and 2 with one assigned IRQ
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* each handling all IRQs.
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*/
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@@ -70,10 +70,10 @@
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<0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */
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<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
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/* IDSEL 2 */
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- <0x1000 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 9 */
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- <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
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- <0x1000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 9 */
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- <0x1000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 9 */
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+ <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
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+ <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */
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+ <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */
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+ <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */
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};
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ethernet@c8009000 {
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@ -1,60 +0,0 @@
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From f8a9ef38de91ddffa51255d15589c460bb6d9916 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Mon, 10 Feb 2025 10:31:17 +0100
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Subject: [PATCH 2/2] ARM: dts: ixp4xx: Add Netgear WG302 v1 GPIOs
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This adds GPIO LED indicators, the reset GPIO RESET
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button on the Netgear WG302 v1 to the device tree.
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Link: https://lore.kernel.org/20250210-ixp4xx-dts-v1-3-6b752d745e04@linaro.org
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---
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.../ixp/intel-ixp42x-netgear-wg302v1.dts | 30 +++++++++++++++++++
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1 file changed, 30 insertions(+)
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--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts
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+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts
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@@ -8,6 +8,7 @@
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#include "intel-ixp42x.dtsi"
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#include <dt-bindings/input/input.h>
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+#include <dt-bindings/leds/common.h>
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/ {
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model = "Netgear WG302 v1";
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@@ -32,6 +33,35 @@
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serial0 = &uart1;
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};
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+ leds {
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+ compatible = "gpio-leds";
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+ test_led: led-test {
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+ color = <LED_COLOR_ID_AMBER>;
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+ function = "test";
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+ gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
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+ default-state = "off";
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+ };
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+ wlan_led: led-wlan {
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+ color = <LED_COLOR_ID_GREEN>;
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+ function = LED_FUNCTION_WLAN;
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+ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
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+ default-state = "off";
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+ linux,default-trigger = "phy0tx";
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+ };
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+ };
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+
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+ gpio_keys {
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+ /* RESET is on GPIO13 which can't fire interrupts */
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+ compatible = "gpio-keys-polled";
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+ poll-interval = <100>;
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+
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+ button-reset {
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+ linux,code = <KEY_RESTART>;
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+ label = "reset";
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+ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+
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soc {
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bus@c4000000 {
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flash@0,0 {
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@ -1,26 +0,0 @@
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From 38623d532c99ebd926f4eebb7c7de19cb7e5aef4 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Fri, 22 Aug 2025 17:46:28 +0200
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Subject: [PATCH] gpio: mmio: Add compatible for the ixp4xx eb MMIO
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The IXP4xx expansion bus can have simple memory-mapped GPIO
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on it. Using the proper device tree bindings, support probing
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this directly from the device tree.
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Link: https://lore.kernel.org/r/20250822-ixp4xx-eb-mmio-gpio-v2-3-bd2edd4a9c74@linaro.org
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Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
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---
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drivers/gpio/gpio-mmio.c | 1 +
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1 file changed, 1 insertion(+)
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--- a/drivers/gpio/gpio-mmio.c
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+++ b/drivers/gpio/gpio-mmio.c
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@@ -687,6 +687,7 @@ static const struct of_device_id bgpio_o
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{ .compatible = "brcm,bcm6345-gpio" },
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{ .compatible = "wd,mbl-gpio" },
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{ .compatible = "ni,169445-nand-gpio" },
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+ { .compatible = "intel,ixp4xx-expansion-bus-mmio-gpio" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, bgpio_of_match);
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@ -1,156 +0,0 @@
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From c9cc6b6a7d23eea7ada69a9185a550c4f0b62319 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Wed, 25 Jun 2025 08:51:25 +0200
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Subject: [PATCH] ARM: dts: Fix up wrv54g device tree
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Fix up the KS8995 switch and PHYs the way that is most likely:
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- Phy 1-4 is certainly the PHYs of the KS8995 (mask 0x1e in
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the outoftree code masks PHYs 1,2,3,4).
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- Phy 5 is the MII-P5 separate WAN phy of the KS8995 directly
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connected to EthC.
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- The EthB MII is probably connected as CPU interface to the
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KS8995.
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Properly integrate the KS8995 switch using the new bindings.
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Link: https://patch.msgid.link/20250625-ks8995-dsa-bindings-v2-2-ce71dce9be0b@linaro.org
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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.../intel/ixp/intel-ixp42x-linksys-wrv54g.dts | 92 ++++++++++++++++---
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1 file changed, 78 insertions(+), 14 deletions(-)
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--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
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+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
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@@ -72,10 +72,55 @@
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cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
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num-chipselects = <1>;
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- switch@0 {
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+ ethernet-switch@0 {
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compatible = "micrel,ks8995";
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reg = <0>;
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spi-max-frequency = <50000000>;
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+
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+ /*
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+ * The PHYs are accessed over the external MDIO
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+ * bus and not internally through the switch control
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+ * registers.
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+ */
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+ ethernet-ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ethernet-port@0 {
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+ reg = <0>;
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+ label = "1";
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+ phy-mode = "mii";
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+ phy-handle = <&phy1>;
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+ };
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+ ethernet-port@1 {
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+ reg = <1>;
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+ label = "2";
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+ phy-mode = "mii";
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+ phy-handle = <&phy2>;
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+ };
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+ ethernet-port@2 {
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+ reg = <2>;
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+ label = "3";
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+ phy-mode = "mii";
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+ phy-handle = <&phy3>;
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+ };
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+ ethernet-port@3 {
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+ reg = <3>;
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+ label = "4";
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+ phy-mode = "mii";
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+ phy-handle = <&phy4>;
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+ };
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+ ethernet-port@4 {
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+ reg = <4>;
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+ ethernet = <ðb>;
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+ phy-mode = "mii";
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+ fixed-link {
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+ speed = <100>;
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+ full-duplex;
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+ };
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+ };
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+
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+ };
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};
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};
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@@ -135,40 +180,59 @@
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};
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/*
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- * EthB - connected to the KS8995 switch ports 1-4
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- * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to
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- * all four switch ports, also using an out of tree multiphy patch.
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- * Do we need a new binding and property for this?
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+ * EthB connects to the KS8995 CPU port and faces ports 1-4
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+ * through the switch fabric.
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+ *
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+ * To complicate things, the MDIO channel is also only
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+ * accessible through EthB, but used independently for PHY
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+ * control.
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*/
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- ethernet@c8009000 {
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+ ethb: ethernet@c8009000 {
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status = "okay";
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queue-rx = <&qmgr 3>;
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queue-txready = <&qmgr 20>;
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- phy-mode = "rgmii";
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- phy-handle = <&phy4>;
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+ phy-mode = "mii";
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+ fixed-link {
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+ speed = <100>;
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+ full-duplex;
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+ };
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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- /* Should be ports 1-4 on the KS8995 switch */
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+ /*
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+ * LAN ports 1-4 on the KS8995 switch
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+ * and PHY5 for WAN need to be accessed
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+ * through this external MDIO channel.
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+ */
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+ phy1: ethernet-phy@1 {
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+ reg = <1>;
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+ };
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+ phy2: ethernet-phy@2 {
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+ reg = <2>;
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+ };
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+ phy3: ethernet-phy@3 {
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+ reg = <3>;
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+ };
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phy4: ethernet-phy@4 {
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reg = <4>;
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};
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-
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- /* Should be port 5 on the KS8995 switch */
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phy5: ethernet-phy@5 {
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reg = <5>;
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};
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};
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};
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- /* EthC - connected to KS8995 switch port 5 */
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- ethernet@c800a000 {
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+ /*
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+ * EthC connects to MII-P5 on the KS8995 bypassing
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+ * all of the switch logic and facing PHY5
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+ */
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+ ethc: ethernet@c800a000 {
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status = "okay";
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queue-rx = <&qmgr 4>;
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queue-txready = <&qmgr 21>;
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- phy-mode = "rgmii";
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+ phy-mode = "mii";
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phy-handle = <&phy5>;
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};
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};
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@ -1,391 +0,0 @@
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From 85ac6b806993200fe117f4fd047c74784ec6b515 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Fri, 22 Aug 2025 19:56:16 +0200
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Subject: [PATCH] ARM: dts: Add ixp4xx Actiontec MI424WR device trees
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The Actiontex MI424WR is a pretty widespread home router, made
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in many different revisions.
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Revisions A, C and D are based on IXP42x. We add a device tree
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for the A/C variant and one for the D variant as these differ in
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the location of the WAN PHY on the MDIO bus, and the ethernet
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interfaces for the WAN PHY and the DSA switch are switched around.
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-3-cc804884474d@linaro.org
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---
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arch/arm/boot/dts/intel/ixp/Makefile | 2 +
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.../ixp/intel-ixp42x-actiontec-mi424wr-ac.dts | 37 +++
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.../ixp/intel-ixp42x-actiontec-mi424wr-d.dts | 38 +++
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.../ixp/intel-ixp42x-actiontec-mi424wr.dtsi | 272 ++++++++++++++++++
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4 files changed, 349 insertions(+)
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create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts
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create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts
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create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi
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--- a/arch/arm/boot/dts/intel/ixp/Makefile
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+++ b/arch/arm/boot/dts/intel/ixp/Makefile
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@@ -1,5 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_IXP4XX) += \
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+ intel-ixp42x-actiontec-mi424wr-ac.dtb \
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+ intel-ixp42x-actiontec-mi424wr-d.dtb \
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intel-ixp42x-linksys-nslu2.dtb \
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intel-ixp42x-linksys-wrv54g.dtb \
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intel-ixp42x-freecom-fsg-3.dtb \
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--- /dev/null
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+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts
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@@ -0,0 +1,37 @@
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+// SPDX-License-Identifier: ISC
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+/*
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+ * Device Tree file for the IXP425-based Actiontec MI424WR revision A and C
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+ * Based on a board file from OpenWrt by Jose Vasconcellos.
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+ */
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+
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+/dts-v1/;
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+
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+#include "intel-ixp42x-actiontec-mi424wr.dtsi"
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+
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+/ {
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+ model = "Actiontec MI424WR rev A/C";
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+ compatible = "actiontec,mi424wr-ac", "intel,ixp42x";
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+
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+ soc {
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+ /* EthB used for WAN */
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+ ethernet@c8009000 {
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+ phy-handle = <&phy17>; // 17 on revision A-C
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+
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+ mdio {
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+ phy17: ethernet-phy@17 {
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+ /* WAN */
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+ reg = <17>;
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+ };
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+ };
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+ };
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+
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+ /* EthC used for LAN */
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+ ethernet@c800a000 {
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+ /* Fixed link to the CPU MII port on the KS8995 */
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+ fixed-link {
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+ speed = <100>;
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+ full-duplex;
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+ };
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts
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@@ -0,0 +1,38 @@
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+// SPDX-License-Identifier: ISC
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+/*
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+ * Device Tree file for the IXP425-based Actiontec MI424WR revision D
|
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+ * Based on a board file from OpenWrt by Jose Vasconcellos.
|
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+ */
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+
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+/dts-v1/;
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+
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+#include "intel-ixp42x-actiontec-mi424wr.dtsi"
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+
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+/ {
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+ model = "Actiontec MI424WR rev D";
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+ compatible = "actiontec,mi424wr-d", "intel,ixp42x";
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+
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+ soc {
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+ /* EthB used for LAN */
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+ ethernet@c8009000 {
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+ /* Fixed link to the CPU MII port on the KS8995 */
|
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+ fixed-link {
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+ speed = <100>;
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+ full-duplex;
|
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+ };
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+
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+ mdio {
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+ /* PHY ID 0x00221450 */
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+ phy5: ethernet-phy@5 {
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+ /* WAN */
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+ reg = <5>;
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+ };
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+ };
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+ };
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+
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+ /* EthC used for WAN */
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+ ethernet@c800a000 {
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+ phy-handle = <&phy5>; // 5 on revision D
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+ };
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+ };
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+};
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--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi
|
||||
@@ -0,0 +1,272 @@
|
||||
+// SPDX-License-Identifier: ISC
|
||||
+/*
|
||||
+ * Device Tree file for the IXP425-based Actiontec MI424WR
|
||||
+ * Based on a board file from OpenWrt by Jose Vasconcellos.
|
||||
+ */
|
||||
+
|
||||
+#include "intel-ixp42x.dtsi"
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ memory@0 {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x00000000 0x02000000>;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,115200n8";
|
||||
+ stdout-path = "uart1:115200n8";
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ led-wan-coax {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = "wan-coax";
|
||||
+ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-power-alarm {
|
||||
+ color = <LED_COLOR_ID_RED>;
|
||||
+ function = LED_FUNCTION_ALARM;
|
||||
+ gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-power {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_POWER;
|
||||
+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "on";
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ };
|
||||
+ led-wireless {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_WLAN;
|
||||
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-internet-down {
|
||||
+ color = <LED_COLOR_ID_RED>;
|
||||
+ function = "internet-down";
|
||||
+ gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-internet-up {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = "internet-up";
|
||||
+ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-lan-coax {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = "lan-coax";
|
||||
+ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-wan-ethernet-alarm {
|
||||
+ color = <LED_COLOR_ID_RED>;
|
||||
+ function = "wan-ethernet-alarm";
|
||||
+ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ /* The last three LEDs are not mounted but traces exist on the PCB */
|
||||
+ led-phone-1 {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = "phone-1";
|
||||
+ gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-phone-2 {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = "phone-2";
|
||||
+ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-voip {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = "voip";
|
||||
+ gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio_keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+
|
||||
+ button-reset {
|
||||
+ wakeup-source;
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ label = "reset";
|
||||
+ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ spi {
|
||||
+ compatible = "spi-gpio";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ sck-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
|
||||
+ mosi-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
|
||||
+ miso-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
|
||||
+ cs-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
|
||||
+ num-chipselects = <1>;
|
||||
+
|
||||
+ ethernet-switch@0 {
|
||||
+ compatible = "micrel,ks8995";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <50000000>;
|
||||
+
|
||||
+ ethernet-ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ ethernet-port@0 {
|
||||
+ reg = <0>;
|
||||
+ label = "lan1";
|
||||
+ phy-mode = "mii";
|
||||
+ phy-handle = <&phy1>;
|
||||
+ };
|
||||
+ ethernet-port@1 {
|
||||
+ reg = <1>;
|
||||
+ label = "lan2";
|
||||
+ phy-mode = "mii";
|
||||
+ phy-handle = <&phy2>;
|
||||
+ };
|
||||
+ ethernet-port@2 {
|
||||
+ reg = <2>;
|
||||
+ label = "lan3";
|
||||
+ phy-mode = "mii";
|
||||
+ phy-handle = <&phy3>;
|
||||
+ };
|
||||
+ ethernet-port@3 {
|
||||
+ reg = <3>;
|
||||
+ label = "lan4";
|
||||
+ phy-mode = "mii";
|
||||
+ phy-handle = <&phy4>;
|
||||
+ };
|
||||
+ ethernet-port@4 {
|
||||
+ reg = <4>;
|
||||
+ ethernet = <ðc>;
|
||||
+ phy-mode = "mii";
|
||||
+ fixed-link {
|
||||
+ speed = <100>;
|
||||
+ full-duplex;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ soc {
|
||||
+ bus@c4000000 {
|
||||
+ flash@0,0 {
|
||||
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
|
||||
+ bank-width = <2>;
|
||||
+ /*
|
||||
+ * 8 MB of Flash in 64 0x20000 sized blocks
|
||||
+ * mapped in at CS0.
|
||||
+ */
|
||||
+ reg = <0 0x00000000 0x0800000>;
|
||||
+
|
||||
+ /* Configure expansion bus to allow writes */
|
||||
+ intel,ixp4xx-eb-write-enable = <1>;
|
||||
+
|
||||
+ partitions {
|
||||
+ compatible = "redboot-fis";
|
||||
+ fis-index-block = <0x3f>;
|
||||
+ };
|
||||
+ };
|
||||
+ gpio1: gpio@1,0 {
|
||||
+ /* MMIO GPIO at CS1 */
|
||||
+ compatible = "intel,ixp4xx-expansion-bus-mmio-gpio";
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+ big-endian;
|
||||
+ reg = <1 0x00000000 0x2>;
|
||||
+ reg-names = "dat";
|
||||
+ /* Expansion bus settings */
|
||||
+ intel,ixp4xx-eb-write-enable = <1>;
|
||||
+
|
||||
+ pci-reset-hog {
|
||||
+ gpio-hog;
|
||||
+ gpios = <7 GPIO_ACTIVE_HIGH>;
|
||||
+ output-high;
|
||||
+ line-name = "PCI reset";
|
||||
+ };
|
||||
+ pstn-relay-hog-1 {
|
||||
+ gpio-hog;
|
||||
+ gpios = <11 GPIO_ACTIVE_HIGH>;
|
||||
+ output-low;
|
||||
+ line-name = "PSTN relay control 1";
|
||||
+ };
|
||||
+ pstn-relay-hog-2 {
|
||||
+ gpio-hog;
|
||||
+ gpios = <12 GPIO_ACTIVE_HIGH>;
|
||||
+ output-low;
|
||||
+ line-name = "PSTN relay control 2";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pci@c0000000 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0xf800 0 0 7>;
|
||||
+ interrupt-map =
|
||||
+ /* IDSEL 13 */
|
||||
+ <0x6800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 8 */
|
||||
+ <0x6800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 6 */
|
||||
+ /* IDSEL 14 */
|
||||
+ <0x7000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
|
||||
+ <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 8 */
|
||||
+ /* IDSEL 15 */
|
||||
+ <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 6 */
|
||||
+ <0x7800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 15 is irq 7 */
|
||||
+ };
|
||||
+
|
||||
+ ethb: ethernet@c8009000 {
|
||||
+ status = "okay";
|
||||
+ queue-rx = <&qmgr 3>;
|
||||
+ queue-txready = <&qmgr 20>;
|
||||
+ phy-mode = "mii";
|
||||
+
|
||||
+ mdio {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ /* 1, 2, 3 and 4 are ports on the KS8995 switch */
|
||||
+ phy1: ethernet-phy@1 {
|
||||
+ /* LAN1 */
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+ phy2: ethernet-phy@2 {
|
||||
+ /* LAN2 */
|
||||
+ reg = <2>;
|
||||
+ };
|
||||
+ phy3: ethernet-phy@3 {
|
||||
+ /* LAN3 */
|
||||
+ reg = <3>;
|
||||
+ };
|
||||
+ phy4: ethernet-phy@4 {
|
||||
+ /* LAN4 */
|
||||
+ reg = <4>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ethc: ethernet@c800a000 {
|
||||
+ status = "okay";
|
||||
+ queue-rx = <&qmgr 4>;
|
||||
+ queue-txready = <&qmgr 21>;
|
||||
+ phy-mode = "mii";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
Loading…
x
Reference in New Issue
Block a user