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realtek: mdio: use regmap_bulk_write() in RTL839x path

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Convert the RTL839x I/O path to the new bulk write pattern. For this

- Enhance the rtmdio_839x_run_cmd() helper to take care of all register
  access and error handling.
- Convert the c22/c45/read/write functions so that they only prepare
  the I/O data without any register access.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23092
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Markus Stockhausen 2026-04-27 18:58:59 +02:00 committed by Hauke Mehrtens
parent 2d2f0fbc70
commit 5915fa8b74
1 changed files with 58 additions and 46 deletions
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104
target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c
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@ -51,8 +51,8 @@
#define RTMDIO_838X_SMI_POLL_CTRL (0xa17c)
#define RTMDIO_838X_SMI_PORT0_5_ADDR_CTRL (0xa1c8)
#define RTMDIO_839X_PHYREG_CTRL (0x03E0)
#define RTMDIO_839X_PHYREG_PORT_CTRL (0x03E4)
#define RTMDIO_839X_C22_DATA(page, reg) ((reg) << 5 | (page) << 10 | \
(((page) == 8191) ? 0x1f : 0) << 23)
#define RTMDIO_839X_PHYREG_ACCESS_CTRL (0x03DC)
#define RTMDIO_839X_CMD_FAIL BIT(1)
#define RTMDIO_839X_CMD_READ_C22 0
@ -61,7 +61,6 @@
#define RTMDIO_839X_CMD_WRITE_C45 (BIT(2) | BIT(3))
#define RTMDIO_839X_CMD_MASK GENMASK(3, 0)
#define RTMDIO_839X_PHYREG_DATA_CTRL (0x03F0)
#define RTMDIO_839X_PHYREG_MMD_CTRL (0x03F4)
#define RTMDIO_839X_SMI_PORT_POLLING_CTRL (0x03fc)
#define RTMDIO_839X_SMI_GLB_CTRL (0x03f8)
@ -235,6 +234,16 @@ struct rtmdio_838x_smi_access {
u32 ctrl_3;
};
struct rtmdio_839x_smi_access {
u32 accs_ctrl;
u32 main_ctrl;
u32 prt0_ctrl;
u32 prt1_ctrl;
u32 bcst_ctrl;
u32 data_ctrl;
u32 mmd0_ctrl;
};
static int rtmdio_phy_to_port(struct mii_bus *bus, int phy)
{
struct rtmdio_chan *chan = bus->priv;
@ -332,70 +341,73 @@ static int rtmdio_838x_write_mmd_phy(struct mii_bus *bus, u32 pn, u32 devnum, u3
return rtmdio_838x_run_cmd(bus, RTMDIO_838X_CMD_WRITE_C45, &smi_access, NULL);
}
static int rtmdio_839x_run_cmd(struct mii_bus *bus, int cmd)
static int rtmdio_839x_run_cmd(struct mii_bus *bus, int cmd,
struct rtmdio_839x_smi_access *smi_access, u32 *val)
{
return rtmdio_run_cmd(bus, cmd, RTMDIO_839X_CMD_MASK,
RTMDIO_839X_PHYREG_ACCESS_CTRL, RTMDIO_839X_CMD_FAIL);
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
int ret;
ret = regmap_bulk_write(ctrl->map, RTMDIO_839X_PHYREG_ACCESS_CTRL,
smi_access, sizeof(*smi_access) / sizeof(u32));
if (ret)
return ret;
ret = rtmdio_run_cmd(bus, cmd, RTMDIO_839X_CMD_MASK,
RTMDIO_839X_PHYREG_ACCESS_CTRL, RTMDIO_839X_CMD_FAIL);
if (ret || !val)
return ret;
ret = regmap_read(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, val);
if (!ret)
*val &= RTMDIO_DATA_MASK;
return ret;
}
static int rtmdio_839x_read_phy(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
int err;
struct rtmdio_839x_smi_access smi_access = {
.main_ctrl = 0x1ff,
.data_ctrl = pn << 16,
.accs_ctrl = RTMDIO_839X_C22_DATA(page, reg),
};
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_CTRL, 0x1ff);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, pn << 16);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_ACCESS_CTRL,
reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23);
err = rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_READ_C22);
if (!err)
err = regmap_read(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, val);
if (!err)
*val &= GENMASK(15, 0);
return err;
return rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_READ_C22, &smi_access, val);
}
static int rtmdio_839x_write_phy(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
struct rtmdio_839x_smi_access smi_access = {
.main_ctrl = 0x1ff,
.data_ctrl = val << 16,
.prt0_ctrl = (u32)(BIT_ULL(pn)),
.prt1_ctrl = (u32)(BIT_ULL(pn) >> 32),
.accs_ctrl = RTMDIO_839X_C22_DATA(page, reg),
};
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_CTRL, 0x1ff);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, val << 16);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL, BIT_ULL(pn));
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL + 4, BIT_ULL(pn) >> 32);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_ACCESS_CTRL,
reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23);
return rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_WRITE_C22);
return rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_WRITE_C22, &smi_access, NULL);
}
static int rtmdio_839x_read_mmd_phy(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
int err;
struct rtmdio_839x_smi_access smi_access = {
.data_ctrl = pn << 16,
.mmd0_ctrl = RTMDIO_C45_DATA(devnum, regnum),
};
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, pn << 16);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_MMD_CTRL, (devnum << 16) | (regnum & 0xffff));
err = rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_READ_C45);
if (!err)
err = regmap_read(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, val);
if (!err)
*val &= GENMASK(15, 0);
return err;
return rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_READ_C45, &smi_access, val);
}
static int rtmdio_839x_write_mmd_phy(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
struct rtmdio_839x_smi_access smi_access = {
.data_ctrl = val << 16,
.prt0_ctrl = (u32)(BIT_ULL(pn)),
.prt1_ctrl = (u32)(BIT_ULL(pn) >> 32),
.mmd0_ctrl = RTMDIO_C45_DATA(devnum, regnum),
};
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL, BIT_ULL(pn));
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL + 4, BIT_ULL(pn) >> 32);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, val << 16);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_MMD_CTRL, (devnum << 16) | (regnum & 0xffff));
return rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_WRITE_C45);
return rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_WRITE_C45, &smi_access, NULL);
}
static int rtmdio_930x_run_cmd(struct mii_bus *bus, int cmd)