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mediatek: filogic: kn-1812: fix phy reset deassert

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The RTL8261BE 10GbE PHY's `reset-deassert-us` was set to 100ms (100000us),
but the **RTL8261N datasheet (Table 108, parameter t7)** specifies a
minimum **SMI-ready time of 150ms** after nRESET release before the MDIO
(SMI) bus can be used.

Note: Essentially, the RTL8261N and RTL8261BE are architecturally identical
chips, so their initialization parameters should be consistent.

Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22575
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Maxim Anisimov 2026-03-23 09:19:30 +03:00 committed by Hauke Mehrtens
parent 3487722fbf
commit 44a52a8769
1 changed files with 1 additions and 1 deletions
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target/linux/mediatek/dts/mt7988d-keenetic-kn-1812.dtsi
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@ -400,7 +400,7 @@
reset-gpios = <&pio 4 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
reset-deassert-us = <100000>;
reset-deassert-us = <221000>;
};
};