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realtek: mdio: convert to regmap_assign_bits()
Use regmap_assign_bits() where it improves readability. With this there is no need to calculate masks and values in separate lines. Splitting the single update_bits() in rtmdio_931x_setup_polling() into two separate assign_bits() is uncritical. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/23099 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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@ -739,14 +739,10 @@ static int rtmdio_839x_setup_ctrl(struct rtmdio_ctrl *ctrl)
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static int rtmdio_930x_setup_ctrl(struct rtmdio_ctrl *ctrl)
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{
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unsigned int mask, val;
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/* Define C22/C45 bus feature set */
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for (int smi_bus = 0; smi_bus < RTMDIO_MAX_SMI_BUSSES; smi_bus++) {
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mask = BIT(16 + smi_bus);
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val = ctrl->bus[smi_bus].is_c45 ? mask : 0;
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regmap_update_bits(ctrl->map, RTMDIO_930X_SMI_GLB_CTRL, mask, val);
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}
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for (int smi_bus = 0; smi_bus < RTMDIO_MAX_SMI_BUSSES; smi_bus++)
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regmap_assign_bits(ctrl->map, RTMDIO_930X_SMI_GLB_CTRL,
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BIT(16 + smi_bus), ctrl->bus[smi_bus].is_c45);
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return 0;
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}
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@ -770,14 +766,12 @@ static void rtmdio_930x_setup_polling(struct rtmdio_ctrl *ctrl)
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regmap_update_bits(ctrl->map, RTMDIO_930X_SMI_MAC_TYPE_CTRL, mask, val);
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/* polling via standard or resolution register */
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mask = BIT(20 + ctrl->port[pn].smi_bus);
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val = phyinfo.has_res_reg ? mask : 0;
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regmap_update_bits(ctrl->map, RTMDIO_930X_SMI_GLB_CTRL, mask, val);
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regmap_assign_bits(ctrl->map, RTMDIO_930X_SMI_GLB_CTRL,
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BIT(20 + ctrl->port[pn].smi_bus), phyinfo.has_res_reg);
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/* proprietary Realtek 1G/2.5 lite polling */
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mask = BIT(pn);
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val = phyinfo.has_giga_lite ? mask : 0;
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regmap_update_bits(ctrl->map, RTMDIO_930X_SMI_PRVTE_POLLING_CTRL, mask, val);
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regmap_assign_bits(ctrl->map, RTMDIO_930X_SMI_PRVTE_POLLING_CTRL,
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BIT(pn), phyinfo.has_giga_lite);
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/* special duplex/advertisement polling registers */
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if (phyinfo.poll_duplex || phyinfo.poll_adv_1000 || phyinfo.poll_lpa_1000) {
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@ -830,24 +824,17 @@ static void rtmdio_931x_setup_polling(struct rtmdio_ctrl *ctrl)
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val = RTMDIO_931X_SMI_PHY_ABLTY_MDIO << (ffs(mask) - 1);
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regmap_update_bits(ctrl->map, RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL + (pn / 16) * 4,
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mask, val);
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mask = val = 0;
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/* PRVTE0 polling */
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mask |= BIT(20 + smi_bus);
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if (phyinfo.has_res_reg)
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val |= BIT(20 + smi_bus);
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regmap_assign_bits(ctrl->map, RTMDIO_931X_SMI_GLB_CTRL0,
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BIT(20 + smi_bus), phyinfo.has_res_reg);
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/* PRVTE1 polling */
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mask |= BIT(24 + smi_bus);
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if (phyinfo.force_res)
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val |= BIT(24 + smi_bus);
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regmap_update_bits(ctrl->map, RTMDIO_931X_SMI_GLB_CTRL0, mask, val);
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regmap_assign_bits(ctrl->map, RTMDIO_931X_SMI_GLB_CTRL0,
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BIT(24 + smi_bus), phyinfo.force_res);
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/* polling std. or proprietary format (bit 0 of SMI_SETX_FMT_SEL) */
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mask = BIT(smi_bus * 2);
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val = phyinfo.force_res ? mask : 0;
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regmap_update_bits(ctrl->map, RTMDIO_931X_SMI_GLB_CTRL1, mask, val);
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regmap_assign_bits(ctrl->map, RTMDIO_931X_SMI_GLB_CTRL1,
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BIT(smi_bus * 2), phyinfo.force_res);
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/* special polling registers */
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if (phyinfo.poll_duplex || phyinfo.poll_adv_1000 || phyinfo.poll_lpa_1000) {
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