/dts-v1/;

#include "rtl839x.dtsi"

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	compatible = "zyxel,gs1900-48-a1", "realtek,rtl8393-soc";
	model = "Zyxel GS1900-48 A1";

	aliases {
		led-boot = &led_sys;
		led-failsafe = &led_sys;
		led-running = &led_sys;
		led-upgrade = &led_sys;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x8000000>;
	};

	leds {
		pinctrl-names = "default";
		pinctrl-0 = <&pinmux_disable_sys_led>;
		compatible = "gpio-leds";

		led_sys: sys {
			label = "green:sys";
			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
		};
	};

	keys {
		compatible = "gpio-keys-polled";
		poll-interval = <20>;

		reset {
			label = "reset";
			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
			debounce-interval = <100>;
		};
	};

	/* i2c of the left SFP cage: port 49 */
	i2c0: i2c-gpio-0 {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		i2c-gpio,delay-us = <2>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	sfp0: sfp-p49 {
		compatible = "sff,sfp";
		i2c-bus = <&i2c0>;
		los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
		tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
		mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
		tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
	};

	/* i2c of the right SFP cage: port 50 */
	i2c1: i2c-gpio-1 {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		i2c-gpio,delay-us = <2>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	sfp1: sfp-p50 {
		compatible = "sff,sfp";
		i2c-bus = <&i2c1>;
		los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
		tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
		mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
		tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
	};
};

&mdio_aux {
	status = "okay";

	gpio1: expander@3 {
		compatible = "realtek,rtl8231";
		reg = <3>;

		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&gpio1 0 0 37>;

		led-controller {
			compatible = "realtek,rtl8231-leds";
			status = "disabled";
		};
	};
};

&spi0 {
	status = "okay";
	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0x40000>;
				read-only;
			};
			partition@40000 {
				label = "u-boot-env";
				reg = <0x40000 0x10000>;
			};
			partition@50000 {
				label = "u-boot-env2";
				reg = <0x50000 0x10000>;
			};
			partition@60000 {
				label = "jffs";
				reg = <0x60000 0x100000>;
			};
			partition@160000 {
				label = "jffs2";
				reg = <0x160000 0x100000>;
			};
			partition@260000 {
				label = "firmware";
				reg = <0x260000 0xda0000>;
				compatible = "openwrt,uimage", "denx,uimage";
				openwrt,ih-magic = <0x83800000>;
			};
		};
	};
};

&mdio_bus0 {
	/* External phy RTL8218B #1 */
	EXTERNAL_PHY(0)
	EXTERNAL_PHY(1)
	EXTERNAL_PHY(2)
	EXTERNAL_PHY(3)
	EXTERNAL_PHY(4)
	EXTERNAL_PHY(5)
	EXTERNAL_PHY(6)
	EXTERNAL_PHY(7)

	/* External phy RTL8218B #2 */
	EXTERNAL_PHY(8)
	EXTERNAL_PHY(9)
	EXTERNAL_PHY(10)
	EXTERNAL_PHY(11)
	EXTERNAL_PHY(12)
	EXTERNAL_PHY(13)
	EXTERNAL_PHY(14)
	EXTERNAL_PHY(15)

	/* External phy RTL8218B #3 */
	EXTERNAL_PHY(16)
	EXTERNAL_PHY(17)
	EXTERNAL_PHY(18)
	EXTERNAL_PHY(19)
	EXTERNAL_PHY(20)
	EXTERNAL_PHY(21)
	EXTERNAL_PHY(22)
	EXTERNAL_PHY(23)

	/* External phy RTL8218B #4 */
	EXTERNAL_PHY(24)
	EXTERNAL_PHY(25)
	EXTERNAL_PHY(26)
	EXTERNAL_PHY(27)
	EXTERNAL_PHY(28)
	EXTERNAL_PHY(29)
	EXTERNAL_PHY(30)
	EXTERNAL_PHY(31)

	/* External phy RTL8218B #5 */
	EXTERNAL_PHY(32)
	EXTERNAL_PHY(33)
	EXTERNAL_PHY(34)
	EXTERNAL_PHY(35)
	EXTERNAL_PHY(36)
	EXTERNAL_PHY(37)
	EXTERNAL_PHY(38)
	EXTERNAL_PHY(39)

	/* External phy RTL8218B #6 */
	EXTERNAL_PHY(40)
	EXTERNAL_PHY(41)
	EXTERNAL_PHY(42)
	EXTERNAL_PHY(43)
	EXTERNAL_PHY(44)
	EXTERNAL_PHY(45)
	EXTERNAL_PHY(46)
	EXTERNAL_PHY(47)
};

&switch0 {
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		SWITCH_PORT_SDS(0, 1, 0, qsgmii)
		SWITCH_PORT_SDS(1, 2, 0, qsgmii)
		SWITCH_PORT_SDS(2, 3, 0, qsgmii)
		SWITCH_PORT_SDS(3, 4, 0, qsgmii)
		SWITCH_PORT_SDS(4, 5, 1, qsgmii)
		SWITCH_PORT_SDS(5, 6, 1, qsgmii)
		SWITCH_PORT_SDS(6, 7, 1, qsgmii)
		SWITCH_PORT_SDS(7, 8, 1, qsgmii)

		SWITCH_PORT_SDS(8, 9, 2, qsgmii)
		SWITCH_PORT_SDS(9, 10, 2, qsgmii)
		SWITCH_PORT_SDS(10, 11, 2, qsgmii)
		SWITCH_PORT_SDS(11, 12, 2, qsgmii)
		SWITCH_PORT_SDS(12, 13, 3, qsgmii)
		SWITCH_PORT_SDS(13, 14, 3, qsgmii)
		SWITCH_PORT_SDS(14, 15, 3, qsgmii)
		SWITCH_PORT_SDS(15, 16, 3, qsgmii)

		SWITCH_PORT_SDS(16, 17, 4, qsgmii)
		SWITCH_PORT_SDS(17, 18, 4, qsgmii)
		SWITCH_PORT_SDS(18, 19, 4, qsgmii)
		SWITCH_PORT_SDS(19, 20, 4, qsgmii)
		SWITCH_PORT_SDS(20, 21, 5, qsgmii)
		SWITCH_PORT_SDS(21, 22, 5, qsgmii)
		SWITCH_PORT_SDS(22, 23, 5, qsgmii)
		SWITCH_PORT_SDS(23, 24, 5, qsgmii)

		SWITCH_PORT_SDS(24, 25, 6, qsgmii)
		SWITCH_PORT_SDS(25, 26, 6, qsgmii)
		SWITCH_PORT_SDS(26, 27, 6, qsgmii)
		SWITCH_PORT_SDS(27, 28, 6, qsgmii)
		SWITCH_PORT_SDS(28, 29, 7, qsgmii)
		SWITCH_PORT_SDS(29, 30, 7, qsgmii)
		SWITCH_PORT_SDS(30, 31, 7, qsgmii)
		SWITCH_PORT_SDS(31, 32, 7, qsgmii)

		SWITCH_PORT_SDS(32, 33, 8, qsgmii)
		SWITCH_PORT_SDS(33, 34, 8, qsgmii)
		SWITCH_PORT_SDS(34, 35, 8, qsgmii)
		SWITCH_PORT_SDS(35, 36, 8, qsgmii)
		SWITCH_PORT_SDS(36, 37, 9, qsgmii)
		SWITCH_PORT_SDS(37, 38, 9, qsgmii)
		SWITCH_PORT_SDS(38, 39, 9, qsgmii)
		SWITCH_PORT_SDS(39, 40, 9, qsgmii)

		SWITCH_PORT_SDS(40, 41, 10, qsgmii)
		SWITCH_PORT_SDS(41, 42, 10, qsgmii)
		SWITCH_PORT_SDS(42, 43, 10, qsgmii)
		SWITCH_PORT_SDS(43, 44, 10, qsgmii)
		SWITCH_PORT_SDS(44, 45, 11, qsgmii)
		SWITCH_PORT_SDS(45, 46, 11, qsgmii)
		SWITCH_PORT_SDS(46, 47, 11, qsgmii)
		SWITCH_PORT_SDS(47, 48, 11, qsgmii)

		/* SFP cages */
		port@48 {
			reg = <48>;
			label = "lan49";
			pcs-handle = <&serdes12>;
			phy-mode = "1000base-x";
			managed = "in-band-status";
			sfp = <&sfp0>;
		};

		port@49 {
			reg = <49>;
			label = "lan50";
			pcs-handle = <&serdes13>;
			phy-mode = "1000base-x";
			managed = "in-band-status";
			sfp = <&sfp1>;
		};

		/* CPU-Port */
		port@52 {
			ethernet = <&ethernet0>;
			reg = <52>;
			phy-mode = "internal";
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};
