app-emulation/qemu: Sync with Gentoo

It's from Gentoo commit 7add6e2519c5f9c8922ea9e1a010ac334b0ce179.

Signed-off-by: Flatcar Buildbot <buildbot@flatcar-linux.org>

sdk_container/src/third_party/portage-stable/app-emulation/qemu/Manifest

@@ -6,8 +6,10 @@ DIST qemu-10.0.0.tar.xz 135618260 BLAKE2B 3408c7b2a38ace7f0b2e0912411a26cab96cb2
 DIST qemu-10.0.2.tar.xz 135678180 BLAKE2B be4ddf050d2102cefded5b4967222df749ee8af92c2427c31a9b29b3800fac8bb328daf2c38d11aa307b51eb7d7243f9b064b3bf24d446a001e5520359ee83c3 SHA512 7fda582c3845ea663aa5eda21bb38ebcfb6c25bccf8944ea6cdf8b5be6946b5a874b36674a7f5db3e325abb9cca0dd9bc0727837fdceb71a8c947d96169a9b20
 DIST qemu-10.0.3.tar.xz 135736600 BLAKE2B 382800d9a9f5241123ebeb43d8eaa6a4aaf9acae0df7a25f2c7831aa7eeb97014cff29886c53f03ea0a1ac98729b85bad1e4d5634e592a373af84f79a9219adc SHA512 7f37c2df5ac7048fb32f1d89a7c2da0929be9d2f5767bc209ca1e99167f196fb5867fc8b69f915c8c349c58089ce3d7e08c9a3f35a73223abff258b9a5bf3466
 DIST qemu-10.0.4.tar.xz 141652160 BLAKE2B 987b69f2d9f2e98a1447c321a00a5c8df7114285c2bfabe7e127d57afb8b1d0b56dc34967be9e161652fd07dc25a0b09135a01758a82973ef819d71a2d5c6748 SHA512 1737124306b293401362ce33b5ce226df237cc577466afdff510b7f8e851e16708c7ec8d282e86dce3d66b54d1ff14876ac448061faf43d59de375b817155a1e
+DIST qemu-10.0.5.tar.xz 141642600 BLAKE2B bd7abfd5a977cf47862f0a7b26ce4e36c857dd858e0d0def652c00e9186fe476f461005b673bac6031162b5de47d412c1b7faebdbf4456487501f6d4a37f69b7 SHA512 c87948868910f458aeb724ebfe71db10f0ca1e9e0e6b4c4f082c2776d1c8f64c36f65bc5714d4625f6919d4064452f4378a7578273b69db6d4295d90b75fc86f
 DIST qemu-10.1.0-docs.tar.xz 2788092 BLAKE2B c9f1138e6eb19966da05b5be6e28640cabf698cb7c4247e0a69b29ed71d462423ba356efc8c0f26a727a58b4adc84edc3eefbff12a35e0c93e475f0ab51e6ff7 SHA512 96d9133d83991014c3ce9a57273a017f45bf29ae3f7029c5b926c8c5fbfd0e8da80dbbecca038b981312cec68b931a0471837a0aebd3e5dbc1648eb49e28ecc9
 DIST qemu-10.1.0.tar.xz 141999456 BLAKE2B 025012e73cdd2468b1b0fdef9b34aae41893780cfcad0d52c05e7f67ff7a9969c8c596f006b8a7e6f1b59e39da8fdec07d6f241911c604502755acd26bb750b6 SHA512 20552a524b6b298181df1af7084b470ded3fe8d1505f05011dda3c33cbc3d91f518ce026b44ba1a8b7f34c64ae81afddceda383066f4772a3a2a6333a2638caf
+DIST qemu-10.1.1.tar.xz 142046220 BLAKE2B 3617898fb4275e1e18f9567e9a9137ad0f3e3e3bc6a1b77301fd59614047757d77a9b810ece2e504ff47c1b98e2b9881a1ff551a4bc356c87c0d5d85f471a59b SHA512 72ca08894fb63c734163a53c6a836a6237de0f9f4ece4570e871bf80bcfba43fb5d4f11715564e0aef7244b7b3c4fe1890d5f10bbb05528b592d25cd95a57dfa
 DIST qemu-9.1.0-docs.tar.xz 2376072 BLAKE2B 31d13133b3a2e21a7d9b5af028407610ae8f2fa61dd296fc35e57fc12eb66cfd1a39ec5e3b5a3852095d10a388f424f8a38417b3ab58ca30d0817ece779328cf SHA512 5b705b577daad6aa010d5c713db9dc314114334b89901840ebcecc9032595a969f5ad9054e42b36b2be5ef9f5d6dc1159841ff46dbb08314b5c48491aa631040
 DIST qemu-9.1.3.tar.xz 132492084 BLAKE2B 268c8fb91dd5fc4e393a46a578537338861e5d2a92c381517447c6c2fe67604ed9aacc96371c864dc7f4a800cc9b9f94118d17c5dcc24f3fac5be0a18ca553e5 SHA512 e7b938e72eb4a8a4a6680ce3b282a4e5cbd1ad30003bed959e51ea2621acea7434b4366ef6559e3622fac8865ad212702f393ba7698be38cf2fc8f264b951318
 DIST qemu-9.2.0-docs.tar.xz 2431076 BLAKE2B 420148b9d7cafbdc9aea21b0d0a84a53ca0d17fb99fc34ae4c0786fa7d4ce40838f4b3173508b90742d6dfbfd4b58dda25b2e5cd1394241b0b56a64fe5705d9b SHA512 88816e326e9eac9acf0a1c73e677552845d6885e220b55e795241c40d2c1bd1b1994a22e56f95046e420225e0b7dc839d459f1c1e5318c8c36392727a86b3008

sdk_container/src/third_party/portage-stable/app-emulation/qemu/files/qemu-10.0.5-hppa1.1.patch

@@ -0,0 +1,44 @@
+target/hppa: correct size bit parity for fmpyadd
+
+For the fmpyadd instruction on the hppa architecture, there is a bit
+used to specify whether the instruction is operating on a 32 bit or 64
+bit floating point register. For most instructions, such a bit is 0 when
+operating on the smaller register and 1 when operating on the larger
+register. However, according to page 6-57 of the PA-RISC 1.1 Architecture
+and Instruction Set Reference Manual, this convention is reversed for the
+fmpyadd instruction specifically, meaning the bit is 1 for operations on
+32 bit registers and 0 for 64 bit registers. Previously, QEMU decoded
+this operation as operating on the other size of register, leading to
+bugs when translating the fmpyadd instruction. This patch fixes that
+issue.
+
+Reported-by: Andreas Hüttel <andreas.huettel@ur.de>
+Signed-off-by: Gabriel Brookman <brookmangabriel@gmail.com>
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3096
+---
+ target/hppa/insns.decode | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
+index 4eaac750ea..13c6a55bf2 100644
+--- a/target/hppa/insns.decode
++++ b/target/hppa/insns.decode
+@@ -365,10 +365,10 @@ fstd            011100 ..... ..... .. ............1.    @ldstim11
+ &mpyadd         rm1 rm2 ta ra tm
+ @mpyadd         ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5     &mpyadd
+ 
+-fmpyadd_f       000110 ..... ..... ..... ..... 0 .....  @mpyadd
+-fmpyadd_d       000110 ..... ..... ..... ..... 1 .....  @mpyadd
+-fmpysub_f       100110 ..... ..... ..... ..... 0 .....  @mpyadd
+-fmpysub_d       100110 ..... ..... ..... ..... 1 .....  @mpyadd
++fmpyadd_f       000110 ..... ..... ..... ..... 1 .....  @mpyadd
++fmpyadd_d       000110 ..... ..... ..... ..... 0 .....  @mpyadd
++fmpysub_f       100110 ..... ..... ..... ..... 1 .....  @mpyadd
++fmpysub_d       100110 ..... ..... ..... ..... 0 .....  @mpyadd
+ 
+ ####
+ # Conditional Branches
+
+---
+base-commit: 94474a7733a57365d5a27efc28c05462e90e8944
+change-id: 20251009-hppa-correct-fmpyadd-size-bit-decoding-059501a0ae49