mirror of
https://github.com/flatcar/scripts.git
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Merge pull request #1577 from flatcar-linux/jepio/hyperv-pci
sys-kernel: backport hyper-v PCI patches from v5.17-rc1
This commit is contained in:
Jeremi Piotrowski
GitHub
commit
d7eb5593b6
@ -92,7 +92,6 @@ CONFIG_NET_SWITCHDEV=y
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CONFIG_NVRAM=m
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CONFIG_OPTPROBES=y
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CONFIG_PARAVIRT_SPINLOCKS=y
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CONFIG_PCI_HYPERV=m
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CONFIG_PCI_MMCONFIG=y
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CONFIG_PHYSICAL_ALIGN=0x1000000
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CONFIG_PMIC_OPREGION=y
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@ -730,6 +730,7 @@ CONFIG_PCI=y
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CONFIG_PCIEAER=y
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CONFIG_PCIEPORTBUS=y
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CONFIG_PCIE_ECRC=y
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CONFIG_PCI_HYPERV=m
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CONFIG_PCI_IOV=y
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CONFIG_PCI_MSI=y
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CONFIG_PCNET32=m
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@ -8,7 +8,7 @@ ETYPE="sources"
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# Final releases should be versioned L.M.N, even for N == 0
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# Only needed for RCs
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K_BASE_VER="5.10"
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K_BASE_VER="5.15"
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inherit kernel-2
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EXTRAVERSION="-flatcar"
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@ -34,4 +34,6 @@ IUSE=""
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UNIPATCH_LIST="
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${PATCH_DIR}/z0001-kbuild-derive-relative-path-for-srctree-from-CURDIR.patch \
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${PATCH_DIR}/z0002-tools-objtool-Makefile-Don-t-fail-on-fallthrough-wit.patch \
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${PATCH_DIR}/z0003-PCI-hv-Make-the-code-arch-neutral-by-adding-arch-spe.patch \
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${PATCH_DIR}/z0004-PCI-hv-Add-arm64-Hyper-V-vPCI-support.patch \
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"
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@ -0,0 +1,334 @@
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From 831c1ae725f7d2f8f858b0840692b48e75b49331 Mon Sep 17 00:00:00 2001
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From: Sunil Muthuswamy <sunilmut@microsoft.com>
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Date: Wed, 5 Jan 2022 11:32:35 -0800
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Subject: [PATCH 1/2] PCI: hv: Make the code arch neutral by adding arch
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specific interfaces
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Encapsulate arch dependencies in Hyper-V vPCI through a set of
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arch-dependent interfaces. Adding these arch specific interfaces will
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allow for an implementation for other architectures, such as arm64.
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There are no functional changes expected from this patch.
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Link: https://lore.kernel.org/r/1641411156-31705-2-git-send-email-sunilmut@linux.microsoft.com
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Signed-off-by: Sunil Muthuswamy <sunilmut@microsoft.com>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Reviewed-by: Boqun Feng <boqun.feng@gmail.com>
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Reviewed-by: Marc Zyngier <maz@kernel.org>
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Reviewed-by: Michael Kelley <mikelley@microsoft.com>
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---
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arch/x86/include/asm/hyperv-tlfs.h | 33 ++++++++++++
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arch/x86/include/asm/mshyperv.h | 7 ---
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drivers/pci/controller/pci-hyperv.c | 79 ++++++++++++++++++++---------
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include/asm-generic/hyperv-tlfs.h | 33 ------------
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4 files changed, 87 insertions(+), 65 deletions(-)
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diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h
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index 381e88122a5f..0a9407dc0859 100644
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--- a/arch/x86/include/asm/hyperv-tlfs.h
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+++ b/arch/x86/include/asm/hyperv-tlfs.h
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@@ -602,6 +602,39 @@ enum hv_interrupt_type {
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HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A,
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};
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+union hv_msi_address_register {
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+ u32 as_uint32;
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+ struct {
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+ u32 reserved1:2;
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+ u32 destination_mode:1;
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+ u32 redirection_hint:1;
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+ u32 reserved2:8;
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+ u32 destination_id:8;
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+ u32 msi_base:12;
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+ };
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+} __packed;
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+
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+union hv_msi_data_register {
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+ u32 as_uint32;
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+ struct {
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+ u32 vector:8;
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+ u32 delivery_mode:3;
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+ u32 reserved1:3;
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+ u32 level_assert:1;
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+ u32 trigger_mode:1;
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+ u32 reserved2:16;
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+ };
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+} __packed;
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+
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+/* HvRetargetDeviceInterrupt hypercall */
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+union hv_msi_entry {
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+ u64 as_uint64;
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+ struct {
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+ union hv_msi_address_register address;
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+ union hv_msi_data_register data;
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+ } __packed;
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+};
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+
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#include <asm-generic/hyperv-tlfs.h>
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#endif
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diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyperv.h
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index da3972fe5a7a..a1c3dceff8eb 100644
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--- a/arch/x86/include/asm/mshyperv.h
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+++ b/arch/x86/include/asm/mshyperv.h
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@@ -169,13 +169,6 @@ bool hv_vcpu_is_preempted(int vcpu);
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static inline void hv_apic_init(void) {}
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#endif
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-static inline void hv_set_msi_entry_from_desc(union hv_msi_entry *msi_entry,
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- struct msi_desc *msi_desc)
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-{
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- msi_entry->address.as_uint32 = msi_desc->msg.address_lo;
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- msi_entry->data.as_uint32 = msi_desc->msg.data;
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-}
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-
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struct irq_domain *hv_create_pci_msi_domain(void);
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int hv_map_ioapic_interrupt(int ioapic_id, bool level, int vcpu, int vector,
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diff --git a/drivers/pci/controller/pci-hyperv.c b/drivers/pci/controller/pci-hyperv.c
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index 6733cb14e775..ead7d6cb6bf1 100644
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--- a/drivers/pci/controller/pci-hyperv.c
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+++ b/drivers/pci/controller/pci-hyperv.c
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@@ -43,9 +43,6 @@
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#include <linux/pci-ecam.h>
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#include <linux/delay.h>
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#include <linux/semaphore.h>
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-#include <linux/irqdomain.h>
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-#include <asm/irqdomain.h>
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-#include <asm/apic.h>
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <linux/hyperv.h>
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@@ -583,6 +580,42 @@ struct hv_pci_compl {
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static void hv_pci_onchannelcallback(void *context);
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+#ifdef CONFIG_X86
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+#define DELIVERY_MODE APIC_DELIVERY_MODE_FIXED
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+#define FLOW_HANDLER handle_edge_irq
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+#define FLOW_NAME "edge"
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+
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+static int hv_pci_irqchip_init(void)
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+{
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+ return 0;
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+}
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+
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+static struct irq_domain *hv_pci_get_root_domain(void)
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+{
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+ return x86_vector_domain;
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+}
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+
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+static unsigned int hv_msi_get_int_vector(struct irq_data *data)
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+{
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+ struct irq_cfg *cfg = irqd_cfg(data);
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+
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+ return cfg->vector;
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+}
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+
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+static void hv_set_msi_entry_from_desc(union hv_msi_entry *msi_entry,
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+ struct msi_desc *msi_desc)
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+{
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+ msi_entry->address.as_uint32 = msi_desc->msg.address_lo;
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+ msi_entry->data.as_uint32 = msi_desc->msg.data;
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+}
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+
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+static int hv_msi_prepare(struct irq_domain *domain, struct device *dev,
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+ int nvec, msi_alloc_info_t *info)
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+{
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+ return pci_msi_prepare(domain, dev, nvec, info);
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+}
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+#endif /* CONFIG_X86 */
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+
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/**
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* hv_pci_generic_compl() - Invoked for a completion packet
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* @context: Set up by the sender of the packet.
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@@ -1191,14 +1224,6 @@ static void hv_msi_free(struct irq_domain *domain, struct msi_domain_info *info,
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put_pcichild(hpdev);
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}
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-static int hv_set_affinity(struct irq_data *data, const struct cpumask *dest,
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- bool force)
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-{
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- struct irq_data *parent = data->parent_data;
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-
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- return parent->chip->irq_set_affinity(parent, dest, force);
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-}
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-
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static void hv_irq_mask(struct irq_data *data)
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{
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pci_msi_mask_irq(data);
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@@ -1217,7 +1242,6 @@ static void hv_irq_mask(struct irq_data *data)
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static void hv_irq_unmask(struct irq_data *data)
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{
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struct msi_desc *msi_desc = irq_data_get_msi_desc(data);
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- struct irq_cfg *cfg = irqd_cfg(data);
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struct hv_retarget_device_interrupt *params;
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struct hv_pcibus_device *hbus;
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struct cpumask *dest;
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@@ -1246,7 +1270,7 @@ static void hv_irq_unmask(struct irq_data *data)
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(hbus->hdev->dev_instance.b[7] << 8) |
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(hbus->hdev->dev_instance.b[6] & 0xf8) |
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PCI_FUNC(pdev->devfn);
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- params->int_target.vector = cfg->vector;
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+ params->int_target.vector = hv_msi_get_int_vector(data);
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/*
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* Honoring apic->delivery_mode set to APIC_DELIVERY_MODE_FIXED by
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@@ -1347,7 +1371,7 @@ static u32 hv_compose_msi_req_v1(
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int_pkt->wslot.slot = slot;
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int_pkt->int_desc.vector = vector;
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int_pkt->int_desc.vector_count = 1;
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- int_pkt->int_desc.delivery_mode = APIC_DELIVERY_MODE_FIXED;
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+ int_pkt->int_desc.delivery_mode = DELIVERY_MODE;
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/*
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* Create MSI w/ dummy vCPU set, overwritten by subsequent retarget in
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@@ -1377,7 +1401,7 @@ static u32 hv_compose_msi_req_v2(
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int_pkt->wslot.slot = slot;
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int_pkt->int_desc.vector = vector;
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int_pkt->int_desc.vector_count = 1;
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- int_pkt->int_desc.delivery_mode = APIC_DELIVERY_MODE_FIXED;
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+ int_pkt->int_desc.delivery_mode = DELIVERY_MODE;
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cpu = hv_compose_msi_req_get_cpu(affinity);
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int_pkt->int_desc.processor_array[0] =
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hv_cpu_number_to_vp_number(cpu);
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@@ -1397,7 +1421,7 @@ static u32 hv_compose_msi_req_v3(
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int_pkt->int_desc.vector = vector;
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int_pkt->int_desc.reserved = 0;
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int_pkt->int_desc.vector_count = 1;
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- int_pkt->int_desc.delivery_mode = APIC_DELIVERY_MODE_FIXED;
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+ int_pkt->int_desc.delivery_mode = DELIVERY_MODE;
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cpu = hv_compose_msi_req_get_cpu(affinity);
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int_pkt->int_desc.processor_array[0] =
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hv_cpu_number_to_vp_number(cpu);
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@@ -1419,7 +1443,6 @@ static u32 hv_compose_msi_req_v3(
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*/
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static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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- struct irq_cfg *cfg = irqd_cfg(data);
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struct hv_pcibus_device *hbus;
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struct vmbus_channel *channel;
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struct hv_pci_dev *hpdev;
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@@ -1470,7 +1493,7 @@ static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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size = hv_compose_msi_req_v1(&ctxt.int_pkts.v1,
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dest,
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hpdev->desc.win_slot.slot,
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- cfg->vector);
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+ hv_msi_get_int_vector(data));
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break;
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case PCI_PROTOCOL_VERSION_1_2:
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@@ -1478,14 +1501,14 @@ static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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size = hv_compose_msi_req_v2(&ctxt.int_pkts.v2,
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dest,
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hpdev->desc.win_slot.slot,
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- cfg->vector);
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+ hv_msi_get_int_vector(data));
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break;
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case PCI_PROTOCOL_VERSION_1_4:
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size = hv_compose_msi_req_v3(&ctxt.int_pkts.v3,
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dest,
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hpdev->desc.win_slot.slot,
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- cfg->vector);
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+ hv_msi_get_int_vector(data));
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break;
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default:
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@@ -1594,14 +1617,14 @@ static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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static struct irq_chip hv_msi_irq_chip = {
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.name = "Hyper-V PCIe MSI",
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.irq_compose_msi_msg = hv_compose_msi_msg,
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- .irq_set_affinity = hv_set_affinity,
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+ .irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_ack = irq_chip_ack_parent,
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.irq_mask = hv_irq_mask,
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.irq_unmask = hv_irq_unmask,
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};
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static struct msi_domain_ops hv_msi_ops = {
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- .msi_prepare = pci_msi_prepare,
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+ .msi_prepare = hv_msi_prepare,
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.msi_free = hv_msi_free,
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};
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@@ -1625,12 +1648,12 @@ static int hv_pcie_init_irq_domain(struct hv_pcibus_device *hbus)
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hbus->msi_info.flags = (MSI_FLAG_USE_DEF_DOM_OPS |
|
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MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI |
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MSI_FLAG_PCI_MSIX);
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- hbus->msi_info.handler = handle_edge_irq;
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- hbus->msi_info.handler_name = "edge";
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+ hbus->msi_info.handler = FLOW_HANDLER;
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+ hbus->msi_info.handler_name = FLOW_NAME;
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hbus->msi_info.data = hbus;
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hbus->irq_domain = pci_msi_create_irq_domain(hbus->fwnode,
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&hbus->msi_info,
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- x86_vector_domain);
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+ hv_pci_get_root_domain());
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if (!hbus->irq_domain) {
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dev_err(&hbus->hdev->device,
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"Failed to build an MSI IRQ domain\n");
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@@ -3542,9 +3565,15 @@ static void __exit exit_hv_pci_drv(void)
|
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|
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static int __init init_hv_pci_drv(void)
|
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{
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+ int ret;
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+
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if (!hv_is_hyperv_initialized())
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return -ENODEV;
|
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+ ret = hv_pci_irqchip_init();
|
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+ if (ret)
|
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+ return ret;
|
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+
|
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/* Set the invalid domain number's bit, so it will not be used */
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set_bit(HVPCI_DOM_INVALID, hvpci_dom_map);
|
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|
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diff --git a/include/asm-generic/hyperv-tlfs.h b/include/asm-generic/hyperv-tlfs.h
|
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index 8ed6733d5146..8f97c2927bee 100644
|
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--- a/include/asm-generic/hyperv-tlfs.h
|
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+++ b/include/asm-generic/hyperv-tlfs.h
|
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@@ -540,39 +540,6 @@ enum hv_interrupt_source {
|
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HV_INTERRUPT_SOURCE_IOAPIC,
|
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};
|
||||
|
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-union hv_msi_address_register {
|
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- u32 as_uint32;
|
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- struct {
|
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- u32 reserved1:2;
|
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- u32 destination_mode:1;
|
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- u32 redirection_hint:1;
|
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- u32 reserved2:8;
|
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- u32 destination_id:8;
|
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- u32 msi_base:12;
|
||||
- };
|
||||
-} __packed;
|
||||
-
|
||||
-union hv_msi_data_register {
|
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- u32 as_uint32;
|
||||
- struct {
|
||||
- u32 vector:8;
|
||||
- u32 delivery_mode:3;
|
||||
- u32 reserved1:3;
|
||||
- u32 level_assert:1;
|
||||
- u32 trigger_mode:1;
|
||||
- u32 reserved2:16;
|
||||
- };
|
||||
-} __packed;
|
||||
-
|
||||
-/* HvRetargetDeviceInterrupt hypercall */
|
||||
-union hv_msi_entry {
|
||||
- u64 as_uint64;
|
||||
- struct {
|
||||
- union hv_msi_address_register address;
|
||||
- union hv_msi_data_register data;
|
||||
- } __packed;
|
||||
-};
|
||||
-
|
||||
union hv_ioapic_rte {
|
||||
u64 as_uint64;
|
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|
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--
|
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2.32.0
|
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|
||||
@ -0,0 +1,349 @@
|
||||
From d9932b46915664c88709d59927fa67e797adec56 Mon Sep 17 00:00:00 2001
|
||||
From: Sunil Muthuswamy <sunilmut@microsoft.com>
|
||||
Date: Wed, 5 Jan 2022 11:32:36 -0800
|
||||
Subject: [PATCH 2/2] PCI: hv: Add arm64 Hyper-V vPCI support
|
||||
|
||||
Add arm64 Hyper-V vPCI support by implementing the arch specific
|
||||
interfaces. Introduce an IRQ domain and chip specific to Hyper-v vPCI that
|
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is based on SPIs. The IRQ domain parents itself to the arch GIC IRQ domain
|
||||
for basic vector management.
|
||||
|
||||
[bhelgaas: squash in fix from Yang Li <yang.lee@linux.alibaba.com>:
|
||||
https://lore.kernel.org/r/20220112003324.62755-1-yang.lee@linux.alibaba.com]
|
||||
Link: https://lore.kernel.org/r/1641411156-31705-3-git-send-email-sunilmut@linux.microsoft.com
|
||||
Signed-off-by: Sunil Muthuswamy <sunilmut@microsoft.com>
|
||||
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
||||
Reviewed-by: Marc Zyngier <maz@kernel.org>
|
||||
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
|
||||
---
|
||||
arch/arm64/include/asm/hyperv-tlfs.h | 9 +
|
||||
drivers/pci/Kconfig | 2 +-
|
||||
drivers/pci/controller/Kconfig | 2 +-
|
||||
drivers/pci/controller/pci-hyperv.c | 235 ++++++++++++++++++++++++++-
|
||||
4 files changed, 245 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/arch/arm64/include/asm/hyperv-tlfs.h b/arch/arm64/include/asm/hyperv-tlfs.h
|
||||
index 4d964a7f02ee..bc6c7ac934a1 100644
|
||||
--- a/arch/arm64/include/asm/hyperv-tlfs.h
|
||||
+++ b/arch/arm64/include/asm/hyperv-tlfs.h
|
||||
@@ -64,6 +64,15 @@
|
||||
#define HV_REGISTER_STIMER0_CONFIG 0x000B0000
|
||||
#define HV_REGISTER_STIMER0_COUNT 0x000B0001
|
||||
|
||||
+union hv_msi_entry {
|
||||
+ u64 as_uint64[2];
|
||||
+ struct {
|
||||
+ u64 address;
|
||||
+ u32 data;
|
||||
+ u32 reserved;
|
||||
+ } __packed;
|
||||
+};
|
||||
+
|
||||
#include <asm-generic/hyperv-tlfs.h>
|
||||
|
||||
#endif
|
||||
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
|
||||
index 43e615aa12ff..d98fafdd0f99 100644
|
||||
--- a/drivers/pci/Kconfig
|
||||
+++ b/drivers/pci/Kconfig
|
||||
@@ -184,7 +184,7 @@ config PCI_LABEL
|
||||
|
||||
config PCI_HYPERV
|
||||
tristate "Hyper-V PCI Frontend"
|
||||
- depends on X86_64 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && SYSFS
|
||||
+ depends on ((X86 && X86_64) || ARM64) && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && SYSFS
|
||||
select PCI_HYPERV_INTERFACE
|
||||
help
|
||||
The PCI device frontend driver allows the kernel to import arbitrary
|
||||
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
|
||||
index 93b141110537..2536abcc045a 100644
|
||||
--- a/drivers/pci/controller/Kconfig
|
||||
+++ b/drivers/pci/controller/Kconfig
|
||||
@@ -281,7 +281,7 @@ config PCIE_BRCMSTB
|
||||
|
||||
config PCI_HYPERV_INTERFACE
|
||||
tristate "Hyper-V PCI Interface"
|
||||
- depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
|
||||
+ depends on ((X86 && X86_64) || ARM64) && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN
|
||||
help
|
||||
The Hyper-V PCI Interface is a helper driver allows other drivers to
|
||||
have a common interface with the Hyper-V PCI frontend driver.
|
||||
diff --git a/drivers/pci/controller/pci-hyperv.c b/drivers/pci/controller/pci-hyperv.c
|
||||
index ead7d6cb6bf1..31743f93199e 100644
|
||||
--- a/drivers/pci/controller/pci-hyperv.c
|
||||
+++ b/drivers/pci/controller/pci-hyperv.c
|
||||
@@ -47,6 +47,8 @@
|
||||
#include <linux/msi.h>
|
||||
#include <linux/hyperv.h>
|
||||
#include <linux/refcount.h>
|
||||
+#include <linux/irqdomain.h>
|
||||
+#include <linux/acpi.h>
|
||||
#include <asm/mshyperv.h>
|
||||
|
||||
/*
|
||||
@@ -614,7 +616,230 @@ static int hv_msi_prepare(struct irq_domain *domain, struct device *dev,
|
||||
{
|
||||
return pci_msi_prepare(domain, dev, nvec, info);
|
||||
}
|
||||
-#endif /* CONFIG_X86 */
|
||||
+#elif defined(CONFIG_ARM64)
|
||||
+/*
|
||||
+ * SPI vectors to use for vPCI; arch SPIs range is [32, 1019], but leaving a bit
|
||||
+ * of room at the start to allow for SPIs to be specified through ACPI and
|
||||
+ * starting with a power of two to satisfy power of 2 multi-MSI requirement.
|
||||
+ */
|
||||
+#define HV_PCI_MSI_SPI_START 64
|
||||
+#define HV_PCI_MSI_SPI_NR (1020 - HV_PCI_MSI_SPI_START)
|
||||
+#define DELIVERY_MODE 0
|
||||
+#define FLOW_HANDLER NULL
|
||||
+#define FLOW_NAME NULL
|
||||
+#define hv_msi_prepare NULL
|
||||
+
|
||||
+struct hv_pci_chip_data {
|
||||
+ DECLARE_BITMAP(spi_map, HV_PCI_MSI_SPI_NR);
|
||||
+ struct mutex map_lock;
|
||||
+};
|
||||
+
|
||||
+/* Hyper-V vPCI MSI GIC IRQ domain */
|
||||
+static struct irq_domain *hv_msi_gic_irq_domain;
|
||||
+
|
||||
+/* Hyper-V PCI MSI IRQ chip */
|
||||
+static struct irq_chip hv_arm64_msi_irq_chip = {
|
||||
+ .name = "MSI",
|
||||
+ .irq_set_affinity = irq_chip_set_affinity_parent,
|
||||
+ .irq_eoi = irq_chip_eoi_parent,
|
||||
+ .irq_mask = irq_chip_mask_parent,
|
||||
+ .irq_unmask = irq_chip_unmask_parent
|
||||
+};
|
||||
+
|
||||
+static unsigned int hv_msi_get_int_vector(struct irq_data *irqd)
|
||||
+{
|
||||
+ return irqd->parent_data->hwirq;
|
||||
+}
|
||||
+
|
||||
+static void hv_set_msi_entry_from_desc(union hv_msi_entry *msi_entry,
|
||||
+ struct msi_desc *msi_desc)
|
||||
+{
|
||||
+ msi_entry->address = ((u64)msi_desc->msg.address_hi << 32) |
|
||||
+ msi_desc->msg.address_lo;
|
||||
+ msi_entry->data = msi_desc->msg.data;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * @nr_bm_irqs: Indicates the number of IRQs that were allocated from
|
||||
+ * the bitmap.
|
||||
+ * @nr_dom_irqs: Indicates the number of IRQs that were allocated from
|
||||
+ * the parent domain.
|
||||
+ */
|
||||
+static void hv_pci_vec_irq_free(struct irq_domain *domain,
|
||||
+ unsigned int virq,
|
||||
+ unsigned int nr_bm_irqs,
|
||||
+ unsigned int nr_dom_irqs)
|
||||
+{
|
||||
+ struct hv_pci_chip_data *chip_data = domain->host_data;
|
||||
+ struct irq_data *d = irq_domain_get_irq_data(domain, virq);
|
||||
+ int first = d->hwirq - HV_PCI_MSI_SPI_START;
|
||||
+ int i;
|
||||
+
|
||||
+ mutex_lock(&chip_data->map_lock);
|
||||
+ bitmap_release_region(chip_data->spi_map,
|
||||
+ first,
|
||||
+ get_count_order(nr_bm_irqs));
|
||||
+ mutex_unlock(&chip_data->map_lock);
|
||||
+ for (i = 0; i < nr_dom_irqs; i++) {
|
||||
+ if (i)
|
||||
+ d = irq_domain_get_irq_data(domain, virq + i);
|
||||
+ irq_domain_reset_irq_data(d);
|
||||
+ }
|
||||
+
|
||||
+ irq_domain_free_irqs_parent(domain, virq, nr_dom_irqs);
|
||||
+}
|
||||
+
|
||||
+static void hv_pci_vec_irq_domain_free(struct irq_domain *domain,
|
||||
+ unsigned int virq,
|
||||
+ unsigned int nr_irqs)
|
||||
+{
|
||||
+ hv_pci_vec_irq_free(domain, virq, nr_irqs, nr_irqs);
|
||||
+}
|
||||
+
|
||||
+static int hv_pci_vec_alloc_device_irq(struct irq_domain *domain,
|
||||
+ unsigned int nr_irqs,
|
||||
+ irq_hw_number_t *hwirq)
|
||||
+{
|
||||
+ struct hv_pci_chip_data *chip_data = domain->host_data;
|
||||
+ int index;
|
||||
+
|
||||
+ /* Find and allocate region from the SPI bitmap */
|
||||
+ mutex_lock(&chip_data->map_lock);
|
||||
+ index = bitmap_find_free_region(chip_data->spi_map,
|
||||
+ HV_PCI_MSI_SPI_NR,
|
||||
+ get_count_order(nr_irqs));
|
||||
+ mutex_unlock(&chip_data->map_lock);
|
||||
+ if (index < 0)
|
||||
+ return -ENOSPC;
|
||||
+
|
||||
+ *hwirq = index + HV_PCI_MSI_SPI_START;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int hv_pci_vec_irq_gic_domain_alloc(struct irq_domain *domain,
|
||||
+ unsigned int virq,
|
||||
+ irq_hw_number_t hwirq)
|
||||
+{
|
||||
+ struct irq_fwspec fwspec;
|
||||
+ struct irq_data *d;
|
||||
+ int ret;
|
||||
+
|
||||
+ fwspec.fwnode = domain->parent->fwnode;
|
||||
+ fwspec.param_count = 2;
|
||||
+ fwspec.param[0] = hwirq;
|
||||
+ fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
|
||||
+
|
||||
+ ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /*
|
||||
+ * Since the interrupt specifier is not coming from ACPI or DT, the
|
||||
+ * trigger type will need to be set explicitly. Otherwise, it will be
|
||||
+ * set to whatever is in the GIC configuration.
|
||||
+ */
|
||||
+ d = irq_domain_get_irq_data(domain->parent, virq);
|
||||
+
|
||||
+ return d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
|
||||
+}
|
||||
+
|
||||
+static int hv_pci_vec_irq_domain_alloc(struct irq_domain *domain,
|
||||
+ unsigned int virq, unsigned int nr_irqs,
|
||||
+ void *args)
|
||||
+{
|
||||
+ irq_hw_number_t hwirq;
|
||||
+ unsigned int i;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = hv_pci_vec_alloc_device_irq(domain, nr_irqs, &hwirq);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ for (i = 0; i < nr_irqs; i++) {
|
||||
+ ret = hv_pci_vec_irq_gic_domain_alloc(domain, virq + i,
|
||||
+ hwirq + i);
|
||||
+ if (ret) {
|
||||
+ hv_pci_vec_irq_free(domain, virq, nr_irqs, i);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ irq_domain_set_hwirq_and_chip(domain, virq + i,
|
||||
+ hwirq + i,
|
||||
+ &hv_arm64_msi_irq_chip,
|
||||
+ domain->host_data);
|
||||
+ pr_debug("pID:%d vID:%u\n", (int)(hwirq + i), virq + i);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * Pick the first cpu as the irq affinity that can be temporarily used for
|
||||
+ * composing MSI from the hypervisor. GIC will eventually set the right
|
||||
+ * affinity for the irq and the 'unmask' will retarget the interrupt to that
|
||||
+ * cpu.
|
||||
+ */
|
||||
+static int hv_pci_vec_irq_domain_activate(struct irq_domain *domain,
|
||||
+ struct irq_data *irqd, bool reserve)
|
||||
+{
|
||||
+ int cpu = cpumask_first(cpu_present_mask);
|
||||
+
|
||||
+ irq_data_update_effective_affinity(irqd, cpumask_of(cpu));
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct irq_domain_ops hv_pci_domain_ops = {
|
||||
+ .alloc = hv_pci_vec_irq_domain_alloc,
|
||||
+ .free = hv_pci_vec_irq_domain_free,
|
||||
+ .activate = hv_pci_vec_irq_domain_activate,
|
||||
+};
|
||||
+
|
||||
+static int hv_pci_irqchip_init(void)
|
||||
+{
|
||||
+ static struct hv_pci_chip_data *chip_data;
|
||||
+ struct fwnode_handle *fn = NULL;
|
||||
+ int ret = -ENOMEM;
|
||||
+
|
||||
+ chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
|
||||
+ if (!chip_data)
|
||||
+ return ret;
|
||||
+
|
||||
+ mutex_init(&chip_data->map_lock);
|
||||
+ fn = irq_domain_alloc_named_fwnode("hv_vpci_arm64");
|
||||
+ if (!fn)
|
||||
+ goto free_chip;
|
||||
+
|
||||
+ /*
|
||||
+ * IRQ domain once enabled, should not be removed since there is no
|
||||
+ * way to ensure that all the corresponding devices are also gone and
|
||||
+ * no interrupts will be generated.
|
||||
+ */
|
||||
+ hv_msi_gic_irq_domain = acpi_irq_create_hierarchy(0, HV_PCI_MSI_SPI_NR,
|
||||
+ fn, &hv_pci_domain_ops,
|
||||
+ chip_data);
|
||||
+
|
||||
+ if (!hv_msi_gic_irq_domain) {
|
||||
+ pr_err("Failed to create Hyper-V arm64 vPCI MSI IRQ domain\n");
|
||||
+ goto free_chip;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+free_chip:
|
||||
+ kfree(chip_data);
|
||||
+ if (fn)
|
||||
+ irq_domain_free_fwnode(fn);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static struct irq_domain *hv_pci_get_root_domain(void)
|
||||
+{
|
||||
+ return hv_msi_gic_irq_domain;
|
||||
+}
|
||||
+#endif /* CONFIG_ARM64 */
|
||||
|
||||
/**
|
||||
* hv_pci_generic_compl() - Invoked for a completion packet
|
||||
@@ -1227,6 +1452,8 @@ static void hv_msi_free(struct irq_domain *domain, struct msi_domain_info *info,
|
||||
static void hv_irq_mask(struct irq_data *data)
|
||||
{
|
||||
pci_msi_mask_irq(data);
|
||||
+ if (data->parent_data->chip->irq_mask)
|
||||
+ irq_chip_mask_parent(data);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1343,6 +1570,8 @@ static void hv_irq_unmask(struct irq_data *data)
|
||||
dev_err(&hbus->hdev->device,
|
||||
"%s() failed: %#llx", __func__, res);
|
||||
|
||||
+ if (data->parent_data->chip->irq_unmask)
|
||||
+ irq_chip_unmask_parent(data);
|
||||
pci_msi_unmask_irq(data);
|
||||
}
|
||||
|
||||
@@ -1618,7 +1847,11 @@ static struct irq_chip hv_msi_irq_chip = {
|
||||
.name = "Hyper-V PCIe MSI",
|
||||
.irq_compose_msi_msg = hv_compose_msi_msg,
|
||||
.irq_set_affinity = irq_chip_set_affinity_parent,
|
||||
+#ifdef CONFIG_X86
|
||||
.irq_ack = irq_chip_ack_parent,
|
||||
+#elif defined(CONFIG_ARM64)
|
||||
+ .irq_eoi = irq_chip_eoi_parent,
|
||||
+#endif
|
||||
.irq_mask = hv_irq_mask,
|
||||
.irq_unmask = hv_irq_unmask,
|
||||
};
|
||||
--
|
||||
2.32.0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user