mirrors/flatcar-scripts
1
0
Fork 0
mirror of https://github.com/flatcar/scripts.git synced 2025-10-03 19:42:15 +02:00
Code Issues Packages Projects Releases Wiki Activity

sys-firmware/intel-microcode: rev bump; sync with upstream

Browse Source 
- Mask sig 0x000406e3, pf_mask 0xc0, revision=0xd6 [Link 1]
- Mask sig 0x000406e3, pf_mask 0xc0, revision=0xda [Bug 722768]
This will basically downgrade microcode for 0x000406e3 back to rev 0x00d6 from 2019-10-03.

Link1: c1d8ba62ab

Signed-off-by: Sayan Chowdhury <sayan@kinvolk.io>
This commit is contained in:
Sayan Chowdhury 2020-06-15 16:54:15 +05:30
parent cbbed18c20
commit 5ae07c842e
2 changed files with 12 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
sdk_container/src/third_party/coreos-overlay/sys-firmware/intel-microcode/Manifest vendored
View File

@ -1,2 +1,3 @@
DIST intel-microcode-collection-20200601.tar.xz 6163976 BLAKE2B eb17605a09f771562189924b916b0d2426d6c2b6f9d76447d05d614679f097acf71fc70dd96132c0ad9d3f1a954f5809456fa951ca42fa0db2373da2288417b7 SHA512 60e798dd357ce85d8bd1f78e0447d983d6916aec87bf8a3f375091e4c57ffa8fb654459a8ed7d2d83184a828060509e16aa37e3a23f70684ac1b170736a12d54
DIST intel-ucode-sig_0x406e3-rev_0xd6.bin 101376 BLAKE2B 66d55867954d69dda1425febd93bb8c89f7aa836d504f8b5fee127f8505bcf2246f4fcc55cc245bc5e532528d60cca2eee278de7ab5174dc2862db7982a2b36f SHA512 248066b521bf512b5d8e4a8c7e921464ce52169c954d6e4ca580d8c172cd789519e22b4cf56c212e452b4191741f0202019f7061d322c9433b5af9ce5413b567
DIST microcode-20200609.tar.gz 3043809 BLAKE2B 08e69e8cf0c6932d6cb9909f18c1c55f359491ed29ad296c28111e6301c9f6371ec25c4ce1c8884a50900b9ba9dfcab38e77c7f3ebb58f3a3d8518ed839c8d22 SHA512 bfcaaea2811214b79445d632e256cd35af82d62f748799d47f7bc2490c5a6fd53f020bcaa3331a96b54c91ded1d17dfd9946b40174694b9a7ad17810f58293ae

11
sdk_container/src/third_party/coreos-overlay/sys-firmware/intel-microcode/intel-microcode-20200609_p20200601.ebuild → sdk_container/src/third_party/coreos-overlay/sys-firmware/intel-microcode/intel-microcode-20200609_p20200601-r1.ebuild vendored
View File

@ -16,6 +16,7 @@ INTEL_SNAPSHOT="${PV/_p*}"
DESCRIPTION="Intel IA32/IA64 microcode update data"
HOMEPAGE="https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files http://inertiawar.com/microcode/"
SRC_URI="https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/archive/microcode-${INTEL_SNAPSHOT}.tar.gz
https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/raw/437f382b1be4412b9d03e2bbdcda46d83d581242/intel-ucode/06-4e-03 -> intel-ucode-sig_0x406e3-rev_0xd6.bin
https://dev.gentoo.org/~whissi/dist/intel-microcode/intel-microcode-collection-${COLLECTION_SNAPSHOT}.tar.xz"
LICENSE="intel-ucode"
@ -37,6 +38,12 @@ S=${WORKDIR}
# 0x000406f1 aka 06-4f-01 aka CPUID 406F1 require newer microcode loader
MICROCODE_BLACKLIST_DEFAULT="-s !0x000406f1"
# https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/31
MICROCODE_BLACKLIST_DEFAULT+=" -s !0x000406e3,0xc0,eq:0x00dc"
# https://bugs.gentoo.org/722768
MICROCODE_BLACKLIST_DEFAULT+=" -s !0x000406e3,0xc0,eq:0x00da"
# In case we want to set some defaults ...
MICROCODE_SIGNATURES_DEFAULT=""
@ -60,6 +67,9 @@ src_prepare() {
rm -r Intel-Linux-Processor-Microcode-Data* || die
fi
mkdir intel-ucode-old || die
cp "${DISTDIR}"/intel-ucode-sig_0x406e3-rev_0xd6.bin "${S}"/intel-ucode-old/ || die
# Prevent "invalid file format" errors from iucode_tool
rm -f "${S}"/intel-ucod*/list || die
}
@ -72,6 +82,7 @@ src_install() {
MICROCODE_SRC=(
"${S}"/intel-ucode/
"${S}"/intel-ucode-with-caveats/
"${S}"/intel-ucode-old/
)
# Allow users who are scared about microcode updates not included in Intel's official