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91 lines
3.7 KiB
Diff
91 lines
3.7 KiB
Diff
From d99740197a9776b9332d21b9f3b05dab658a90eb Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Sat, 26 Oct 2019 15:44:15 +0200
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Subject: [PATCH 26/44] media: cedrus: hevc: Add support for multiple slices
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Now that segment address is available, support for multi-slice frames
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can be easily added.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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.../staging/media/sunxi/cedrus/cedrus_h265.c | 26 ++++++++++++-------
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.../staging/media/sunxi/cedrus/cedrus_video.c | 1 +
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2 files changed, 17 insertions(+), 10 deletions(-)
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--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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@@ -309,6 +309,8 @@ static void cedrus_h265_setup(struct ced
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const struct v4l2_ctrl_hevc_pps *pps;
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const struct v4l2_ctrl_hevc_slice_params *slice_params;
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const struct v4l2_hevc_pred_weight_table *pred_weight_table;
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+ unsigned int width_in_ctb_luma, ctb_size_luma;
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+ unsigned int log2_max_luma_coding_block_size;
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dma_addr_t src_buf_addr;
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dma_addr_t src_buf_end_addr;
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u32 chroma_log2_weight_denom;
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@@ -321,15 +323,17 @@ static void cedrus_h265_setup(struct ced
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slice_params = run->h265.slice_params;
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pred_weight_table = &slice_params->pred_weight_table;
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+ log2_max_luma_coding_block_size =
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+ sps->log2_min_luma_coding_block_size_minus3 + 3 +
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+ sps->log2_diff_max_min_luma_coding_block_size;
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+ ctb_size_luma = 1UL << log2_max_luma_coding_block_size;
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+ width_in_ctb_luma =
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+ DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma);
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+
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/* MV column buffer size and allocation. */
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if (!ctx->codec.h265.mv_col_buf_size) {
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unsigned int num_buffers =
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run->dst->vb2_buf.vb2_queue->num_buffers;
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- unsigned int log2_max_luma_coding_block_size =
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- sps->log2_min_luma_coding_block_size_minus3 + 3 +
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- sps->log2_diff_max_min_luma_coding_block_size;
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- unsigned int ctb_size_luma =
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- 1UL << log2_max_luma_coding_block_size;
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/*
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* Each CTB requires a MV col buffer with a specific unit size.
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@@ -383,15 +387,17 @@ static void cedrus_h265_setup(struct ced
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reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr);
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cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg);
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- /* Coding tree block address: start at the beginning. */
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- reg = VE_DEC_H265_DEC_CTB_ADDR_X(0) | VE_DEC_H265_DEC_CTB_ADDR_Y(0);
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+ /* Coding tree block address */
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+ reg = VE_DEC_H265_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma);
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+ reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma);
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cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg);
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cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0);
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cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0);
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/* Clear the number of correctly-decoded coding tree blocks. */
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- cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0);
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+ if (ctx->fh.m2m_ctx->new_frame)
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+ cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0);
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/* Initialize bitstream access. */
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cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC);
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@@ -543,8 +549,8 @@ static void cedrus_h265_setup(struct ced
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V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT,
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pps->flags);
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- /* FIXME: For multi-slice support. */
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- reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC;
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+ if (ctx->fh.m2m_ctx->new_frame)
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+ reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC;
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cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO0, reg);
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--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c
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+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
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@@ -332,6 +332,7 @@ static int cedrus_s_fmt_vid_out(struct f
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switch (ctx->src_fmt.pixelformat) {
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case V4L2_PIX_FMT_H264_SLICE:
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+ case V4L2_PIX_FMT_HEVC_SLICE:
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vq->subsystem_flags |=
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VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF;
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break;
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