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314061c3c3
* Improve sunxi fix-a64-timejump.patch Current patch still throws BUG: WARNING: CPU: 2 PID: 31 at drivers/clocksource/arm_arch_timer.c:364 sun50i_a64_read_cntpct_el0+0x2c/0x38 Cause: Timer values are required to be exactly the same, while it may increase in between reads. Seems to happen especially during boot Timer values are like: x2 : 0000000015014561 - x0 : 0000000015014567 Solution: Normalize timer values and return normalized value. * Add patch for 5.12.y Note. Small changes on upstream solution: GENMASK(9, 0 ... -> GENMASK(8, 0 ... Co-authored-by: Igor Pecovnik <igor.pecovnik@gmail.com>
37 lines
2.0 KiB
Diff
37 lines
2.0 KiB
Diff
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
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index 9a5464c62..91142959c 100644
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--- a/drivers/clocksource/arm_arch_timer.c
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+++ b/drivers/clocksource/arm_arch_timer.c
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@@ -341,17 +341,20 @@ static u64 notrace arm64_858921_read_cntvct_el0(void)
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* with all ones or all zeros in the low bits. Bound the loop by the maximum
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* number of CPU cycles in 3 consecutive 24 MHz counter periods.
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*/
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-#define __sun50i_a64_read_reg(reg) ({ \
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- u64 _val; \
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- int _retries = 150; \
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- \
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- do { \
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- _val = read_sysreg(reg); \
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- _retries--; \
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- } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \
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- \
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- WARN_ON_ONCE(!_retries); \
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- _val; \
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+#define __sun50i_a64_read_reg(reg) ({ \
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+ register u64 _tries = 5, _old, _new; \
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+ \
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+ do { \
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+ if (unlikely(_tries < 3)) \
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+ isb(); \
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+ _old = read_sysreg(reg); \
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+ _new = read_sysreg(reg); \
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+ } while (unlikely((_new - _old) >> 4) && --_tries); \
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+ \
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+ if (unlikely(!_tries)) \
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+ pr_err("(cpu %d) returning possibly incorrect counter value %llx (%llx)\n", \
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+ smp_processor_id() + 1, _new, _old); \
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+ _new; \
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})
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static u64 notrace sun50i_a64_read_cntpct_el0(void)
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