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3b3d85e25c
* Bump imx6 edge to 5.12.y * Bump odroid xu4 edge to 5.12.y * Bump Jetson nano edge to 5.12.y * WIP: Bump sunxi to 5.12.y - create a copy of patches and make a new link - wireless patches needs adjutement to 5.12 - some patches are still failing * Adjust wireless patches to build on 5.12.y * Remove template wireless patch * Move Espressobin edge to 5.12.y * Bump mvebu to 5.12 - patch 92-mvebu-gpio-remove-hardcoded-timer-assignment.patch was disabled @heisath - adjusted wireless driver for 8723ds * Adjust sunxi / sunxi64 edge to compile * Fix kernel config for Jetson nano edge * bump meson64 to 5.12.y * bump rockchip edge to 5.12.y * Bump rockchip64 to 5.12.y * Bump rk322x edge to 5.12.y @paolosabatino * Cleanup im6, re-add 5.10.y patches since one is missing in 5.12.y * Update odroidxu4 edge links * rk322x: moved rk322x-edge to kernel 5.12, fix overlay compilation, retouched included kernel modules * Cleanup: remove deprecated config Co-authored-by: Paolo Sabatino <paolo.sabatino@gmail.com>
56 lines
1.7 KiB
Diff
56 lines
1.7 KiB
Diff
From 2298f59cecc69b0fc6471c5fd3f7629af2d274b2 Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@arm.linux.org.uk>
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Date: Tue, 29 Nov 2016 10:13:48 +0000
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Subject: [PATCH] implement slot capabilities (SSPL)
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---
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drivers/pci/controller/pci-mvebu.c | 23 +++++++++++++++++++++++
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1 file changed, 23 insertions(+)
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--- a/drivers/pci/controller/pci-mvebu.c
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+++ b/drivers/pci/controller/pci-mvebu.c
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@@ -66,6 +66,12 @@
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#define PCIE_STAT_BUS 0xff00
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#define PCIE_STAT_DEV 0x1f0000
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#define PCIE_STAT_LINK_DOWN BIT(0)
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+#define PCIE_SSPL 0x1a0c
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+#define PCIE_SSPL_MSGEN BIT(14)
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+#define PCIE_SSPL_SPLS(x) (((x) & 3) << 8)
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+#define PCIE_SSPL_SPLS_VAL(x) (((x) >> 8) & 3)
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+#define PCIE_SSPL_SPLV(x) ((x) & 0xff)
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+#define PCIE_SSPL_SPLV_VAL(x) ((x) & 0xff)
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#define PCIE_RC_RTSTA 0x1a14
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#define PCIE_DEBUG_CTRL 0x1a60
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#define PCIE_DEBUG_SOFT_RESET BIT(20)
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@@ -515,6 +521,14 @@ mvebu_pci_bridge_emul_pcie_conf_read(str
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*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
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break;
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+ case PCI_EXP_SLTCAP:
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+ {
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+ u32 tmp = mvebu_readl(port, PCIE_SSPL);
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+ *value = PCIE_SSPL_SPLS_VAL(tmp) << 15 |
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+ PCIE_SSPL_SPLV_VAL(tmp) << 7;
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+ break;
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+ }
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+
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case PCI_EXP_SLTCTL:
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*value = PCI_EXP_SLTSTA_PDS << 16;
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break;
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@@ -643,6 +657,15 @@ mvebu_pci_bridge_emul_pcie_conf_write(st
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mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
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break;
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+ case PCI_EXP_SLTCAP:
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+ {
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+ u32 sspl = PCIE_SSPL_SPLV((new & PCI_EXP_SLTCAP_SPLV) >> 7) |
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+ PCIE_SSPL_SPLS((new & PCI_EXP_SLTCAP_SPLS) >> 15) |
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+ PCIE_SSPL_MSGEN;
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+ mvebu_writel(port, sspl, PCIE_SSPL);
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+ break;
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+ }
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+
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case PCI_EXP_RTSTA:
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mvebu_writel(port, new, PCIE_RC_RTSTA);
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break;
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