Ross Bencina
fa78fdfbc7
Fix issue with audio quality on NanoPi M4, see: https://forum.armbian.com/topic/9605-sound-problems-with-nanopi-m4/. Reinstate FriendlyElec rk3399-nanopi4-common.dtsi &i2s1 entry that assigns i2s1 master clock SCLK_I2S1_8CH to i2s_8ch_mclk output pin clock source SCLK_I2S_8CH. By default the i2s1 node is disabled, therefore this clock assignment is not applied unless (1) i2s1 is enabled by user DT changes, or (2) i2s1 is enabled in a specific nanopi board .dts -- at this time the only such board is NanoPi M4. On NanoPi M4 this change will send i2s1 mclk to the rt5651 codec, which is the desired clock routing (prior to this change, the codec was getting i2s0 mclk, which was the cause of the bad audio). On other nanopis if the user enables i2s1 in DT, this change will route i2s1 mclk to the mclk line on the 40 pin header (and, on NanoPC T4, also to the onboard codec, which is less desirable, but that's how the board is wired).
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Fix issue with audio quality on NanoPi M4, see: https://forum.armbian.com/topic/9605-sound-problems-with-nanopi-m4/. Reinstate FriendlyElec rk3399-nanopi4-common.dtsi &i2s1 entry that assigns i2s1 master clock SCLK_I2S1_8CH to i2s_8ch_mclk output pin clock source SCLK_I2S_8CH. By default the i2s1 node is disabled, therefore this clock assignment is not applied unless (1) i2s1 is enabled by user DT changes, or (2) i2s1 is enabled in a specific nanopi board .dts -- at this time the only such board is NanoPi M4. On NanoPi M4 this change will send i2s1 mclk to the rt5651 codec, which is the desired clock routing (prior to this change, the codec was getting i2s0 mclk, which was the cause of the bad audio). On other nanopis if the user enables i2s1 in DT, this change will route i2s1 mclk to the mclk line on the 40 pin header (and, on NanoPC T4, also to the onboard codec, which is less desirable, but that's how the board is wired).
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