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https://github.com/armbian/build.git
synced 2025-08-26 17:01:10 +02:00
1c9ef0872b
* Updated rockchip64-dev to u-boot v2019.10 and BL31 v1.30 (rk3399 boards) * Updated rk3399 to u-boot v2019.10 and BL31 v1.30 * Revert changes to renegade u-boot patches * Moved renegade u-boot patches into board dir * Added debug info for RockPro64 and switched sdmmc to fifo-mode * Disabled regulators in SPL for RockPro64 * Re-enabled sd vcc regulator in SPL for RockPro64 * Some device tree and config changes for OrangePi RK3399 * Fixed Rock Pi 4A's $BOOTCONFIG * Let some boards use mainline atf instead of the one in rkbin For example, roc-rk3399-pc can just boot the kernel using the mainline atf. * Add roc-rk3399-pc * Fixed reset in mainline ATF * Attached ATF version to v2.2 tag * WIP: sdmmc fifo-mode in SPL only * Renamed source config files * Reverted changes to rockchip64 sources config * Reverted patch moves * Add missing trust.ini patch to rk3399 u-boot * Reinstated tpl/spl patches in rk3399 family * Added $RKBIN_DIR prefix in rk3399 sources * Add demonstration of boards bootloader assignment in rk3399
64 lines
2.1 KiB
Diff
64 lines
2.1 KiB
Diff
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
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index 42589b9..8f2a419 100644
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--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
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+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
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@@ -400,7 +400,26 @@ static void pmu_power_domains_resume(void)
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clk_gate_con_restore();
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}
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-void rk3399_flush_l2_b(void)
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+void pmu_power_domains_on(void)
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+{
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+ clk_gate_con_disable();
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+ pmu_set_power_domain(PD_VDU, pmu_pd_on);
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+ pmu_set_power_domain(PD_VCODEC, pmu_pd_on);
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+ pmu_set_power_domain(PD_RGA, pmu_pd_on);
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+ pmu_set_power_domain(PD_IEP, pmu_pd_on);
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+ pmu_set_power_domain(PD_EDP, pmu_pd_on);
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+ pmu_set_power_domain(PD_GMAC, pmu_pd_on);
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+ pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_on);
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+ pmu_set_power_domain(PD_HDCP, pmu_pd_on);
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+ pmu_set_power_domain(PD_ISP1, pmu_pd_on);
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+ pmu_set_power_domain(PD_ISP0, pmu_pd_on);
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+ pmu_set_power_domain(PD_VO, pmu_pd_on);
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+ pmu_set_power_domain(PD_TCPD1, pmu_pd_on);
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+ pmu_set_power_domain(PD_TCPD0, pmu_pd_on);
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+ pmu_set_power_domain(PD_GPU, pmu_pd_on);
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+}
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+
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+void rk3399_flush_l2_b(void)
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{
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uint32_t wait_cnt = 0;
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diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h
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index e1ba410..27a453b 100644
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--- a/plat/rockchip/rk3399/drivers/pmu/pmu.h
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+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h
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@@ -136,5 +136,6 @@ struct pmu_slpdata_s {
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extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT];
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extern void sram_func_set_ddrctl_pll(uint32_t pll_src);
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+void pmu_power_domains_on(void);
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#endif /* PMU_H */
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diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c
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index c877dbd..98b5ad6 100644
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--- a/plat/rockchip/rk3399/drivers/soc/soc.c
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+++ b/plat/rockchip/rk3399/drivers/soc/soc.c
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@@ -17,6 +17,7 @@
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#include <dram.h>
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#include <m0_ctl.h>
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#include <plat_private.h>
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+#include <pmu.h>
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#include <rk3399_def.h>
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#include <secure.h>
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#include <soc.h>
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@@ -327,6 +328,7 @@ void soc_global_soft_reset_init(void)
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void __dead2 soc_global_soft_reset(void)
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{
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+ pmu_power_domains_on();
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set_pll_slow_mode(VPLL_ID);
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set_pll_slow_mode(NPLL_ID);
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set_pll_slow_mode(GPLL_ID);
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