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d1186b8a0e
I have changed the way the patches are generated a bit. Instead of using orange-pi branch from megous tree for 6.6 kernel, I have used the following kernel branches a83t-suspend, af8133j, anx, audio, axp, cam, drm, err, fixes, mbus, modem, opi3, pb, pinetab, pp, ppkb, samuel, speed, tbs-a711, ths These branches were carefully chosen to include only allwinner related patches and remove importing of the rockchip related patches into the allwinner kernel. Following patches are modified to fix patch application failure - patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch - patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch - patches.armbian/arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-v1_6_2.patch - patches.armbian/arm64-dts-allwinner-h616-LED-green_power_on-red_status_heartbeat.patch - patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch - patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1.patch Following patches are modified because of kernel api change to fix compilation failure - patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch - patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch
181 lines
6.9 KiB
Diff
181 lines
6.9 KiB
Diff
From 62eb86473f2ccdd278983f4c6f1e41c895edc9b7 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Sat, 26 Oct 2019 21:23:55 +0200
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Subject: [PATCH 033/170] drv:media: cedrus: hevc: tiles hack
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/staging/media/sunxi/cedrus/cedrus.h | 2 +
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.../staging/media/sunxi/cedrus/cedrus_h265.c | 93 +++++++++++++++++--
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2 files changed, 89 insertions(+), 6 deletions(-)
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diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h
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index 3bc094eb4..9d34e5785 100644
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--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
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+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
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@@ -146,6 +146,8 @@ struct cedrus_ctx {
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ssize_t mv_col_buf_unit_size;
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void *neighbor_info_buf;
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dma_addr_t neighbor_info_buf_addr;
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+ void *entry_points_buf;
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+ dma_addr_t entry_points_buf_addr;
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} h265;
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struct {
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unsigned int last_frame_p_type;
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diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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index 44f385be9..f71ce6f87 100644
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--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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@@ -329,6 +329,61 @@ static int cedrus_h265_is_low_delay(struct cedrus_run *run)
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return 0;
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}
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+static void write_entry_point_list(struct cedrus_ctx *ctx,
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+ struct cedrus_run *run,
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+ unsigned int ctb_addr_x,
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+ unsigned int ctb_addr_y)
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+{
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+ const struct v4l2_ctrl_hevc_slice_params *slice_params;
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+ const struct v4l2_ctrl_hevc_pps *pps;
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+ struct cedrus_dev *dev = ctx->dev;
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+ int i, x, tx, y, ty;
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+ u32 *entry_points;
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+
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+ pps = run->h265.pps;
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+ slice_params = run->h265.slice_params;
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+
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+ for (x = 0, tx = 0; tx < pps->num_tile_columns_minus1 + 1; tx++) {
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+ if (x + pps->column_width_minus1[tx] + 1 > ctb_addr_x)
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+ break;
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+
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+ x += pps->column_width_minus1[tx] + 1;
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+ }
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+
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+ for (y = 0, ty = 0; ty < pps->num_tile_rows_minus1 + 1; ty++) {
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+ if (y + pps->row_height_minus1[ty] + 1 > ctb_addr_y)
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+ break;
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+
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+ y += pps->row_height_minus1[ty] + 1;
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+ }
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+
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+ cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, (y << 16) | (x << 0));
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+ cedrus_write(dev, VE_DEC_H265_TILE_END_CTB,
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+ ((y + pps->row_height_minus1[ty]) << 16) |
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+ ((x + pps->column_width_minus1[tx]) << 0));
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+
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+ entry_points = ctx->codec.h265.entry_points_buf;
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+ if (pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED) {
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+ for (i = 0; i < slice_params->num_entry_point_offsets; i++)
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+ entry_points[i] = slice_params->entry_point_offset_minus1[i] + 1;
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+ } else {
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+ for (i = 0; i < slice_params->num_entry_point_offsets; i++) {
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+ if (tx + 1 >= pps->num_tile_columns_minus1 + 1) {
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+ x = 0;
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+ tx = 0;
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+ y += pps->row_height_minus1[ty++] + 1;
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+ } else {
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+ x += pps->column_width_minus1[tx++] + 1;
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+ }
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+
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+ entry_points[i * 4 + 0] = slice_params->entry_point_offset_minus1[i] + 1;
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+ entry_points[i * 4 + 1] = 0x0;
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+ entry_points[i * 4 + 2] = (y << 16) | (x << 0);
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+ entry_points[i * 4 + 3] = ((y + pps->row_height_minus1[ty]) << 16) | ((x + pps->column_width_minus1[tx]) << 0);
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+ }
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+ }
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+}
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+
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static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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struct cedrus_run *run)
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{
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@@ -340,6 +395,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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const struct v4l2_hevc_pred_weight_table *pred_weight_table;
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unsigned int width_in_ctb_luma, ctb_size_luma;
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unsigned int log2_max_luma_coding_block_size;
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+ unsigned int ctb_addr_x, ctb_addr_y;
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dma_addr_t src_buf_addr;
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dma_addr_t src_buf_end_addr;
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u32 chroma_log2_weight_denom;
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@@ -419,12 +475,19 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg);
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/* Coding tree block address */
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- reg = VE_DEC_H265_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma);
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- reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma);
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+ ctb_addr_x = slice_params->slice_segment_addr % width_in_ctb_luma;
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+ ctb_addr_y = slice_params->slice_segment_addr / width_in_ctb_luma;
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+ reg = VE_DEC_H265_DEC_CTB_ADDR_X(ctb_addr_x);
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+ reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(ctb_addr_y);
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cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg);
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- cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0);
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- cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0);
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+ if ((pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) ||
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+ (pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED)) {
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+ write_entry_point_list(ctx, run, ctb_addr_x, ctb_addr_y);
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+ } else {
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+ cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0);
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+ cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0);
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+ }
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/* Clear the number of correctly-decoded coding tree blocks. */
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if (ctx->fh.m2m_ctx->new_frame)
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@@ -528,7 +591,9 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED,
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pps->flags);
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- /* TODO: VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED */
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+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED,
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+ V4L2_HEVC_PPS_FLAG_TILES_ENABLED,
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+ pps->flags);
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reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED,
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V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED,
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@@ -606,12 +671,14 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom +
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pred_weight_table->delta_chroma_log2_weight_denom;
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- reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(0) |
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+ reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(slice_params->num_entry_point_offsets) |
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VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(chroma_log2_weight_denom) |
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VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(pred_weight_table->luma_log2_weight_denom);
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cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO2, reg);
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+ cedrus_write(dev, VE_DEC_H265_ENTRY_POINT_OFFSET_ADDR, ctx->codec.h265.entry_points_buf_addr >> 8);
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+
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/* Decoded picture size. */
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reg = VE_DEC_H265_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) |
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@@ -706,6 +773,17 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx)
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if (!ctx->codec.h265.neighbor_info_buf)
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return -ENOMEM;
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+ ctx->codec.h265.entry_points_buf =
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+ dma_alloc_coherent(dev->dev, CEDRUS_H265_ENTRY_POINTS_BUF_SIZE,
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+ &ctx->codec.h265.entry_points_buf_addr,
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+ GFP_KERNEL);
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+ if (!ctx->codec.h265.entry_points_buf) {
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+ dma_free_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE,
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+ ctx->codec.h265.neighbor_info_buf,
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+ ctx->codec.h265.neighbor_info_buf_addr);
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+ return -ENOMEM;
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+ }
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+
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return 0;
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}
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@@ -726,6 +804,9 @@ static void cedrus_h265_stop(struct cedrus_ctx *ctx)
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ctx->codec.h265.neighbor_info_buf,
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ctx->codec.h265.neighbor_info_buf_addr,
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DMA_ATTR_NO_KERNEL_MAPPING);
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+ dma_free_coherent(dev->dev, CEDRUS_H265_ENTRY_POINTS_BUF_SIZE,
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+ ctx->codec.h265.entry_points_buf,
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+ ctx->codec.h265.entry_points_buf_addr);
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}
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static void cedrus_h265_trigger(struct cedrus_ctx *ctx)
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--
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2.35.3
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