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- `risc-v`: rework RichNeese's boards, reduce families, move tweaks to boards - `risc-v`/`starfive`: `CONFIG_MOTORCOMM_PHY=m` for the onboard Ethernet - `risc-v`/`starfive`: use mainline kernel 6.1.y, with StarFive's rebased patches against `v6.1.5` - from https://github.com/starfive-tech/linux/commits/visionfive - contention point: `1022-soc-sifive-ccache-Add-StarFive-JH71x0-support.patch` which I merged half-assed, need review/fixes? - `risc-v`/`starfive`: update kernel config, sans changes - `risc-v`/`starfive`: switch from `grub` to `extlinux` - `risc-v`/`starfive`: new `starfive` family with their (vendor) kernel Co-authored-by: Richard Neese <r.neese@gmail.com>
39 lines
1.1 KiB
Diff
39 lines
1.1 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Date: Mon, 7 Nov 2022 21:05:18 +0100
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Subject: net: phy: motorcomm: Disable rgmii rx delay
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Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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---
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drivers/net/phy/motorcomm.c | 7 +++++++
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1 file changed, 7 insertions(+)
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diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
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index c7593f224177..35a4f2a76996 100644
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--- a/drivers/net/phy/motorcomm.c
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+++ b/drivers/net/phy/motorcomm.c
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@@ -160,6 +160,7 @@
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#define YT8521_CHIP_CONFIG_REG 0xA001
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#define YT8521_CCR_SW_RST BIT(15)
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+#define YT8521_CCR_RXC_DLY_EN BIT(8)
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#define YT8521_CCR_MODE_SEL_MASK (BIT(2) | BIT(1) | BIT(0))
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#define YT8521_CCR_MODE_UTP_TO_RGMII 0
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@@ -1150,6 +1151,12 @@ static int yt8521_config_init(struct phy_device *phydev)
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val);
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if (ret < 0)
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goto err_restore_page;
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+
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+ /* disable rx delay */
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+ ret = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
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+ YT8521_CCR_RXC_DLY_EN, 0);
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+ if (ret < 0)
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+ goto err_restore_page;
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}
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/* disable auto sleep */
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--
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Armbian
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