mirrors/armbian_build
1
0
Fork 0
mirror of https://github.com/armbian/build.git synced 2025-09-19 12:41:39 +02:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity
armbian_build/patch/kernel/archive/spacemit-6.1/046-include-dt-bindings.patch
ColorfulRhino 91b514d982 SpacemiT: current: Rewrite kernel patches
2024-07-01 19:15:00 +02:00

774 lines
21 KiB
Diff
Raw Blame History

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Patrick Yavitz <pyavitz@armbian.com>
Date: Fri, 21 Jun 2024 11:54:06 -0400
Subject: add spacemit patch set
source: https://gitee.com/bianbu-linux/linux-6.1
Signed-off-by: Patrick Yavitz <pyavitz@armbian.com>
---
include/dt-bindings/clock/spacemit-k1x-clock.h | 201 ++++++++++
include/dt-bindings/display/spacemit-dpu.h | 40 ++
include/dt-bindings/dma/k1x-dmac.h | 58 +++
include/dt-bindings/mmc/k1x_sdhci.h | 53 +++
include/dt-bindings/pinctrl/k1-x-pinctrl.h | 198 +++++++++
include/dt-bindings/pmu/k1x_pmu.h | 16 +
include/dt-bindings/reset/spacemit-k1x-reset.h | 122 ++++++
include/dt-bindings/usb/k1x_ci_usb.h | 15 +
8 files changed, 703 insertions(+)
diff --git a/include/dt-bindings/clock/spacemit-k1x-clock.h b/include/dt-bindings/clock/spacemit-k1x-clock.h
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/include/dt-bindings/clock/spacemit-k1x-clock.h
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+
+#ifndef _DT_BINDINGS_CLK_SPACEMIT_K1X_H_
+#define _DT_BINDINGS_CLK_SPACEMIT_K1X_H_
+
+#define CLK_PLL2 0
+#define CLK_PLL3 1
+#define CLK_PLL1_D2 2
+#define CLK_PLL1_D3 3
+#define CLK_PLL1_D4 4
+#define CLK_PLL1_D5 5
+#define CLK_PLL1_D6 6
+#define CLK_PLL1_D7 7
+#define CLK_PLL1_D8 8
+#define CLK_PLL1_D11 9
+#define CLK_PLL1_D13 10
+#define CLK_PLL1_D23 11
+#define CLK_PLL1_D64 12
+#define CLK_PLL1_D10_AUD 13
+#define CLK_PLL1_D100_AUD 14
+#define CLK_PLL2_D1 15
+#define CLK_PLL2_D2 16
+#define CLK_PLL2_D3 17
+#define CLK_PLL2_D4 18
+#define CLK_PLL2_D5 19
+#define CLK_PLL2_D6 20
+#define CLK_PLL2_D7 21
+#define CLK_PLL2_D8 22
+#define CLK_PLL3_D1 23
+#define CLK_PLL3_D2 24
+#define CLK_PLL3_D3 25
+#define CLK_PLL3_D4 26
+#define CLK_PLL3_D5 27
+#define CLK_PLL3_D6 28
+#define CLK_PLL3_D7 29
+#define CLK_PLL3_D8 30
+#define CLK_PLL1_307P2 31
+#define CLK_PLL1_76P8 32
+#define CLK_PLL1_61P44 33
+#define CLK_PLL1_153P6 34
+#define CLK_PLL1_102P4 35
+#define CLK_PLL1_51P2 36
+#define CLK_PLL1_51P2_AP 37
+#define CLK_PLL1_57P6 38
+#define CLK_PLL1_25P6 39
+#define CLK_PLL1_12P8 40
+#define CLK_PLL1_12P8_WDT 41
+#define CLK_PLL1_6P4 42
+#define CLK_PLL1_3P2 43
+#define CLK_PLL1_1P6 44
+#define CLK_PLL1_0P8 45
+#define CLK_PLL1_351 46
+#define CLK_PLL1_409P6 47
+#define CLK_PLL1_204P8 48
+#define CLK_PLL1_491 49
+#define CLK_PLL1_245P76 50
+#define CLK_PLL1_614 51
+#define CLK_PLL1_47P26 52
+#define CLK_PLL1_31P5 53
+#define CLK_PLL1_819 54
+#define CLK_PLL1_1228 55
+#define CLK_SLOW_UART1 56
+#define CLK_SLOW_UART2 57
+#define CLK_UART1 58
+#define CLK_UART2 59
+#define CLK_UART3 60
+#define CLK_UART4 61
+#define CLK_UART5 62
+#define CLK_UART6 63
+#define CLK_UART7 64
+#define CLK_UART8 65
+#define CLK_UART9 66
+#define CLK_GPIO 67
+#define CLK_PWM0 68
+#define CLK_PWM1 69
+#define CLK_PWM2 70
+#define CLK_PWM3 71
+#define CLK_PWM4 72
+#define CLK_PWM5 73
+#define CLK_PWM6 74
+#define CLK_PWM7 75
+#define CLK_PWM8 76
+#define CLK_PWM9 77
+#define CLK_PWM10 78
+#define CLK_PWM11 79
+#define CLK_PWM12 80
+#define CLK_PWM13 81
+#define CLK_PWM14 82
+#define CLK_PWM15 83
+#define CLK_PWM16 84
+#define CLK_PWM17 85
+#define CLK_PWM18 86
+#define CLK_PWM19 87
+#define CLK_SSP3 88
+#define CLK_RTC 89
+#define CLK_TWSI0 90
+#define CLK_TWSI1 91
+#define CLK_TWSI2 92
+#define CLK_TWSI4 93
+#define CLK_TWSI5 94
+#define CLK_TWSI6 95
+#define CLK_TWSI7 96
+#define CLK_TWSI8 97
+#define CLK_TIMERS1 98
+#define CLK_TIMERS2 99
+#define CLK_AIB 100
+#define CLK_ONEWIRE 101
+#define CLK_SSPA0 102
+#define CLK_SSPA1 103
+#define CLK_DRO 104
+#define CLK_IR 105
+#define CLK_TSEN 106
+#define CLK_IPC_AP2AUD 107
+#define CLK_CAN0 108
+#define CLK_CAN0_BUS 109
+#define CLK_WDT 110
+#define CLK_RIPC 111
+#define CLK_JPG 112
+#define CLK_JPF_4KAFBC 113
+#define CLK_JPF_2KAFBC 114
+#define CLK_CCIC2PHY 115
+#define CLK_CCIC3PHY 116
+#define CLK_CSI 117
+#define CLK_CAMM0 118
+#define CLK_CAMM1 119
+#define CLK_CAMM2 120
+#define CLK_ISP_CPP 121
+#define CLK_ISP_BUS 122
+#define CLK_ISP 123
+#define CLK_DPU_MCLK 124
+#define CLK_DPU_ESC 125
+#define CLK_DPU_BIT 126
+#define CLK_DPU_PXCLK 127
+#define CLK_DPU_HCLK 128
+#define CLK_DPU_SPI 129
+#define CLK_DPU_SPI_HBUS 130
+#define CLK_DPU_SPIBUS 131
+#define CLK_SPU_SPI_ACLK 132
+#define CLK_V2D 133
+#define CLK_CCIC_4X 134
+#define CLK_CCIC1PHY 135
+#define CLK_SDH_AXI 136
+#define CLK_SDH0 137
+#define CLK_SDH1 138
+#define CLK_SDH2 139
+#define CLK_USB_P1 140
+#define CLK_USB_AXI 141
+#define CLK_USB30 142
+#define CLK_QSPI 143
+#define CLK_QSPI_BUS 144
+#define CLK_DMA 145
+#define CLK_AES 146
+#define CLK_VPU 147
+#define CLK_GPU 148
+#define CLK_EMMC 149
+#define CLK_EMMC_X 150
+#define CLK_AUDIO 151
+#define CLK_HDMI 152
+#define CLK_CCI550 153
+#define CLK_PMUA_ACLK 154
+#define CLK_CPU_C0_HI 155
+#define CLK_CPU_C0_CORE 156
+#define CLK_CPU_C0_ACE 157
+#define CLK_CPU_C0_TCM 158
+#define CLK_CPU_C1_HI 159
+#define CLK_CPU_C1_CORE 160
+#define CLK_CPU_C1_ACE 161
+#define CLK_PCIE0 162
+#define CLK_PCIE1 163
+#define CLK_PCIE2 164
+#define CLK_EMAC0_BUS 165
+#define CLK_EMAC0_PTP 166
+#define CLK_EMAC1_BUS 167
+#define CLK_EMAC1_PTP 168
+
+#define CLK_SEC_UART1 169
+#define CLK_SEC_SSP2 170
+#define CLK_SEC_TWSI3 171
+#define CLK_SEC_RTC 172
+#define CLK_SEC_TIMERS0 173
+#define CLK_SEC_KPC 174
+#define CLK_SEC_GPIO 175
+
+#define CLK_APB 176
+
+#define CLK_PLL3_80 177
+#define CLK_PLL3_40 178
+#define CLK_PLL3_20 179
+
+#define CLK_SLOW_UART 180
+
+#define CLK_I2S_SYSCLK 181
+#define CLK_I2S_BCLK 182
+#define CLK_RCPU_HDMIAUDIO 183
+#define CLK_RCPU_CAN 184
+#define CLK_RCPU_CAN_BUS 185
+
+#define CLK_RCPU2_PWM 186
+
+#define CLK_MAX_NO 187
+#endif /* _DT_BINDINGS_CLK_SPACEMIT_K1X_H_ */
diff --git a/include/dt-bindings/display/spacemit-dpu.h b/include/dt-bindings/display/spacemit-dpu.h
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/include/dt-bindings/display/spacemit-dpu.h
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#ifndef SPACEMIT_DT_BINDINGS_DISPLAY_DPU_H
+#define SPACEMIT_DT_BINDINGS_DISPLAY_DPU_H
+
+/* DPU type */
+#define HDMI 0
+#define DSI 1
+
+/* DPU sub component */
+#define ONLINE0 0
+#define ONLINE1 1
+#define ONLINE2 2
+#define OFFLINE0 3
+#define OFFLINE1 4
+
+/* online/offline path id */
+#define WB0 (1<<0)
+#define WB1 (1<<1)
+#define COMPOSER0 (1<<2)
+#define COMPOSER1 (1<<3)
+#define COMPOSER2 (1<<4)
+#define COMPOSER3 (1<<5)
+#define PP0 (1<<6)
+#define PP1 (1<<7)
+#define PP2 (1<<8)
+#define SCALER0 (1<<9)
+#define SCALER1 (1<<10)
+#define SCALER2 (1<<11)
+#define SCALER3 (1<<12)
+#define SCALER4 (1<<13)
+#define ACAD0 (1<<14)
+#define ACAD1 (1<<15)
+#define ACAD2 (1<<16)
+#define LUT3D0 (1<<17)
+#define LUT3D1 (1<<18)
+#define LUT3D2 (1<<19)
+
+#endif /* SPACEMIT_DT_BINDINGS_DISPLAY_DPU_H */
+
diff --git a/include/dt-bindings/dma/k1x-dmac.h b/include/dt-bindings/dma/k1x-dmac.h
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/include/dt-bindings/dma/k1x-dmac.h
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This header provides constants for SPACEMIT DMA channel map table.
+ *
+ * Copyright (C) 2023 Spacemit
+ */
+
+#ifndef __DTS_K1X_DMAC_H
+#define __DTS_K1X_DMAC_H
+
+#define DMA_UART0_TX 3
+#define DMA_UART0_RX 4
+#define DMA_UART2_TX 5
+#define DMA_UART2_RX 6
+#define DMA_UART3_TX 7
+#define DMA_UART3_RX 8
+#define DMA_UART4_TX 9
+#define DMA_UART4_RX 10
+#define DMA_UART5_TX 25
+#define DMA_UART5_RX 26
+#define DMA_UART6_TX 27
+#define DMA_UART6_RX 28
+#define DMA_UART7_TX 29
+#define DMA_UART7_RX 30
+#define DMA_UART8_TX 31
+#define DMA_UART8_RX 32
+#define DMA_UART9_TX 33
+#define DMA_UART9_RX 34
+
+#define DMA_I2C0_TX 11
+#define DMA_I2C0_RX 12
+#define DMA_I2C1_TX 13
+#define DMA_I2C1_RX 14
+#define DMA_I2C2_TX 15
+#define DMA_I2C2_RX 16
+#define DMA_I2C4_TX 17
+#define DMA_I2C4_RX 18
+#define DMA_I2C5_TX 35
+#define DMA_I2C5_RX 36
+#define DMA_I2C6_TX 37
+#define DMA_I2C6_RX 38
+#define DMA_I2C7_TX 39
+#define DMA_I2C7_RX 40
+#define DMA_I2C8_TX 41
+#define DMA_I2C8_RX 42
+
+#define DMA_SSP3_TX 19
+#define DMA_SSP3_RX 20
+#define DMA_SSPA0_TX 21
+#define DMA_SSPA0_RX 22
+#define DMA_SSPA1_TX 23
+#define DMA_SSPA1_RX 24
+#define DMA_QSPI_RX 44
+#define DMA_QSPI_TX 45
+
+#define DMA_CAN0_RX 43
+
+#endif /*__DTS_K1X_DMAC_H*/
diff --git a/include/dt-bindings/mmc/k1x_sdhci.h b/include/dt-bindings/mmc/k1x_sdhci.h
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/include/dt-bindings/mmc/k1x_sdhci.h
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * include/linux/dt-bindings/mmc/k1x_sdhci.h
+ *
+ * SDH driver for SPACEMIT K1X SDCHI
+ * Copyright (C) 2023 Spacemit
+ */
+
+#ifndef K1X_DT_BINDINGS_MMC_SDHCI_H
+#define K1X_DT_BINDINGS_MMC_SDHCI_H
+
+/* K1x specific flag */
+
+/* MMC Quirks */
+/* Controller has an unusable ADMA engine */
+#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
+#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
+/* Controller does not support HS200 */
+#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)
+/* Support SDH controller on FPGA */
+#define SDHCI_QUIRK2_SUPPORT_PHY_BYPASS (1<<25)
+/* Disable scan card at probe phase */
+#define SDHCI_QUIRK2_DISABLE_PROBE_CDSCAN (1<<26)
+/* Need to set IO capability by SOC part register */
+#define SDHCI_QUIRK2_SET_AIB_MMC (1<<27)
+/* Controller not support phy module */
+#define SDHCI_QUIRK2_BROKEN_PHY_MODULE (1<<28)
+/* Controller support encrypt module */
+#define SDHCI_QUIRK2_SUPPORT_ENCRYPT (1<<29)
+
+/* Common flag */
+/* Controller provides an incorrect timeout value for transfers */
+#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
+/* Controller has unreliable card detection */
+#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
+
+/* Controller reports inverted write-protect state */
+#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
+
+/* MMC caps */
+#define MMC_CAP2_CRC_SW_RETRY (1 << 30)
+
+/* for SDIO */
+#define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */
+
+/* for SD card */
+#define MMC_CAP_UHS_SDR12 (1 << 16) /* Host supports UHS SDR12 mode */
+#define MMC_CAP_UHS_SDR25 (1 << 17) /* Host supports UHS SDR25 mode */
+#define MMC_CAP_UHS_SDR50 (1 << 18) /* Host supports UHS SDR50 mode */
+#define MMC_CAP_UHS_SDR104 (1 << 19) /* Host supports UHS SDR104 mode */
+#define MMC_CAP_UHS_DDR50 (1 << 20) /* Host supports UHS DDR50 mode */
+#endif /* K1X_DT_BINDINGS_MMC_SDHCI_H */
+
diff --git a/include/dt-bindings/pinctrl/k1-x-pinctrl.h b/include/dt-bindings/pinctrl/k1-x-pinctrl.h
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/include/dt-bindings/pinctrl/k1-x-pinctrl.h
@@ -0,0 +1,198 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __DT_BINDINGS_K1X_PINCTRL_H
+#define __DT_BINDINGS_K1X_PINCTRL_H
+
+/* pin offset */
+#define PINID(x) ((x) + 1)
+
+#define GPIO_00 PINID(0)
+#define GPIO_01 PINID(1)
+#define GPIO_02 PINID(2)
+#define GPIO_03 PINID(3)
+#define GPIO_04 PINID(4)
+#define GPIO_05 PINID(5)
+#define GPIO_06 PINID(6)
+#define GPIO_07 PINID(7)
+#define GPIO_08 PINID(8)
+#define GPIO_09 PINID(9)
+#define GPIO_10 PINID(10)
+#define GPIO_11 PINID(11)
+#define GPIO_12 PINID(12)
+#define GPIO_13 PINID(13)
+#define GPIO_14 PINID(14)
+#define GPIO_15 PINID(15)
+#define GPIO_16 PINID(16)
+#define GPIO_17 PINID(17)
+#define GPIO_18 PINID(18)
+#define GPIO_19 PINID(19)
+#define GPIO_20 PINID(20)
+#define GPIO_21 PINID(21)
+#define GPIO_22 PINID(22)
+#define GPIO_23 PINID(23)
+#define GPIO_24 PINID(24)
+#define GPIO_25 PINID(25)
+#define GPIO_26 PINID(26)
+#define GPIO_27 PINID(27)
+#define GPIO_28 PINID(28)
+#define GPIO_29 PINID(29)
+#define GPIO_30 PINID(30)
+#define GPIO_31 PINID(31)
+
+#define GPIO_32 PINID(32)
+#define GPIO_33 PINID(33)
+#define GPIO_34 PINID(34)
+#define GPIO_35 PINID(35)
+#define GPIO_36 PINID(36)
+#define GPIO_37 PINID(37)
+#define GPIO_38 PINID(38)
+#define GPIO_39 PINID(39)
+#define GPIO_40 PINID(40)
+#define GPIO_41 PINID(41)
+#define GPIO_42 PINID(42)
+#define GPIO_43 PINID(43)
+#define GPIO_44 PINID(44)
+#define GPIO_45 PINID(45)
+#define GPIO_46 PINID(46)
+#define GPIO_47 PINID(47)
+#define GPIO_48 PINID(48)
+#define GPIO_49 PINID(49)
+#define GPIO_50 PINID(50)
+#define GPIO_51 PINID(51)
+#define GPIO_52 PINID(52)
+#define GPIO_53 PINID(53)
+#define GPIO_54 PINID(54)
+#define GPIO_55 PINID(55)
+#define GPIO_56 PINID(56)
+#define GPIO_57 PINID(57)
+#define GPIO_58 PINID(58)
+#define GPIO_59 PINID(59)
+#define GPIO_60 PINID(60)
+#define GPIO_61 PINID(61)
+#define GPIO_62 PINID(62)
+#define GPIO_63 PINID(63)
+
+#define GPIO_64 PINID(64)
+#define GPIO_65 PINID(65)
+#define GPIO_66 PINID(66)
+#define GPIO_67 PINID(67)
+#define GPIO_68 PINID(68)
+#define GPIO_69 PINID(69)
+#define PRI_TDI PINID(70)
+#define PRI_TMS PINID(71)
+#define PRI_TCK PINID(72)
+#define PRI_TDO PINID(73)
+#define GPIO_74 PINID(74)
+#define GPIO_75 PINID(75)
+#define GPIO_76 PINID(76)
+#define GPIO_77 PINID(77)
+#define GPIO_78 PINID(78)
+#define GPIO_79 PINID(79)
+#define GPIO_80 PINID(80)
+#define GPIO_81 PINID(81)
+#define GPIO_82 PINID(82)
+#define GPIO_83 PINID(83)
+#define GPIO_84 PINID(84)
+#define GPIO_85 PINID(85)
+
+#define QSPI_DAT0 PINID(89)
+#define QSPI_DAT1 PINID(90)
+#define QSPI_DAT2 PINID(91)
+#define QSPI_DAT3 PINID(92)
+#define QSPI_CSI PINID(93)
+#define QSPI_CLK PINID(94)
+
+#define MMC1_DAT3 PINID(109)
+#define MMC1_DAT2 PINID(110)
+#define MMC1_DAT1 PINID(111)
+#define MMC1_DAT0 PINID(112)
+#define MMC1_CMD PINID(113)
+#define MMC1_CLK PINID(114)
+#define GPIO_110 PINID(115)
+#define PWR_SCL PINID(116)
+#define PWR_SDA PINID(117)
+#define VCXO_EN PINID(118)
+#define DVL0 PINID(119)
+#define DVL1 PINID(120)
+#define PMIC_INT_N PINID(121)
+#define GPIO_86 PINID(122)
+#define GPIO_87 PINID(123)
+#define GPIO_88 PINID(124)
+#define GPIO_89 PINID(125)
+#define GPIO_90 PINID(126)
+#define GPIO_91 PINID(127)
+#define GPIO_92 PINID(128)
+
+#define GPIO_111 PINID(130)
+#define GPIO_112 PINID(131)
+#define GPIO_113 PINID(132)
+#define GPIO_114 PINID(133)
+#define GPIO_115 PINID(134)
+#define GPIO_116 PINID(135)
+#define GPIO_117 PINID(136)
+#define GPIO_118 PINID(137)
+#define GPIO_119 PINID(138)
+#define GPIO_120 PINID(139)
+#define GPIO_121 PINID(140)
+#define GPIO_122 PINID(141)
+#define GPIO_123 PINID(142)
+#define GPIO_124 PINID(143)
+#define GPIO_125 PINID(144)
+#define GPIO_126 PINID(145)
+#define GPIO_127 PINID(146)
+
+/* pin mux */
+#define MUX_MODE0 0
+#define MUX_MODE1 1
+#define MUX_MODE2 2
+#define MUX_MODE3 3
+#define MUX_MODE4 4
+#define MUX_MODE5 5
+#define MUX_MODE6 6
+#define MUX_MODE7 7
+
+/* strong pull resistor */
+#define SPU_EN (1 << 3)
+
+/* edge detect */
+#define EDGE_NONE (1 << 6)
+#define EDGE_RISE (1 << 4)
+#define EDGE_FALL (1 << 5)
+#define EDGE_BOTH (3 << 4)
+
+/* slew rate output control */
+#define SLE_EN (1 << 7)
+
+/* schmitter trigger input threshhold */
+#define ST00 (0 << 8)
+#define ST01 (1 << 8)
+#define ST02 (2 << 8)
+#define ST03 (3 << 8)
+
+/* driver strength*/
+#define PAD_1V8_DS0 (0 << 11)
+#define PAD_1V8_DS1 (1 << 11)
+#define PAD_1V8_DS2 (2 << 11)
+#define PAD_1V8_DS3 (3 << 11)
+
+/*
+ * notice: !!!
+ * ds2 ---> bit10, ds1 ----> bit12, ds0 ----> bit11
+*/
+#define PAD_3V_DS0 (0 << 10) /* bit[12:10] 000 */
+#define PAD_3V_DS1 (2 << 10) /* bit[12:10] 010 */
+#define PAD_3V_DS2 (4 << 10) /* bit[12:10] 100 */
+#define PAD_3V_DS3 (6 << 10) /* bit[12:10] 110 */
+#define PAD_3V_DS4 (1 << 10) /* bit[12:10] 001 */
+#define PAD_3V_DS5 (3 << 10) /* bit[12:10] 011 */
+#define PAD_3V_DS6 (5 << 10) /* bit[12:10] 101 */
+#define PAD_3V_DS7 (7 << 10) /* bit[12:10] 111 */
+
+/* pull up/down */
+#define PULL_DIS (0 << 13) /* bit[15:13] 000 */
+#define PULL_UP (6 << 13) /* bit[15:13] 110 */
+#define PULL_DOWN (5 << 13) /* bit[15:13] 101 */
+
+#define K1X_PADCONF(pinid, conf, mux) ((pinid) * 4) (conf) (mux)
+
+#endif /* __DT_BINDINGS_K1PRO_PINCTRL_H */
diff --git a/include/dt-bindings/pmu/k1x_pmu.h b/include/dt-bindings/pmu/k1x_pmu.h
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/include/dt-bindings/pmu/k1x_pmu.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __DT_BINDINGS_PMU_K1X_H__
+#define __DT_BINDINGS_PMU_K1X_H__
+
+#define K1X_PMU_BUS_PWR_DOMAIN 0
+#define K1X_PMU_VPU_PWR_DOMAIN 1
+#define K1X_PMU_GPU_PWR_DOMAIN 2
+#define K1X_PMU_LCD_PWR_DOMAIN 3
+#define K1X_PMU_ISP_PWR_DOMAIN 4
+#define K1X_PMU_AUD_PWR_DOMAIN 5
+#define K1X_PMU_GNSS_PWR_DOMAIN 6
+#define K1X_PMU_HDMI_PWR_DOMAIN 7
+#define K1X_PMU_DUMMY_PWR_DOMAIN 8
+
+#endif
diff --git a/include/dt-bindings/reset/spacemit-k1x-reset.h b/include/dt-bindings/reset/spacemit-k1x-reset.h
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/include/dt-bindings/reset/spacemit-k1x-reset.h
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#ifndef __DT_BINDINGS_RESET_SAPCEMIT_K1X_H__
+#define __DT_BINDINGS_RESET_SAPCEMIT_K1X_H__
+//APBC
+#define RESET_UART1 1
+#define RESET_UART2 2
+#define RESET_GPIO 3
+#define RESET_PWM0 4
+#define RESET_PWM1 5
+#define RESET_PWM2 6
+#define RESET_PWM3 7
+#define RESET_PWM4 8
+#define RESET_PWM5 9
+#define RESET_PWM6 10
+#define RESET_PWM7 11
+#define RESET_PWM8 12
+#define RESET_PWM9 13
+#define RESET_PWM10 14
+#define RESET_PWM11 15
+#define RESET_PWM12 16
+#define RESET_PWM13 17
+#define RESET_PWM14 18
+#define RESET_PWM15 19
+#define RESET_PWM16 20
+#define RESET_PWM17 21
+#define RESET_PWM18 22
+#define RESET_PWM19 23
+#define RESET_SSP3 24
+#define RESET_UART3 25
+#define RESET_RTC 26
+#define RESET_TWSI0 27
+
+#define RESET_TIMERS1 28
+#define RESET_AIB 29
+#define RESET_TIMERS2 30
+#define RESET_ONEWIRE 31
+#define RESET_SSPA0 32
+#define RESET_SSPA1 33
+#define RESET_DRO 34
+#define RESET_IR 35
+#define RESET_TWSI1 36
+
+#define RESET_TSEN 37
+#define RESET_TWSI2 38
+#define RESET_TWSI4 39
+#define RESET_TWSI5 40
+#define RESET_TWSI6 41
+#define RESET_TWSI7 42
+#define RESET_TWSI8 43
+#define RESET_IPC_AP2AUD 44
+#define RESET_UART4 45
+#define RESET_UART5 46
+#define RESET_UART6 47
+#define RESET_UART7 48
+#define RESET_UART8 49
+#define RESET_UART9 50
+#define RESET_CAN0 51
+
+//MPMU
+#define RESET_WDT 52
+
+//APMU
+#define RESET_JPG 53
+#define RESET_CSI 54
+#define RESET_CCIC2_PHY 55
+#define RESET_CCIC3_PHY 56
+#define RESET_ISP 57
+#define RESET_ISP_AHB 58
+#define RESET_ISP_CI 59
+#define RESET_ISP_CPP 60
+#define RESET_LCD 61
+#define RESET_DSI_ESC 62
+#define RESET_V2D 63
+#define RESET_MIPI 64
+#define RESET_LCD_SPI 65
+#define RESET_LCD_SPI_BUS 66
+#define RESET_LCD_SPI_HBUS 67
+#define RESET_LCD_MCLK 68
+#define RESET_CCIC_4X 69
+#define RESET_CCIC1_PHY 70
+#define RESET_SDH_AXI 71
+#define RESET_SDH0 72
+#define RESET_SDH1 73
+#define RESET_USB_AXI 74
+#define RESET_USBP1_AXI 75
+#define RESET_USB3_0 76
+#define RESET_QSPI 77
+#define RESET_QSPI_BUS 78
+#define RESET_DMA 79
+#define RESET_AES 80
+#define RESET_VPU 81
+#define RESET_GPU 82
+#define RESET_SDH2 83
+#define RESET_MC 84
+#define RESET_EM_AXI 85
+#define RESET_EM 86
+#define RESET_AUDIO_SYS 87
+#define RESET_HDMI 88
+#define RESET_PCIE0 89
+#define RESET_PCIE1 90
+#define RESET_PCIE2 91
+#define RESET_EMAC0 92
+#define RESET_EMAC1 93
+
+//APBC2
+#define RESET_SEC_UART1 94
+#define RESET_SEC_SSP2 95
+#define RESET_SEC_TWSI3 96
+#define RESET_SEC_RTC 97
+#define RESET_SEC_TIMERS0 98
+#define RESET_SEC_KPC 99
+#define RESET_SEC_GPIO 100
+
+#define RESET_RCPU_HDMIAUDIO 101
+#define RESET_RCPU_CAN 102
+
+#define RESET_RCPU2_PWM 103
+
+#define RESET_NUMBER 104
+
+#endif /* __DT_BINDINGS_RESET_SAPCEMIT_K1X_H__ */
diff --git a/include/dt-bindings/usb/k1x_ci_usb.h b/include/dt-bindings/usb/k1x_ci_usb.h
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/include/dt-bindings/usb/k1x_ci_usb.h
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#ifndef _DT_BINDINGS_USB_MV_USB_H
+#define _DT_BINDINGS_USB_MV_USB_H
+
+#define MV_USB_HAS_VBUS_DETECTION (1 << 0)
+#define MV_USB_HAS_IDPIN_DETECTION (1 << 1)
+#define MV_USB_HAS_VBUS_IDPIN_DETECTION \
+ (MV_USB_HAS_VBUS_DETECTION | MV_USB_HAS_IDPIN_DETECTION)
+
+#define MV_USB_MODE_UDC (0)
+#define MV_USB_MODE_OTG (1)
+#define MV_USB_MODE_HOST (2)
+
+#endif
--
Armbian
Reference in New Issue View Git Blame Copy Permalink