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68 lines
2.5 KiB
Diff
68 lines
2.5 KiB
Diff
From 31af191867e9272d80820cc452e3c209a24713fa Mon Sep 17 00:00:00 2001
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From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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Date: Sun, 26 Apr 2020 00:00:09 +0200
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Subject: [PATCH 47/96] drm/meson: Use 24 bits per pixel for the framebuffer on
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Meson8/8b/8m2
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All SoC generations before GXBB don't have a way to configure the
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alpha value for DRM_FORMAT_XRGB8888 and DRM_FORMAT_XBGR8888. These
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formats have an X component instead of an alpha component. On
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Meson8/8b/8m2 there is no way to configure the alpha value to use
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instead of the X component. This results in the fact that the
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formats with X component are only supported on GXBB and newer. Use
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24 bits per pixel and therefore DRM_FORMAT_RGB888 to get a
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working framebuffer console.
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Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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---
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drivers/gpu/drm/meson/meson_drv.c | 26 +++++++++++++++++++++++++-
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1 file changed, 25 insertions(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
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index 17a5cca00..60298cf3b 100644
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--- a/drivers/gpu/drm/meson/meson_drv.c
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+++ b/drivers/gpu/drm/meson/meson_drv.c
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@@ -159,6 +159,30 @@ static void meson_vpu_init(struct meson_drm *priv)
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writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
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}
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+static void meson_fbdev_setup(struct meson_drm *priv)
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+{
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+ unsigned int preferred_bpp;
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+
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+ /*
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+ * All SoC generations before GXBB don't have a way to configure the
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+ * alpha value for DRM_FORMAT_XRGB8888 and DRM_FORMAT_XBGR8888. These
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+ * formats have an X component instead of an alpha component. On
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+ * Meson8/8b/8m2 there is no way to configure the alpha value to use
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+ * instead of the X component. This results in the fact that the
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+ * formats with X component are only supported on GXBB and newer. Use
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+ * 24 bits per pixel and therefore DRM_FORMAT_RGB888 to get a
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+ * working framebuffer console.
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+ */
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+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
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+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
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+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2))
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+ preferred_bpp = 24;
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+ else
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+ preferred_bpp = 32;
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+
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+ drm_fbdev_dma_setup(priv->drm, preferred_bpp);
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+}
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+
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struct meson_drm_soc_attr {
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struct meson_drm_soc_limits limits;
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const struct soc_device_attribute *attrs;
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@@ -362,7 +386,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
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if (ret)
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goto uninstall_irq;
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- drm_fbdev_dma_setup(drm, 32);
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+ meson_fbdev_setup(priv);
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return 0;
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--
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2.45.1
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