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1a12994e79
* [Early WIP] Update sunxi-next to kernel 4.17 * Switch Allwinner 32 and 64bit to U-boot 2018.05 * Adjust patched for 4.17.y / sunxi-next - adjust both configurations - removing FAT support from u-boot (breaks if you try to save) Tested those boards: Cubietruck: wlan fails http://ix.io/1fYS USB OK, HDMI yes Bananapi R40: http://ix.io/1fZm USB OK, HDMI yes Lime A64: USB no, HDMI no, wireless buggy, eMMC yes Orangepi prime H5: OK http://ix.io/1fZJ DVFS no Orangepi2e: DVFS OK, HDMI OK, net OK, wifi OK, eMMC ok, http://ix.io/1fZT * Kernel config update, enabling HDMI on CT+ * Trying to fix A64 HDMI but failed. Fixed M64 ethernet instead * Update orangepioneplus.wip * Update orangepioneplus.wip * Fix H6 build process * Add regulator bits for Orangepizero+, thanks to @5kft * add H5 support for optional 1.3v regulator and 1.3GHz operation This patch adds two optional overlays that can be used to: 1) enable the 1.1v/1.3v regulator on boards that provide the necessary compatible H/W support 2) modify the default CPU clock operating table to add new 1.2GHz and 1.3GHz clocks Note that the generated regulator overlay will only support boards whose 1.1v/1.3v regulator is controlled by GPIO PL6. * updates for the NanoPi NEO Plus2 This change introduces a patch that provides two changes for the NanoPi NEO Plus2: * Configure the "cpu0" to use the "vdd_cpux" regulator; this enables the ability to use higher CPU clocks * Correct the configurations of the on-board power and status LEDs * Adjust nightly building and few boards config cleanup
60 lines
1.9 KiB
Diff
60 lines
1.9 KiB
Diff
From d9ad129ac7a3114568a323f44316d9d5bfd9a3f9 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= <mylene.josserand@bootlin.com>
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Date: Mon, 5 Mar 2018 11:04:31 +0100
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Subject: [PATCH 39/60] ARM: dts: sun8i: Add the H3/H5 CSI controller
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The H3 and H5 features the same CSI controller that was initially found on
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the A31.
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Add a DT node for it.
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Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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---
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arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 +++++++++++++++++++
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.../platform/sunxi/sun6i-csi/sun6i_csi.c | 1 +
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2 files changed, 23 insertions(+)
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diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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index ff05c532792d..be75e7cfdc3a 100644
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--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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@@ -550,6 +550,13 @@
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interrupt-controller;
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#interrupt-cells = <3>;
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+ csi_pins: csi {
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+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
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+ "PE5", "PE6", "PE7", "PE8", "PE9",
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+ "PE10", "PE11";
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+ function = "csi";
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+ };
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+
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emac_rgmii_pins: emac0 {
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pins = "PD0", "PD1", "PD2", "PD3", "PD4",
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"PD5", "PD7", "PD8", "PD9", "PD10",
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@@ -936,6 +943,21 @@
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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+ csi: camera@1cb0000 {
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+ compatible = "allwinner,sun8i-h3-csi",
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+ "allwinner,sun6i-a31-csi";
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+ reg = <0x01cb0000 0x1000>;
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+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_CSI>,
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+ <&ccu CLK_CSI_SCLK>,
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+ <&ccu CLK_DRAM_CSI>;
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+ clock-names = "bus", "mod", "ram";
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+ resets = <&ccu RST_BUS_CSI>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&csi_pins>;
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+ status = "disabled";
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+ };
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+
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rtc: rtc@1f00000 {
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compatible = "allwinner,sun6i-a31-rtc";
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reg = <0x01f00000 0x54>;
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