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synced 2025-09-08 23:31:29 +02:00
1a12994e79
* [Early WIP] Update sunxi-next to kernel 4.17 * Switch Allwinner 32 and 64bit to U-boot 2018.05 * Adjust patched for 4.17.y / sunxi-next - adjust both configurations - removing FAT support from u-boot (breaks if you try to save) Tested those boards: Cubietruck: wlan fails http://ix.io/1fYS USB OK, HDMI yes Bananapi R40: http://ix.io/1fZm USB OK, HDMI yes Lime A64: USB no, HDMI no, wireless buggy, eMMC yes Orangepi prime H5: OK http://ix.io/1fZJ DVFS no Orangepi2e: DVFS OK, HDMI OK, net OK, wifi OK, eMMC ok, http://ix.io/1fZT * Kernel config update, enabling HDMI on CT+ * Trying to fix A64 HDMI but failed. Fixed M64 ethernet instead * Update orangepioneplus.wip * Update orangepioneplus.wip * Fix H6 build process * Add regulator bits for Orangepizero+, thanks to @5kft * add H5 support for optional 1.3v regulator and 1.3GHz operation This patch adds two optional overlays that can be used to: 1) enable the 1.1v/1.3v regulator on boards that provide the necessary compatible H/W support 2) modify the default CPU clock operating table to add new 1.2GHz and 1.3GHz clocks Note that the generated regulator overlay will only support boards whose 1.1v/1.3v regulator is controlled by GPIO PL6. * updates for the NanoPi NEO Plus2 This change introduces a patch that provides two changes for the NanoPi NEO Plus2: * Configure the "cpu0" to use the "vdd_cpux" regulator; this enables the ability to use higher CPU clocks * Correct the configurations of the on-board power and status LEDs * Adjust nightly building and few boards config cleanup
142 lines
4.3 KiB
Diff
142 lines
4.3 KiB
Diff
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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index fffd6d5..2af680c 100644
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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@@ -723,6 +723,9 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
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/* default */
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break;
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case PHY_INTERFACE_MODE_RGMII:
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+ case PHY_INTERFACE_MODE_RGMII_ID:
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+ case PHY_INTERFACE_MODE_RGMII_RXID:
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+ case PHY_INTERFACE_MODE_RGMII_TXID:
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reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
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break;
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case PHY_INTERFACE_MODE_RMII:
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diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
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index 9cbe645..d820d00 100644
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--- a/drivers/net/phy/realtek.c
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+++ b/drivers/net/phy/realtek.c
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@@ -22,11 +22,13 @@
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#define RTL821x_INER 0x12
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#define RTL821x_INER_INIT 0x6400
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#define RTL821x_INSR 0x13
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+
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+#define RTL8211_PAGE_SELECT 0x1f
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+
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#define RTL8211E_INER_LINK_STATUS 0x400
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#define RTL8211F_INER_LINK_STATUS 0x0010
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#define RTL8211F_INSR 0x1d
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-#define RTL8211F_PAGE_SELECT 0x1f
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#define RTL8211F_TX_DELAY 0x100
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MODULE_DESCRIPTION("Realtek PHY driver");
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@@ -46,10 +48,10 @@ static int rtl8211f_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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- phy_write(phydev, RTL8211F_PAGE_SELECT, 0xa43);
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+ phy_write(phydev, RTL8211_PAGE_SELECT, 0xa43);
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err = phy_read(phydev, RTL8211F_INSR);
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/* restore to default page 0 */
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- phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
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+ phy_write(phydev, RTL8211_PAGE_SELECT, 0x0);
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return (err < 0) ? err : 0;
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}
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@@ -102,7 +104,7 @@ static int rtl8211f_config_init(struct phy_device *phydev)
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if (ret < 0)
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return ret;
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- phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
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+ phy_write(phydev, RTL8211_PAGE_SELECT, 0xd08);
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reg = phy_read(phydev, 0x11);
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/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
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@@ -114,7 +116,7 @@ static int rtl8211f_config_init(struct phy_device *phydev)
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phy_write(phydev, 0x11, reg);
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/* restore to default page 0 */
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- phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
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+ phy_write(phydev, RTL8211_PAGE_SELECT, 0x0);
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return 0;
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}
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diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
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index d820d00..bb368a5 100644
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--- a/drivers/net/phy/realtek.c
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+++ b/drivers/net/phy/realtek.c
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@@ -13,6 +13,7 @@
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* option) any later version.
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*
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*/
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+#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/module.h>
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@@ -26,6 +27,8 @@
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#define RTL8211_PAGE_SELECT 0x1f
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#define RTL8211E_INER_LINK_STATUS 0x400
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+#define RTL8211E_EXT_PAGE_SELECT 0x1e
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+#define RTL8211E_EXT_PAGE 0x7
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#define RTL8211F_INER_LINK_STATUS 0x0010
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#define RTL8211F_INSR 0x1d
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@@ -121,6 +124,34 @@ static int rtl8211f_config_init(struct phy_device *phydev)
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return 0;
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}
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+static int rtl8211e_config_init(struct phy_device *phydev)
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+{
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+ struct device *dev = &phydev->mdio.dev;
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+ struct device_node *of_node = dev->of_node;
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+ int ret;
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+
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+ ret = genphy_config_init(phydev);
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+ if (ret < 0)
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+ return ret;
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+
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+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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+ /*
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+ * Disable the RX internal delay here.
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+ *
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+ * All the magic numbers are not documented on RTL8211E
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+ * datasheet. They're said to be from Realtek by Pine64.
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+ */
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+ phy_write(phydev, RTL8211_PAGE_SELECT, RTL8211E_EXT_PAGE);
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+ phy_write(phydev, RTL8211E_EXT_PAGE_SELECT, 0xa4);
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+ phy_write(phydev, 0x1c, 0xb591);
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+
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+ /* Restore to default page 0 */
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+ phy_write(phydev, RTL8211_PAGE_SELECT, 0);
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+ }
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+
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+ return 0;
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+}
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+
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static struct phy_driver realtek_drvs[] = {
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{
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.phy_id = 0x00008201,
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@@ -159,6 +190,7 @@ static int rtl8211f_config_init(struct phy_device *phydev)
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.config_aneg = &genphy_config_aneg,
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+ .config_init = rtl8211e_config_init,
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.read_status = &genphy_read_status,
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.ack_interrupt = &rtl821x_ack_interrupt,
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.config_intr = &rtl8211e_config_intr,
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
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index 24f1aac..ed71542 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
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@@ -52,7 +52,7 @@
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&emac {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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- phy-mode = "rgmii";
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+ phy-mode = "rgmii-txid";
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phy-handle = <&ext_rgmii_phy>;
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status = "okay";
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};
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