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* [Early WIP] Update sunxi-next to kernel 4.17 * Switch Allwinner 32 and 64bit to U-boot 2018.05 * Adjust patched for 4.17.y / sunxi-next - adjust both configurations - removing FAT support from u-boot (breaks if you try to save) Tested those boards: Cubietruck: wlan fails http://ix.io/1fYS USB OK, HDMI yes Bananapi R40: http://ix.io/1fZm USB OK, HDMI yes Lime A64: USB no, HDMI no, wireless buggy, eMMC yes Orangepi prime H5: OK http://ix.io/1fZJ DVFS no Orangepi2e: DVFS OK, HDMI OK, net OK, wifi OK, eMMC ok, http://ix.io/1fZT * Kernel config update, enabling HDMI on CT+ * Trying to fix A64 HDMI but failed. Fixed M64 ethernet instead * Update orangepioneplus.wip * Update orangepioneplus.wip * Fix H6 build process * Add regulator bits for Orangepizero+, thanks to @5kft * add H5 support for optional 1.3v regulator and 1.3GHz operation This patch adds two optional overlays that can be used to: 1) enable the 1.1v/1.3v regulator on boards that provide the necessary compatible H/W support 2) modify the default CPU clock operating table to add new 1.2GHz and 1.3GHz clocks Note that the generated regulator overlay will only support boards whose 1.1v/1.3v regulator is controlled by GPIO PL6. * updates for the NanoPi NEO Plus2 This change introduces a patch that provides two changes for the NanoPi NEO Plus2: * Configure the "cpu0" to use the "vdd_cpux" regulator; this enables the ability to use higher CPU clocks * Correct the configurations of the on-board power and status LEDs * Adjust nightly building and few boards config cleanup
56 lines
2.1 KiB
Diff
56 lines
2.1 KiB
Diff
From 35fbec685e9ccdcf154f00a93b46eafb9d0cc87a Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Sun, 3 Sep 2017 11:32:34 +0200
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Subject: [PATCH] drm: bridge: Add audio workaround for dw_hdmi v1.32a
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Allwinner SoCs with dw hdmi v1.32a seems to have an issue with manual
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setting CTS value. BSP driver sets it to auto mode and that works
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here too.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 30 ++++++++++++++++++++----------
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1 file changed, 20 insertions(+), 10 deletions(-)
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diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
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index 72969240a9d42..984fab8b658b5 100644
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--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
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+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
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@@ -424,16 +424,26 @@ static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
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static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
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unsigned int n)
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{
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- /* Must be set/cleared first */
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- hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
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-
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- /* nshift factor = 0 */
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- hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
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-
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- hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
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- HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
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- hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
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- hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
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+ /*
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+ * Manual CTS setting doesn't work correctly on Allwinner SoCs with
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+ * dw hdmi v1.32a.
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+ */
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+ if (hdmi->version != 0x132a) {
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+ /* Must be set/cleared first */
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+ hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
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+
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+ /* nshift factor = 0 */
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+ hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
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+
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+ hdmi_writeb(hdmi,
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+ ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
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+ HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
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+ hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
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+ hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
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+ } else {
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+ /* set automatic CTS calculation */
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+ hdmi_writeb(hdmi, 0x00, HDMI_AUD_CTS3);
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+ }
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hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
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hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
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