armbian_build/patch/kernel/archive/mvebu-6.6/20-pcie-bridge-emul.patch
2025-01-05 10:15:14 +01:00

56 lines
2.3 KiB
Diff

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@armlinux.org.uk>
Date: Tue, 2 Feb 2021 13:45:28 +0000
Subject: PCI: pci-bridge-emul: re-arrange register tests
Re-arrange the tests for which sets of registers are being accessed
so that it is easier to add further regions later. No functional
change.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
drivers/pci/pci-bridge-emul.c | 15 ++++++----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
index 111111111111..222222222222 100644
--- a/drivers/pci/pci-bridge-emul.c
+++ b/drivers/pci/pci-bridge-emul.c
@@ -479,8 +479,11 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
read_op = pci_bridge_emul_read_ssid;
cfgspace = NULL;
behavior = NULL;
- } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF &&
- bridge->has_pcie) {
+ } else if (!bridge->has_pcie) {
+ /* PCIe space is not implemented, and no PCI capabilities */
+ *value = 0;
+ return PCIBIOS_SUCCESSFUL;
+ } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF) {
/* Our emulated PCIe capability */
reg -= bridge->pcie_start;
read_op = bridge->ops->read_pcie;
@@ -553,14 +556,16 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
write_op = bridge->ops->write_base;
cfgspace = (__le32 *) &bridge->conf;
behavior = bridge->pci_regs_behavior;
- } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF &&
- bridge->has_pcie) {
+ } else if (!bridge->has_pcie) {
+ /* PCIe space is not implemented, and no PCI capabilities */
+ return PCIBIOS_SUCCESSFUL;
+ } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF) {
/* Our emulated PCIe capability */
reg -= bridge->pcie_start;
write_op = bridge->ops->write_pcie;
cfgspace = (__le32 *) &bridge->pcie_conf;
behavior = bridge->pcie_cap_regs_behavior;
- } else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {
+ } else if (reg >= PCI_CFG_SPACE_SIZE) {
/* PCIe extended capability space */
reg -= PCI_CFG_SPACE_SIZE;
write_op = bridge->ops->write_ext;
--
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