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- `risc-v`: rework RichNeese's boards, reduce families, move tweaks to boards - `risc-v`/`starfive`: `CONFIG_MOTORCOMM_PHY=m` for the onboard Ethernet - `risc-v`/`starfive`: use mainline kernel 6.1.y, with StarFive's rebased patches against `v6.1.5` - from https://github.com/starfive-tech/linux/commits/visionfive - contention point: `1022-soc-sifive-ccache-Add-StarFive-JH71x0-support.patch` which I merged half-assed, need review/fixes? - `risc-v`/`starfive`: update kernel config, sans changes - `risc-v`/`starfive`: switch from `grub` to `extlinux` - `risc-v`/`starfive`: new `starfive` family with their (vendor) kernel Co-authored-by: Richard Neese <r.neese@gmail.com>
34 lines
1.0 KiB
Diff
34 lines
1.0 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Sat, 20 Nov 2021 21:33:08 +0100
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Subject: RISC-V: Add StarFive JH7100 audio reset node
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Add device tree node for the audio resets on the StarFive JH7100 RISC-V
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SoC.
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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---
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arch/riscv/boot/dts/starfive/jh7100.dtsi | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
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index 0b948f61e253..9f387fdf4afc 100644
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--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
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@@ -144,6 +144,12 @@ audclk: clock-controller@10480000 {
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#clock-cells = <1>;
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};
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+ audrst: reset-controller@10490000 {
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+ compatible = "starfive,jh7100-audrst";
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+ reg = <0x0 0x10490000 0x0 0x10000>;
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+ #reset-cells = <1>;
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+ };
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+
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clkgen: clock-controller@11800000 {
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compatible = "starfive,jh7100-clkgen";
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reg = <0x0 0x11800000 0x0 0x10000>;
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--
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Armbian
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