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dbdb03ddb8
Now the names of the patch files correspond to the entry in the commit message. Patches that have been transferred (copied) since time immemorial and require revision have been removed. No one wants to deal with them.
64 lines
2.0 KiB
Diff
64 lines
2.0 KiB
Diff
From 073fe82934a9ca83fa80f9415d48f6d69dd6c69f Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Mon, 25 Dec 2017 12:08:01 +0800
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Subject: Doc:dt-bindings:usb: add binding for DWC3 controller on Allwinner SoC
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The Allwinner H6 SoC uses DWC3 controller for USB3.
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Add its device tree binding document.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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.../bindings/usb/allwinner,dwc3.txt | 39 +++++++++++++++++++
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1 file changed, 39 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/usb/allwinner,dwc3.txt
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diff --git a/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt b/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt
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new file mode 100644
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index 000000000000..3f7714636785
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt
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@@ -0,0 +1,39 @@
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+Allwinner SuperSpeed DWC3 USB SoC controller
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+
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+Required properties:
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+- compatible: should contain "allwinner,sun50i-h6-dwc3" for H6 SoC
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+- clocks: A list of phandle + clock-specifier pairs for the
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+ clocks listed in clock-names
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+- clock-names: Should contain the following:
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+ "bus" The bus clock of the DWC3 part
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+- resets: A list of phandle + reset-specifier pairs for the
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+ resets listed in reset-names
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+- reset-names: Should contain the following:
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+ "bus" The bus reset of the DWC3 part
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+
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+Required child node:
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+A child node must exist to represent the core DWC3 IP block. The name of
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+the node is not important. The content of the node is defined in dwc3.txt.
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+
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+Phy documentation is provided in the following places:
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+Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
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+
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+Example device nodes:
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+ usb3: usb@5200000 {
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+ compatible = "allwinner,sun50i-h6-dwc3";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ clocks = <&ccu CLK_BUS_XHCI>;
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+ clock-names = "bus";
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+ resets = <&ccu RST_BUS_XHCI>;
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+ reset-names = "bus";
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+
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+ dwc3: dwc3 {
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+ compatible = "snps,dwc3";
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+ reg = <0x5200000 0x10000>;
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+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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+ phys = <&usb3phy>;
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+ phy-names = "usb3-phy";
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+ };
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+ };
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--
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2.35.3
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